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393daa81 RY |
1 | /* |
2 | * pinmux driver for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/init.h> | |
10 | #include <linux/module.h> | |
51302162 | 11 | #include <linux/irq.h> |
393daa81 RY |
12 | #include <linux/platform_device.h> |
13 | #include <linux/io.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/err.h> | |
51302162 | 16 | #include <linux/irqdomain.h> |
393daa81 RY |
17 | #include <linux/pinctrl/pinctrl.h> |
18 | #include <linux/pinctrl/pinmux.h> | |
51302162 | 19 | #include <linux/pinctrl/consumer.h> |
393daa81 RY |
20 | #include <linux/of.h> |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/of_platform.h> | |
24 | #include <linux/bitops.h> | |
51302162 BS |
25 | #include <linux/gpio.h> |
26 | #include <linux/of_gpio.h> | |
393daa81 RY |
27 | |
28 | #define DRIVER_NAME "pinmux-sirf" | |
29 | ||
30 | #define SIRFSOC_NUM_PADS 622 | |
393daa81 RY |
31 | #define SIRFSOC_RSC_PIN_MUX 0x4 |
32 | ||
51302162 BS |
33 | #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) |
34 | #define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4) | |
35 | #define SIRFSOC_GPIO_DSP_EN0 (0x80) | |
36 | #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) | |
37 | #define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C) | |
38 | ||
39 | #define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1 | |
40 | #define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2 | |
41 | #define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4 | |
42 | #define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8 | |
43 | #define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10 | |
44 | #define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20 | |
45 | #define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40 | |
46 | #define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80 | |
47 | #define SIRFSOC_GPIO_CTL_PULL_MASK 0x100 | |
48 | #define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200 | |
49 | #define SIRFSOC_GPIO_CTL_DSP_INT 0x400 | |
50 | ||
51 | #define SIRFSOC_GPIO_NO_OF_BANKS 5 | |
52 | #define SIRFSOC_GPIO_BANK_SIZE 32 | |
53 | #define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index)) | |
54 | ||
55 | struct sirfsoc_gpio_bank { | |
56 | struct of_mm_gpio_chip chip; | |
57 | struct irq_domain *domain; | |
58 | int id; | |
59 | int parent_irq; | |
60 | spinlock_t lock; | |
61 | }; | |
62 | ||
63 | static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; | |
64 | static DEFINE_SPINLOCK(sgpio_lock); | |
65 | ||
393daa81 RY |
66 | /* |
67 | * pad list for the pinmux subsystem | |
68 | * refer to CS-131858-DC-6A.xls | |
69 | */ | |
25aec320 | 70 | static const struct pinctrl_pin_desc sirfsoc_pads[] = { |
393daa81 RY |
71 | PINCTRL_PIN(4, "pwm0"), |
72 | PINCTRL_PIN(5, "pwm1"), | |
73 | PINCTRL_PIN(6, "pwm2"), | |
74 | PINCTRL_PIN(7, "pwm3"), | |
75 | PINCTRL_PIN(8, "warm_rst_b"), | |
76 | PINCTRL_PIN(9, "odo_0"), | |
77 | PINCTRL_PIN(10, "odo_1"), | |
78 | PINCTRL_PIN(11, "dr_dir"), | |
79 | PINCTRL_PIN(13, "scl_1"), | |
80 | PINCTRL_PIN(15, "sda_1"), | |
81 | PINCTRL_PIN(16, "x_ldd[16]"), | |
82 | PINCTRL_PIN(17, "x_ldd[17]"), | |
83 | PINCTRL_PIN(18, "x_ldd[18]"), | |
84 | PINCTRL_PIN(19, "x_ldd[19]"), | |
85 | PINCTRL_PIN(20, "x_ldd[20]"), | |
86 | PINCTRL_PIN(21, "x_ldd[21]"), | |
87 | PINCTRL_PIN(22, "x_ldd[22]"), | |
88 | PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"), | |
89 | PINCTRL_PIN(24, "gps_sgn"), | |
90 | PINCTRL_PIN(25, "gps_mag"), | |
91 | PINCTRL_PIN(26, "gps_clk"), | |
92 | PINCTRL_PIN(27, "sd_cd_b_1"), | |
93 | PINCTRL_PIN(28, "sd_vcc_on_1"), | |
94 | PINCTRL_PIN(29, "sd_wp_b_1"), | |
95 | PINCTRL_PIN(30, "sd_clk_3"), | |
96 | PINCTRL_PIN(31, "sd_cmd_3"), | |
97 | ||
98 | PINCTRL_PIN(32, "x_sd_dat_3[0]"), | |
99 | PINCTRL_PIN(33, "x_sd_dat_3[1]"), | |
100 | PINCTRL_PIN(34, "x_sd_dat_3[2]"), | |
101 | PINCTRL_PIN(35, "x_sd_dat_3[3]"), | |
102 | PINCTRL_PIN(36, "x_sd_clk_4"), | |
103 | PINCTRL_PIN(37, "x_sd_cmd_4"), | |
104 | PINCTRL_PIN(38, "x_sd_dat_4[0]"), | |
105 | PINCTRL_PIN(39, "x_sd_dat_4[1]"), | |
106 | PINCTRL_PIN(40, "x_sd_dat_4[2]"), | |
107 | PINCTRL_PIN(41, "x_sd_dat_4[3]"), | |
108 | PINCTRL_PIN(42, "x_cko_1"), | |
109 | PINCTRL_PIN(43, "x_ac97_bit_clk"), | |
110 | PINCTRL_PIN(44, "x_ac97_dout"), | |
111 | PINCTRL_PIN(45, "x_ac97_din"), | |
112 | PINCTRL_PIN(46, "x_ac97_sync"), | |
113 | PINCTRL_PIN(47, "x_txd_1"), | |
114 | PINCTRL_PIN(48, "x_txd_2"), | |
115 | PINCTRL_PIN(49, "x_rxd_1"), | |
116 | PINCTRL_PIN(50, "x_rxd_2"), | |
117 | PINCTRL_PIN(51, "x_usclk_0"), | |
118 | PINCTRL_PIN(52, "x_utxd_0"), | |
119 | PINCTRL_PIN(53, "x_urxd_0"), | |
120 | PINCTRL_PIN(54, "x_utfs_0"), | |
121 | PINCTRL_PIN(55, "x_urfs_0"), | |
122 | PINCTRL_PIN(56, "x_usclk_1"), | |
123 | PINCTRL_PIN(57, "x_utxd_1"), | |
124 | PINCTRL_PIN(58, "x_urxd_1"), | |
125 | PINCTRL_PIN(59, "x_utfs_1"), | |
126 | PINCTRL_PIN(60, "x_urfs_1"), | |
127 | PINCTRL_PIN(61, "x_usclk_2"), | |
128 | PINCTRL_PIN(62, "x_utxd_2"), | |
129 | PINCTRL_PIN(63, "x_urxd_2"), | |
130 | ||
131 | PINCTRL_PIN(64, "x_utfs_2"), | |
132 | PINCTRL_PIN(65, "x_urfs_2"), | |
133 | PINCTRL_PIN(66, "x_df_we_b"), | |
134 | PINCTRL_PIN(67, "x_df_re_b"), | |
135 | PINCTRL_PIN(68, "x_txd_0"), | |
136 | PINCTRL_PIN(69, "x_rxd_0"), | |
137 | PINCTRL_PIN(78, "x_cko_0"), | |
138 | PINCTRL_PIN(79, "x_vip_pxd[7]"), | |
139 | PINCTRL_PIN(80, "x_vip_pxd[6]"), | |
140 | PINCTRL_PIN(81, "x_vip_pxd[5]"), | |
141 | PINCTRL_PIN(82, "x_vip_pxd[4]"), | |
142 | PINCTRL_PIN(83, "x_vip_pxd[3]"), | |
143 | PINCTRL_PIN(84, "x_vip_pxd[2]"), | |
144 | PINCTRL_PIN(85, "x_vip_pxd[1]"), | |
145 | PINCTRL_PIN(86, "x_vip_pxd[0]"), | |
146 | PINCTRL_PIN(87, "x_vip_vsync"), | |
147 | PINCTRL_PIN(88, "x_vip_hsync"), | |
148 | PINCTRL_PIN(89, "x_vip_pxclk"), | |
149 | PINCTRL_PIN(90, "x_sda_0"), | |
150 | PINCTRL_PIN(91, "x_scl_0"), | |
151 | PINCTRL_PIN(92, "x_df_ry_by"), | |
152 | PINCTRL_PIN(93, "x_df_cs_b[1]"), | |
153 | PINCTRL_PIN(94, "x_df_cs_b[0]"), | |
154 | PINCTRL_PIN(95, "x_l_pclk"), | |
155 | ||
156 | PINCTRL_PIN(96, "x_l_lck"), | |
157 | PINCTRL_PIN(97, "x_l_fck"), | |
158 | PINCTRL_PIN(98, "x_l_de"), | |
159 | PINCTRL_PIN(99, "x_ldd[0]"), | |
160 | PINCTRL_PIN(100, "x_ldd[1]"), | |
161 | PINCTRL_PIN(101, "x_ldd[2]"), | |
162 | PINCTRL_PIN(102, "x_ldd[3]"), | |
163 | PINCTRL_PIN(103, "x_ldd[4]"), | |
164 | PINCTRL_PIN(104, "x_ldd[5]"), | |
165 | PINCTRL_PIN(105, "x_ldd[6]"), | |
166 | PINCTRL_PIN(106, "x_ldd[7]"), | |
167 | PINCTRL_PIN(107, "x_ldd[8]"), | |
168 | PINCTRL_PIN(108, "x_ldd[9]"), | |
169 | PINCTRL_PIN(109, "x_ldd[10]"), | |
170 | PINCTRL_PIN(110, "x_ldd[11]"), | |
171 | PINCTRL_PIN(111, "x_ldd[12]"), | |
172 | PINCTRL_PIN(112, "x_ldd[13]"), | |
173 | PINCTRL_PIN(113, "x_ldd[14]"), | |
174 | PINCTRL_PIN(114, "x_ldd[15]"), | |
175 | }; | |
176 | ||
177 | /** | |
178 | * @dev: a pointer back to containing device | |
179 | * @virtbase: the offset to the controller in virtual memory | |
180 | */ | |
181 | struct sirfsoc_pmx { | |
182 | struct device *dev; | |
183 | struct pinctrl_dev *pmx; | |
184 | void __iomem *gpio_virtbase; | |
185 | void __iomem *rsc_virtbase; | |
186 | }; | |
187 | ||
188 | /* SIRFSOC_GPIO_PAD_EN set */ | |
189 | struct sirfsoc_muxmask { | |
190 | unsigned long group; | |
191 | unsigned long mask; | |
192 | }; | |
193 | ||
194 | struct sirfsoc_padmux { | |
195 | unsigned long muxmask_counts; | |
196 | const struct sirfsoc_muxmask *muxmask; | |
197 | /* RSC_PIN_MUX set */ | |
198 | unsigned long funcmask; | |
199 | unsigned long funcval; | |
200 | }; | |
201 | ||
202 | /** | |
203 | * struct sirfsoc_pin_group - describes a SiRFprimaII pin group | |
204 | * @name: the name of this specific pin group | |
205 | * @pins: an array of discrete physical pins used in this group, taken | |
206 | * from the driver-local pin enumeration space | |
207 | * @num_pins: the number of pins in this group array, i.e. the number of | |
208 | * elements in .pins so we can iterate over that array | |
209 | */ | |
210 | struct sirfsoc_pin_group { | |
211 | const char *name; | |
212 | const unsigned int *pins; | |
213 | const unsigned num_pins; | |
214 | }; | |
215 | ||
216 | static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { | |
217 | { | |
218 | .group = 3, | |
219 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | | |
220 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | | |
221 | BIT(17) | BIT(18), | |
222 | }, { | |
223 | .group = 2, | |
224 | .mask = BIT(31), | |
225 | }, | |
226 | }; | |
227 | ||
228 | static const struct sirfsoc_padmux lcd_16bits_padmux = { | |
229 | .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), | |
230 | .muxmask = lcd_16bits_sirfsoc_muxmask, | |
231 | .funcmask = BIT(4), | |
232 | .funcval = 0, | |
233 | }; | |
234 | ||
235 | static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, | |
236 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; | |
237 | ||
238 | static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { | |
239 | { | |
240 | .group = 3, | |
241 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | | |
242 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | | |
243 | BIT(17) | BIT(18), | |
244 | }, { | |
245 | .group = 2, | |
246 | .mask = BIT(31), | |
247 | }, { | |
248 | .group = 0, | |
249 | .mask = BIT(16) | BIT(17), | |
250 | }, | |
251 | }; | |
252 | ||
253 | static const struct sirfsoc_padmux lcd_18bits_padmux = { | |
254 | .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), | |
255 | .muxmask = lcd_18bits_muxmask, | |
256 | .funcmask = BIT(4), | |
257 | .funcval = 0, | |
258 | }; | |
259 | ||
260 | static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, | |
261 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; | |
262 | ||
263 | static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { | |
264 | { | |
265 | .group = 3, | |
266 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | | |
267 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | | |
268 | BIT(17) | BIT(18), | |
269 | }, { | |
270 | .group = 2, | |
271 | .mask = BIT(31), | |
272 | }, { | |
273 | .group = 0, | |
274 | .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), | |
275 | }, | |
276 | }; | |
277 | ||
278 | static const struct sirfsoc_padmux lcd_24bits_padmux = { | |
279 | .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), | |
280 | .muxmask = lcd_24bits_muxmask, | |
281 | .funcmask = BIT(4), | |
282 | .funcval = 0, | |
283 | }; | |
284 | ||
285 | static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, | |
286 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; | |
287 | ||
288 | static const struct sirfsoc_muxmask lcdrom_muxmask[] = { | |
289 | { | |
290 | .group = 3, | |
291 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | | |
292 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | | |
293 | BIT(17) | BIT(18), | |
294 | }, { | |
295 | .group = 2, | |
296 | .mask = BIT(31), | |
297 | }, { | |
298 | .group = 0, | |
299 | .mask = BIT(23), | |
300 | }, | |
301 | }; | |
302 | ||
303 | static const struct sirfsoc_padmux lcdrom_padmux = { | |
304 | .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), | |
305 | .muxmask = lcdrom_muxmask, | |
306 | .funcmask = BIT(4), | |
307 | .funcval = BIT(4), | |
308 | }; | |
309 | ||
310 | static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, | |
311 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; | |
312 | ||
313 | static const struct sirfsoc_muxmask uart0_muxmask[] = { | |
314 | { | |
315 | .group = 2, | |
316 | .mask = BIT(4) | BIT(5), | |
317 | }, { | |
318 | .group = 1, | |
319 | .mask = BIT(23) | BIT(28), | |
320 | }, | |
321 | }; | |
322 | ||
323 | static const struct sirfsoc_padmux uart0_padmux = { | |
324 | .muxmask_counts = ARRAY_SIZE(uart0_muxmask), | |
325 | .muxmask = uart0_muxmask, | |
326 | .funcmask = BIT(9), | |
327 | .funcval = BIT(9), | |
328 | }; | |
329 | ||
330 | static const unsigned uart0_pins[] = { 55, 60, 68, 69 }; | |
331 | ||
332 | static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { | |
333 | { | |
334 | .group = 2, | |
335 | .mask = BIT(4) | BIT(5), | |
336 | }, | |
337 | }; | |
338 | ||
339 | static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { | |
340 | .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask), | |
341 | .muxmask = uart0_nostreamctrl_muxmask, | |
342 | }; | |
343 | ||
344 | static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 }; | |
345 | ||
346 | static const struct sirfsoc_muxmask uart1_muxmask[] = { | |
347 | { | |
348 | .group = 1, | |
349 | .mask = BIT(15) | BIT(17), | |
350 | }, | |
351 | }; | |
352 | ||
353 | static const struct sirfsoc_padmux uart1_padmux = { | |
354 | .muxmask_counts = ARRAY_SIZE(uart1_muxmask), | |
355 | .muxmask = uart1_muxmask, | |
356 | }; | |
357 | ||
358 | static const unsigned uart1_pins[] = { 47, 49 }; | |
359 | ||
360 | static const struct sirfsoc_muxmask uart2_muxmask[] = { | |
361 | { | |
362 | .group = 1, | |
363 | .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27), | |
364 | }, | |
365 | }; | |
366 | ||
367 | static const struct sirfsoc_padmux uart2_padmux = { | |
368 | .muxmask_counts = ARRAY_SIZE(uart2_muxmask), | |
369 | .muxmask = uart2_muxmask, | |
370 | .funcmask = BIT(10), | |
371 | .funcval = BIT(10), | |
372 | }; | |
373 | ||
374 | static const unsigned uart2_pins[] = { 48, 50, 56, 59 }; | |
375 | ||
376 | static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { | |
377 | { | |
378 | .group = 1, | |
379 | .mask = BIT(16) | BIT(18), | |
380 | }, | |
381 | }; | |
382 | ||
383 | static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { | |
384 | .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask), | |
385 | .muxmask = uart2_nostreamctrl_muxmask, | |
386 | }; | |
387 | ||
388 | static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; | |
389 | ||
390 | static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { | |
391 | { | |
392 | .group = 0, | |
393 | .mask = BIT(30) | BIT(31), | |
394 | }, { | |
395 | .group = 1, | |
396 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), | |
397 | }, | |
398 | }; | |
399 | ||
400 | static const struct sirfsoc_padmux sdmmc3_padmux = { | |
401 | .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), | |
402 | .muxmask = sdmmc3_muxmask, | |
403 | .funcmask = BIT(7), | |
404 | .funcval = 0, | |
405 | }; | |
406 | ||
407 | static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; | |
408 | ||
409 | static const struct sirfsoc_muxmask spi0_muxmask[] = { | |
410 | { | |
411 | .group = 1, | |
412 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), | |
413 | }, | |
414 | }; | |
415 | ||
416 | static const struct sirfsoc_padmux spi0_padmux = { | |
417 | .muxmask_counts = ARRAY_SIZE(spi0_muxmask), | |
418 | .muxmask = spi0_muxmask, | |
419 | .funcmask = BIT(7), | |
420 | .funcval = BIT(7), | |
421 | }; | |
422 | ||
423 | static const unsigned spi0_pins[] = { 32, 33, 34, 35 }; | |
424 | ||
425 | static const struct sirfsoc_muxmask sdmmc4_muxmask[] = { | |
426 | { | |
427 | .group = 1, | |
428 | .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9), | |
429 | }, | |
430 | }; | |
431 | ||
432 | static const struct sirfsoc_padmux sdmmc4_padmux = { | |
433 | .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask), | |
434 | .muxmask = sdmmc4_muxmask, | |
435 | }; | |
436 | ||
437 | static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 }; | |
438 | ||
439 | static const struct sirfsoc_muxmask cko1_muxmask[] = { | |
440 | { | |
441 | .group = 1, | |
442 | .mask = BIT(10), | |
443 | }, | |
444 | }; | |
445 | ||
446 | static const struct sirfsoc_padmux cko1_padmux = { | |
447 | .muxmask_counts = ARRAY_SIZE(cko1_muxmask), | |
448 | .muxmask = cko1_muxmask, | |
449 | .funcmask = BIT(3), | |
450 | .funcval = 0, | |
451 | }; | |
452 | ||
453 | static const unsigned cko1_pins[] = { 42 }; | |
454 | ||
455 | static const struct sirfsoc_muxmask i2s_muxmask[] = { | |
456 | { | |
457 | .group = 1, | |
458 | .mask = | |
459 | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19) | |
460 | | BIT(23) | BIT(28), | |
461 | }, | |
462 | }; | |
463 | ||
464 | static const struct sirfsoc_padmux i2s_padmux = { | |
465 | .muxmask_counts = ARRAY_SIZE(i2s_muxmask), | |
466 | .muxmask = i2s_muxmask, | |
467 | .funcmask = BIT(3) | BIT(9), | |
468 | .funcval = BIT(3), | |
469 | }; | |
470 | ||
471 | static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 }; | |
472 | ||
473 | static const struct sirfsoc_muxmask ac97_muxmask[] = { | |
474 | { | |
475 | .group = 1, | |
476 | .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), | |
477 | }, | |
478 | }; | |
479 | ||
480 | static const struct sirfsoc_padmux ac97_padmux = { | |
481 | .muxmask_counts = ARRAY_SIZE(ac97_muxmask), | |
482 | .muxmask = ac97_muxmask, | |
483 | .funcmask = BIT(8), | |
484 | .funcval = 0, | |
485 | }; | |
486 | ||
487 | static const unsigned ac97_pins[] = { 33, 34, 35, 36 }; | |
488 | ||
489 | static const struct sirfsoc_muxmask spi1_muxmask[] = { | |
490 | { | |
491 | .group = 1, | |
492 | .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), | |
493 | }, | |
494 | }; | |
495 | ||
496 | static const struct sirfsoc_padmux spi1_padmux = { | |
497 | .muxmask_counts = ARRAY_SIZE(spi1_muxmask), | |
498 | .muxmask = spi1_muxmask, | |
499 | .funcmask = BIT(8), | |
500 | .funcval = BIT(8), | |
501 | }; | |
502 | ||
f59d28dc | 503 | static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; |
393daa81 RY |
504 | |
505 | static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { | |
506 | { | |
507 | .group = 0, | |
508 | .mask = BIT(27) | BIT(28) | BIT(29), | |
509 | }, | |
510 | }; | |
511 | ||
512 | static const struct sirfsoc_padmux sdmmc1_padmux = { | |
513 | .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), | |
514 | .muxmask = sdmmc1_muxmask, | |
515 | }; | |
516 | ||
517 | static const unsigned sdmmc1_pins[] = { 27, 28, 29 }; | |
518 | ||
519 | static const struct sirfsoc_muxmask gps_muxmask[] = { | |
520 | { | |
521 | .group = 0, | |
522 | .mask = BIT(24) | BIT(25) | BIT(26), | |
523 | }, | |
524 | }; | |
525 | ||
526 | static const struct sirfsoc_padmux gps_padmux = { | |
527 | .muxmask_counts = ARRAY_SIZE(gps_muxmask), | |
528 | .muxmask = gps_muxmask, | |
529 | .funcmask = BIT(12) | BIT(13) | BIT(14), | |
530 | .funcval = BIT(12), | |
531 | }; | |
532 | ||
533 | static const unsigned gps_pins[] = { 24, 25, 26 }; | |
534 | ||
535 | static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { | |
536 | { | |
537 | .group = 0, | |
538 | .mask = BIT(24) | BIT(25) | BIT(26), | |
539 | }, { | |
540 | .group = 1, | |
541 | .mask = BIT(29), | |
542 | }, { | |
543 | .group = 2, | |
544 | .mask = BIT(0) | BIT(1), | |
545 | }, | |
546 | }; | |
547 | ||
548 | static const struct sirfsoc_padmux sdmmc5_padmux = { | |
549 | .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), | |
550 | .muxmask = sdmmc5_muxmask, | |
551 | .funcmask = BIT(13) | BIT(14), | |
552 | .funcval = BIT(13) | BIT(14), | |
553 | }; | |
554 | ||
555 | static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 }; | |
556 | ||
557 | static const struct sirfsoc_muxmask usp0_muxmask[] = { | |
558 | { | |
559 | .group = 1, | |
560 | .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), | |
561 | }, | |
562 | }; | |
563 | ||
564 | static const struct sirfsoc_padmux usp0_padmux = { | |
565 | .muxmask_counts = ARRAY_SIZE(usp0_muxmask), | |
566 | .muxmask = usp0_muxmask, | |
567 | .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9), | |
568 | .funcval = 0, | |
569 | }; | |
570 | ||
571 | static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; | |
572 | ||
573 | static const struct sirfsoc_muxmask usp1_muxmask[] = { | |
574 | { | |
575 | .group = 1, | |
576 | .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28), | |
577 | }, | |
578 | }; | |
579 | ||
580 | static const struct sirfsoc_padmux usp1_padmux = { | |
581 | .muxmask_counts = ARRAY_SIZE(usp1_muxmask), | |
582 | .muxmask = usp1_muxmask, | |
583 | .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11), | |
584 | .funcval = 0, | |
585 | }; | |
586 | ||
587 | static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 }; | |
588 | ||
589 | static const struct sirfsoc_muxmask usp2_muxmask[] = { | |
590 | { | |
591 | .group = 1, | |
592 | .mask = BIT(29) | BIT(30) | BIT(31), | |
593 | }, { | |
594 | .group = 2, | |
595 | .mask = BIT(0) | BIT(1), | |
596 | }, | |
597 | }; | |
598 | ||
599 | static const struct sirfsoc_padmux usp2_padmux = { | |
600 | .muxmask_counts = ARRAY_SIZE(usp2_muxmask), | |
601 | .muxmask = usp2_muxmask, | |
602 | .funcmask = BIT(13) | BIT(14), | |
603 | .funcval = 0, | |
604 | }; | |
605 | ||
606 | static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 }; | |
607 | ||
608 | static const struct sirfsoc_muxmask nand_muxmask[] = { | |
609 | { | |
610 | .group = 2, | |
611 | .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), | |
612 | }, | |
613 | }; | |
614 | ||
615 | static const struct sirfsoc_padmux nand_padmux = { | |
616 | .muxmask_counts = ARRAY_SIZE(nand_muxmask), | |
617 | .muxmask = nand_muxmask, | |
618 | .funcmask = BIT(5), | |
619 | .funcval = 0, | |
620 | }; | |
621 | ||
622 | static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 }; | |
623 | ||
624 | static const struct sirfsoc_padmux sdmmc0_padmux = { | |
625 | .muxmask_counts = 0, | |
626 | .funcmask = BIT(5), | |
627 | .funcval = 0, | |
628 | }; | |
629 | ||
630 | static const unsigned sdmmc0_pins[] = { }; | |
631 | ||
632 | static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { | |
633 | { | |
634 | .group = 2, | |
635 | .mask = BIT(2) | BIT(3), | |
636 | }, | |
637 | }; | |
638 | ||
639 | static const struct sirfsoc_padmux sdmmc2_padmux = { | |
640 | .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), | |
641 | .muxmask = sdmmc2_muxmask, | |
642 | .funcmask = BIT(5), | |
643 | .funcval = BIT(5), | |
644 | }; | |
645 | ||
646 | static const unsigned sdmmc2_pins[] = { 66, 67 }; | |
647 | ||
648 | static const struct sirfsoc_muxmask cko0_muxmask[] = { | |
649 | { | |
650 | .group = 2, | |
651 | .mask = BIT(14), | |
652 | }, | |
653 | }; | |
654 | ||
655 | static const struct sirfsoc_padmux cko0_padmux = { | |
656 | .muxmask_counts = ARRAY_SIZE(cko0_muxmask), | |
657 | .muxmask = cko0_muxmask, | |
658 | }; | |
659 | ||
660 | static const unsigned cko0_pins[] = { 78 }; | |
661 | ||
662 | static const struct sirfsoc_muxmask vip_muxmask[] = { | |
663 | { | |
664 | .group = 2, | |
665 | .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | |
666 | | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | | |
667 | BIT(25), | |
668 | }, | |
669 | }; | |
670 | ||
671 | static const struct sirfsoc_padmux vip_padmux = { | |
672 | .muxmask_counts = ARRAY_SIZE(vip_muxmask), | |
673 | .muxmask = vip_muxmask, | |
674 | .funcmask = BIT(0), | |
675 | .funcval = 0, | |
676 | }; | |
677 | ||
678 | static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; | |
679 | ||
680 | static const struct sirfsoc_muxmask i2c0_muxmask[] = { | |
681 | { | |
682 | .group = 2, | |
683 | .mask = BIT(26) | BIT(27), | |
684 | }, | |
685 | }; | |
686 | ||
687 | static const struct sirfsoc_padmux i2c0_padmux = { | |
688 | .muxmask_counts = ARRAY_SIZE(i2c0_muxmask), | |
689 | .muxmask = i2c0_muxmask, | |
690 | }; | |
691 | ||
692 | static const unsigned i2c0_pins[] = { 90, 91 }; | |
693 | ||
694 | static const struct sirfsoc_muxmask i2c1_muxmask[] = { | |
695 | { | |
696 | .group = 0, | |
697 | .mask = BIT(13) | BIT(15), | |
698 | }, | |
699 | }; | |
700 | ||
701 | static const struct sirfsoc_padmux i2c1_padmux = { | |
702 | .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), | |
703 | .muxmask = i2c1_muxmask, | |
704 | }; | |
705 | ||
706 | static const unsigned i2c1_pins[] = { 13, 15 }; | |
707 | ||
708 | static const struct sirfsoc_muxmask viprom_muxmask[] = { | |
709 | { | |
710 | .group = 2, | |
711 | .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | |
712 | | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | | |
713 | BIT(25), | |
714 | }, { | |
715 | .group = 0, | |
716 | .mask = BIT(12), | |
717 | }, | |
718 | }; | |
719 | ||
720 | static const struct sirfsoc_padmux viprom_padmux = { | |
721 | .muxmask_counts = ARRAY_SIZE(viprom_muxmask), | |
722 | .muxmask = viprom_muxmask, | |
723 | .funcmask = BIT(0), | |
724 | .funcval = BIT(0), | |
725 | }; | |
726 | ||
727 | static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; | |
728 | ||
729 | static const struct sirfsoc_muxmask pwm0_muxmask[] = { | |
730 | { | |
731 | .group = 0, | |
732 | .mask = BIT(4), | |
733 | }, | |
734 | }; | |
735 | ||
736 | static const struct sirfsoc_padmux pwm0_padmux = { | |
737 | .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), | |
738 | .muxmask = pwm0_muxmask, | |
739 | .funcmask = BIT(12), | |
740 | .funcval = 0, | |
741 | }; | |
742 | ||
743 | static const unsigned pwm0_pins[] = { 4 }; | |
744 | ||
745 | static const struct sirfsoc_muxmask pwm1_muxmask[] = { | |
746 | { | |
747 | .group = 0, | |
748 | .mask = BIT(5), | |
749 | }, | |
750 | }; | |
751 | ||
752 | static const struct sirfsoc_padmux pwm1_padmux = { | |
753 | .muxmask_counts = ARRAY_SIZE(pwm1_muxmask), | |
754 | .muxmask = pwm1_muxmask, | |
755 | }; | |
756 | ||
757 | static const unsigned pwm1_pins[] = { 5 }; | |
758 | ||
759 | static const struct sirfsoc_muxmask pwm2_muxmask[] = { | |
760 | { | |
761 | .group = 0, | |
762 | .mask = BIT(6), | |
763 | }, | |
764 | }; | |
765 | ||
766 | static const struct sirfsoc_padmux pwm2_padmux = { | |
767 | .muxmask_counts = ARRAY_SIZE(pwm2_muxmask), | |
768 | .muxmask = pwm2_muxmask, | |
769 | }; | |
770 | ||
771 | static const unsigned pwm2_pins[] = { 6 }; | |
772 | ||
773 | static const struct sirfsoc_muxmask pwm3_muxmask[] = { | |
774 | { | |
775 | .group = 0, | |
776 | .mask = BIT(7), | |
777 | }, | |
778 | }; | |
779 | ||
780 | static const struct sirfsoc_padmux pwm3_padmux = { | |
781 | .muxmask_counts = ARRAY_SIZE(pwm3_muxmask), | |
782 | .muxmask = pwm3_muxmask, | |
783 | }; | |
784 | ||
785 | static const unsigned pwm3_pins[] = { 7 }; | |
786 | ||
787 | static const struct sirfsoc_muxmask warm_rst_muxmask[] = { | |
788 | { | |
789 | .group = 0, | |
790 | .mask = BIT(8), | |
791 | }, | |
792 | }; | |
793 | ||
794 | static const struct sirfsoc_padmux warm_rst_padmux = { | |
795 | .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), | |
796 | .muxmask = warm_rst_muxmask, | |
797 | }; | |
798 | ||
799 | static const unsigned warm_rst_pins[] = { 8 }; | |
800 | ||
801 | static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = { | |
802 | { | |
803 | .group = 1, | |
804 | .mask = BIT(22), | |
805 | }, | |
806 | }; | |
807 | static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = { | |
808 | .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask), | |
809 | .muxmask = usb0_utmi_drvbus_muxmask, | |
810 | .funcmask = BIT(6), | |
811 | .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */ | |
812 | }; | |
813 | ||
814 | static const unsigned usb0_utmi_drvbus_pins[] = { 54 }; | |
815 | ||
816 | static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { | |
817 | { | |
818 | .group = 1, | |
819 | .mask = BIT(27), | |
820 | }, | |
821 | }; | |
822 | ||
823 | static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { | |
824 | .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), | |
825 | .muxmask = usb1_utmi_drvbus_muxmask, | |
826 | .funcmask = BIT(11), | |
827 | .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ | |
828 | }; | |
829 | ||
830 | static const unsigned usb1_utmi_drvbus_pins[] = { 59 }; | |
831 | ||
832 | static const struct sirfsoc_muxmask pulse_count_muxmask[] = { | |
833 | { | |
834 | .group = 0, | |
835 | .mask = BIT(9) | BIT(10) | BIT(11), | |
836 | }, | |
837 | }; | |
838 | ||
839 | static const struct sirfsoc_padmux pulse_count_padmux = { | |
840 | .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask), | |
841 | .muxmask = pulse_count_muxmask, | |
842 | }; | |
843 | ||
844 | static const unsigned pulse_count_pins[] = { 9, 10, 11 }; | |
845 | ||
846 | #define SIRFSOC_PIN_GROUP(n, p) \ | |
847 | { \ | |
848 | .name = n, \ | |
849 | .pins = p, \ | |
850 | .num_pins = ARRAY_SIZE(p), \ | |
851 | } | |
852 | ||
853 | static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { | |
854 | SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), | |
855 | SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), | |
856 | SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), | |
857 | SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), | |
858 | SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), | |
859 | SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), | |
860 | SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), | |
861 | SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), | |
862 | SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), | |
863 | SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), | |
864 | SIRFSOC_PIN_GROUP("usp2grp", usp2_pins), | |
865 | SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), | |
866 | SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), | |
867 | SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), | |
868 | SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins), | |
869 | SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins), | |
870 | SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins), | |
871 | SIRFSOC_PIN_GROUP("vipgrp", vip_pins), | |
872 | SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins), | |
873 | SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), | |
874 | SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins), | |
875 | SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins), | |
876 | SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), | |
877 | SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), | |
878 | SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), | |
879 | SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins), | |
880 | SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins), | |
881 | SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), | |
882 | SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins), | |
883 | SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), | |
884 | SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), | |
885 | SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), | |
886 | SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), | |
887 | SIRFSOC_PIN_GROUP("nandgrp", nand_pins), | |
888 | SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), | |
889 | SIRFSOC_PIN_GROUP("spi1grp", spi1_pins), | |
890 | SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), | |
891 | }; | |
892 | ||
d1e90e9e | 893 | static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) |
393daa81 | 894 | { |
d1e90e9e | 895 | return ARRAY_SIZE(sirfsoc_pin_groups); |
393daa81 RY |
896 | } |
897 | ||
898 | static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, | |
899 | unsigned selector) | |
900 | { | |
393daa81 RY |
901 | return sirfsoc_pin_groups[selector].name; |
902 | } | |
903 | ||
904 | static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
a5818a8b | 905 | const unsigned **pins, |
ad7761ab | 906 | unsigned *num_pins) |
393daa81 | 907 | { |
a5818a8b | 908 | *pins = sirfsoc_pin_groups[selector].pins; |
393daa81 RY |
909 | *num_pins = sirfsoc_pin_groups[selector].num_pins; |
910 | return 0; | |
911 | } | |
912 | ||
913 | static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
914 | unsigned offset) | |
915 | { | |
916 | seq_printf(s, " " DRIVER_NAME); | |
917 | } | |
918 | ||
919 | static struct pinctrl_ops sirfsoc_pctrl_ops = { | |
d1e90e9e | 920 | .get_groups_count = sirfsoc_get_groups_count, |
393daa81 RY |
921 | .get_group_name = sirfsoc_get_group_name, |
922 | .get_group_pins = sirfsoc_get_group_pins, | |
923 | .pin_dbg_show = sirfsoc_pin_dbg_show, | |
924 | }; | |
925 | ||
926 | struct sirfsoc_pmx_func { | |
927 | const char *name; | |
928 | const char * const *groups; | |
929 | const unsigned num_groups; | |
930 | const struct sirfsoc_padmux *padmux; | |
931 | }; | |
932 | ||
933 | static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; | |
934 | static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; | |
935 | static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; | |
936 | static const char * const lcdromgrp[] = { "lcdromgrp" }; | |
937 | static const char * const uart0grp[] = { "uart0grp" }; | |
938 | static const char * const uart1grp[] = { "uart1grp" }; | |
939 | static const char * const uart2grp[] = { "uart2grp" }; | |
940 | static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; | |
941 | static const char * const usp0grp[] = { "usp0grp" }; | |
942 | static const char * const usp1grp[] = { "usp1grp" }; | |
943 | static const char * const usp2grp[] = { "usp2grp" }; | |
944 | static const char * const i2c0grp[] = { "i2c0grp" }; | |
945 | static const char * const i2c1grp[] = { "i2c1grp" }; | |
946 | static const char * const pwm0grp[] = { "pwm0grp" }; | |
947 | static const char * const pwm1grp[] = { "pwm1grp" }; | |
948 | static const char * const pwm2grp[] = { "pwm2grp" }; | |
949 | static const char * const pwm3grp[] = { "pwm3grp" }; | |
950 | static const char * const vipgrp[] = { "vipgrp" }; | |
951 | static const char * const vipromgrp[] = { "vipromgrp" }; | |
952 | static const char * const warm_rstgrp[] = { "warm_rstgrp" }; | |
953 | static const char * const cko0grp[] = { "cko0grp" }; | |
954 | static const char * const cko1grp[] = { "cko1grp" }; | |
955 | static const char * const sdmmc0grp[] = { "sdmmc0grp" }; | |
956 | static const char * const sdmmc1grp[] = { "sdmmc1grp" }; | |
957 | static const char * const sdmmc2grp[] = { "sdmmc2grp" }; | |
958 | static const char * const sdmmc3grp[] = { "sdmmc3grp" }; | |
959 | static const char * const sdmmc4grp[] = { "sdmmc4grp" }; | |
960 | static const char * const sdmmc5grp[] = { "sdmmc5grp" }; | |
961 | static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; | |
962 | static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; | |
963 | static const char * const pulse_countgrp[] = { "pulse_countgrp" }; | |
964 | static const char * const i2sgrp[] = { "i2sgrp" }; | |
965 | static const char * const ac97grp[] = { "ac97grp" }; | |
966 | static const char * const nandgrp[] = { "nandgrp" }; | |
967 | static const char * const spi0grp[] = { "spi0grp" }; | |
968 | static const char * const spi1grp[] = { "spi1grp" }; | |
969 | static const char * const gpsgrp[] = { "gpsgrp" }; | |
970 | ||
971 | #define SIRFSOC_PMX_FUNCTION(n, g, m) \ | |
972 | { \ | |
973 | .name = n, \ | |
974 | .groups = g, \ | |
975 | .num_groups = ARRAY_SIZE(g), \ | |
976 | .padmux = &m, \ | |
977 | } | |
978 | ||
979 | static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { | |
980 | SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), | |
981 | SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), | |
982 | SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), | |
983 | SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), | |
984 | SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), | |
985 | SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), | |
986 | SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), | |
987 | SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), | |
988 | SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), | |
989 | SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), | |
990 | SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux), | |
991 | SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), | |
992 | SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), | |
993 | SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), | |
994 | SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux), | |
995 | SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux), | |
996 | SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux), | |
997 | SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux), | |
998 | SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux), | |
999 | SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux), | |
1000 | SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux), | |
1001 | SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux), | |
1002 | SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux), | |
1003 | SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux), | |
1004 | SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), | |
1005 | SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), | |
1006 | SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux), | |
1007 | SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), | |
1008 | SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), | |
1009 | SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), | |
1010 | SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), | |
1011 | SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), | |
1012 | SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), | |
1013 | SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), | |
1014 | SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), | |
1015 | SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux), | |
1016 | SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), | |
1017 | }; | |
1018 | ||
1019 | static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, | |
1020 | bool enable) | |
1021 | { | |
1022 | int i; | |
1023 | const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; | |
1024 | const struct sirfsoc_muxmask *mask = mux->muxmask; | |
1025 | ||
1026 | for (i = 0; i < mux->muxmask_counts; i++) { | |
1027 | u32 muxval; | |
1028 | muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
1029 | if (enable) | |
1030 | muxval = muxval & ~mask[i].mask; | |
1031 | else | |
1032 | muxval = muxval | mask[i].mask; | |
1033 | writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
1034 | } | |
1035 | ||
1036 | if (mux->funcmask && enable) { | |
1037 | u32 func_en_val; | |
1038 | func_en_val = | |
1039 | readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); | |
1040 | func_en_val = | |
1041 | (func_en_val & ~mux->funcmask) | (mux-> | |
1042 | funcval); | |
1043 | writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); | |
1044 | } | |
1045 | } | |
1046 | ||
1047 | static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, | |
1048 | unsigned group) | |
1049 | { | |
1050 | struct sirfsoc_pmx *spmx; | |
1051 | ||
1052 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
1053 | sirfsoc_pinmux_endisable(spmx, selector, true); | |
1054 | ||
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector, | |
1059 | unsigned group) | |
1060 | { | |
1061 | struct sirfsoc_pmx *spmx; | |
1062 | ||
1063 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
1064 | sirfsoc_pinmux_endisable(spmx, selector, false); | |
1065 | } | |
1066 | ||
d1e90e9e | 1067 | static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) |
393daa81 | 1068 | { |
d1e90e9e | 1069 | return ARRAY_SIZE(sirfsoc_pmx_functions); |
393daa81 RY |
1070 | } |
1071 | ||
1072 | static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, | |
1073 | unsigned selector) | |
1074 | { | |
1075 | return sirfsoc_pmx_functions[selector].name; | |
1076 | } | |
1077 | ||
1078 | static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
1079 | const char * const **groups, | |
1080 | unsigned * const num_groups) | |
1081 | { | |
1082 | *groups = sirfsoc_pmx_functions[selector].groups; | |
1083 | *num_groups = sirfsoc_pmx_functions[selector].num_groups; | |
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, | |
1088 | struct pinctrl_gpio_range *range, unsigned offset) | |
1089 | { | |
1090 | struct sirfsoc_pmx *spmx; | |
1091 | ||
1092 | int group = range->id; | |
1093 | ||
1094 | u32 muxval; | |
1095 | ||
1096 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
1097 | ||
1098 | muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); | |
3c739ad0 | 1099 | muxval = muxval | (1 << (offset - range->pin_base)); |
393daa81 RY |
1100 | writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); |
1101 | ||
1102 | return 0; | |
1103 | } | |
1104 | ||
1105 | static struct pinmux_ops sirfsoc_pinmux_ops = { | |
393daa81 RY |
1106 | .enable = sirfsoc_pinmux_enable, |
1107 | .disable = sirfsoc_pinmux_disable, | |
d1e90e9e | 1108 | .get_functions_count = sirfsoc_pinmux_get_funcs_count, |
393daa81 RY |
1109 | .get_function_name = sirfsoc_pinmux_get_func_name, |
1110 | .get_function_groups = sirfsoc_pinmux_get_groups, | |
1111 | .gpio_request_enable = sirfsoc_pinmux_request_gpio, | |
1112 | }; | |
1113 | ||
1114 | static struct pinctrl_desc sirfsoc_pinmux_desc = { | |
1115 | .name = DRIVER_NAME, | |
1116 | .pins = sirfsoc_pads, | |
1117 | .npins = ARRAY_SIZE(sirfsoc_pads), | |
393daa81 RY |
1118 | .pctlops = &sirfsoc_pctrl_ops, |
1119 | .pmxops = &sirfsoc_pinmux_ops, | |
1120 | .owner = THIS_MODULE, | |
1121 | }; | |
1122 | ||
1123 | /* | |
1124 | * Todo: bind irq_chip to every pinctrl_gpio_range | |
1125 | */ | |
1126 | static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = { | |
1127 | { | |
1128 | .name = "sirfsoc-gpio*", | |
1129 | .id = 0, | |
1130 | .base = 0, | |
3c739ad0 | 1131 | .pin_base = 0, |
393daa81 RY |
1132 | .npins = 32, |
1133 | }, { | |
1134 | .name = "sirfsoc-gpio*", | |
1135 | .id = 1, | |
1136 | .base = 32, | |
3c739ad0 | 1137 | .pin_base = 32, |
393daa81 RY |
1138 | .npins = 32, |
1139 | }, { | |
1140 | .name = "sirfsoc-gpio*", | |
1141 | .id = 2, | |
1142 | .base = 64, | |
3c739ad0 | 1143 | .pin_base = 64, |
393daa81 RY |
1144 | .npins = 32, |
1145 | }, { | |
1146 | .name = "sirfsoc-gpio*", | |
1147 | .id = 3, | |
1148 | .base = 96, | |
3c739ad0 | 1149 | .pin_base = 96, |
393daa81 RY |
1150 | .npins = 19, |
1151 | }, | |
1152 | }; | |
1153 | ||
1154 | static void __iomem *sirfsoc_rsc_of_iomap(void) | |
1155 | { | |
1156 | const struct of_device_id rsc_ids[] = { | |
1157 | { .compatible = "sirf,prima2-rsc" }, | |
1158 | {} | |
1159 | }; | |
1160 | struct device_node *np; | |
1161 | ||
1162 | np = of_find_matching_node(NULL, rsc_ids); | |
1163 | if (!np) | |
1164 | panic("unable to find compatible rsc node in dtb\n"); | |
1165 | ||
1166 | return of_iomap(np, 0); | |
1167 | } | |
1168 | ||
1169 | static int __devinit sirfsoc_pinmux_probe(struct platform_device *pdev) | |
1170 | { | |
1171 | int ret; | |
1172 | struct sirfsoc_pmx *spmx; | |
1173 | struct device_node *np = pdev->dev.of_node; | |
1174 | int i; | |
1175 | ||
1176 | /* Create state holders etc for this driver */ | |
1177 | spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); | |
1178 | if (!spmx) | |
1179 | return -ENOMEM; | |
1180 | ||
1181 | spmx->dev = &pdev->dev; | |
1182 | ||
1183 | platform_set_drvdata(pdev, spmx); | |
1184 | ||
1185 | spmx->gpio_virtbase = of_iomap(np, 0); | |
1186 | if (!spmx->gpio_virtbase) { | |
1187 | ret = -ENOMEM; | |
1188 | dev_err(&pdev->dev, "can't map gpio registers\n"); | |
1189 | goto out_no_gpio_remap; | |
1190 | } | |
1191 | ||
1192 | spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); | |
1193 | if (!spmx->rsc_virtbase) { | |
1194 | ret = -ENOMEM; | |
1195 | dev_err(&pdev->dev, "can't map rsc registers\n"); | |
1196 | goto out_no_rsc_remap; | |
1197 | } | |
1198 | ||
1199 | /* Now register the pin controller and all pins it handles */ | |
1200 | spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); | |
1201 | if (!spmx->pmx) { | |
1202 | dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); | |
1203 | ret = -EINVAL; | |
1204 | goto out_no_pmx; | |
1205 | } | |
1206 | ||
1207 | for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) | |
1208 | pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]); | |
1209 | ||
1210 | dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); | |
1211 | ||
1212 | return 0; | |
1213 | ||
1214 | out_no_pmx: | |
1215 | iounmap(spmx->rsc_virtbase); | |
1216 | out_no_rsc_remap: | |
1217 | iounmap(spmx->gpio_virtbase); | |
1218 | out_no_gpio_remap: | |
1219 | platform_set_drvdata(pdev, NULL); | |
1220 | devm_kfree(&pdev->dev, spmx); | |
1221 | return ret; | |
1222 | } | |
1223 | ||
1253585d | 1224 | static const struct of_device_id pinmux_ids[] __devinitconst = { |
393daa81 RY |
1225 | { .compatible = "sirf,prima2-gpio-pinmux" }, |
1226 | {} | |
1227 | }; | |
1228 | ||
1229 | static struct platform_driver sirfsoc_pinmux_driver = { | |
1230 | .driver = { | |
1231 | .name = DRIVER_NAME, | |
1232 | .owner = THIS_MODULE, | |
1233 | .of_match_table = pinmux_ids, | |
1234 | }, | |
1235 | .probe = sirfsoc_pinmux_probe, | |
1236 | }; | |
1237 | ||
1238 | static int __init sirfsoc_pinmux_init(void) | |
1239 | { | |
1240 | return platform_driver_register(&sirfsoc_pinmux_driver); | |
1241 | } | |
1242 | arch_initcall(sirfsoc_pinmux_init); | |
1243 | ||
51302162 BS |
1244 | static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
1245 | { | |
1246 | struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), | |
1247 | struct sirfsoc_gpio_bank, chip); | |
1248 | ||
1249 | return irq_find_mapping(bank->domain, offset); | |
1250 | } | |
1251 | ||
1252 | static inline int sirfsoc_gpio_to_offset(unsigned int gpio) | |
1253 | { | |
1254 | return gpio % SIRFSOC_GPIO_BANK_SIZE; | |
1255 | } | |
1256 | ||
1257 | static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio) | |
1258 | { | |
1259 | return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE]; | |
1260 | } | |
1261 | ||
1262 | void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode) | |
1263 | { | |
1264 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio); | |
1265 | int idx = sirfsoc_gpio_to_offset(gpio); | |
1266 | u32 val, offset; | |
1267 | unsigned long flags; | |
1268 | ||
1269 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1270 | ||
1271 | spin_lock_irqsave(&sgpio_lock, flags); | |
1272 | ||
1273 | val = readl(bank->chip.regs + offset); | |
1274 | ||
1275 | switch (mode) { | |
1276 | case SIRFSOC_GPIO_PULL_NONE: | |
1277 | val &= ~SIRFSOC_GPIO_CTL_PULL_MASK; | |
1278 | break; | |
1279 | case SIRFSOC_GPIO_PULL_UP: | |
1280 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; | |
1281 | val |= SIRFSOC_GPIO_CTL_PULL_HIGH; | |
1282 | break; | |
1283 | case SIRFSOC_GPIO_PULL_DOWN: | |
1284 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; | |
1285 | val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; | |
1286 | break; | |
1287 | default: | |
1288 | break; | |
1289 | } | |
1290 | ||
1291 | writel(val, bank->chip.regs + offset); | |
1292 | ||
1293 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1294 | } | |
1295 | EXPORT_SYMBOL(sirfsoc_gpio_set_pull); | |
1296 | ||
1297 | static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip) | |
1298 | { | |
1299 | return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip); | |
1300 | } | |
1301 | ||
1302 | static void sirfsoc_gpio_irq_ack(struct irq_data *d) | |
1303 | { | |
1304 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1305 | int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; | |
1306 | u32 val, offset; | |
1307 | unsigned long flags; | |
1308 | ||
1309 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1310 | ||
1311 | spin_lock_irqsave(&sgpio_lock, flags); | |
1312 | ||
1313 | val = readl(bank->chip.regs + offset); | |
1314 | ||
1315 | writel(val, bank->chip.regs + offset); | |
1316 | ||
1317 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1318 | } | |
1319 | ||
1320 | static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx) | |
1321 | { | |
1322 | u32 val, offset; | |
1323 | unsigned long flags; | |
1324 | ||
1325 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1326 | ||
1327 | spin_lock_irqsave(&sgpio_lock, flags); | |
1328 | ||
1329 | val = readl(bank->chip.regs + offset); | |
1330 | val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
1331 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
1332 | writel(val, bank->chip.regs + offset); | |
1333 | ||
1334 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1335 | } | |
1336 | ||
1337 | static void sirfsoc_gpio_irq_mask(struct irq_data *d) | |
1338 | { | |
1339 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1340 | ||
1341 | __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); | |
1342 | } | |
1343 | ||
1344 | static void sirfsoc_gpio_irq_unmask(struct irq_data *d) | |
1345 | { | |
1346 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1347 | int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; | |
1348 | u32 val, offset; | |
1349 | unsigned long flags; | |
1350 | ||
1351 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1352 | ||
1353 | spin_lock_irqsave(&sgpio_lock, flags); | |
1354 | ||
1355 | val = readl(bank->chip.regs + offset); | |
1356 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
1357 | val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
1358 | writel(val, bank->chip.regs + offset); | |
1359 | ||
1360 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1361 | } | |
1362 | ||
1363 | static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) | |
1364 | { | |
1365 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1366 | int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; | |
1367 | u32 val, offset; | |
1368 | unsigned long flags; | |
1369 | ||
1370 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1371 | ||
1372 | spin_lock_irqsave(&sgpio_lock, flags); | |
1373 | ||
1374 | val = readl(bank->chip.regs + offset); | |
1375 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
1376 | ||
1377 | switch (type) { | |
1378 | case IRQ_TYPE_NONE: | |
1379 | break; | |
1380 | case IRQ_TYPE_EDGE_RISING: | |
1381 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
1382 | val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; | |
1383 | break; | |
1384 | case IRQ_TYPE_EDGE_FALLING: | |
1385 | val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
1386 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
1387 | break; | |
1388 | case IRQ_TYPE_EDGE_BOTH: | |
1389 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | | |
1390 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
1391 | break; | |
1392 | case IRQ_TYPE_LEVEL_LOW: | |
1393 | val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
1394 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; | |
1395 | break; | |
1396 | case IRQ_TYPE_LEVEL_HIGH: | |
1397 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
1398 | val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
1399 | break; | |
1400 | } | |
1401 | ||
1402 | writel(val, bank->chip.regs + offset); | |
1403 | ||
1404 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | static struct irq_chip sirfsoc_irq_chip = { | |
1410 | .name = "sirf-gpio-irq", | |
1411 | .irq_ack = sirfsoc_gpio_irq_ack, | |
1412 | .irq_mask = sirfsoc_gpio_irq_mask, | |
1413 | .irq_unmask = sirfsoc_gpio_irq_unmask, | |
1414 | .irq_set_type = sirfsoc_gpio_irq_type, | |
1415 | }; | |
1416 | ||
1417 | static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) | |
1418 | { | |
1419 | struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq); | |
1420 | u32 status, ctrl; | |
1421 | int idx = 0; | |
1422 | unsigned int first_irq; | |
1423 | ||
1424 | status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); | |
1425 | if (!status) { | |
1426 | printk(KERN_WARNING | |
1427 | "%s: gpio id %d status %#x no interrupt is flaged\n", | |
1428 | __func__, bank->id, status); | |
1429 | handle_bad_irq(irq, desc); | |
1430 | return; | |
1431 | } | |
1432 | ||
1433 | first_irq = bank->domain->revmap_data.legacy.first_irq; | |
1434 | ||
1435 | while (status) { | |
1436 | ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); | |
1437 | ||
1438 | /* | |
1439 | * Here we must check whether the corresponding GPIO's interrupt | |
1440 | * has been enabled, otherwise just skip it | |
1441 | */ | |
1442 | if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { | |
1443 | pr_debug("%s: gpio id %d idx %d happens\n", | |
1444 | __func__, bank->id, idx); | |
1445 | generic_handle_irq(first_irq + idx); | |
1446 | } | |
1447 | ||
1448 | idx++; | |
1449 | status = status >> 1; | |
1450 | } | |
1451 | } | |
1452 | ||
1453 | static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset) | |
1454 | { | |
1455 | u32 val; | |
1456 | unsigned long flags; | |
1457 | ||
1458 | spin_lock_irqsave(&bank->lock, flags); | |
1459 | ||
1460 | val = readl(bank->chip.regs + ctrl_offset); | |
1461 | val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; | |
1462 | writel(val, bank->chip.regs + ctrl_offset); | |
1463 | ||
1464 | spin_unlock_irqrestore(&bank->lock, flags); | |
1465 | } | |
1466 | ||
1467 | static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) | |
1468 | { | |
1469 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1470 | unsigned long flags; | |
1471 | ||
1472 | if (pinctrl_request_gpio(chip->base + offset)) | |
1473 | return -ENODEV; | |
1474 | ||
1475 | spin_lock_irqsave(&bank->lock, flags); | |
1476 | ||
1477 | /* | |
1478 | * default status: | |
1479 | * set direction as input and mask irq | |
1480 | */ | |
1481 | sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1482 | __sirfsoc_gpio_irq_mask(bank, offset); | |
1483 | ||
1484 | spin_unlock_irqrestore(&bank->lock, flags); | |
1485 | ||
1486 | return 0; | |
1487 | } | |
1488 | ||
1489 | static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1490 | { | |
1491 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1492 | unsigned long flags; | |
1493 | ||
1494 | spin_lock_irqsave(&bank->lock, flags); | |
1495 | ||
1496 | __sirfsoc_gpio_irq_mask(bank, offset); | |
1497 | sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1498 | ||
1499 | spin_unlock_irqrestore(&bank->lock, flags); | |
1500 | ||
1501 | pinctrl_free_gpio(chip->base + offset); | |
1502 | } | |
1503 | ||
1504 | static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
1505 | { | |
1506 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1507 | int idx = sirfsoc_gpio_to_offset(gpio); | |
1508 | unsigned long flags; | |
1509 | unsigned offset; | |
1510 | ||
1511 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1512 | ||
1513 | spin_lock_irqsave(&bank->lock, flags); | |
1514 | ||
1515 | sirfsoc_gpio_set_input(bank, offset); | |
1516 | ||
1517 | spin_unlock_irqrestore(&bank->lock, flags); | |
1518 | ||
1519 | return 0; | |
1520 | } | |
1521 | ||
1522 | static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset, | |
1523 | int value) | |
1524 | { | |
1525 | u32 out_ctrl; | |
1526 | unsigned long flags; | |
1527 | ||
1528 | spin_lock_irqsave(&bank->lock, flags); | |
1529 | ||
1530 | out_ctrl = readl(bank->chip.regs + offset); | |
1531 | if (value) | |
1532 | out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
1533 | else | |
1534 | out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
1535 | ||
1536 | out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
1537 | out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; | |
1538 | writel(out_ctrl, bank->chip.regs + offset); | |
1539 | ||
1540 | spin_unlock_irqrestore(&bank->lock, flags); | |
1541 | } | |
1542 | ||
1543 | static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) | |
1544 | { | |
1545 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1546 | int idx = sirfsoc_gpio_to_offset(gpio); | |
1547 | u32 offset; | |
1548 | unsigned long flags; | |
1549 | ||
1550 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1551 | ||
1552 | spin_lock_irqsave(&sgpio_lock, flags); | |
1553 | ||
1554 | sirfsoc_gpio_set_output(bank, offset, value); | |
1555 | ||
1556 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
1561 | static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) | |
1562 | { | |
1563 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1564 | u32 val; | |
1565 | unsigned long flags; | |
1566 | ||
1567 | spin_lock_irqsave(&bank->lock, flags); | |
1568 | ||
1569 | val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1570 | ||
1571 | spin_unlock_irqrestore(&bank->lock, flags); | |
1572 | ||
1573 | return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); | |
1574 | } | |
1575 | ||
1576 | static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, | |
1577 | int value) | |
1578 | { | |
1579 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1580 | u32 ctrl; | |
1581 | unsigned long flags; | |
1582 | ||
1583 | spin_lock_irqsave(&bank->lock, flags); | |
1584 | ||
1585 | ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1586 | if (value) | |
1587 | ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
1588 | else | |
1589 | ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
1590 | writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1591 | ||
1592 | spin_unlock_irqrestore(&bank->lock, flags); | |
1593 | } | |
1594 | ||
1595 | int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
1596 | irq_hw_number_t hwirq) | |
1597 | { | |
1598 | struct sirfsoc_gpio_bank *bank = d->host_data; | |
1599 | ||
1600 | if (!bank) | |
1601 | return -EINVAL; | |
1602 | ||
1603 | irq_set_chip(irq, &sirfsoc_irq_chip); | |
1604 | irq_set_handler(irq, handle_level_irq); | |
1605 | irq_set_chip_data(irq, bank); | |
1606 | set_irq_flags(irq, IRQF_VALID); | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = { | |
1612 | .map = sirfsoc_gpio_irq_map, | |
1613 | .xlate = irq_domain_xlate_twocell, | |
1614 | }; | |
1615 | ||
1616 | static int __devinit sirfsoc_gpio_probe(struct device_node *np) | |
1617 | { | |
1618 | int i, err = 0; | |
1619 | struct sirfsoc_gpio_bank *bank; | |
1620 | void *regs; | |
1621 | struct platform_device *pdev; | |
1622 | ||
1623 | pdev = of_find_device_by_node(np); | |
1624 | if (!pdev) | |
1625 | return -ENODEV; | |
1626 | ||
1627 | regs = of_iomap(np, 0); | |
1628 | if (!regs) | |
1629 | return -ENOMEM; | |
1630 | ||
1631 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
1632 | bank = &sgpio_bank[i]; | |
1633 | spin_lock_init(&bank->lock); | |
1634 | bank->chip.gc.request = sirfsoc_gpio_request; | |
1635 | bank->chip.gc.free = sirfsoc_gpio_free; | |
1636 | bank->chip.gc.direction_input = sirfsoc_gpio_direction_input; | |
1637 | bank->chip.gc.get = sirfsoc_gpio_get_value; | |
1638 | bank->chip.gc.direction_output = sirfsoc_gpio_direction_output; | |
1639 | bank->chip.gc.set = sirfsoc_gpio_set_value; | |
1640 | bank->chip.gc.to_irq = sirfsoc_gpio_to_irq; | |
1641 | bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE; | |
1642 | bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE; | |
1643 | bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); | |
1644 | bank->chip.gc.of_node = np; | |
1645 | bank->chip.regs = regs; | |
1646 | bank->id = i; | |
1647 | bank->parent_irq = platform_get_irq(pdev, i); | |
1648 | if (bank->parent_irq < 0) { | |
1649 | err = bank->parent_irq; | |
1650 | goto out; | |
1651 | } | |
1652 | ||
1653 | err = gpiochip_add(&bank->chip.gc); | |
1654 | if (err) { | |
1655 | pr_err("%s: error in probe function with status %d\n", | |
1656 | np->full_name, err); | |
1657 | goto out; | |
1658 | } | |
1659 | ||
1660 | bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE, | |
1661 | SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0, | |
1662 | &sirfsoc_gpio_irq_simple_ops, bank); | |
1663 | ||
1664 | if (!bank->domain) { | |
1665 | pr_err("%s: Failed to create irqdomain\n", np->full_name); | |
1666 | err = -ENOSYS; | |
1667 | goto out; | |
1668 | } | |
1669 | ||
1670 | irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq); | |
1671 | irq_set_handler_data(bank->parent_irq, bank); | |
1672 | } | |
1673 | ||
1674 | out: | |
1675 | iounmap(regs); | |
1676 | return err; | |
1677 | } | |
1678 | ||
1679 | static int __init sirfsoc_gpio_init(void) | |
1680 | { | |
1681 | ||
1682 | struct device_node *np; | |
1683 | ||
1684 | np = of_find_matching_node(NULL, pinmux_ids); | |
1685 | ||
1686 | if (!np) | |
1687 | return -ENODEV; | |
1688 | ||
1689 | return sirfsoc_gpio_probe(np); | |
1690 | } | |
1691 | subsys_initcall(sirfsoc_gpio_init); | |
1692 | ||
393daa81 | 1693 | MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " |
51302162 | 1694 | "Yuping Luo <yuping.luo@csr.com>, " |
393daa81 RY |
1695 | "Barry Song <baohua.song@csr.com>"); |
1696 | MODULE_DESCRIPTION("SIRFSOC pin control driver"); | |
1697 | MODULE_LICENSE("GPL"); |