Commit | Line | Data |
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8b8b091b TL |
1 | /* |
2 | * Generic device tree based pinctrl driver for one register per pin | |
3 | * type pinmux controllers | |
4 | * | |
5 | * Copyright (C) 2012 Texas Instruments, Inc. | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/io.h> | |
060f03e9 | 15 | #include <linux/platform_device.h> |
8b8b091b TL |
16 | #include <linux/slab.h> |
17 | #include <linux/err.h> | |
18 | #include <linux/list.h> | |
3e6cee17 | 19 | #include <linux/interrupt.h> |
3e6cee17 | 20 | #include <linux/irqchip/chained_irq.h> |
8b8b091b | 21 | #include <linux/of.h> |
3e6cee17 | 22 | #include <linux/of_irq.h> |
486e0d87 | 23 | #include <linux/seq_file.h> |
8b8b091b | 24 | |
486e0d87 AS |
25 | #include <linux/pinctrl/pinconf-generic.h> |
26 | #include <linux/pinctrl/pinconf.h> | |
8b8b091b TL |
27 | #include <linux/pinctrl/pinctrl.h> |
28 | #include <linux/pinctrl/pinmux.h> | |
29 | ||
dc7743aa TL |
30 | #include <linux/platform_data/pinctrl-single.h> |
31 | ||
8b8b091b | 32 | #include "core.h" |
4622215f | 33 | #include "devicetree.h" |
9dddb4df | 34 | #include "pinconf.h" |
571aec4d | 35 | #include "pinmux.h" |
8b8b091b TL |
36 | |
37 | #define DRIVER_NAME "pinctrl-single" | |
8b8b091b TL |
38 | #define PCS_OFF_DISABLED ~0U |
39 | ||
8b8b091b TL |
40 | /** |
41 | * struct pcs_func_vals - mux function register offset and value pair | |
42 | * @reg: register virtual address | |
43 | * @val: register value | |
0ba5ab00 | 44 | * @mask: mask |
8b8b091b TL |
45 | */ |
46 | struct pcs_func_vals { | |
47 | void __iomem *reg; | |
48 | unsigned val; | |
9e605cb6 | 49 | unsigned mask; |
8b8b091b TL |
50 | }; |
51 | ||
9dddb4df HZ |
52 | /** |
53 | * struct pcs_conf_vals - pinconf parameter, pinconf register offset | |
54 | * and value, enable, disable, mask | |
55 | * @param: config parameter | |
56 | * @val: user input bits in the pinconf register | |
57 | * @enable: enable bits in the pinconf register | |
58 | * @disable: disable bits in the pinconf register | |
59 | * @mask: mask bits in the register value | |
60 | */ | |
61 | struct pcs_conf_vals { | |
62 | enum pin_config_param param; | |
63 | unsigned val; | |
64 | unsigned enable; | |
65 | unsigned disable; | |
66 | unsigned mask; | |
67 | }; | |
68 | ||
69 | /** | |
70 | * struct pcs_conf_type - pinconf property name, pinconf param pair | |
71 | * @name: property name in DTS file | |
72 | * @param: config parameter | |
73 | */ | |
74 | struct pcs_conf_type { | |
75 | const char *name; | |
76 | enum pin_config_param param; | |
77 | }; | |
78 | ||
8b8b091b TL |
79 | /** |
80 | * struct pcs_function - pinctrl function | |
81 | * @name: pinctrl function name | |
82 | * @vals: register and vals array | |
83 | * @nvals: number of entries in vals array | |
0ba5ab00 LJ |
84 | * @conf: array of pin configurations |
85 | * @nconfs: number of pin configurations available | |
8b8b091b TL |
86 | * @node: list node |
87 | */ | |
88 | struct pcs_function { | |
89 | const char *name; | |
90 | struct pcs_func_vals *vals; | |
91 | unsigned nvals; | |
9dddb4df HZ |
92 | struct pcs_conf_vals *conf; |
93 | int nconfs; | |
8b8b091b TL |
94 | struct list_head node; |
95 | }; | |
96 | ||
a1a277eb HZ |
97 | /** |
98 | * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function | |
99 | * @offset: offset base of pins | |
100 | * @npins: number pins with the same mux value of gpio function | |
101 | * @gpiofunc: mux value of gpio function | |
102 | * @node: list node | |
103 | */ | |
104 | struct pcs_gpiofunc_range { | |
105 | unsigned offset; | |
106 | unsigned npins; | |
107 | unsigned gpiofunc; | |
108 | struct list_head node; | |
109 | }; | |
110 | ||
8b8b091b TL |
111 | /** |
112 | * struct pcs_data - wrapper for data needed by pinctrl framework | |
113 | * @pa: pindesc array | |
114 | * @cur: index to current element | |
115 | * | |
116 | * REVISIT: We should be able to drop this eventually by adding | |
117 | * support for registering pins individually in the pinctrl | |
118 | * framework for those drivers that don't need a static array. | |
119 | */ | |
120 | struct pcs_data { | |
121 | struct pinctrl_pin_desc *pa; | |
122 | int cur; | |
123 | }; | |
124 | ||
02e483f6 TL |
125 | /** |
126 | * struct pcs_soc_data - SoC specific settings | |
127 | * @flags: initial SoC specific PCS_FEAT_xxx values | |
3e6cee17 TL |
128 | * @irq: optional interrupt for the controller |
129 | * @irq_enable_mask: optional SoC specific interrupt enable mask | |
130 | * @irq_status_mask: optional SoC specific interrupt status mask | |
dc7743aa | 131 | * @rearm: optional SoC specific wake-up rearm function |
02e483f6 TL |
132 | */ |
133 | struct pcs_soc_data { | |
134 | unsigned flags; | |
3e6cee17 TL |
135 | int irq; |
136 | unsigned irq_enable_mask; | |
137 | unsigned irq_status_mask; | |
dc7743aa | 138 | void (*rearm)(void); |
02e483f6 TL |
139 | }; |
140 | ||
8b8b091b TL |
141 | /** |
142 | * struct pcs_device - pinctrl device instance | |
143 | * @res: resources | |
144 | * @base: virtual address of the controller | |
88a1dbde | 145 | * @saved_vals: saved values for the controller |
8b8b091b TL |
146 | * @size: size of the ioremapped area |
147 | * @dev: device entry | |
4622215f | 148 | * @np: device tree node |
8b8b091b | 149 | * @pctl: pin controller device |
02e483f6 | 150 | * @flags: mask of PCS_FEAT_xxx values |
4622215f TL |
151 | * @missing_nr_pinctrl_cells: for legacy binding, may go away |
152 | * @socdata: soc specific data | |
3e6cee17 | 153 | * @lock: spinlock for register access |
8b8b091b TL |
154 | * @mutex: mutex protecting the lists |
155 | * @width: bits per mux register | |
156 | * @fmask: function register mask | |
157 | * @fshift: function register shift | |
158 | * @foff: value to turn mux off | |
159 | * @fmax: max number of functions in fmask | |
4622215f TL |
160 | * @bits_per_mux: number of bits per mux |
161 | * @bits_per_pin: number of bits per pin | |
8b8b091b | 162 | * @pins: physical pins on the SoC |
a1a277eb | 163 | * @gpiofuncs: list of gpio functions |
3e6cee17 TL |
164 | * @irqs: list of interrupt registers |
165 | * @chip: chip container for this instance | |
166 | * @domain: IRQ domain for this instance | |
8b8b091b TL |
167 | * @desc: pin controller descriptor |
168 | * @read: register read function to use | |
169 | * @write: register write function to use | |
170 | */ | |
171 | struct pcs_device { | |
172 | struct resource *res; | |
173 | void __iomem *base; | |
88a1dbde | 174 | void *saved_vals; |
8b8b091b TL |
175 | unsigned size; |
176 | struct device *dev; | |
4622215f | 177 | struct device_node *np; |
8b8b091b | 178 | struct pinctrl_dev *pctl; |
02e483f6 | 179 | unsigned flags; |
88a1dbde | 180 | #define PCS_CONTEXT_LOSS_OFF (1 << 3) |
3e6cee17 TL |
181 | #define PCS_QUIRK_SHARED_IRQ (1 << 2) |
182 | #define PCS_FEAT_IRQ (1 << 1) | |
02e483f6 | 183 | #define PCS_FEAT_PINCONF (1 << 0) |
4622215f | 184 | struct property *missing_nr_pinctrl_cells; |
3e6cee17 TL |
185 | struct pcs_soc_data socdata; |
186 | raw_spinlock_t lock; | |
8b8b091b TL |
187 | struct mutex mutex; |
188 | unsigned width; | |
189 | unsigned fmask; | |
190 | unsigned fshift; | |
191 | unsigned foff; | |
192 | unsigned fmax; | |
9e605cb6 | 193 | bool bits_per_mux; |
4e7e8017 | 194 | unsigned bits_per_pin; |
8b8b091b | 195 | struct pcs_data pins; |
a1a277eb | 196 | struct list_head gpiofuncs; |
3e6cee17 TL |
197 | struct list_head irqs; |
198 | struct irq_chip chip; | |
199 | struct irq_domain *domain; | |
8b8b091b TL |
200 | struct pinctrl_desc desc; |
201 | unsigned (*read)(void __iomem *reg); | |
202 | void (*write)(unsigned val, void __iomem *reg); | |
203 | }; | |
204 | ||
3e6cee17 TL |
205 | #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ) |
206 | #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ) | |
02e483f6 TL |
207 | #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF) |
208 | ||
9dddb4df HZ |
209 | static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, |
210 | unsigned long *config); | |
211 | static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, | |
03b054e9 | 212 | unsigned long *configs, unsigned num_configs); |
9dddb4df HZ |
213 | |
214 | static enum pin_config_param pcs_bias[] = { | |
215 | PIN_CONFIG_BIAS_PULL_DOWN, | |
216 | PIN_CONFIG_BIAS_PULL_UP, | |
217 | }; | |
218 | ||
3c177a16 SH |
219 | /* |
220 | * This lock class tells lockdep that irqchip core that this single | |
221 | * pinctrl can be in a different category than its parents, so it won't | |
222 | * report false recursion. | |
223 | */ | |
224 | static struct lock_class_key pcs_lock_class; | |
225 | ||
39c3fd58 AL |
226 | /* Class for the IRQ request mutex */ |
227 | static struct lock_class_key pcs_request_class; | |
228 | ||
8b8b091b TL |
229 | /* |
230 | * REVISIT: Reads and writes could eventually use regmap or something | |
231 | * generic. But at least on omaps, some mux registers are performance | |
232 | * critical as they may need to be remuxed every time before and after | |
233 | * idle. Adding tests for register access width for every read and | |
234 | * write like regmap is doing is not desired, and caching the registers | |
235 | * does not help in this case. | |
236 | */ | |
237 | ||
af68c2af | 238 | static unsigned int pcs_readb(void __iomem *reg) |
8b8b091b TL |
239 | { |
240 | return readb(reg); | |
241 | } | |
242 | ||
af68c2af | 243 | static unsigned int pcs_readw(void __iomem *reg) |
8b8b091b TL |
244 | { |
245 | return readw(reg); | |
246 | } | |
247 | ||
af68c2af | 248 | static unsigned int pcs_readl(void __iomem *reg) |
8b8b091b TL |
249 | { |
250 | return readl(reg); | |
251 | } | |
252 | ||
af68c2af | 253 | static void pcs_writeb(unsigned int val, void __iomem *reg) |
8b8b091b TL |
254 | { |
255 | writeb(val, reg); | |
256 | } | |
257 | ||
af68c2af | 258 | static void pcs_writew(unsigned int val, void __iomem *reg) |
8b8b091b TL |
259 | { |
260 | writew(val, reg); | |
261 | } | |
262 | ||
af68c2af | 263 | static void pcs_writel(unsigned int val, void __iomem *reg) |
8b8b091b TL |
264 | { |
265 | writel(val, reg); | |
266 | } | |
267 | ||
bd85125e HH |
268 | static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs, |
269 | unsigned int pin) | |
270 | { | |
271 | unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; | |
272 | ||
273 | if (pcs->bits_per_mux) { | |
274 | unsigned int pin_offset_bytes; | |
275 | ||
276 | pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; | |
277 | return (pin_offset_bytes / mux_bytes) * mux_bytes; | |
278 | } | |
279 | ||
280 | return pin * mux_bytes; | |
281 | } | |
282 | ||
283 | static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs, | |
284 | unsigned int pin) | |
285 | { | |
286 | return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; | |
287 | } | |
288 | ||
8b8b091b TL |
289 | static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, |
290 | struct seq_file *s, | |
e7ed6718 | 291 | unsigned pin) |
8b8b091b | 292 | { |
7d66ce7f | 293 | struct pcs_device *pcs; |
bd85125e | 294 | unsigned int val; |
223decc4 TL |
295 | unsigned long offset; |
296 | size_t pa; | |
7d66ce7f MP |
297 | |
298 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
299 | ||
bd85125e | 300 | offset = pcs_pin_reg_offset_get(pcs, pin); |
223decc4 | 301 | val = pcs->read(pcs->base + offset); |
bd85125e HH |
302 | |
303 | if (pcs->bits_per_mux) | |
304 | val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin); | |
305 | ||
223decc4 | 306 | pa = pcs->res->start + offset; |
7d66ce7f | 307 | |
223decc4 | 308 | seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); |
8b8b091b TL |
309 | } |
310 | ||
311 | static void pcs_dt_free_map(struct pinctrl_dev *pctldev, | |
312 | struct pinctrl_map *map, unsigned num_maps) | |
313 | { | |
314 | struct pcs_device *pcs; | |
315 | ||
316 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
317 | devm_kfree(pcs->dev, map); | |
318 | } | |
319 | ||
320 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
321 | struct device_node *np_config, | |
322 | struct pinctrl_map **map, unsigned *num_maps); | |
323 | ||
022ab148 | 324 | static const struct pinctrl_ops pcs_pinctrl_ops = { |
caeb774e TL |
325 | .get_groups_count = pinctrl_generic_get_group_count, |
326 | .get_group_name = pinctrl_generic_get_group_name, | |
327 | .get_group_pins = pinctrl_generic_get_group_pins, | |
8b8b091b TL |
328 | .pin_dbg_show = pcs_pin_dbg_show, |
329 | .dt_node_to_map = pcs_dt_node_to_map, | |
330 | .dt_free_map = pcs_dt_free_map, | |
331 | }; | |
332 | ||
9dddb4df HZ |
333 | static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, |
334 | struct pcs_function **func) | |
335 | { | |
336 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); | |
337 | struct pin_desc *pdesc = pin_desc_get(pctldev, pin); | |
338 | const struct pinctrl_setting_mux *setting; | |
571aec4d | 339 | struct function_desc *function; |
9dddb4df HZ |
340 | unsigned fselector; |
341 | ||
342 | /* If pin is not described in DTS & enabled, mux_setting is NULL. */ | |
343 | setting = pdesc->mux_setting; | |
344 | if (!setting) | |
345 | return -ENOTSUPP; | |
346 | fselector = setting->func; | |
571aec4d TL |
347 | function = pinmux_generic_get_function(pctldev, fselector); |
348 | *func = function->data; | |
9dddb4df HZ |
349 | if (!(*func)) { |
350 | dev_err(pcs->dev, "%s could not find function%i\n", | |
351 | __func__, fselector); | |
352 | return -ENOTSUPP; | |
353 | } | |
354 | return 0; | |
355 | } | |
356 | ||
03e9f0ca | 357 | static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, |
8b8b091b TL |
358 | unsigned group) |
359 | { | |
360 | struct pcs_device *pcs; | |
571aec4d | 361 | struct function_desc *function; |
8b8b091b TL |
362 | struct pcs_function *func; |
363 | int i; | |
364 | ||
365 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
477ac771 HZ |
366 | /* If function mask is null, needn't enable it. */ |
367 | if (!pcs->fmask) | |
368 | return 0; | |
571aec4d | 369 | function = pinmux_generic_get_function(pctldev, fselector); |
d2d73e6d MK |
370 | if (!function) |
371 | return -EINVAL; | |
571aec4d | 372 | func = function->data; |
8b8b091b TL |
373 | if (!func) |
374 | return -EINVAL; | |
375 | ||
376 | dev_dbg(pcs->dev, "enabling %s function%i\n", | |
377 | func->name, fselector); | |
378 | ||
379 | for (i = 0; i < func->nvals; i++) { | |
380 | struct pcs_func_vals *vals; | |
3e6cee17 | 381 | unsigned long flags; |
9e605cb6 | 382 | unsigned val, mask; |
8b8b091b TL |
383 | |
384 | vals = &func->vals[i]; | |
3e6cee17 | 385 | raw_spin_lock_irqsave(&pcs->lock, flags); |
8b8b091b | 386 | val = pcs->read(vals->reg); |
4e7e8017 MP |
387 | |
388 | if (pcs->bits_per_mux) | |
389 | mask = vals->mask; | |
9e605cb6 | 390 | else |
4e7e8017 | 391 | mask = pcs->fmask; |
9e605cb6 PU |
392 | |
393 | val &= ~mask; | |
394 | val |= (vals->val & mask); | |
8b8b091b | 395 | pcs->write(val, vals->reg); |
3e6cee17 | 396 | raw_spin_unlock_irqrestore(&pcs->lock, flags); |
8b8b091b TL |
397 | } |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
8b8b091b | 402 | static int pcs_request_gpio(struct pinctrl_dev *pctldev, |
a1a277eb | 403 | struct pinctrl_gpio_range *range, unsigned pin) |
8b8b091b | 404 | { |
a1a277eb HZ |
405 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
406 | struct pcs_gpiofunc_range *frange = NULL; | |
407 | struct list_head *pos, *tmp; | |
a1a277eb HZ |
408 | unsigned data; |
409 | ||
477ac771 HZ |
410 | /* If function mask is null, return directly. */ |
411 | if (!pcs->fmask) | |
412 | return -ENOTSUPP; | |
413 | ||
a1a277eb | 414 | list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { |
bd85125e HH |
415 | u32 offset; |
416 | ||
a1a277eb HZ |
417 | frange = list_entry(pos, struct pcs_gpiofunc_range, node); |
418 | if (pin >= frange->offset + frange->npins | |
419 | || pin < frange->offset) | |
420 | continue; | |
45dcb54f | 421 | |
bd85125e | 422 | offset = pcs_pin_reg_offset_get(pcs, pin); |
45dcb54f | 423 | |
bd85125e HH |
424 | if (pcs->bits_per_mux) { |
425 | int pin_shift = pcs_pin_shift_reg_get(pcs, pin); | |
45dcb54f DL |
426 | |
427 | data = pcs->read(pcs->base + offset); | |
428 | data &= ~(pcs->fmask << pin_shift); | |
429 | data |= frange->gpiofunc << pin_shift; | |
430 | pcs->write(data, pcs->base + offset); | |
431 | } else { | |
bd85125e | 432 | data = pcs->read(pcs->base + offset); |
45dcb54f DL |
433 | data &= ~pcs->fmask; |
434 | data |= frange->gpiofunc; | |
bd85125e | 435 | pcs->write(data, pcs->base + offset); |
45dcb54f | 436 | } |
a1a277eb HZ |
437 | break; |
438 | } | |
439 | return 0; | |
8b8b091b TL |
440 | } |
441 | ||
022ab148 | 442 | static const struct pinmux_ops pcs_pinmux_ops = { |
571aec4d TL |
443 | .get_functions_count = pinmux_generic_get_function_count, |
444 | .get_function_name = pinmux_generic_get_function_name, | |
445 | .get_function_groups = pinmux_generic_get_function_groups, | |
9e3a979f | 446 | .set_mux = pcs_set_mux, |
8b8b091b TL |
447 | .gpio_request_enable = pcs_request_gpio, |
448 | }; | |
449 | ||
9dddb4df HZ |
450 | /* Clear BIAS value */ |
451 | static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) | |
452 | { | |
453 | unsigned long config; | |
454 | int i; | |
455 | for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { | |
456 | config = pinconf_to_config_packed(pcs_bias[i], 0); | |
03b054e9 | 457 | pcs_pinconf_set(pctldev, pin, &config, 1); |
9dddb4df HZ |
458 | } |
459 | } | |
460 | ||
461 | /* | |
462 | * Check whether PIN_CONFIG_BIAS_DISABLE is valid. | |
463 | * It's depend on that PULL_DOWN & PULL_UP configs are all invalid. | |
464 | */ | |
465 | static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin) | |
466 | { | |
467 | unsigned long config; | |
468 | int i; | |
469 | ||
470 | for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { | |
471 | config = pinconf_to_config_packed(pcs_bias[i], 0); | |
472 | if (!pcs_pinconf_get(pctldev, pin, &config)) | |
473 | goto out; | |
474 | } | |
475 | return true; | |
476 | out: | |
477 | return false; | |
478 | } | |
479 | ||
8b8b091b TL |
480 | static int pcs_pinconf_get(struct pinctrl_dev *pctldev, |
481 | unsigned pin, unsigned long *config) | |
482 | { | |
9dddb4df HZ |
483 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
484 | struct pcs_function *func; | |
485 | enum pin_config_param param; | |
486 | unsigned offset = 0, data = 0, i, j, ret; | |
487 | ||
488 | ret = pcs_get_function(pctldev, pin, &func); | |
489 | if (ret) | |
490 | return ret; | |
491 | ||
492 | for (i = 0; i < func->nconfs; i++) { | |
493 | param = pinconf_to_config_param(*config); | |
494 | if (param == PIN_CONFIG_BIAS_DISABLE) { | |
495 | if (pcs_pinconf_bias_disable(pctldev, pin)) { | |
496 | *config = 0; | |
497 | return 0; | |
498 | } else { | |
499 | return -ENOTSUPP; | |
500 | } | |
501 | } else if (param != func->conf[i].param) { | |
502 | continue; | |
503 | } | |
504 | ||
505 | offset = pin * (pcs->width / BITS_PER_BYTE); | |
506 | data = pcs->read(pcs->base + offset) & func->conf[i].mask; | |
507 | switch (func->conf[i].param) { | |
508 | /* 4 parameters */ | |
509 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
510 | case PIN_CONFIG_BIAS_PULL_UP: | |
511 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
512 | if ((data != func->conf[i].enable) || | |
513 | (data == func->conf[i].disable)) | |
514 | return -ENOTSUPP; | |
515 | *config = 0; | |
516 | break; | |
517 | /* 2 parameters */ | |
518 | case PIN_CONFIG_INPUT_SCHMITT: | |
519 | for (j = 0; j < func->nconfs; j++) { | |
520 | switch (func->conf[j].param) { | |
521 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
522 | if (data != func->conf[j].enable) | |
523 | return -ENOTSUPP; | |
524 | break; | |
525 | default: | |
526 | break; | |
527 | } | |
528 | } | |
529 | *config = data; | |
530 | break; | |
531 | case PIN_CONFIG_DRIVE_STRENGTH: | |
532 | case PIN_CONFIG_SLEW_RATE: | |
31f9a421 | 533 | case PIN_CONFIG_MODE_LOW_POWER: |
8c987eb1 | 534 | case PIN_CONFIG_INPUT_ENABLE: |
9dddb4df HZ |
535 | default: |
536 | *config = data; | |
537 | break; | |
538 | } | |
539 | return 0; | |
540 | } | |
8b8b091b TL |
541 | return -ENOTSUPP; |
542 | } | |
543 | ||
544 | static int pcs_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
545 | unsigned pin, unsigned long *configs, |
546 | unsigned num_configs) | |
8b8b091b | 547 | { |
9dddb4df HZ |
548 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
549 | struct pcs_function *func; | |
7cba5b3f | 550 | unsigned offset = 0, shift = 0, i, data, ret; |
58957d2e | 551 | u32 arg; |
03b054e9 | 552 | int j; |
b5fe46ef | 553 | enum pin_config_param param; |
9dddb4df HZ |
554 | |
555 | ret = pcs_get_function(pctldev, pin, &func); | |
556 | if (ret) | |
557 | return ret; | |
558 | ||
03b054e9 | 559 | for (j = 0; j < num_configs; j++) { |
b5fe46ef MK |
560 | param = pinconf_to_config_param(configs[j]); |
561 | ||
562 | /* BIAS_DISABLE has no entry in the func->conf table */ | |
563 | if (param == PIN_CONFIG_BIAS_DISABLE) { | |
564 | /* This just disables all bias entries */ | |
565 | pcs_pinconf_clear_bias(pctldev, pin); | |
566 | continue; | |
567 | } | |
568 | ||
03b054e9 | 569 | for (i = 0; i < func->nconfs; i++) { |
b5fe46ef | 570 | if (param != func->conf[i].param) |
03b054e9 SY |
571 | continue; |
572 | ||
9dddb4df HZ |
573 | offset = pin * (pcs->width / BITS_PER_BYTE); |
574 | data = pcs->read(pcs->base + offset); | |
03b054e9 | 575 | arg = pinconf_to_config_argument(configs[j]); |
b5fe46ef | 576 | switch (param) { |
9dddb4df HZ |
577 | /* 2 parameters */ |
578 | case PIN_CONFIG_INPUT_SCHMITT: | |
579 | case PIN_CONFIG_DRIVE_STRENGTH: | |
580 | case PIN_CONFIG_SLEW_RATE: | |
31f9a421 | 581 | case PIN_CONFIG_MODE_LOW_POWER: |
8c987eb1 | 582 | case PIN_CONFIG_INPUT_ENABLE: |
9dddb4df | 583 | shift = ffs(func->conf[i].mask) - 1; |
9dddb4df HZ |
584 | data &= ~func->conf[i].mask; |
585 | data |= (arg << shift) & func->conf[i].mask; | |
586 | break; | |
587 | /* 4 parameters */ | |
9dddb4df HZ |
588 | case PIN_CONFIG_BIAS_PULL_DOWN: |
589 | case PIN_CONFIG_BIAS_PULL_UP: | |
7cba5b3f | 590 | if (arg) |
9dddb4df | 591 | pcs_pinconf_clear_bias(pctldev, pin); |
c4429556 | 592 | fallthrough; |
9dddb4df HZ |
593 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
594 | data &= ~func->conf[i].mask; | |
7cba5b3f | 595 | if (arg) |
9dddb4df HZ |
596 | data |= func->conf[i].enable; |
597 | else | |
598 | data |= func->conf[i].disable; | |
599 | break; | |
600 | default: | |
601 | return -ENOTSUPP; | |
602 | } | |
603 | pcs->write(data, pcs->base + offset); | |
03b054e9 SY |
604 | |
605 | break; | |
9dddb4df | 606 | } |
03b054e9 SY |
607 | if (i >= func->nconfs) |
608 | return -ENOTSUPP; | |
609 | } /* for each config */ | |
610 | ||
611 | return 0; | |
8b8b091b TL |
612 | } |
613 | ||
614 | static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, | |
615 | unsigned group, unsigned long *config) | |
616 | { | |
9dddb4df HZ |
617 | const unsigned *pins; |
618 | unsigned npins, old = 0; | |
619 | int i, ret; | |
620 | ||
caeb774e | 621 | ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); |
9dddb4df HZ |
622 | if (ret) |
623 | return ret; | |
624 | for (i = 0; i < npins; i++) { | |
625 | if (pcs_pinconf_get(pctldev, pins[i], config)) | |
626 | return -ENOTSUPP; | |
627 | /* configs do not match between two pins */ | |
628 | if (i && (old != *config)) | |
629 | return -ENOTSUPP; | |
630 | old = *config; | |
631 | } | |
632 | return 0; | |
8b8b091b TL |
633 | } |
634 | ||
635 | static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
636 | unsigned group, unsigned long *configs, |
637 | unsigned num_configs) | |
8b8b091b | 638 | { |
9dddb4df HZ |
639 | const unsigned *pins; |
640 | unsigned npins; | |
641 | int i, ret; | |
642 | ||
caeb774e | 643 | ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); |
9dddb4df HZ |
644 | if (ret) |
645 | return ret; | |
646 | for (i = 0; i < npins; i++) { | |
03b054e9 | 647 | if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs)) |
9dddb4df HZ |
648 | return -ENOTSUPP; |
649 | } | |
650 | return 0; | |
8b8b091b TL |
651 | } |
652 | ||
653 | static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
9dddb4df | 654 | struct seq_file *s, unsigned pin) |
8b8b091b TL |
655 | { |
656 | } | |
657 | ||
658 | static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
659 | struct seq_file *s, unsigned selector) | |
660 | { | |
661 | } | |
662 | ||
9dddb4df HZ |
663 | static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, |
664 | struct seq_file *s, | |
665 | unsigned long config) | |
666 | { | |
667 | pinconf_generic_dump_config(pctldev, s, config); | |
668 | } | |
669 | ||
022ab148 | 670 | static const struct pinconf_ops pcs_pinconf_ops = { |
8b8b091b TL |
671 | .pin_config_get = pcs_pinconf_get, |
672 | .pin_config_set = pcs_pinconf_set, | |
673 | .pin_config_group_get = pcs_pinconf_group_get, | |
674 | .pin_config_group_set = pcs_pinconf_group_set, | |
675 | .pin_config_dbg_show = pcs_pinconf_dbg_show, | |
676 | .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, | |
9dddb4df | 677 | .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show, |
a7bbdd7f | 678 | .is_generic = true, |
8b8b091b TL |
679 | }; |
680 | ||
681 | /** | |
682 | * pcs_add_pin() - add a pin to the static per controller pin array | |
683 | * @pcs: pcs driver instance | |
684 | * @offset: register offset from base | |
685 | */ | |
8fa2ea20 | 686 | static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset) |
8b8b091b | 687 | { |
58968625 | 688 | struct pcs_soc_data *pcs_soc = &pcs->socdata; |
8b8b091b | 689 | struct pinctrl_pin_desc *pin; |
8b8b091b TL |
690 | int i; |
691 | ||
692 | i = pcs->pins.cur; | |
693 | if (i >= pcs->desc.npins) { | |
694 | dev_err(pcs->dev, "too many pins, max %i\n", | |
695 | pcs->desc.npins); | |
696 | return -ENOMEM; | |
697 | } | |
698 | ||
58968625 TL |
699 | if (pcs_soc->irq_enable_mask) { |
700 | unsigned val; | |
701 | ||
702 | val = pcs->read(pcs->base + offset); | |
703 | if (val & pcs_soc->irq_enable_mask) { | |
704 | dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", | |
705 | (unsigned long)pcs->res->start + offset, val); | |
706 | val &= ~pcs_soc->irq_enable_mask; | |
707 | pcs->write(val, pcs->base + offset); | |
708 | } | |
709 | } | |
710 | ||
8b8b091b | 711 | pin = &pcs->pins.pa[i]; |
8b8b091b TL |
712 | pin->number = i; |
713 | pcs->pins.cur++; | |
714 | ||
715 | return i; | |
716 | } | |
717 | ||
718 | /** | |
719 | * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver | |
720 | * @pcs: pcs driver instance | |
721 | * | |
722 | * In case of errors, resources are freed in pcs_free_resources. | |
723 | * | |
724 | * If your hardware needs holes in the address space, then just set | |
725 | * up multiple driver instances. | |
726 | */ | |
150632b0 | 727 | static int pcs_allocate_pin_table(struct pcs_device *pcs) |
8b8b091b TL |
728 | { |
729 | int mux_bytes, nr_pins, i; | |
730 | ||
731 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
4e7e8017 | 732 | |
64c15033 | 733 | if (pcs->bits_per_mux && pcs->fmask) { |
4e7e8017 MP |
734 | pcs->bits_per_pin = fls(pcs->fmask); |
735 | nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; | |
736 | } else { | |
737 | nr_pins = pcs->size / mux_bytes; | |
738 | } | |
8b8b091b TL |
739 | |
740 | dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); | |
a86854d0 KC |
741 | pcs->pins.pa = devm_kcalloc(pcs->dev, |
742 | nr_pins, sizeof(*pcs->pins.pa), | |
8b8b091b TL |
743 | GFP_KERNEL); |
744 | if (!pcs->pins.pa) | |
745 | return -ENOMEM; | |
746 | ||
8b8b091b TL |
747 | pcs->desc.pins = pcs->pins.pa; |
748 | pcs->desc.npins = nr_pins; | |
749 | ||
750 | for (i = 0; i < pcs->desc.npins; i++) { | |
751 | unsigned offset; | |
752 | int res; | |
753 | ||
bd85125e | 754 | offset = pcs_pin_reg_offset_get(pcs, i); |
8fa2ea20 | 755 | res = pcs_add_pin(pcs, offset); |
8b8b091b TL |
756 | if (res < 0) { |
757 | dev_err(pcs->dev, "error adding pins: %i\n", res); | |
758 | return res; | |
759 | } | |
760 | } | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | /** | |
766 | * pcs_add_function() - adds a new function to the function list | |
767 | * @pcs: pcs driver instance | |
a4ab1086 | 768 | * @fcn: new function allocated |
8b8b091b TL |
769 | * @name: name of the function |
770 | * @vals: array of mux register value pairs used by the function | |
771 | * @nvals: number of mux register value pairs | |
772 | * @pgnames: array of pingroup names for the function | |
773 | * @npgnames: number of pingroup names | |
a4ab1086 TL |
774 | * |
775 | * Caller must take care of locking. | |
8b8b091b | 776 | */ |
a4ab1086 TL |
777 | static int pcs_add_function(struct pcs_device *pcs, |
778 | struct pcs_function **fcn, | |
779 | const char *name, | |
780 | struct pcs_func_vals *vals, | |
781 | unsigned int nvals, | |
782 | const char **pgnames, | |
783 | unsigned int npgnames) | |
8b8b091b TL |
784 | { |
785 | struct pcs_function *function; | |
a4ab1086 | 786 | int selector; |
8b8b091b TL |
787 | |
788 | function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); | |
789 | if (!function) | |
a4ab1086 | 790 | return -ENOMEM; |
8b8b091b | 791 | |
8b8b091b TL |
792 | function->vals = vals; |
793 | function->nvals = nvals; | |
4739b1b1 | 794 | function->name = name; |
8b8b091b | 795 | |
a4ab1086 TL |
796 | selector = pinmux_generic_add_function(pcs->pctl, name, |
797 | pgnames, npgnames, | |
798 | function); | |
799 | if (selector < 0) { | |
800 | devm_kfree(pcs->dev, function); | |
801 | *fcn = NULL; | |
802 | } else { | |
803 | *fcn = function; | |
804 | } | |
8b8b091b | 805 | |
a4ab1086 | 806 | return selector; |
8b8b091b TL |
807 | } |
808 | ||
8b8b091b TL |
809 | /** |
810 | * pcs_get_pin_by_offset() - get a pin index based on the register offset | |
811 | * @pcs: pcs driver instance | |
812 | * @offset: register offset from the base | |
813 | * | |
814 | * Note that this is OK as long as the pins are in a static array. | |
815 | */ | |
816 | static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) | |
817 | { | |
818 | unsigned index; | |
819 | ||
820 | if (offset >= pcs->size) { | |
821 | dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", | |
822 | offset, pcs->size); | |
823 | return -EINVAL; | |
824 | } | |
825 | ||
4e7e8017 MP |
826 | if (pcs->bits_per_mux) |
827 | index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; | |
828 | else | |
829 | index = offset / (pcs->width / BITS_PER_BYTE); | |
8b8b091b TL |
830 | |
831 | return index; | |
832 | } | |
833 | ||
9dddb4df HZ |
834 | /* |
835 | * check whether data matches enable bits or disable bits | |
836 | * Return value: 1 for matching enable bits, 0 for matching disable bits, | |
837 | * and negative value for matching failure. | |
838 | */ | |
839 | static int pcs_config_match(unsigned data, unsigned enable, unsigned disable) | |
840 | { | |
841 | int ret = -EINVAL; | |
842 | ||
843 | if (data == enable) | |
844 | ret = 1; | |
845 | else if (data == disable) | |
846 | ret = 0; | |
847 | return ret; | |
848 | } | |
849 | ||
850 | static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param, | |
851 | unsigned value, unsigned enable, unsigned disable, | |
852 | unsigned mask) | |
853 | { | |
854 | (*conf)->param = param; | |
855 | (*conf)->val = value; | |
856 | (*conf)->enable = enable; | |
857 | (*conf)->disable = disable; | |
858 | (*conf)->mask = mask; | |
859 | (*conf)++; | |
860 | } | |
861 | ||
862 | static void add_setting(unsigned long **setting, enum pin_config_param param, | |
863 | unsigned arg) | |
864 | { | |
865 | **setting = pinconf_to_config_packed(param, arg); | |
866 | (*setting)++; | |
867 | } | |
868 | ||
869 | /* add pinconf setting with 2 parameters */ | |
870 | static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np, | |
871 | const char *name, enum pin_config_param param, | |
872 | struct pcs_conf_vals **conf, unsigned long **settings) | |
873 | { | |
7cba5b3f | 874 | unsigned value[2], shift; |
9dddb4df HZ |
875 | int ret; |
876 | ||
877 | ret = of_property_read_u32_array(np, name, value, 2); | |
878 | if (ret) | |
879 | return; | |
880 | /* set value & mask */ | |
881 | value[0] &= value[1]; | |
7cba5b3f | 882 | shift = ffs(value[1]) - 1; |
9dddb4df HZ |
883 | /* skip enable & disable */ |
884 | add_config(conf, param, value[0], 0, 0, value[1]); | |
7cba5b3f | 885 | add_setting(settings, param, value[0] >> shift); |
9dddb4df HZ |
886 | } |
887 | ||
888 | /* add pinconf setting with 4 parameters */ | |
889 | static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np, | |
890 | const char *name, enum pin_config_param param, | |
891 | struct pcs_conf_vals **conf, unsigned long **settings) | |
892 | { | |
893 | unsigned value[4]; | |
894 | int ret; | |
895 | ||
896 | /* value to set, enable, disable, mask */ | |
897 | ret = of_property_read_u32_array(np, name, value, 4); | |
898 | if (ret) | |
899 | return; | |
900 | if (!value[3]) { | |
901 | dev_err(pcs->dev, "mask field of the property can't be 0\n"); | |
902 | return; | |
903 | } | |
904 | value[0] &= value[3]; | |
905 | value[1] &= value[3]; | |
906 | value[2] &= value[3]; | |
907 | ret = pcs_config_match(value[0], value[1], value[2]); | |
908 | if (ret < 0) | |
909 | dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); | |
910 | add_config(conf, param, value[0], value[1], value[2], value[3]); | |
911 | add_setting(settings, param, ret); | |
912 | } | |
913 | ||
914 | static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, | |
915 | struct pcs_function *func, | |
916 | struct pinctrl_map **map) | |
917 | ||
918 | { | |
919 | struct pinctrl_map *m = *map; | |
920 | int i = 0, nconfs = 0; | |
921 | unsigned long *settings = NULL, *s = NULL; | |
922 | struct pcs_conf_vals *conf = NULL; | |
b582658a | 923 | static const struct pcs_conf_type prop2[] = { |
9dddb4df HZ |
924 | { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, |
925 | { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, | |
8c987eb1 | 926 | { "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, }, |
9dddb4df | 927 | { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, |
31f9a421 | 928 | { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, }, |
9dddb4df | 929 | }; |
b582658a | 930 | static const struct pcs_conf_type prop4[] = { |
9dddb4df HZ |
931 | { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, |
932 | { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, | |
933 | { "pinctrl-single,input-schmitt-enable", | |
934 | PIN_CONFIG_INPUT_SCHMITT_ENABLE, }, | |
935 | }; | |
936 | ||
937 | /* If pinconf isn't supported, don't parse properties in below. */ | |
02e483f6 | 938 | if (!PCS_HAS_PINCONF) |
f46fe79f | 939 | return -ENOTSUPP; |
9dddb4df HZ |
940 | |
941 | /* cacluate how much properties are supported in current node */ | |
942 | for (i = 0; i < ARRAY_SIZE(prop2); i++) { | |
e0e8fbf8 | 943 | if (of_property_present(np, prop2[i].name)) |
9dddb4df HZ |
944 | nconfs++; |
945 | } | |
946 | for (i = 0; i < ARRAY_SIZE(prop4); i++) { | |
e0e8fbf8 | 947 | if (of_property_present(np, prop4[i].name)) |
9dddb4df HZ |
948 | nconfs++; |
949 | } | |
950 | if (!nconfs) | |
f46fe79f | 951 | return -ENOTSUPP; |
9dddb4df | 952 | |
a86854d0 KC |
953 | func->conf = devm_kcalloc(pcs->dev, |
954 | nconfs, sizeof(struct pcs_conf_vals), | |
9dddb4df HZ |
955 | GFP_KERNEL); |
956 | if (!func->conf) | |
957 | return -ENOMEM; | |
958 | func->nconfs = nconfs; | |
959 | conf = &(func->conf[0]); | |
960 | m++; | |
a86854d0 | 961 | settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long), |
9dddb4df HZ |
962 | GFP_KERNEL); |
963 | if (!settings) | |
964 | return -ENOMEM; | |
965 | s = &settings[0]; | |
966 | ||
967 | for (i = 0; i < ARRAY_SIZE(prop2); i++) | |
968 | pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param, | |
969 | &conf, &s); | |
970 | for (i = 0; i < ARRAY_SIZE(prop4); i++) | |
971 | pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param, | |
972 | &conf, &s); | |
973 | m->type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
974 | m->data.configs.group_or_pin = np->name; | |
975 | m->data.configs.configs = settings; | |
976 | m->data.configs.num_configs = nconfs; | |
977 | return 0; | |
978 | } | |
979 | ||
8b8b091b | 980 | /** |
bc6d2015 | 981 | * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry |
8b8b091b TL |
982 | * @pcs: pinctrl driver instance |
983 | * @np: device node of the mux entry | |
984 | * @map: map entry | |
9dddb4df | 985 | * @num_maps: number of map |
8b8b091b TL |
986 | * @pgnames: pingroup names |
987 | * | |
988 | * Note that this binding currently supports only sets of one register + value. | |
989 | * | |
990 | * Also note that this driver tries to avoid understanding pin and function | |
991 | * names because of the extra bloat they would cause especially in the case of | |
992 | * a large number of pins. This driver just sets what is specified for the board | |
993 | * in the .dts file. Further user space debugging tools can be developed to | |
994 | * decipher the pin and function names using debugfs. | |
995 | * | |
996 | * If you are concerned about the boot time, set up the static pins in | |
997 | * the bootloader, and only set up selected pins as device tree entries. | |
998 | */ | |
999 | static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, | |
1000 | struct device_node *np, | |
1001 | struct pinctrl_map **map, | |
9dddb4df | 1002 | unsigned *num_maps, |
8b8b091b TL |
1003 | const char **pgnames) |
1004 | { | |
4622215f | 1005 | const char *name = "pinctrl-single,pins"; |
8b8b091b | 1006 | struct pcs_func_vals *vals; |
a4ab1086 TL |
1007 | int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; |
1008 | struct pcs_function *function = NULL; | |
8b8b091b | 1009 | |
4622215f | 1010 | rows = pinctrl_count_index_with_args(np, name); |
de7416bc | 1011 | if (rows <= 0) { |
059a6e63 | 1012 | dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); |
de7416bc AH |
1013 | return -EINVAL; |
1014 | } | |
8b8b091b | 1015 | |
a86854d0 | 1016 | vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL); |
8b8b091b TL |
1017 | if (!vals) |
1018 | return -ENOMEM; | |
1019 | ||
a86854d0 | 1020 | pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL); |
8b8b091b TL |
1021 | if (!pins) |
1022 | goto free_vals; | |
1023 | ||
4622215f TL |
1024 | for (i = 0; i < rows; i++) { |
1025 | struct of_phandle_args pinctrl_spec; | |
1026 | unsigned int offset; | |
8b8b091b TL |
1027 | int pin; |
1028 | ||
4622215f TL |
1029 | res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); |
1030 | if (res) | |
1031 | return res; | |
1032 | ||
9b9448f3 | 1033 | if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) { |
4622215f TL |
1034 | dev_err(pcs->dev, "invalid args_count for spec: %i\n", |
1035 | pinctrl_spec.args_count); | |
1036 | break; | |
1037 | } | |
1038 | ||
4622215f | 1039 | offset = pinctrl_spec.args[0]; |
8b8b091b | 1040 | vals[found].reg = pcs->base + offset; |
a1339541 DF |
1041 | |
1042 | switch (pinctrl_spec.args_count) { | |
1043 | case 2: | |
1044 | vals[found].val = pinctrl_spec.args[1]; | |
1045 | break; | |
1046 | case 3: | |
1047 | vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]); | |
1048 | break; | |
1049 | } | |
4622215f | 1050 | |
94f4e54c | 1051 | dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n", |
f4a2b19c | 1052 | pinctrl_spec.np, offset, vals[found].val); |
8b8b091b TL |
1053 | |
1054 | pin = pcs_get_pin_by_offset(pcs, offset); | |
1055 | if (pin < 0) { | |
1056 | dev_err(pcs->dev, | |
94f4e54c RH |
1057 | "could not add functions for %pOFn %ux\n", |
1058 | np, offset); | |
8b8b091b TL |
1059 | break; |
1060 | } | |
1061 | pins[found++] = pin; | |
1062 | } | |
1063 | ||
1064 | pgnames[0] = np->name; | |
a4ab1086 TL |
1065 | mutex_lock(&pcs->mutex); |
1066 | fsel = pcs_add_function(pcs, &function, np->name, vals, found, | |
1067 | pgnames, 1); | |
1068 | if (fsel < 0) { | |
1069 | res = fsel; | |
8b8b091b | 1070 | goto free_pins; |
712778d0 | 1071 | } |
8b8b091b | 1072 | |
a4ab1086 TL |
1073 | gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); |
1074 | if (gsel < 0) { | |
1075 | res = gsel; | |
8b8b091b | 1076 | goto free_function; |
a4ab1086 | 1077 | } |
8b8b091b TL |
1078 | |
1079 | (*map)->type = PIN_MAP_TYPE_MUX_GROUP; | |
1080 | (*map)->data.mux.group = np->name; | |
1081 | (*map)->data.mux.function = np->name; | |
1082 | ||
a4ab1086 | 1083 | if (PCS_HAS_PINCONF && function) { |
18442e65 | 1084 | res = pcs_parse_pinconf(pcs, np, function, map); |
f46fe79f DF |
1085 | if (res == 0) |
1086 | *num_maps = 2; | |
1087 | else if (res == -ENOTSUPP) | |
1088 | *num_maps = 1; | |
1089 | else | |
9dddb4df | 1090 | goto free_pingroups; |
9dddb4df HZ |
1091 | } else { |
1092 | *num_maps = 1; | |
1093 | } | |
a4ab1086 TL |
1094 | mutex_unlock(&pcs->mutex); |
1095 | ||
8b8b091b TL |
1096 | return 0; |
1097 | ||
9dddb4df | 1098 | free_pingroups: |
a4ab1086 | 1099 | pinctrl_generic_remove_group(pcs->pctl, gsel); |
9dddb4df | 1100 | *num_maps = 1; |
8b8b091b | 1101 | free_function: |
a4ab1086 | 1102 | pinmux_generic_remove_function(pcs->pctl, fsel); |
8b8b091b | 1103 | free_pins: |
673ba5a0 | 1104 | mutex_unlock(&pcs->mutex); |
8b8b091b TL |
1105 | devm_kfree(pcs->dev, pins); |
1106 | ||
4e7e8017 MP |
1107 | free_vals: |
1108 | devm_kfree(pcs->dev, vals); | |
1109 | ||
1110 | return res; | |
1111 | } | |
1112 | ||
4e7e8017 MP |
1113 | static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, |
1114 | struct device_node *np, | |
1115 | struct pinctrl_map **map, | |
1116 | unsigned *num_maps, | |
1117 | const char **pgnames) | |
1118 | { | |
dd68a526 | 1119 | const char *name = "pinctrl-single,bits"; |
4e7e8017 | 1120 | struct pcs_func_vals *vals; |
2ac48d0d | 1121 | int rows, *pins, found = 0, res = -ENOMEM, i, fsel; |
4e7e8017 | 1122 | int npins_in_row; |
a4ab1086 | 1123 | struct pcs_function *function = NULL; |
4e7e8017 | 1124 | |
22d5127e | 1125 | rows = pinctrl_count_index_with_args(np, name); |
de7416bc AH |
1126 | if (rows <= 0) { |
1127 | dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); | |
1128 | return -EINVAL; | |
1129 | } | |
4e7e8017 | 1130 | |
2ac48d0d ZL |
1131 | if (PCS_HAS_PINCONF) { |
1132 | dev_err(pcs->dev, "pinconf not supported\n"); | |
1133 | return -ENOTSUPP; | |
1134 | } | |
1135 | ||
4e7e8017 MP |
1136 | npins_in_row = pcs->width / pcs->bits_per_pin; |
1137 | ||
a86854d0 KC |
1138 | vals = devm_kzalloc(pcs->dev, |
1139 | array3_size(rows, npins_in_row, sizeof(*vals)), | |
1140 | GFP_KERNEL); | |
4e7e8017 MP |
1141 | if (!vals) |
1142 | return -ENOMEM; | |
1143 | ||
a86854d0 KC |
1144 | pins = devm_kzalloc(pcs->dev, |
1145 | array3_size(rows, npins_in_row, sizeof(*pins)), | |
1146 | GFP_KERNEL); | |
4e7e8017 MP |
1147 | if (!pins) |
1148 | goto free_vals; | |
1149 | ||
22d5127e TL |
1150 | for (i = 0; i < rows; i++) { |
1151 | struct of_phandle_args pinctrl_spec; | |
4e7e8017 MP |
1152 | unsigned offset, val; |
1153 | unsigned mask, bit_pos, val_pos, mask_pos, submask; | |
1154 | unsigned pin_num_from_lsb; | |
1155 | int pin; | |
1156 | ||
22d5127e TL |
1157 | res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); |
1158 | if (res) | |
1159 | return res; | |
1160 | ||
1161 | if (pinctrl_spec.args_count < 3) { | |
1162 | dev_err(pcs->dev, "invalid args_count for spec: %i\n", | |
1163 | pinctrl_spec.args_count); | |
1164 | break; | |
1165 | } | |
1166 | ||
1167 | /* Index plus two value cells */ | |
1168 | offset = pinctrl_spec.args[0]; | |
1169 | val = pinctrl_spec.args[1]; | |
1170 | mask = pinctrl_spec.args[2]; | |
1171 | ||
94f4e54c RH |
1172 | dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n", |
1173 | pinctrl_spec.np, offset, val, mask); | |
4e7e8017 MP |
1174 | |
1175 | /* Parse pins in each row from LSB */ | |
1176 | while (mask) { | |
56b367c0 | 1177 | bit_pos = __ffs(mask); |
4e7e8017 | 1178 | pin_num_from_lsb = bit_pos / pcs->bits_per_pin; |
56b367c0 | 1179 | mask_pos = ((pcs->fmask) << bit_pos); |
4e7e8017 MP |
1180 | val_pos = val & mask_pos; |
1181 | submask = mask & mask_pos; | |
ad5d25fe TV |
1182 | |
1183 | if ((mask & mask_pos) == 0) { | |
1184 | dev_err(pcs->dev, | |
94f4e54c RH |
1185 | "Invalid mask for %pOFn at 0x%x\n", |
1186 | np, offset); | |
ad5d25fe TV |
1187 | break; |
1188 | } | |
1189 | ||
4e7e8017 MP |
1190 | mask &= ~mask_pos; |
1191 | ||
1192 | if (submask != mask_pos) { | |
1193 | dev_warn(pcs->dev, | |
94f4e54c RH |
1194 | "Invalid submask 0x%x for %pOFn at 0x%x\n", |
1195 | submask, np, offset); | |
4e7e8017 MP |
1196 | continue; |
1197 | } | |
1198 | ||
1199 | vals[found].mask = submask; | |
1200 | vals[found].reg = pcs->base + offset; | |
1201 | vals[found].val = val_pos; | |
1202 | ||
1203 | pin = pcs_get_pin_by_offset(pcs, offset); | |
1204 | if (pin < 0) { | |
1205 | dev_err(pcs->dev, | |
94f4e54c RH |
1206 | "could not add functions for %pOFn %ux\n", |
1207 | np, offset); | |
4e7e8017 MP |
1208 | break; |
1209 | } | |
1210 | pins[found++] = pin + pin_num_from_lsb; | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | pgnames[0] = np->name; | |
a4ab1086 TL |
1215 | mutex_lock(&pcs->mutex); |
1216 | fsel = pcs_add_function(pcs, &function, np->name, vals, found, | |
1217 | pgnames, 1); | |
1218 | if (fsel < 0) { | |
1219 | res = fsel; | |
4e7e8017 | 1220 | goto free_pins; |
712778d0 | 1221 | } |
4e7e8017 | 1222 | |
2ac48d0d ZL |
1223 | res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); |
1224 | if (res < 0) | |
4e7e8017 MP |
1225 | goto free_function; |
1226 | ||
1227 | (*map)->type = PIN_MAP_TYPE_MUX_GROUP; | |
1228 | (*map)->data.mux.group = np->name; | |
1229 | (*map)->data.mux.function = np->name; | |
1230 | ||
4e7e8017 | 1231 | *num_maps = 1; |
a4ab1086 TL |
1232 | mutex_unlock(&pcs->mutex); |
1233 | ||
4e7e8017 MP |
1234 | return 0; |
1235 | ||
4e7e8017 | 1236 | free_function: |
a4ab1086 | 1237 | pinmux_generic_remove_function(pcs->pctl, fsel); |
4e7e8017 | 1238 | free_pins: |
673ba5a0 | 1239 | mutex_unlock(&pcs->mutex); |
4e7e8017 MP |
1240 | devm_kfree(pcs->dev, pins); |
1241 | ||
8b8b091b TL |
1242 | free_vals: |
1243 | devm_kfree(pcs->dev, vals); | |
1244 | ||
1245 | return res; | |
1246 | } | |
1247 | /** | |
1248 | * pcs_dt_node_to_map() - allocates and parses pinctrl maps | |
1249 | * @pctldev: pinctrl instance | |
1250 | * @np_config: device tree pinmux entry | |
1251 | * @map: array of map entries | |
1252 | * @num_maps: number of maps | |
1253 | */ | |
1254 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
1255 | struct device_node *np_config, | |
1256 | struct pinctrl_map **map, unsigned *num_maps) | |
1257 | { | |
1258 | struct pcs_device *pcs; | |
1259 | const char **pgnames; | |
1260 | int ret; | |
1261 | ||
1262 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
1263 | ||
9dddb4df | 1264 | /* create 2 maps. One is for pinmux, and the other is for pinconf. */ |
a86854d0 | 1265 | *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL); |
00e79d12 | 1266 | if (!*map) |
8b8b091b TL |
1267 | return -ENOMEM; |
1268 | ||
1269 | *num_maps = 0; | |
1270 | ||
1271 | pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); | |
1272 | if (!pgnames) { | |
1273 | ret = -ENOMEM; | |
1274 | goto free_map; | |
1275 | } | |
1276 | ||
4e7e8017 MP |
1277 | if (pcs->bits_per_mux) { |
1278 | ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, | |
1279 | num_maps, pgnames); | |
1280 | if (ret < 0) { | |
94f4e54c RH |
1281 | dev_err(pcs->dev, "no pins entries for %pOFn\n", |
1282 | np_config); | |
4e7e8017 MP |
1283 | goto free_pgnames; |
1284 | } | |
1285 | } else { | |
1286 | ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, | |
1287 | num_maps, pgnames); | |
1288 | if (ret < 0) { | |
94f4e54c RH |
1289 | dev_err(pcs->dev, "no pins entries for %pOFn\n", |
1290 | np_config); | |
4e7e8017 MP |
1291 | goto free_pgnames; |
1292 | } | |
8b8b091b | 1293 | } |
8b8b091b TL |
1294 | |
1295 | return 0; | |
1296 | ||
1297 | free_pgnames: | |
1298 | devm_kfree(pcs->dev, pgnames); | |
1299 | free_map: | |
1300 | devm_kfree(pcs->dev, *map); | |
1301 | ||
1302 | return ret; | |
1303 | } | |
1304 | ||
3e6cee17 TL |
1305 | /** |
1306 | * pcs_irq_free() - free interrupt | |
1307 | * @pcs: pcs driver instance | |
1308 | */ | |
1309 | static void pcs_irq_free(struct pcs_device *pcs) | |
1310 | { | |
1311 | struct pcs_soc_data *pcs_soc = &pcs->socdata; | |
1312 | ||
1313 | if (pcs_soc->irq < 0) | |
1314 | return; | |
1315 | ||
1316 | if (pcs->domain) | |
1317 | irq_domain_remove(pcs->domain); | |
1318 | ||
1319 | if (PCS_QUIRK_HAS_SHARED_IRQ) | |
1320 | free_irq(pcs_soc->irq, pcs_soc); | |
1321 | else | |
1322 | irq_set_chained_handler(pcs_soc->irq, NULL); | |
1323 | } | |
1324 | ||
8b8b091b TL |
1325 | /** |
1326 | * pcs_free_resources() - free memory used by this driver | |
1327 | * @pcs: pcs driver instance | |
1328 | */ | |
1329 | static void pcs_free_resources(struct pcs_device *pcs) | |
1330 | { | |
3e6cee17 | 1331 | pcs_irq_free(pcs); |
f10a2585 | 1332 | pinctrl_unregister(pcs->pctl); |
caeb774e | 1333 | |
4622215f TL |
1334 | #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) |
1335 | if (pcs->missing_nr_pinctrl_cells) | |
1336 | of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); | |
1337 | #endif | |
8b8b091b TL |
1338 | } |
1339 | ||
a1a277eb HZ |
1340 | static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) |
1341 | { | |
1342 | const char *propname = "pinctrl-single,gpio-range"; | |
1343 | const char *cellname = "#pinctrl-single,gpio-range-cells"; | |
1344 | struct of_phandle_args gpiospec; | |
1345 | struct pcs_gpiofunc_range *range; | |
1346 | int ret, i; | |
1347 | ||
1348 | for (i = 0; ; i++) { | |
1349 | ret = of_parse_phandle_with_args(node, propname, cellname, | |
1350 | i, &gpiospec); | |
1351 | /* Do not treat it as error. Only treat it as end condition. */ | |
1352 | if (ret) { | |
1353 | ret = 0; | |
1354 | break; | |
1355 | } | |
1356 | range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); | |
1357 | if (!range) { | |
1358 | ret = -ENOMEM; | |
1359 | break; | |
1360 | } | |
1361 | range->offset = gpiospec.args[0]; | |
1362 | range->npins = gpiospec.args[1]; | |
1363 | range->gpiofunc = gpiospec.args[2]; | |
1364 | mutex_lock(&pcs->mutex); | |
1365 | list_add_tail(&range->node, &pcs->gpiofuncs); | |
1366 | mutex_unlock(&pcs->mutex); | |
1367 | } | |
1368 | return ret; | |
1369 | } | |
0ba5ab00 | 1370 | |
3e6cee17 | 1371 | /** |
0ba5ab00 | 1372 | * struct pcs_interrupt |
3e6cee17 TL |
1373 | * @reg: virtual address of interrupt register |
1374 | * @hwirq: hardware irq number | |
1375 | * @irq: virtual irq number | |
1376 | * @node: list node | |
1377 | */ | |
1378 | struct pcs_interrupt { | |
1379 | void __iomem *reg; | |
1380 | irq_hw_number_t hwirq; | |
1381 | unsigned int irq; | |
1382 | struct list_head node; | |
1383 | }; | |
1384 | ||
1385 | /** | |
1386 | * pcs_irq_set() - enables or disables an interrupt | |
0ba5ab00 LJ |
1387 | * @pcs_soc: SoC specific settings |
1388 | * @irq: interrupt | |
1389 | * @enable: enable or disable the interrupt | |
3e6cee17 TL |
1390 | * |
1391 | * Note that this currently assumes one interrupt per pinctrl | |
1392 | * register that is typically used for wake-up events. | |
1393 | */ | |
1394 | static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc, | |
1395 | int irq, const bool enable) | |
1396 | { | |
1397 | struct pcs_device *pcs; | |
1398 | struct list_head *pos; | |
1399 | unsigned mask; | |
1400 | ||
1401 | pcs = container_of(pcs_soc, struct pcs_device, socdata); | |
1402 | list_for_each(pos, &pcs->irqs) { | |
1403 | struct pcs_interrupt *pcswi; | |
1404 | unsigned soc_mask; | |
1405 | ||
1406 | pcswi = list_entry(pos, struct pcs_interrupt, node); | |
1407 | if (irq != pcswi->irq) | |
1408 | continue; | |
1409 | ||
1410 | soc_mask = pcs_soc->irq_enable_mask; | |
1411 | raw_spin_lock(&pcs->lock); | |
1412 | mask = pcs->read(pcswi->reg); | |
1413 | if (enable) | |
1414 | mask |= soc_mask; | |
1415 | else | |
1416 | mask &= ~soc_mask; | |
1417 | pcs->write(mask, pcswi->reg); | |
0ac3c0a4 TL |
1418 | |
1419 | /* flush posted write */ | |
1420 | mask = pcs->read(pcswi->reg); | |
3e6cee17 TL |
1421 | raw_spin_unlock(&pcs->lock); |
1422 | } | |
c9b3a7d2 RQ |
1423 | |
1424 | if (pcs_soc->rearm) | |
1425 | pcs_soc->rearm(); | |
3e6cee17 TL |
1426 | } |
1427 | ||
1428 | /** | |
1429 | * pcs_irq_mask() - mask pinctrl interrupt | |
1430 | * @d: interrupt data | |
1431 | */ | |
1432 | static void pcs_irq_mask(struct irq_data *d) | |
1433 | { | |
1434 | struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); | |
1435 | ||
1436 | pcs_irq_set(pcs_soc, d->irq, false); | |
1437 | } | |
1438 | ||
1439 | /** | |
1440 | * pcs_irq_unmask() - unmask pinctrl interrupt | |
1441 | * @d: interrupt data | |
1442 | */ | |
1443 | static void pcs_irq_unmask(struct irq_data *d) | |
1444 | { | |
1445 | struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); | |
1446 | ||
1447 | pcs_irq_set(pcs_soc, d->irq, true); | |
1448 | } | |
1449 | ||
1450 | /** | |
1451 | * pcs_irq_set_wake() - toggle the suspend and resume wake up | |
1452 | * @d: interrupt data | |
1453 | * @state: wake-up state | |
1454 | * | |
1455 | * Note that this should be called only for suspend and resume. | |
1456 | * For runtime PM, the wake-up events should be enabled by default. | |
1457 | */ | |
1458 | static int pcs_irq_set_wake(struct irq_data *d, unsigned int state) | |
1459 | { | |
1460 | if (state) | |
1461 | pcs_irq_unmask(d); | |
1462 | else | |
1463 | pcs_irq_mask(d); | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | /** | |
1469 | * pcs_irq_handle() - common interrupt handler | |
0ba5ab00 | 1470 | * @pcs_soc: SoC specific settings |
3e6cee17 TL |
1471 | * |
1472 | * Note that this currently assumes we have one interrupt bit per | |
1473 | * mux register. This interrupt is typically used for wake-up events. | |
1474 | * For more complex interrupts different handlers can be specified. | |
1475 | */ | |
1476 | static int pcs_irq_handle(struct pcs_soc_data *pcs_soc) | |
1477 | { | |
1478 | struct pcs_device *pcs; | |
1479 | struct list_head *pos; | |
1480 | int count = 0; | |
1481 | ||
1482 | pcs = container_of(pcs_soc, struct pcs_device, socdata); | |
1483 | list_for_each(pos, &pcs->irqs) { | |
1484 | struct pcs_interrupt *pcswi; | |
1485 | unsigned mask; | |
1486 | ||
1487 | pcswi = list_entry(pos, struct pcs_interrupt, node); | |
1488 | raw_spin_lock(&pcs->lock); | |
1489 | mask = pcs->read(pcswi->reg); | |
1490 | raw_spin_unlock(&pcs->lock); | |
1491 | if (mask & pcs_soc->irq_status_mask) { | |
a9cb09b7 MZ |
1492 | generic_handle_domain_irq(pcs->domain, |
1493 | pcswi->hwirq); | |
3e6cee17 TL |
1494 | count++; |
1495 | } | |
1496 | } | |
1497 | ||
1498 | return count; | |
1499 | } | |
1500 | ||
1501 | /** | |
1502 | * pcs_irq_handler() - handler for the shared interrupt case | |
1503 | * @irq: interrupt | |
1504 | * @d: data | |
1505 | * | |
1506 | * Use this for cases where multiple instances of | |
1507 | * pinctrl-single share a single interrupt like on omaps. | |
1508 | */ | |
1509 | static irqreturn_t pcs_irq_handler(int irq, void *d) | |
1510 | { | |
1511 | struct pcs_soc_data *pcs_soc = d; | |
1512 | ||
1513 | return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE; | |
1514 | } | |
1515 | ||
1516 | /** | |
b9045af9 | 1517 | * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case |
3e6cee17 TL |
1518 | * @desc: interrupt descriptor |
1519 | * | |
1520 | * Use this if you have a separate interrupt for each | |
1521 | * pinctrl-single instance. | |
1522 | */ | |
bd0b9ac4 | 1523 | static void pcs_irq_chain_handler(struct irq_desc *desc) |
3e6cee17 TL |
1524 | { |
1525 | struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); | |
1526 | struct irq_chip *chip; | |
3e6cee17 | 1527 | |
5663bb27 | 1528 | chip = irq_desc_get_chip(desc); |
3e6cee17 | 1529 | chained_irq_enter(chip, desc); |
849bfe06 | 1530 | pcs_irq_handle(pcs_soc); |
3e6cee17 TL |
1531 | /* REVISIT: export and add handle_bad_irq(irq, desc)? */ |
1532 | chained_irq_exit(chip, desc); | |
3e6cee17 TL |
1533 | } |
1534 | ||
1535 | static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
1536 | irq_hw_number_t hwirq) | |
1537 | { | |
1538 | struct pcs_soc_data *pcs_soc = d->host_data; | |
1539 | struct pcs_device *pcs; | |
1540 | struct pcs_interrupt *pcswi; | |
1541 | ||
1542 | pcs = container_of(pcs_soc, struct pcs_device, socdata); | |
1543 | pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); | |
1544 | if (!pcswi) | |
1545 | return -ENOMEM; | |
1546 | ||
1547 | pcswi->reg = pcs->base + hwirq; | |
1548 | pcswi->hwirq = hwirq; | |
1549 | pcswi->irq = irq; | |
1550 | ||
1551 | mutex_lock(&pcs->mutex); | |
1552 | list_add_tail(&pcswi->node, &pcs->irqs); | |
1553 | mutex_unlock(&pcs->mutex); | |
1554 | ||
1555 | irq_set_chip_data(irq, pcs_soc); | |
1556 | irq_set_chip_and_handler(irq, &pcs->chip, | |
1557 | handle_level_irq); | |
39c3fd58 | 1558 | irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class); |
1b9c0fb3 | 1559 | irq_set_noprobe(irq); |
3e6cee17 TL |
1560 | |
1561 | return 0; | |
1562 | } | |
1563 | ||
e5b60953 | 1564 | static const struct irq_domain_ops pcs_irqdomain_ops = { |
3e6cee17 TL |
1565 | .map = pcs_irqdomain_map, |
1566 | .xlate = irq_domain_xlate_onecell, | |
1567 | }; | |
1568 | ||
1569 | /** | |
1570 | * pcs_irq_init_chained_handler() - set up a chained interrupt handler | |
1571 | * @pcs: pcs driver instance | |
1572 | * @np: device node pointer | |
1573 | */ | |
1574 | static int pcs_irq_init_chained_handler(struct pcs_device *pcs, | |
1575 | struct device_node *np) | |
1576 | { | |
1577 | struct pcs_soc_data *pcs_soc = &pcs->socdata; | |
1578 | const char *name = "pinctrl"; | |
1579 | int num_irqs; | |
1580 | ||
1581 | if (!pcs_soc->irq_enable_mask || | |
1582 | !pcs_soc->irq_status_mask) { | |
1583 | pcs_soc->irq = -1; | |
1584 | return -EINVAL; | |
1585 | } | |
1586 | ||
1587 | INIT_LIST_HEAD(&pcs->irqs); | |
1588 | pcs->chip.name = name; | |
1589 | pcs->chip.irq_ack = pcs_irq_mask; | |
1590 | pcs->chip.irq_mask = pcs_irq_mask; | |
1591 | pcs->chip.irq_unmask = pcs_irq_unmask; | |
1592 | pcs->chip.irq_set_wake = pcs_irq_set_wake; | |
1593 | ||
1594 | if (PCS_QUIRK_HAS_SHARED_IRQ) { | |
1595 | int res; | |
1596 | ||
1597 | res = request_irq(pcs_soc->irq, pcs_irq_handler, | |
c10372e6 GS |
1598 | IRQF_SHARED | IRQF_NO_SUSPEND | |
1599 | IRQF_NO_THREAD, | |
3e6cee17 TL |
1600 | name, pcs_soc); |
1601 | if (res) { | |
1602 | pcs_soc->irq = -1; | |
1603 | return res; | |
1604 | } | |
1605 | } else { | |
20d5d142 TG |
1606 | irq_set_chained_handler_and_data(pcs_soc->irq, |
1607 | pcs_irq_chain_handler, | |
1608 | pcs_soc); | |
3e6cee17 TL |
1609 | } |
1610 | ||
1611 | /* | |
1612 | * We can use the register offset as the hardirq | |
1613 | * number as irq_domain_add_simple maps them lazily. | |
1614 | * This way we can easily support more than one | |
1615 | * interrupt per function if needed. | |
1616 | */ | |
1617 | num_irqs = pcs->size; | |
1618 | ||
1619 | pcs->domain = irq_domain_add_simple(np, num_irqs, 0, | |
1620 | &pcs_irqdomain_ops, | |
1621 | pcs_soc); | |
1622 | if (!pcs->domain) { | |
1623 | irq_set_chained_handler(pcs_soc->irq, NULL); | |
1624 | return -EINVAL; | |
1625 | } | |
1626 | ||
1627 | return 0; | |
1628 | } | |
a1a277eb | 1629 | |
88a1dbde K |
1630 | static int pcs_save_context(struct pcs_device *pcs) |
1631 | { | |
1632 | int i, mux_bytes; | |
1633 | u64 *regsl; | |
1634 | u32 *regsw; | |
1635 | u16 *regshw; | |
1636 | ||
1637 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
1638 | ||
7f57871f | 1639 | if (!pcs->saved_vals) { |
88a1dbde | 1640 | pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); |
7f57871f CIK |
1641 | if (!pcs->saved_vals) |
1642 | return -ENOMEM; | |
1643 | } | |
88a1dbde K |
1644 | |
1645 | switch (pcs->width) { | |
1646 | case 64: | |
7d71b5f4 GU |
1647 | regsl = pcs->saved_vals; |
1648 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1649 | *regsl++ = pcs->read(pcs->base + i); | |
88a1dbde K |
1650 | break; |
1651 | case 32: | |
7d71b5f4 GU |
1652 | regsw = pcs->saved_vals; |
1653 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1654 | *regsw++ = pcs->read(pcs->base + i); | |
88a1dbde K |
1655 | break; |
1656 | case 16: | |
7d71b5f4 GU |
1657 | regshw = pcs->saved_vals; |
1658 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1659 | *regshw++ = pcs->read(pcs->base + i); | |
88a1dbde K |
1660 | break; |
1661 | } | |
1662 | ||
1663 | return 0; | |
1664 | } | |
1665 | ||
1666 | static void pcs_restore_context(struct pcs_device *pcs) | |
1667 | { | |
1668 | int i, mux_bytes; | |
1669 | u64 *regsl; | |
1670 | u32 *regsw; | |
1671 | u16 *regshw; | |
1672 | ||
1673 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
1674 | ||
1675 | switch (pcs->width) { | |
1676 | case 64: | |
7d71b5f4 GU |
1677 | regsl = pcs->saved_vals; |
1678 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1679 | pcs->write(*regsl++, pcs->base + i); | |
88a1dbde K |
1680 | break; |
1681 | case 32: | |
7d71b5f4 GU |
1682 | regsw = pcs->saved_vals; |
1683 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1684 | pcs->write(*regsw++, pcs->base + i); | |
88a1dbde K |
1685 | break; |
1686 | case 16: | |
7d71b5f4 GU |
1687 | regshw = pcs->saved_vals; |
1688 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1689 | pcs->write(*regshw++, pcs->base + i); | |
88a1dbde K |
1690 | break; |
1691 | } | |
1692 | } | |
1693 | ||
85dfe458 | 1694 | static int pinctrl_single_suspend_noirq(struct device *dev) |
0f9bc4bc | 1695 | { |
85dfe458 | 1696 | struct pcs_device *pcs = dev_get_drvdata(dev); |
0f9bc4bc | 1697 | |
7f57871f CIK |
1698 | if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { |
1699 | int ret; | |
1700 | ||
1701 | ret = pcs_save_context(pcs); | |
1702 | if (ret < 0) | |
1703 | return ret; | |
1704 | } | |
88a1dbde | 1705 | |
0f9bc4bc HG |
1706 | return pinctrl_force_sleep(pcs->pctl); |
1707 | } | |
1708 | ||
85dfe458 | 1709 | static int pinctrl_single_resume_noirq(struct device *dev) |
0f9bc4bc | 1710 | { |
85dfe458 | 1711 | struct pcs_device *pcs = dev_get_drvdata(dev); |
0f9bc4bc | 1712 | |
88a1dbde K |
1713 | if (pcs->flags & PCS_CONTEXT_LOSS_OFF) |
1714 | pcs_restore_context(pcs); | |
1715 | ||
0f9bc4bc HG |
1716 | return pinctrl_force_default(pcs->pctl); |
1717 | } | |
85dfe458 TR |
1718 | |
1719 | static DEFINE_NOIRQ_DEV_PM_OPS(pinctrl_single_pm_ops, | |
1720 | pinctrl_single_suspend_noirq, | |
1721 | pinctrl_single_resume_noirq); | |
0f9bc4bc | 1722 | |
4622215f TL |
1723 | /** |
1724 | * pcs_quirk_missing_pinctrl_cells - handle legacy binding | |
1725 | * @pcs: pinctrl driver instance | |
1726 | * @np: device tree node | |
1727 | * @cells: number of cells | |
1728 | * | |
1729 | * Handle legacy binding with no #pinctrl-cells. This should be | |
1730 | * always two pinctrl-single,bit-per-mux and one for others. | |
1731 | * At some point we may want to consider removing this. | |
1732 | */ | |
1733 | static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs, | |
1734 | struct device_node *np, | |
1735 | int cells) | |
1736 | { | |
1737 | struct property *p; | |
1738 | const char *name = "#pinctrl-cells"; | |
1739 | int error; | |
1740 | u32 val; | |
1741 | ||
1742 | error = of_property_read_u32(np, name, &val); | |
1743 | if (!error) | |
1744 | return 0; | |
1745 | ||
1746 | dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", | |
1747 | name, cells); | |
1748 | ||
1749 | p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); | |
1750 | if (!p) | |
1751 | return -ENOMEM; | |
1752 | ||
1753 | p->length = sizeof(__be32); | |
1754 | p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); | |
1755 | if (!p->value) | |
1756 | return -ENOMEM; | |
1757 | *(__be32 *)p->value = cpu_to_be32(cells); | |
1758 | ||
1759 | p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); | |
1760 | if (!p->name) | |
1761 | return -ENOMEM; | |
1762 | ||
1763 | pcs->missing_nr_pinctrl_cells = p; | |
1764 | ||
1765 | #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) | |
1766 | error = of_add_property(np, pcs->missing_nr_pinctrl_cells); | |
1767 | #endif | |
1768 | ||
1769 | return error; | |
1770 | } | |
1771 | ||
150632b0 | 1772 | static int pcs_probe(struct platform_device *pdev) |
8b8b091b TL |
1773 | { |
1774 | struct device_node *np = pdev->dev.of_node; | |
dc7743aa | 1775 | struct pcs_pdata *pdata; |
8b8b091b TL |
1776 | struct resource *res; |
1777 | struct pcs_device *pcs; | |
02e483f6 | 1778 | const struct pcs_soc_data *soc; |
8b8b091b TL |
1779 | int ret; |
1780 | ||
1a8764f4 MY |
1781 | soc = of_device_get_match_data(&pdev->dev); |
1782 | if (WARN_ON(!soc)) | |
8b8b091b TL |
1783 | return -EINVAL; |
1784 | ||
1785 | pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); | |
a14aa271 | 1786 | if (!pcs) |
8b8b091b | 1787 | return -ENOMEM; |
a14aa271 | 1788 | |
8b8b091b | 1789 | pcs->dev = &pdev->dev; |
4622215f | 1790 | pcs->np = np; |
3e6cee17 | 1791 | raw_spin_lock_init(&pcs->lock); |
8b8b091b | 1792 | mutex_init(&pcs->mutex); |
a1a277eb | 1793 | INIT_LIST_HEAD(&pcs->gpiofuncs); |
02e483f6 | 1794 | pcs->flags = soc->flags; |
3e6cee17 | 1795 | memcpy(&pcs->socdata, soc, sizeof(*soc)); |
8b8b091b | 1796 | |
cd23604a TL |
1797 | ret = of_property_read_u32(np, "pinctrl-single,register-width", |
1798 | &pcs->width); | |
1799 | if (ret) { | |
1800 | dev_err(pcs->dev, "register width not specified\n"); | |
1801 | ||
1802 | return ret; | |
1803 | } | |
8b8b091b | 1804 | |
477ac771 HZ |
1805 | ret = of_property_read_u32(np, "pinctrl-single,function-mask", |
1806 | &pcs->fmask); | |
1807 | if (!ret) { | |
56b367c0 | 1808 | pcs->fshift = __ffs(pcs->fmask); |
477ac771 HZ |
1809 | pcs->fmax = pcs->fmask >> pcs->fshift; |
1810 | } else { | |
1811 | /* If mask property doesn't exist, function mux is invalid. */ | |
1812 | pcs->fmask = 0; | |
1813 | pcs->fshift = 0; | |
1814 | pcs->fmax = 0; | |
1815 | } | |
8b8b091b TL |
1816 | |
1817 | ret = of_property_read_u32(np, "pinctrl-single,function-off", | |
1818 | &pcs->foff); | |
1819 | if (ret) | |
1820 | pcs->foff = PCS_OFF_DISABLED; | |
1821 | ||
9e605cb6 PU |
1822 | pcs->bits_per_mux = of_property_read_bool(np, |
1823 | "pinctrl-single,bit-per-mux"); | |
4622215f TL |
1824 | ret = pcs_quirk_missing_pinctrl_cells(pcs, np, |
1825 | pcs->bits_per_mux ? 2 : 1); | |
1826 | if (ret) { | |
1827 | dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); | |
1828 | ||
1829 | return ret; | |
1830 | } | |
9e605cb6 | 1831 | |
8b8b091b TL |
1832 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1833 | if (!res) { | |
1834 | dev_err(pcs->dev, "could not get resource\n"); | |
1835 | return -ENODEV; | |
1836 | } | |
1837 | ||
1838 | pcs->res = devm_request_mem_region(pcs->dev, res->start, | |
1839 | resource_size(res), DRIVER_NAME); | |
1840 | if (!pcs->res) { | |
1841 | dev_err(pcs->dev, "could not get mem_region\n"); | |
1842 | return -EBUSY; | |
1843 | } | |
1844 | ||
1845 | pcs->size = resource_size(pcs->res); | |
1846 | pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); | |
1847 | if (!pcs->base) { | |
1848 | dev_err(pcs->dev, "could not ioremap\n"); | |
1849 | return -ENODEV; | |
1850 | } | |
1851 | ||
8b8b091b TL |
1852 | platform_set_drvdata(pdev, pcs); |
1853 | ||
1854 | switch (pcs->width) { | |
1855 | case 8: | |
1856 | pcs->read = pcs_readb; | |
1857 | pcs->write = pcs_writeb; | |
1858 | break; | |
1859 | case 16: | |
1860 | pcs->read = pcs_readw; | |
1861 | pcs->write = pcs_writew; | |
1862 | break; | |
1863 | case 32: | |
1864 | pcs->read = pcs_readl; | |
1865 | pcs->write = pcs_writel; | |
1866 | break; | |
1867 | default: | |
1868 | break; | |
1869 | } | |
1870 | ||
1871 | pcs->desc.name = DRIVER_NAME; | |
1872 | pcs->desc.pctlops = &pcs_pinctrl_ops; | |
1873 | pcs->desc.pmxops = &pcs_pinmux_ops; | |
02e483f6 | 1874 | if (PCS_HAS_PINCONF) |
a7bbdd7f | 1875 | pcs->desc.confops = &pcs_pinconf_ops; |
8b8b091b TL |
1876 | pcs->desc.owner = THIS_MODULE; |
1877 | ||
1878 | ret = pcs_allocate_pin_table(pcs); | |
1879 | if (ret < 0) | |
1880 | goto free; | |
1881 | ||
950b0d91 TL |
1882 | ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl); |
1883 | if (ret) { | |
8b8b091b | 1884 | dev_err(pcs->dev, "could not register single pinctrl driver\n"); |
8b8b091b TL |
1885 | goto free; |
1886 | } | |
1887 | ||
a1a277eb HZ |
1888 | ret = pcs_add_gpio_func(np, pcs); |
1889 | if (ret < 0) | |
1890 | goto free; | |
1891 | ||
3e6cee17 TL |
1892 | pcs->socdata.irq = irq_of_parse_and_map(np, 0); |
1893 | if (pcs->socdata.irq) | |
1894 | pcs->flags |= PCS_FEAT_IRQ; | |
1895 | ||
dc7743aa TL |
1896 | /* We still need auxdata for some omaps for PRM interrupts */ |
1897 | pdata = dev_get_platdata(&pdev->dev); | |
1898 | if (pdata) { | |
1899 | if (pdata->rearm) | |
1900 | pcs->socdata.rearm = pdata->rearm; | |
1901 | if (pdata->irq) { | |
1902 | pcs->socdata.irq = pdata->irq; | |
1903 | pcs->flags |= PCS_FEAT_IRQ; | |
1904 | } | |
1905 | } | |
1906 | ||
3e6cee17 TL |
1907 | if (PCS_HAS_IRQ) { |
1908 | ret = pcs_irq_init_chained_handler(pcs, np); | |
1909 | if (ret < 0) | |
1910 | dev_warn(pcs->dev, "initialized with no interrupts\n"); | |
1911 | } | |
1912 | ||
c2584927 | 1913 | dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); |
8b8b091b | 1914 | |
61187142 | 1915 | return pinctrl_enable(pcs->pctl); |
8b8b091b TL |
1916 | |
1917 | free: | |
1918 | pcs_free_resources(pcs); | |
1919 | ||
1920 | return ret; | |
1921 | } | |
1922 | ||
a6992a0d | 1923 | static void pcs_remove(struct platform_device *pdev) |
8b8b091b TL |
1924 | { |
1925 | struct pcs_device *pcs = platform_get_drvdata(pdev); | |
1926 | ||
8b8b091b | 1927 | pcs_free_resources(pcs); |
8b8b091b TL |
1928 | } |
1929 | ||
3e6cee17 TL |
1930 | static const struct pcs_soc_data pinctrl_single_omap_wkup = { |
1931 | .flags = PCS_QUIRK_SHARED_IRQ, | |
1932 | .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */ | |
1933 | .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ | |
1934 | }; | |
1935 | ||
31320bea | 1936 | static const struct pcs_soc_data pinctrl_single_dra7 = { |
31320bea NM |
1937 | .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ |
1938 | .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ | |
1939 | }; | |
1940 | ||
aa2293d8 | 1941 | static const struct pcs_soc_data pinctrl_single_am437x = { |
88a1dbde | 1942 | .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, |
aa2293d8 K |
1943 | .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */ |
1944 | .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ | |
1945 | }; | |
1946 | ||
0cec950d TL |
1947 | static const struct pcs_soc_data pinctrl_single_am654 = { |
1948 | .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, | |
1949 | .irq_enable_mask = (1 << 29), /* WKUP_EN */ | |
1950 | .irq_status_mask = (1 << 30), /* WKUP_EVT */ | |
1951 | }; | |
1952 | ||
e24b623d TR |
1953 | static const struct pcs_soc_data pinctrl_single_j7200 = { |
1954 | .flags = PCS_CONTEXT_LOSS_OFF, | |
1955 | }; | |
1956 | ||
02e483f6 TL |
1957 | static const struct pcs_soc_data pinctrl_single = { |
1958 | }; | |
1959 | ||
1960 | static const struct pcs_soc_data pinconf_single = { | |
1961 | .flags = PCS_FEAT_PINCONF, | |
1962 | }; | |
1963 | ||
baa9946e | 1964 | static const struct of_device_id pcs_of_match[] = { |
0cec950d TL |
1965 | { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, |
1966 | { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 }, | |
1967 | { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, | |
3e6cee17 TL |
1968 | { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, |
1969 | { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, | |
1970 | { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, | |
e24b623d | 1971 | { .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 }, |
02e483f6 TL |
1972 | { .compatible = "pinctrl-single", .data = &pinctrl_single }, |
1973 | { .compatible = "pinconf-single", .data = &pinconf_single }, | |
8b8b091b TL |
1974 | { }, |
1975 | }; | |
1976 | MODULE_DEVICE_TABLE(of, pcs_of_match); | |
1977 | ||
1978 | static struct platform_driver pcs_driver = { | |
1979 | .probe = pcs_probe, | |
a6992a0d | 1980 | .remove_new = pcs_remove, |
8b8b091b | 1981 | .driver = { |
8b8b091b TL |
1982 | .name = DRIVER_NAME, |
1983 | .of_match_table = pcs_of_match, | |
85dfe458 | 1984 | .pm = pm_sleep_ptr(&pinctrl_single_pm_ops), |
8b8b091b TL |
1985 | }, |
1986 | }; | |
1987 | ||
1988 | module_platform_driver(pcs_driver); | |
1989 | ||
1990 | MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); | |
1991 | MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); | |
1992 | MODULE_LICENSE("GPL v2"); |