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Merge tag 'hwmon-for-v4.20-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-rza1.c
CommitLineData
a8b4d4cb 1// SPDX-License-Identifier: GPL-2.0
5a49b644
JM		 2/*
3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
4 *
5 * Copyright (C) 2017 Jacopo Mondi
5a49b644
JM		 6 */
7
8/*
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
10 * family.
11 * This includes SoCs which are sub- or super- sets of this particular line,
12 * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
13 */
14
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/gpio/driver.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/pinctrl/pinconf-generic.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/pinmux.h>
27#include <linux/slab.h>
28
29#include "core.h"
30#include "devicetree.h"
31#include "pinconf.h"
32#include "pinmux.h"
33
34#define DRIVER_NAME "pinctrl-rza1"
35
36#define RZA1_P_REG 0x0000
37#define RZA1_PPR_REG 0x0200
38#define RZA1_PM_REG 0x0300
39#define RZA1_PMC_REG 0x0400
40#define RZA1_PFC_REG 0x0500
41#define RZA1_PFCE_REG 0x0600
42#define RZA1_PFCEA_REG 0x0a00
43#define RZA1_PIBC_REG 0x4000
44#define RZA1_PBDC_REG 0x4100
45#define RZA1_PIPC_REG 0x4200
46
47#define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4))
48
49#define RZA1_NPORTS 12
50#define RZA1_PINS_PER_PORT 16
51#define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)
52#define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT)
53#define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT)
54
55/*
56 * Use 16 lower bits [15:0] for pin identifier
57 * Use 16 higher bits [31:16] for pin mux function
58 */
59#define MUX_PIN_ID_MASK GENMASK(15, 0)
60#define MUX_FUNC_MASK GENMASK(31, 16)
61
62#define MUX_FUNC_OFFS 16
63#define MUX_FUNC(pinconf) \
64 ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
65#define MUX_FUNC_PFC_MASK BIT(0)
66#define MUX_FUNC_PFCE_MASK BIT(1)
67#define MUX_FUNC_PFCEA_MASK BIT(2)
68
69/* Pin mux flags */
70#define MUX_FLAGS_BIDIR BIT(0)
71#define MUX_FLAGS_SWIO_INPUT BIT(1)
72#define MUX_FLAGS_SWIO_OUTPUT BIT(2)
73
74/* ----------------------------------------------------------------------------
75 * RZ/A1 pinmux flags
76 */
77
78/**
79 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
80 */
81struct rza1_bidir_pin {
82 u8 pin: 4;
83 u8 func: 4;
84};
85
86/**
87 * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
88 * Each struct rza1_bidir_entry describes a port.
89 */
90struct rza1_bidir_entry {
91 const unsigned int npins;
92 const struct rza1_bidir_pin *pins;
93};
94
95/**
96 * rza1_swio_pin - describe a single pin that needs bidir flag applied.
97 */
98struct rza1_swio_pin {
99 u16 pin: 4;
100 u16 port: 4;
101 u16 func: 4;
102 u16 input: 1;
103};
104
105/**
106 * rza1_swio_entry - describe a list of pins that needs swio flag applied
107 */
108struct rza1_swio_entry {
109 const unsigned int npins;
110 const struct rza1_swio_pin *pins;
111};
112
113/**
114 * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
115 */
116struct rza1_pinmux_conf {
117 const struct rza1_bidir_entry *bidir_entries;
118 const struct rza1_swio_entry *swio_entries;
119};
120
121/* ----------------------------------------------------------------------------
122 * RZ/A1H (r7s72100) pinmux flags
123 */
124
125static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
126 { .pin = 0, .func = 1 },
127 { .pin = 1, .func = 1 },
128 { .pin = 2, .func = 1 },
129 { .pin = 3, .func = 1 },
130 { .pin = 4, .func = 1 },
131 { .pin = 5, .func = 1 },
132 { .pin = 6, .func = 1 },
133 { .pin = 7, .func = 1 },
134};
135
136static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
137 { .pin = 0, .func = 1 },
138 { .pin = 1, .func = 1 },
139 { .pin = 2, .func = 1 },
140 { .pin = 3, .func = 1 },
141 { .pin = 4, .func = 1 },
142 { .pin = 0, .func = 4 },
143 { .pin = 1, .func = 4 },
144 { .pin = 2, .func = 4 },
145 { .pin = 3, .func = 4 },
146 { .pin = 5, .func = 1 },
147 { .pin = 6, .func = 1 },
148 { .pin = 7, .func = 1 },
149 { .pin = 8, .func = 1 },
150 { .pin = 9, .func = 1 },
151 { .pin = 10, .func = 1 },
152 { .pin = 11, .func = 1 },
153 { .pin = 12, .func = 1 },
154 { .pin = 13, .func = 1 },
155 { .pin = 14, .func = 1 },
156 { .pin = 15, .func = 1 },
157 { .pin = 12, .func = 4 },
158 { .pin = 13, .func = 4 },
159 { .pin = 14, .func = 4 },
160 { .pin = 15, .func = 4 },
161};
162
163static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
164 { .pin = 3, .func = 2 },
165 { .pin = 10, .func = 7 },
166 { .pin = 11, .func = 7 },
167 { .pin = 13, .func = 7 },
168 { .pin = 14, .func = 7 },
169 { .pin = 15, .func = 7 },
170 { .pin = 10, .func = 8 },
171 { .pin = 11, .func = 8 },
172 { .pin = 13, .func = 8 },
173 { .pin = 14, .func = 8 },
174 { .pin = 15, .func = 8 },
175};
176
177static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
178 { .pin = 0, .func = 8 },
179 { .pin = 1, .func = 8 },
180 { .pin = 2, .func = 8 },
181 { .pin = 3, .func = 8 },
182 { .pin = 10, .func = 3 },
183 { .pin = 11, .func = 3 },
184 { .pin = 13, .func = 3 },
185 { .pin = 14, .func = 3 },
186 { .pin = 15, .func = 3 },
187 { .pin = 10, .func = 4 },
188 { .pin = 11, .func = 4 },
189 { .pin = 13, .func = 4 },
190 { .pin = 14, .func = 4 },
191 { .pin = 15, .func = 4 },
192 { .pin = 12, .func = 5 },
193 { .pin = 13, .func = 5 },
194 { .pin = 14, .func = 5 },
195 { .pin = 15, .func = 5 },
196};
197
198static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
199 { .pin = 0, .func = 1 },
200 { .pin = 1, .func = 1 },
201 { .pin = 2, .func = 1 },
202 { .pin = 3, .func = 1 },
203 { .pin = 4, .func = 1 },
204 { .pin = 5, .func = 1 },
205 { .pin = 6, .func = 1 },
206 { .pin = 7, .func = 1 },
207 { .pin = 8, .func = 1 },
208 { .pin = 9, .func = 1 },
209 { .pin = 10, .func = 1 },
210 { .pin = 11, .func = 1 },
211 { .pin = 12, .func = 1 },
212 { .pin = 13, .func = 1 },
213 { .pin = 14, .func = 1 },
214 { .pin = 15, .func = 1 },
215};
216
217static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
218 { .pin = 13, .func = 3 },
219};
220
221static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
222 { .pin = 8, .func = 3 },
223 { .pin = 9, .func = 3 },
224 { .pin = 10, .func = 3 },
225 { .pin = 11, .func = 3 },
226 { .pin = 14, .func = 2 },
227 { .pin = 15, .func = 2 },
228 { .pin = 14, .func = 3 },
229 { .pin = 15, .func = 3 },
230};
231
232static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
233 { .pin = 0, .func = 2 },
234 { .pin = 1, .func = 2 },
235 { .pin = 4, .func = 2 },
236 { .pin = 5, .func = 2 },
237 { .pin = 6, .func = 2 },
238 { .pin = 7, .func = 2 },
239};
240
241static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
242 { .pin = 6, .func = 2 },
243 { .pin = 7, .func = 2 },
244 { .pin = 9, .func = 2 },
245 { .pin = 6, .func = 4 },
246 { .pin = 7, .func = 4 },
247 { .pin = 9, .func = 4 },
248 { .pin = 10, .func = 2 },
249 { .pin = 11, .func = 2 },
250 { .pin = 10, .func = 4 },
251 { .pin = 11, .func = 4 },
252 { .pin = 12, .func = 4 },
253 { .pin = 13, .func = 4 },
254 { .pin = 14, .func = 4 },
255 { .pin = 15, .func = 4 },
256};
257
258static const struct rza1_swio_pin rza1h_swio_pins[] = {
259 { .port = 2, .pin = 7, .func = 4, .input = 0 },
260 { .port = 2, .pin = 11, .func = 4, .input = 0 },
261 { .port = 3, .pin = 7, .func = 3, .input = 0 },
262 { .port = 3, .pin = 7, .func = 8, .input = 0 },
263 { .port = 4, .pin = 7, .func = 5, .input = 0 },
264 { .port = 4, .pin = 7, .func = 11, .input = 0 },
265 { .port = 4, .pin = 15, .func = 6, .input = 0 },
266 { .port = 5, .pin = 0, .func = 1, .input = 1 },
267 { .port = 5, .pin = 1, .func = 1, .input = 1 },
268 { .port = 5, .pin = 2, .func = 1, .input = 1 },
269 { .port = 5, .pin = 3, .func = 1, .input = 1 },
270 { .port = 5, .pin = 4, .func = 1, .input = 1 },
271 { .port = 5, .pin = 5, .func = 1, .input = 1 },
272 { .port = 5, .pin = 6, .func = 1, .input = 1 },
273 { .port = 5, .pin = 7, .func = 1, .input = 1 },
274 { .port = 7, .pin = 4, .func = 6, .input = 0 },
275 { .port = 7, .pin = 11, .func = 2, .input = 0 },
276 { .port = 8, .pin = 10, .func = 8, .input = 0 },
277 { .port = 10, .pin = 15, .func = 2, .input = 0 },
278};
279
280static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
281 [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
282 [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
283 [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
284 [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
285 [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
286 [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
287 [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
288 [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
289 [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
290};
291
292static const struct rza1_swio_entry rza1h_swio_entries[] = {
293 [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
294};
295
296/* RZ/A1H (r7s72100x) pinmux flags table */
297static const struct rza1_pinmux_conf rza1h_pmx_conf = {
298 .bidir_entries = rza1h_bidir_entries,
299 .swio_entries = rza1h_swio_entries,
300};
301
039bc58e
CB		 302/* ----------------------------------------------------------------------------
303 * RZ/A1L (r7s72102) pinmux flags
304 */
305
306static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
307 { .pin = 0, .func = 1 },
308 { .pin = 1, .func = 1 },
309 { .pin = 2, .func = 1 },
310 { .pin = 3, .func = 1 },
311 { .pin = 4, .func = 1 },
312 { .pin = 5, .func = 1 },
313 { .pin = 6, .func = 1 },
314 { .pin = 7, .func = 1 },
315};
316
317static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
318 { .pin = 0, .func = 2 },
319 { .pin = 1, .func = 2 },
320 { .pin = 2, .func = 2 },
321 { .pin = 4, .func = 2 },
322 { .pin = 5, .func = 2 },
323 { .pin = 10, .func = 2 },
324 { .pin = 11, .func = 2 },
325 { .pin = 12, .func = 2 },
326 { .pin = 13, .func = 2 },
327};
328
329static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
330 { .pin = 1, .func = 4 },
331 { .pin = 2, .func = 2 },
332 { .pin = 3, .func = 2 },
333 { .pin = 6, .func = 2 },
334 { .pin = 7, .func = 2 },
335};
336
337static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
338 { .pin = 0, .func = 1 },
339 { .pin = 1, .func = 1 },
340 { .pin = 2, .func = 1 },
341 { .pin = 3, .func = 1 },
342 { .pin = 4, .func = 1 },
343 { .pin = 5, .func = 1 },
344 { .pin = 6, .func = 1 },
345 { .pin = 7, .func = 1 },
346 { .pin = 8, .func = 1 },
347 { .pin = 9, .func = 1 },
348 { .pin = 10, .func = 1 },
349 { .pin = 11, .func = 1 },
350 { .pin = 12, .func = 1 },
351 { .pin = 13, .func = 1 },
352 { .pin = 14, .func = 1 },
353 { .pin = 15, .func = 1 },
354 { .pin = 0, .func = 2 },
355 { .pin = 1, .func = 2 },
356 { .pin = 2, .func = 2 },
357 { .pin = 3, .func = 2 },
358};
359
360static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
361 { .pin = 0, .func = 1 },
362 { .pin = 1, .func = 1 },
363 { .pin = 2, .func = 1 },
364 { .pin = 3, .func = 1 },
365 { .pin = 4, .func = 1 },
366 { .pin = 5, .func = 1 },
367 { .pin = 6, .func = 1 },
368 { .pin = 7, .func = 1 },
369 { .pin = 8, .func = 1 },
370 { .pin = 9, .func = 1 },
371 { .pin = 10, .func = 1 },
372 { .pin = 11, .func = 1 },
373 { .pin = 12, .func = 1 },
374 { .pin = 13, .func = 1 },
375 { .pin = 14, .func = 1 },
376 { .pin = 15, .func = 1 },
377};
378
379static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
380 { .pin = 2, .func = 2 },
381 { .pin = 3, .func = 2 },
382 { .pin = 5, .func = 2 },
383 { .pin = 6, .func = 2 },
384 { .pin = 7, .func = 2 },
385 { .pin = 2, .func = 3 },
386 { .pin = 3, .func = 3 },
387 { .pin = 5, .func = 3 },
388 { .pin = 6, .func = 3 },
389 { .pin = 7, .func = 3 },
390};
391
392static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
393 { .pin = 1, .func = 2 },
394 { .pin = 0, .func = 3 },
395 { .pin = 1, .func = 3 },
396 { .pin = 3, .func = 3 },
397 { .pin = 4, .func = 3 },
398 { .pin = 5, .func = 3 },
399};
400
401static const struct rza1_swio_pin rza1l_swio_pins[] = {
402 { .port = 2, .pin = 8, .func = 2, .input = 0 },
403 { .port = 5, .pin = 6, .func = 3, .input = 0 },
404 { .port = 6, .pin = 6, .func = 3, .input = 0 },
405 { .port = 6, .pin = 10, .func = 3, .input = 0 },
406 { .port = 7, .pin = 10, .func = 2, .input = 0 },
407 { .port = 8, .pin = 2, .func = 3, .input = 0 },
408};
409
410static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
411 [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
412 [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
413 [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
414 [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
415 [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
416 [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
417 [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
418};
419
420static const struct rza1_swio_entry rza1l_swio_entries[] = {
421 [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
422};
423
424/* RZ/A1L (r7s72102x) pinmux flags table */
425static const struct rza1_pinmux_conf rza1l_pmx_conf = {
426 .bidir_entries = rza1l_bidir_entries,
427 .swio_entries = rza1l_swio_entries,
428};
429
5a49b644
JM		 430/* ----------------------------------------------------------------------------
431 * RZ/A1 types
432 */
433/**
434 * rza1_mux_conf - describes a pin multiplexing operation
435 *
436 * @id: the pin identifier from 0 to RZA1_NPINS
437 * @port: the port where pin sits on
438 * @pin: pin id
439 * @mux_func: alternate function id number
440 * @mux_flags: alternate function flags
441 * @value: output value to set the pin to
442 */
443struct rza1_mux_conf {
444 u16 id;
445 u8 port;
446 u8 pin;
447 u8 mux_func;
448 u8 mux_flags;
449 u8 value;
450};
451
452/**
453 * rza1_port - describes a pin port
454 *
455 * This is mostly useful to lock register writes per-bank and not globally.
456 *
457 * @lock: protect access to HW registers
458 * @id: port number
459 * @base: logical address base
460 * @pins: pins sitting on this port
461 */
462struct rza1_port {
463 spinlock_t lock;
464 unsigned int id;
465 void __iomem *base;
466 struct pinctrl_pin_desc *pins;
467};
468
469/**
470 * rza1_pinctrl - RZ pincontroller device
471 *
472 * @dev: parent device structure
473 * @mutex: protect [pinctrl|pinmux]_generic functions
474 * @base: logical address base
475 * @nports: number of pin controller ports
476 * @ports: pin controller banks
477 * @pins: pin array for pinctrl core
478 * @desc: pincontroller desc for pinctrl core
479 * @pctl: pinctrl device
480 * @data: device specific data
481 */
482struct rza1_pinctrl {
483 struct device *dev;
484
485 struct mutex mutex;
486
487 void __iomem *base;
488
489 unsigned int nport;
490 struct rza1_port *ports;
491
492 struct pinctrl_pin_desc *pins;
493 struct pinctrl_desc desc;
494 struct pinctrl_dev *pctl;
495
496 const void *data;
497};
498
499/* ----------------------------------------------------------------------------
500 * RZ/A1 pinmux flags
501 */
502static inline bool rza1_pinmux_get_bidir(unsigned int port,
503 unsigned int pin,
504 unsigned int func,
505 const struct rza1_bidir_entry *table)
506{
507 const struct rza1_bidir_entry *entry = &table[port];
508 const struct rza1_bidir_pin *bidir_pin;
509 unsigned int i;
510
511 for (i = 0; i < entry->npins; ++i) {
512 bidir_pin = &entry->pins[i];
513 if (bidir_pin->pin == pin && bidir_pin->func == func)
514 return true;
515 }
516
517 return false;
518}
519
520static inline int rza1_pinmux_get_swio(unsigned int port,
521 unsigned int pin,
522 unsigned int func,
523 const struct rza1_swio_entry *table)
524{
525 const struct rza1_swio_pin *swio_pin;
526 unsigned int i;
527
528
529 for (i = 0; i < table->npins; ++i) {
530 swio_pin = &table->pins[i];
531 if (swio_pin->port == port && swio_pin->pin == pin &&
532 swio_pin->func == func)
533 return swio_pin->input;
534 }
535
536 return -ENOENT;
537}
538
539/**
540 * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
541 */
542static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
543 unsigned int func,
544 struct rza1_pinctrl *rza1_pctl)
545
546{
547 const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
548 const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
549 const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
550 unsigned int pmx_flags = 0;
551 int ret;
552
553 if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
554 pmx_flags |= MUX_FLAGS_BIDIR;
555
556 ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
557 if (ret == 0)
558 pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
559 else if (ret > 0)
560 pmx_flags |= MUX_FLAGS_SWIO_INPUT;
561
562 return pmx_flags;
563}
564
565/* ----------------------------------------------------------------------------
566 * RZ/A1 SoC operations
567 */
568
569/**
570 * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
571 * registers
572 */
573static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
574 unsigned int bit, bool set)
575{
576 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
577 u16 val = ioread16(mem);
578
579 if (set)
580 val |= BIT(bit);
581 else
582 val &= ~BIT(bit);
583
584 iowrite16(val, mem);
585}
586
587static inline unsigned int rza1_get_bit(struct rza1_port *port,
588 unsigned int reg, unsigned int bit)
589{
590 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
591
592 return ioread16(mem) & BIT(bit);
593}
594
595/**
596 * rza1_pin_reset() - reset a pin to default initial state
597 *
598 * Reset pin state disabling input buffer and bi-directional control,
599 * and configure it as input port.
600 * Note that pin is now configured with direction as input but with input
601 * buffer disabled. This implies the pin value cannot be read in this state.
602 *
603 * @port: port where pin sits on
604 * @pin: pin offset
605 */
606static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
607{
608 unsigned long irqflags;
609
610 spin_lock_irqsave(&port->lock, irqflags);
611 rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
612 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
613
614 rza1_set_bit(port, RZA1_PM_REG, pin, 1);
615 rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
616 rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
617 spin_unlock_irqrestore(&port->lock, irqflags);
618}
619
620static inline int rza1_pin_get_direction(struct rza1_port *port,
621 unsigned int pin)
622{
623 unsigned long irqflags;
624 int input;
625
626 spin_lock_irqsave(&port->lock, irqflags);
627 input = rza1_get_bit(port, RZA1_PM_REG, pin);
628 spin_unlock_irqrestore(&port->lock, irqflags);
629
630 return !!input;
631}
632
633/**
634 * rza1_pin_set_direction() - set I/O direction on a pin in port mode
635 *
636 * When running in output port mode keep PBDC enabled to allow reading the
637 * pin value from PPR.
638 *
639 * @port: port where pin sits on
640 * @pin: pin offset
641 * @input: input enable/disable flag
642 */
643static inline void rza1_pin_set_direction(struct rza1_port *port,
644 unsigned int pin, bool input)
645{
646 unsigned long irqflags;
647
648 spin_lock_irqsave(&port->lock, irqflags);
649
650 rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
651 if (input) {
652 rza1_set_bit(port, RZA1_PM_REG, pin, 1);
653 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
654 } else {
655 rza1_set_bit(port, RZA1_PM_REG, pin, 0);
656 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
657 }
658
659 spin_unlock_irqrestore(&port->lock, irqflags);
660}
661
662static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
663 unsigned int value)
664{
665 unsigned long irqflags;
666
667 spin_lock_irqsave(&port->lock, irqflags);
668 rza1_set_bit(port, RZA1_P_REG, pin, !!value);
669 spin_unlock_irqrestore(&port->lock, irqflags);
670}
671
672static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
673{
674 unsigned long irqflags;
675 int val;
676
677 spin_lock_irqsave(&port->lock, irqflags);
678 val = rza1_get_bit(port, RZA1_PPR_REG, pin);
679 spin_unlock_irqrestore(&port->lock, irqflags);
680
681 return val;
682}
683
684/**
685 * rza1_pin_mux_single() - configure pin multiplexing on a single pin
686 *
687 * @pinctrl: RZ/A1 pin controller device
688 * @mux_conf: pin multiplexing descriptor
689 */
690static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
691 struct rza1_mux_conf *mux_conf)
692{
693 struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
694 unsigned int pin = mux_conf->pin;
695 u8 mux_func = mux_conf->mux_func;
696 u8 mux_flags = mux_conf->mux_flags;
697 u8 mux_flags_from_table;
698
699 rza1_pin_reset(port, pin);
700
701 /* SWIO pinmux flags coming from DT are high precedence */
702 mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
703 rza1_pctl);
704 if (mux_flags)
705 mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
706 else
707 mux_flags = mux_flags_from_table;
708
709 if (mux_flags & MUX_FLAGS_BIDIR)
710 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
711
712 /*
713 * Enable alternate function mode and select it.
714 *
715 * Be careful here: the pin mux sub-nodes in device tree
716 * enumerate alternate functions from 1 to 8;
717 * subtract 1 before using macros to match registers configuration
718 * which expects numbers from 0 to 7 instead.
719 *
720 * ----------------------------------------------------
721 * Alternate mode selection table:
722 *
723 * PMC PFC PFCE PFCAE (mux_func - 1)
724 * 1 0 0 0 0
725 * 1 1 0 0 1
726 * 1 0 1 0 2
727 * 1 1 1 0 3
728 * 1 0 0 1 4
729 * 1 1 0 1 5
730 * 1 0 1 1 6
731 * 1 1 1 1 7
732 * ----------------------------------------------------
733 */
734 mux_func -= 1;
735 rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
736 rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
737 rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
738
739 /*
740 * All alternate functions except a few need PIPCn = 1.
741 * If PIPCn has to stay disabled (SW IO mode), configure PMn according
742 * to I/O direction specified by pin configuration -after- PMC has been
743 * set to one.
744 */
745 if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
746 rza1_set_bit(port, RZA1_PM_REG, pin,
747 mux_flags & MUX_FLAGS_SWIO_INPUT);
748 else
749 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
750
751 rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
752
753 return 0;
754}
755
756/* ----------------------------------------------------------------------------
757 * gpio operations
758 */
759
760/**
761 * rza1_gpio_request() - configure pin in port mode
762 *
763 * Configure a pin as gpio (port mode).
764 * After reset, the pin is in input mode with input buffer disabled.
765 * To use the pin as input or output, set_direction shall be called first
766 *
767 * @chip: gpio chip where the gpio sits on
768 * @gpio: gpio offset
769 */
770static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
771{
772 struct rza1_port *port = gpiochip_get_data(chip);
773
774 rza1_pin_reset(port, gpio);
775
776 return 0;
777}
778
779/**
780 * rza1_gpio_disable_free() - reset a pin
781 *
782 * Surprisingly, disable_free a gpio, is equivalent to request it.
783 * Reset pin to port mode, with input buffer disabled. This overwrites all
784 * port direction settings applied with set_direction
785 *
786 * @chip: gpio chip where the gpio sits on
787 * @gpio: gpio offset
788 */
789static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
790{
791 struct rza1_port *port = gpiochip_get_data(chip);
792
793 rza1_pin_reset(port, gpio);
794}
795
796static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
797{
798 struct rza1_port *port = gpiochip_get_data(chip);
799
800 return rza1_pin_get_direction(port, gpio);
801}
802
803static int rza1_gpio_direction_input(struct gpio_chip *chip,
804 unsigned int gpio)
805{
806 struct rza1_port *port = gpiochip_get_data(chip);
807
808 rza1_pin_set_direction(port, gpio, true);
809
810 return 0;
811}
812
813static int rza1_gpio_direction_output(struct gpio_chip *chip,
814 unsigned int gpio,
815 int value)
816{
817 struct rza1_port *port = gpiochip_get_data(chip);
818
819 /* Set value before driving pin direction */
820 rza1_pin_set(port, gpio, value);
821 rza1_pin_set_direction(port, gpio, false);
822
823 return 0;
824}
825
826/**
827 * rza1_gpio_get() - read a gpio pin value
828 *
829 * Read gpio pin value through PPR register.
830 * Requires bi-directional mode to work when reading the value of a pin
831 * in output mode
832 *
833 * @chip: gpio chip where the gpio sits on
834 * @gpio: gpio offset
835 */
836static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
837{
838 struct rza1_port *port = gpiochip_get_data(chip);
839
840 return rza1_pin_get(port, gpio);
841}
842
843static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
844 int value)
845{
846 struct rza1_port *port = gpiochip_get_data(chip);
847
848 rza1_pin_set(port, gpio, value);
849}
850
fa39210d 851static const struct gpio_chip rza1_gpiochip_template = {
5a49b644
JM		 852 .request = rza1_gpio_request,
853 .free = rza1_gpio_free,
854 .get_direction = rza1_gpio_get_direction,
855 .direction_input = rza1_gpio_direction_input,
856 .direction_output = rza1_gpio_direction_output,
857 .get = rza1_gpio_get,
858 .set = rza1_gpio_set,
859};
860/* ----------------------------------------------------------------------------
861 * pinctrl operations
862 */
863
864/**
865 * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
866 * children sub-nodes
867 *
868 * @np: device tree node to parse
869 */
870static int rza1_dt_node_pin_count(struct device_node *np)
871{
872 struct device_node *child;
873 struct property *of_pins;
874 unsigned int npins;
875
876 of_pins = of_find_property(np, "pinmux", NULL);
877 if (of_pins)
878 return of_pins->length / sizeof(u32);
879
880 npins = 0;
881 for_each_child_of_node(np, child) {
882 of_pins = of_find_property(child, "pinmux", NULL);
883 if (!of_pins)
884 return -EINVAL;
885
886 npins += of_pins->length / sizeof(u32);
887 }
888
889 return npins;
890}
891
892/**
893 * rza1_parse_pmx_function() - parse a pin mux sub-node
894 *
895 * @rza1_pctl: RZ/A1 pin controller device
896 * @np: of pmx sub-node
897 * @mux_confs: array of pin mux configurations to fill with parsed info
898 * @grpins: array of pin ids to mux
899 */
900static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
901 struct device_node *np,
902 struct rza1_mux_conf *mux_confs,
903 unsigned int *grpins)
904{
905 struct pinctrl_dev *pctldev = rza1_pctl->pctl;
906 char const *prop_name = "pinmux";
907 unsigned long *pin_configs;
908 unsigned int npin_configs;
909 struct property *of_pins;
910 unsigned int npins;
911 u8 pinmux_flags;
912 unsigned int i;
913 int ret;
914
915 of_pins = of_find_property(np, prop_name, NULL);
916 if (!of_pins) {
917 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
918 return -ENOENT;
919 }
920 npins = of_pins->length / sizeof(u32);
921
922 /*
923 * Collect pin configuration properties: they apply to all pins in
924 * this sub-node
925 */
926 ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
927 &npin_configs);
928 if (ret) {
929 dev_err(rza1_pctl->dev,
94f4e54c
RH		 930 "Unable to parse pin configuration options for %pOFn\n",
931 np);
5a49b644
JM		 932 return ret;
933 }
934
935 /*
936 * Create a mask with pinmux flags from pin configuration;
937 * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
938 * specified in device tree.
939 */
940 pinmux_flags = 0;
941 for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
942 switch (pinconf_to_config_param(pin_configs[i])) {
943 case PIN_CONFIG_INPUT_ENABLE:
944 pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
945 break;
946 case PIN_CONFIG_OUTPUT:
947 pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
948 default:
949 break;
950
951 }
952
953 kfree(pin_configs);
954
955 /* Collect pin positions and their mux settings. */
956 for (i = 0; i < npins; ++i) {
957 u32 of_pinconf;
958 struct rza1_mux_conf *mux_conf = &mux_confs[i];
959
960 ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
961 if (ret)
962 return ret;
963
964 mux_conf->id = of_pinconf & MUX_PIN_ID_MASK;
965 mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id);
966 mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id);
967 mux_conf->mux_func = MUX_FUNC(of_pinconf);
968 mux_conf->mux_flags = pinmux_flags;
969
970 if (mux_conf->port >= RZA1_NPORTS ||
971 mux_conf->pin >= RZA1_PINS_PER_PORT) {
972 dev_err(rza1_pctl->dev,
973 "Wrong port %u pin %u for %s property\n",
974 mux_conf->port, mux_conf->pin, prop_name);
975 return -EINVAL;
976 }
977
978 grpins[i] = mux_conf->id;
979 }
980
981 return npins;
982}
983
984/**
985 * rza1_dt_node_to_map() - map a pin mux node to a function/group
986 *
987 * Parse and register a pin mux function.
988 *
989 * @pctldev: pin controller device
990 * @np: device tree node to parse
991 * @map: pointer to pin map (output)
992 * @num_maps: number of collected maps (output)
993 */
994static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
995 struct device_node *np,
996 struct pinctrl_map **map,
997 unsigned int *num_maps)
998{
999 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1000 struct rza1_mux_conf *mux_confs, *mux_conf;
1001 unsigned int *grpins, *grpin;
1002 struct device_node *child;
1003 const char *grpname;
1004 const char **fngrps;
1005 int ret, npins;
dc4003d2 1006 int gsel, fsel;
5a49b644
JM		 1007
1008 npins = rza1_dt_node_pin_count(np);
1009 if (npins < 0) {
1010 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
1011 return -EINVAL;
1012 }
1013
1014 /*
1015 * Functions are made of 1 group only;
1016 * in fact, functions and groups are identical for this pin controller
1017 * except that functions carry an array of per-pin mux configuration
1018 * settings.
1019 */
1020 mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
1021 GFP_KERNEL);
1022 grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
1023 GFP_KERNEL);
1024 fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
1025
1026 if (!mux_confs || !grpins || !fngrps)
1027 return -ENOMEM;
1028
1029 /*
1030 * Parse the pinmux node.
1031 * If the node does not contain "pinmux" property (-ENOENT)
1032 * that property shall be specified in all its children sub-nodes.
1033 */
1034 mux_conf = &mux_confs[0];
1035 grpin = &grpins[0];
1036
1037 ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
1038 if (ret == -ENOENT)
1039 for_each_child_of_node(np, child) {
1040 ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
1041 grpin);
1042 if (ret < 0)
1043 return ret;
1044
1045 grpin += ret;
1046 mux_conf += ret;
1047 }
1048 else if (ret < 0)
1049 return ret;
1050
1051 /* Register pin group and function name to pinctrl_generic */
1052 grpname = np->name;
1053 fngrps[0] = grpname;
1054
1055 mutex_lock(&rza1_pctl->mutex);
dc4003d2
TL		 1056 gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
1057 NULL);
1058 if (gsel < 0) {
5a49b644 1059 mutex_unlock(&rza1_pctl->mutex);
dc4003d2 1060 return gsel;
5a49b644
JM		 1061 }
1062
dc4003d2
TL		 1063 fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
1064 mux_confs);
1065 if (fsel < 0) {
1066 ret = fsel;
5a49b644 1067 goto remove_group;
dc4003d2 1068 }
5a49b644
JM		 1069
1070 dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
1071 grpname, npins);
1072
1073 /* Create map where to retrieve function and mux settings from */
1074 *num_maps = 0;
1075 *map = kzalloc(sizeof(**map), GFP_KERNEL);
1076 if (!*map) {
1077 ret = -ENOMEM;
1078 goto remove_function;
1079 }
1080
1081 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1082 (*map)->data.mux.group = np->name;
1083 (*map)->data.mux.function = np->name;
1084 *num_maps = 1;
dc4003d2 1085 mutex_unlock(&rza1_pctl->mutex);
5a49b644
JM		 1086
1087 return 0;
1088
1089remove_function:
dc4003d2 1090 pinmux_generic_remove_function(pctldev, fsel);
5a49b644
JM		 1091
1092remove_group:
dc4003d2 1093 pinctrl_generic_remove_group(pctldev, gsel);
5a49b644
JM		 1094 mutex_unlock(&rza1_pctl->mutex);
1095
1096 dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
1097 grpname);
1098
1099 return ret;
1100}
1101
1102static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
1103 struct pinctrl_map *map, unsigned int num_maps)
1104{
1105 kfree(map);
1106}
1107
1108static const struct pinctrl_ops rza1_pinctrl_ops = {
1109 .get_groups_count = pinctrl_generic_get_group_count,
1110 .get_group_name = pinctrl_generic_get_group_name,
1111 .get_group_pins = pinctrl_generic_get_group_pins,
1112 .dt_node_to_map = rza1_dt_node_to_map,
1113 .dt_free_map = rza1_dt_free_map,
1114};
1115
1116/* ----------------------------------------------------------------------------
1117 * pinmux operations
1118 */
1119
1120/**
1121 * rza1_set_mux() - retrieve pins from a group and apply their mux settings
1122 *
1123 * @pctldev: pin controller device
1124 * @selector: function selector
1125 * @group: group selector
1126 */
1127static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1128 unsigned int group)
1129{
1130 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1131 struct rza1_mux_conf *mux_confs;
1132 struct function_desc *func;
1133 struct group_desc *grp;
1134 int i;
1135
1136 grp = pinctrl_generic_get_group(pctldev, group);
1137 if (!grp)
1138 return -EINVAL;
1139
1140 func = pinmux_generic_get_function(pctldev, selector);
1141 if (!func)
1142 return -EINVAL;
1143
1144 mux_confs = (struct rza1_mux_conf *)func->data;
1145 for (i = 0; i < grp->num_pins; ++i) {
1146 int ret;
1147
1148 ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
1149 if (ret)
1150 return ret;
1151 }
1152
1153 return 0;
1154}
1155
b82bfae1 1156static const struct pinmux_ops rza1_pinmux_ops = {
5a49b644
JM		 1157 .get_functions_count = pinmux_generic_get_function_count,
1158 .get_function_name = pinmux_generic_get_function_name,
1159 .get_function_groups = pinmux_generic_get_function_groups,
1160 .set_mux = rza1_set_mux,
1161 .strict = true,
1162};
1163
1164/* ----------------------------------------------------------------------------
1165 * RZ/A1 pin controller driver operations
1166 */
1167
1168static unsigned int rza1_count_gpio_chips(struct device_node *np)
1169{
1170 struct device_node *child;
1171 unsigned int count = 0;
1172
1173 for_each_child_of_node(np, child) {
1174 if (!of_property_read_bool(child, "gpio-controller"))
1175 continue;
1176
1177 count++;
1178 }
1179
1180 return count;
1181}
1182
1183/**
1184 * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1185 *
1186 * The gpio controller subnode shall provide a "gpio-ranges" list property as
1187 * defined by gpio device tree binding documentation.
1188 *
1189 * @rza1_pctl: RZ/A1 pin controller device
1190 * @np: of gpio-controller node
1191 * @chip: gpio chip to register to gpiolib
1192 * @range: pin range to register to pinctrl core
1193 */
1194static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
1195 struct device_node *np,
1196 struct gpio_chip *chip,
1197 struct pinctrl_gpio_range *range)
1198{
1199 const char *list_name = "gpio-ranges";
1200 struct of_phandle_args of_args;
1201 unsigned int gpioport;
1202 u32 pinctrl_base;
1203 int ret;
1204
1205 ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
1206 if (ret) {
1207 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
1208 list_name);
1209 return ret;
1210 }
1211
1212 /*
1213 * Find out on which port this gpio-chip maps to by inspecting the
1214 * second argument of the "gpio-ranges" property.
1215 */
1216 pinctrl_base = of_args.args[1];
1217 gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
faaaba06 1218 if (gpioport >= RZA1_NPORTS) {
5a49b644
JM		 1219 dev_err(rza1_pctl->dev,
1220 "Invalid values in property %s\n", list_name);
1221 return -EINVAL;
1222 }
1223
1224 *chip = rza1_gpiochip_template;
1225 chip->base = -1;
94f4e54c
RH		 1226 chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pOFn",
1227 np);
5a49b644
JM		 1228 chip->ngpio = of_args.args[2];
1229 chip->of_node = np;
1230 chip->parent = rza1_pctl->dev;
1231
1232 range->id = gpioport;
1233 range->name = chip->label;
1234 range->pin_base = range->base = pinctrl_base;
1235 range->npins = of_args.args[2];
1236 range->gc = chip;
1237
1238 ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
1239 &rza1_pctl->ports[gpioport]);
1240 if (ret)
1241 return ret;
1242
1243 pinctrl_add_gpio_range(rza1_pctl->pctl, range);
1244
1245 dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
1246 chip->label, chip->ngpio);
1247
1248 return 0;
1249}
1250
1251/**
1252 * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1253 *
1254 * @rza1_pctl: RZ/A1 pin controller device
1255 */
1256static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
1257{
1258 struct device_node *np = rza1_pctl->dev->of_node;
1259 struct pinctrl_gpio_range *gpio_ranges;
1260 struct gpio_chip *gpio_chips;
1261 struct device_node *child;
1262 unsigned int ngpiochips;
1263 unsigned int i;
1264 int ret;
1265
1266 ngpiochips = rza1_count_gpio_chips(np);
1267 if (ngpiochips == 0) {
1268 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
1269 return 0;
1270 }
1271
1272 gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1273 sizeof(*gpio_chips), GFP_KERNEL);
1274 gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1275 sizeof(*gpio_ranges), GFP_KERNEL);
1276 if (!gpio_chips || !gpio_ranges)
1277 return -ENOMEM;
1278
1279 i = 0;
1280 for_each_child_of_node(np, child) {
1281 if (!of_property_read_bool(child, "gpio-controller"))
1282 continue;
1283
1284 ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
1285 &gpio_ranges[i]);
1286 if (ret)
5fd8d051 1287 return ret;
5a49b644
JM		 1288
1289 ++i;
1290 }
1291
1292 dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
1293
1294 return 0;
5a49b644
JM		 1295}
1296
1297/**
1298 * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1299 * them to pinctrl and gpio cores.
1300 *
1301 * @rza1_pctl: RZ/A1 pin controller device
1302 */
1303static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
1304{
1305 struct pinctrl_pin_desc *pins;
1306 struct rza1_port *ports;
1307 unsigned int i;
1308 int ret;
1309
1310 pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
1311 GFP_KERNEL);
1312 ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
1313 GFP_KERNEL);
1314 if (!pins || !ports)
1315 return -ENOMEM;
1316
1317 rza1_pctl->pins = pins;
1318 rza1_pctl->desc.pins = pins;
1319 rza1_pctl->desc.npins = RZA1_NPINS;
1320 rza1_pctl->ports = ports;
1321
1322 for (i = 0; i < RZA1_NPINS; ++i) {
1323 unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
1324 unsigned int port = RZA1_PIN_ID_TO_PORT(i);
1325
1326 pins[i].number = i;
1327 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
1328 "P%u-%u", port, pin);
1329
1330 if (i % RZA1_PINS_PER_PORT == 0) {
1331 /*
1332 * Setup ports;
1333 * they provide per-port lock and logical base address.
1334 */
1335 unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
1336
1337 ports[port_id].id = port_id;
1338 ports[port_id].base = rza1_pctl->base;
1339 ports[port_id].pins = &pins[i];
1340 spin_lock_init(&ports[port_id].lock);
1341 }
1342 }
1343
1344 ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
1345 rza1_pctl, &rza1_pctl->pctl);
1346 if (ret) {
1347 dev_err(rza1_pctl->dev,
1348 "RZ/A1 pin controller registration failed\n");
1349 return ret;
1350 }
1351
1352 ret = pinctrl_enable(rza1_pctl->pctl);
1353 if (ret) {
1354 dev_err(rza1_pctl->dev,
1355 "RZ/A1 pin controller failed to start\n");
1356 return ret;
1357 }
1358
1359 ret = rza1_gpio_register(rza1_pctl);
1360 if (ret) {
1361 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
1362 return ret;
1363 }
1364
1365 return 0;
1366}
1367
1368static int rza1_pinctrl_probe(struct platform_device *pdev)
1369{
1370 struct rza1_pinctrl *rza1_pctl;
1371 struct resource *res;
1372 int ret;
1373
1374 rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
1375 if (!rza1_pctl)
1376 return -ENOMEM;
1377
1378 rza1_pctl->dev = &pdev->dev;
1379
1380 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5a49b644
JM		 1381 rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res);
1382 if (IS_ERR(rza1_pctl->base))
1383 return PTR_ERR(rza1_pctl->base);
1384
1385 mutex_init(&rza1_pctl->mutex);
1386
1387 platform_set_drvdata(pdev, rza1_pctl);
1388
1389 rza1_pctl->desc.name = DRIVER_NAME;
1390 rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
1391 rza1_pctl->desc.pmxops = &rza1_pinmux_ops;
1392 rza1_pctl->desc.owner = THIS_MODULE;
1393 rza1_pctl->data = of_device_get_match_data(&pdev->dev);
1394
1395 ret = rza1_pinctrl_register(rza1_pctl);
1396 if (ret)
1397 return ret;
1398
1399 dev_info(&pdev->dev,
1400 "RZ/A1 pin controller and gpio successfully registered\n");
1401
1402 return 0;
1403}
1404
1405static const struct of_device_id rza1_pinctrl_of_match[] = {
1406 {
039bc58e 1407 /* RZ/A1H, RZ/A1M */
5a49b644
JM		 1408 .compatible = "renesas,r7s72100-ports",
1409 .data = &rza1h_pmx_conf,
1410 },
039bc58e
CB		 1411 {
1412 /* RZ/A1L */
1413 .compatible = "renesas,r7s72102-ports",
1414 .data = &rza1l_pmx_conf,
1415 },
5a49b644
JM		 1416 { }
1417};
1418
1419static struct platform_driver rza1_pinctrl_driver = {
1420 .driver = {
1421 .name = DRIVER_NAME,
1422 .of_match_table = rza1_pinctrl_of_match,
1423 },
1424 .probe = rza1_pinctrl_probe,
1425};
1426
1427static int __init rza1_pinctrl_init(void)
1428{
1429 return platform_driver_register(&rza1_pinctrl_driver);
1430}
1431core_initcall(rza1_pinctrl_init);
1432
1433MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
1434MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
1435MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)