[linux-block.git] / drivers / pinctrl / pinctrl-rockchip.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
 *
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * With some ideas taken from pinctrl-samsung:
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2012 Linaro Ltd
 *		https://www.linaro.org
 *
 * and pinctrl-at91:
 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */

#ifndef _PINCTRL_ROCKCHIP_H
#define _PINCTRL_ROCKCHIP_H

#define RK_GPIO0_A0	0
#define RK_GPIO0_A1	1
#define RK_GPIO0_A2	2
#define RK_GPIO0_A3	3
#define RK_GPIO0_A4	4
#define RK_GPIO0_A5	5
#define RK_GPIO0_A6	6
#define RK_GPIO0_A7	7
#define RK_GPIO0_B0	8
#define RK_GPIO0_B1	9
#define RK_GPIO0_B2	10
#define RK_GPIO0_B3	11
#define RK_GPIO0_B4	12
#define RK_GPIO0_B5	13
#define RK_GPIO0_B6	14
#define RK_GPIO0_B7	15
#define RK_GPIO0_C0	16
#define RK_GPIO0_C1	17
#define RK_GPIO0_C2	18
#define RK_GPIO0_C3	19
#define RK_GPIO0_C4	20
#define RK_GPIO0_C5	21
#define RK_GPIO0_C6	22
#define RK_GPIO0_C7	23
#define RK_GPIO0_D0	24
#define RK_GPIO0_D1	25
#define RK_GPIO0_D2	26
#define RK_GPIO0_D3	27
#define RK_GPIO0_D4	28
#define RK_GPIO0_D5	29
#define RK_GPIO0_D6	30
#define RK_GPIO0_D7	31

#define RK_GPIO1_A0	32
#define RK_GPIO1_A1	33
#define RK_GPIO1_A2	34
#define RK_GPIO1_A3	35
#define RK_GPIO1_A4	36
#define RK_GPIO1_A5	37
#define RK_GPIO1_A6	38
#define RK_GPIO1_A7	39
#define RK_GPIO1_B0	40
#define RK_GPIO1_B1	41
#define RK_GPIO1_B2	42
#define RK_GPIO1_B3	43
#define RK_GPIO1_B4	44
#define RK_GPIO1_B5	45
#define RK_GPIO1_B6	46
#define RK_GPIO1_B7	47
#define RK_GPIO1_C0	48
#define RK_GPIO1_C1	49
#define RK_GPIO1_C2	50
#define RK_GPIO1_C3	51
#define RK_GPIO1_C4	52
#define RK_GPIO1_C5	53
#define RK_GPIO1_C6	54
#define RK_GPIO1_C7	55
#define RK_GPIO1_D0	56
#define RK_GPIO1_D1	57
#define RK_GPIO1_D2	58
#define RK_GPIO1_D3	59
#define RK_GPIO1_D4	60
#define RK_GPIO1_D5	61
#define RK_GPIO1_D6	62
#define RK_GPIO1_D7	63

#define RK_GPIO2_A0	64
#define RK_GPIO2_A1	65
#define RK_GPIO2_A2	66
#define RK_GPIO2_A3	67
#define RK_GPIO2_A4	68
#define RK_GPIO2_A5	69
#define RK_GPIO2_A6	70
#define RK_GPIO2_A7	71
#define RK_GPIO2_B0	72
#define RK_GPIO2_B1	73
#define RK_GPIO2_B2	74
#define RK_GPIO2_B3	75
#define RK_GPIO2_B4	76
#define RK_GPIO2_B5	77
#define RK_GPIO2_B6	78
#define RK_GPIO2_B7	79
#define RK_GPIO2_C0	80
#define RK_GPIO2_C1	81
#define RK_GPIO2_C2	82
#define RK_GPIO2_C3	83
#define RK_GPIO2_C4	84
#define RK_GPIO2_C5	85
#define RK_GPIO2_C6	86
#define RK_GPIO2_C7	87
#define RK_GPIO2_D0	88
#define RK_GPIO2_D1	89
#define RK_GPIO2_D2	90
#define RK_GPIO2_D3	91
#define RK_GPIO2_D4	92
#define RK_GPIO2_D5	93
#define RK_GPIO2_D6	94
#define RK_GPIO2_D7	95

#define RK_GPIO3_A0	96
#define RK_GPIO3_A1	97
#define RK_GPIO3_A2	98
#define RK_GPIO3_A3	99
#define RK_GPIO3_A4	100
#define RK_GPIO3_A5	101
#define RK_GPIO3_A6	102
#define RK_GPIO3_A7	103
#define RK_GPIO3_B0	104
#define RK_GPIO3_B1	105
#define RK_GPIO3_B2	106
#define RK_GPIO3_B3	107
#define RK_GPIO3_B4	108
#define RK_GPIO3_B5	109
#define RK_GPIO3_B6	110
#define RK_GPIO3_B7	111
#define RK_GPIO3_C0	112
#define RK_GPIO3_C1	113
#define RK_GPIO3_C2	114
#define RK_GPIO3_C3	115
#define RK_GPIO3_C4	116
#define RK_GPIO3_C5	117
#define RK_GPIO3_C6	118
#define RK_GPIO3_C7	119
#define RK_GPIO3_D0	120
#define RK_GPIO3_D1	121
#define RK_GPIO3_D2	122
#define RK_GPIO3_D3	123
#define RK_GPIO3_D4	124
#define RK_GPIO3_D5	125
#define RK_GPIO3_D6	126
#define RK_GPIO3_D7	127

#define RK_GPIO4_A0	128
#define RK_GPIO4_A1	129
#define RK_GPIO4_A2	130
#define RK_GPIO4_A3	131
#define RK_GPIO4_A4	132
#define RK_GPIO4_A5	133
#define RK_GPIO4_A6	134
#define RK_GPIO4_A7	135
#define RK_GPIO4_B0	136
#define RK_GPIO4_B1	137
#define RK_GPIO4_B2	138
#define RK_GPIO4_B3	139
#define RK_GPIO4_B4	140
#define RK_GPIO4_B5	141
#define RK_GPIO4_B6	142
#define RK_GPIO4_B7	143
#define RK_GPIO4_C0	144
#define RK_GPIO4_C1	145
#define RK_GPIO4_C2	146
#define RK_GPIO4_C3	147
#define RK_GPIO4_C4	148
#define RK_GPIO4_C5	149
#define RK_GPIO4_C6	150
#define RK_GPIO4_C7	151
#define RK_GPIO4_D0	152
#define RK_GPIO4_D1	153
#define RK_GPIO4_D2	154
#define RK_GPIO4_D3	155
#define RK_GPIO4_D4	156
#define RK_GPIO4_D5	157
#define RK_GPIO4_D6	158
#define RK_GPIO4_D7	159

enum rockchip_pinctrl_type {
	PX30,
	RV1108,
	RK2928,
	RK3066B,
	RK3128,
	RK3188,
	RK3288,
	RK3308,
	RK3368,
	RK3399,
	RK3568,
	RK3588,
};

/**
 * struct rockchip_gpio_regs
 * @port_dr: data register
 * @port_ddr: data direction register
 * @int_en: interrupt enable
 * @int_mask: interrupt mask
 * @int_type: interrupt trigger type, such as high, low, edge trriger type.
 * @int_polarity: interrupt polarity enable register
 * @int_bothedge: interrupt bothedge enable register
 * @int_status: interrupt status register
 * @int_rawstatus: int_status = int_rawstatus & int_mask
 * @debounce: enable debounce for interrupt signal
 * @dbclk_div_en: enable divider for debounce clock
 * @dbclk_div_con: setting for divider of debounce clock
 * @port_eoi: end of interrupt of the port
 * @ext_port: port data from external
 * @version_id: controller version register
 */
struct rockchip_gpio_regs {
	u32 port_dr;
	u32 port_ddr;
	u32 int_en;
	u32 int_mask;
	u32 int_type;
	u32 int_polarity;
	u32 int_bothedge;
	u32 int_status;
	u32 int_rawstatus;
	u32 debounce;
	u32 dbclk_div_en;
	u32 dbclk_div_con;
	u32 port_eoi;
	u32 ext_port;
	u32 version_id;
};

/**
 * struct rockchip_iomux
 * @type: iomux variant using IOMUX_* constants
 * @offset: if initialized to -1 it will be autocalculated, by specifying
 *	    an initial offset value the relevant source offset can be reset
 *	    to a new value for autocalculating the following iomux registers.
 */
struct rockchip_iomux {
	int type;
	int offset;
};

/*
 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
 */
enum rockchip_pin_drv_type {
	DRV_TYPE_IO_DEFAULT = 0,
	DRV_TYPE_IO_1V8_OR_3V0,
	DRV_TYPE_IO_1V8_ONLY,
	DRV_TYPE_IO_1V8_3V0_AUTO,
	DRV_TYPE_IO_3V3_ONLY,
	DRV_TYPE_MAX
};

/*
 * enum type index corresponding to rockchip_pull_list arrays index.
 */
enum rockchip_pin_pull_type {
	PULL_TYPE_IO_DEFAULT = 0,
	PULL_TYPE_IO_1V8_ONLY,
	PULL_TYPE_MAX
};

/**
 * struct rockchip_drv
 * @drv_type: drive strength variant using rockchip_perpin_drv_type
 * @offset: if initialized to -1 it will be autocalculated, by specifying
 *	    an initial offset value the relevant source offset can be reset
 *	    to a new value for autocalculating the following drive strength
 *	    registers. if used chips own cal_drv func instead to calculate
 *	    registers offset, the variant could be ignored.
 */
struct rockchip_drv {
	enum rockchip_pin_drv_type	drv_type;
	int				offset;
};

/**
 * struct rockchip_pin_bank
 * @dev: the pinctrl device bind to the bank
 * @reg_base: register base of the gpio bank
 * @regmap_pull: optional separate register for additional pull settings
 * @clk: clock of the gpio bank
 * @db_clk: clock of the gpio debounce
 * @irq: interrupt of the gpio bank
 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 * @pin_base: first pin number
 * @nr_pins: number of pins in this bank
 * @name: name of the bank
 * @bank_num: number of the bank, to account for holes
 * @iomux: array describing the 4 iomux sources of the bank
 * @drv: array describing the 4 drive strength sources of the bank
 * @pull_type: array describing the 4 pull type sources of the bank
 * @valid: is all necessary information present
 * @of_node: dt node of this bank
 * @drvdata: common pinctrl basedata
 * @domain: irqdomain of the gpio bank
 * @gpio_chip: gpiolib chip
 * @grange: gpio range
 * @slock: spinlock for the gpio bank
 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
 * @recalced_mask: bit mask to indicate a need to recalulate the mask
 * @route_mask: bits describing the routing pins of per bank
 * @deferred_output: gpio output settings to be done after gpio bank probed
 * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
 */
struct rockchip_pin_bank {
	struct device			*dev;
	void __iomem			*reg_base;
	struct regmap			*regmap_pull;
	struct clk			*clk;
	struct clk			*db_clk;
	int				irq;
	u32				saved_masks;
	u32				pin_base;
	u8				nr_pins;
	char				*name;
	u8				bank_num;
	struct rockchip_iomux		iomux[4];
	struct rockchip_drv		drv[4];
	enum rockchip_pin_pull_type	pull_type[4];
	bool				valid;
	struct device_node		*of_node;
	struct rockchip_pinctrl		*drvdata;
	struct irq_domain		*domain;
	struct gpio_chip		gpio_chip;
	struct pinctrl_gpio_range	grange;
	raw_spinlock_t			slock;
	const struct rockchip_gpio_regs	*gpio_regs;
	u32				gpio_type;
	u32				toggle_edge_mode;
	u32				recalced_mask;
	u32				route_mask;
	struct list_head		deferred_pins;
	struct mutex			deferred_lock;
};

/**
 * struct rockchip_mux_recalced_data: represent a pin iomux data.
 * @num: bank number.
 * @pin: pin number.
 * @bit: index at register.
 * @reg: register offset.
 * @mask: mask bit
 */
struct rockchip_mux_recalced_data {
	u8 num;
	u8 pin;
	u32 reg;
	u8 bit;
	u8 mask;
};

enum rockchip_mux_route_location {
	ROCKCHIP_ROUTE_SAME = 0,
	ROCKCHIP_ROUTE_PMU,
	ROCKCHIP_ROUTE_GRF,
};

/**
 * struct rockchip_mux_recalced_data: represent a pin iomux data.
 * @bank_num: bank number.
 * @pin: index at register or used to calc index.
 * @func: the min pin.
 * @route_location: the mux route location (same, pmu, grf).
 * @route_offset: the max pin.
 * @route_val: the register offset.
 */
struct rockchip_mux_route_data {
	u8 bank_num;
	u8 pin;
	u8 func;
	enum rockchip_mux_route_location route_location;
	u32 route_offset;
	u32 route_val;
};

struct rockchip_pin_ctrl {
	struct rockchip_pin_bank	*pin_banks;
	u32				nr_banks;
	u32				nr_pins;
	char				*label;
	enum rockchip_pinctrl_type	type;
	int				grf_mux_offset;
	int				pmu_mux_offset;
	int				grf_drv_offset;
	int				pmu_drv_offset;
	struct rockchip_mux_recalced_data *iomux_recalced;
	u32				niomux_recalced;
	struct rockchip_mux_route_data *iomux_routes;
	u32				niomux_routes;

	int	(*pull_calc_reg)(struct rockchip_pin_bank *bank,
				    int pin_num, struct regmap **regmap,
				    int *reg, u8 *bit);
	int	(*drv_calc_reg)(struct rockchip_pin_bank *bank,
				    int pin_num, struct regmap **regmap,
				    int *reg, u8 *bit);
	int	(*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
				    int pin_num, struct regmap **regmap,
				    int *reg, u8 *bit);
};

struct rockchip_pin_config {
	unsigned int		func;
	unsigned long		*configs;
	unsigned int		nconfigs;
};

enum pin_config_param;

struct rockchip_pin_deferred {
	struct list_head head;
	unsigned int pin;
	enum pin_config_param param;
	u32 arg;
};

/**
 * struct rockchip_pin_group: represent group of pins of a pinmux function.
 * @name: name of the pin group, used to lookup the group.
 * @pins: the pins included in this group.
 * @npins: number of pins included in this group.
 * @data: local pin configuration
 */
struct rockchip_pin_group {
	const char			*name;
	unsigned int			npins;
	unsigned int			*pins;
	struct rockchip_pin_config	*data;
};

/**
 * struct rockchip_pmx_func: represent a pin function.
 * @name: name of the pin function, used to lookup the function.
 * @groups: one or more names of pin groups that provide this function.
 * @ngroups: number of groups included in @groups.
 */
struct rockchip_pmx_func {
	const char		*name;
	const char		**groups;
	u8			ngroups;
};

struct rockchip_pinctrl {
	struct regmap			*regmap_base;
	int				reg_size;
	struct regmap			*regmap_pull;
	struct regmap			*regmap_pmu;
	struct device			*dev;
	struct rockchip_pin_ctrl	*ctrl;
	struct pinctrl_desc		pctl;
	struct pinctrl_dev		*pctl_dev;
	struct rockchip_pin_group	*groups;
	unsigned int			ngroups;
	struct rockchip_pmx_func	*functions;
	unsigned int			nfunctions;
};

#endif
Commit	Line	Data
e1450694 JX	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
	4	*
	5	* Copyright (c) 2013 MundoReader S.L.
	6	* Author: Heiko Stuebner <heiko@sntech.de>
	7	*
	8	* With some ideas taken from pinctrl-samsung:
	9	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	10	* http://www.samsung.com
	11	* Copyright (c) 2012 Linaro Ltd
	12	* https://www.linaro.org
	13	*
	14	* and pinctrl-at91:
	15	* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	16	*/
	17
	18	#ifndef _PINCTRL_ROCKCHIP_H
	19	#define _PINCTRL_ROCKCHIP_H
	20
fdc33eba JX	21	#define RK_GPIO0_A0 0
	22	#define RK_GPIO0_A1 1
	23	#define RK_GPIO0_A2 2
	24	#define RK_GPIO0_A3 3
	25	#define RK_GPIO0_A4 4
	26	#define RK_GPIO0_A5 5
	27	#define RK_GPIO0_A6 6
	28	#define RK_GPIO0_A7 7
	29	#define RK_GPIO0_B0 8
	30	#define RK_GPIO0_B1 9
	31	#define RK_GPIO0_B2 10
	32	#define RK_GPIO0_B3 11
	33	#define RK_GPIO0_B4 12
	34	#define RK_GPIO0_B5 13
	35	#define RK_GPIO0_B6 14
	36	#define RK_GPIO0_B7 15
	37	#define RK_GPIO0_C0 16
	38	#define RK_GPIO0_C1 17
	39	#define RK_GPIO0_C2 18
	40	#define RK_GPIO0_C3 19
	41	#define RK_GPIO0_C4 20
	42	#define RK_GPIO0_C5 21
	43	#define RK_GPIO0_C6 22
	44	#define RK_GPIO0_C7 23
	45	#define RK_GPIO0_D0 24
	46	#define RK_GPIO0_D1 25
	47	#define RK_GPIO0_D2 26
	48	#define RK_GPIO0_D3 27
	49	#define RK_GPIO0_D4 28
	50	#define RK_GPIO0_D5 29
	51	#define RK_GPIO0_D6 30
	52	#define RK_GPIO0_D7 31
	53
	54	#define RK_GPIO1_A0 32
	55	#define RK_GPIO1_A1 33
	56	#define RK_GPIO1_A2 34
	57	#define RK_GPIO1_A3 35
	58	#define RK_GPIO1_A4 36
	59	#define RK_GPIO1_A5 37
	60	#define RK_GPIO1_A6 38
	61	#define RK_GPIO1_A7 39
	62	#define RK_GPIO1_B0 40
	63	#define RK_GPIO1_B1 41
	64	#define RK_GPIO1_B2 42
	65	#define RK_GPIO1_B3 43
	66	#define RK_GPIO1_B4 44
	67	#define RK_GPIO1_B5 45
	68	#define RK_GPIO1_B6 46
	69	#define RK_GPIO1_B7 47
	70	#define RK_GPIO1_C0 48
	71	#define RK_GPIO1_C1 49
	72	#define RK_GPIO1_C2 50
	73	#define RK_GPIO1_C3 51
	74	#define RK_GPIO1_C4 52
	75	#define RK_GPIO1_C5 53
	76	#define RK_GPIO1_C6 54
	77	#define RK_GPIO1_C7 55
	78	#define RK_GPIO1_D0 56
	79	#define RK_GPIO1_D1 57
	80	#define RK_GPIO1_D2 58
	81	#define RK_GPIO1_D3 59
	82	#define RK_GPIO1_D4 60
	83	#define RK_GPIO1_D5 61
	84	#define RK_GPIO1_D6 62
85	#define RK_GPIO1_D7 63
86
87	#define RK_GPIO2_A0 64
88	#define RK_GPIO2_A1 65
89	#define RK_GPIO2_A2 66
90	#define RK_GPIO2_A3 67
91	#define RK_GPIO2_A4 68
92	#define RK_GPIO2_A5 69
93	#define RK_GPIO2_A6 70
94	#define RK_GPIO2_A7 71
95	#define RK_GPIO2_B0 72
96	#define RK_GPIO2_B1 73
97	#define RK_GPIO2_B2 74
98	#define RK_GPIO2_B3 75
99	#define RK_GPIO2_B4 76
100	#define RK_GPIO2_B5 77
101	#define RK_GPIO2_B6 78
102	#define RK_GPIO2_B7 79
103	#define RK_GPIO2_C0 80
104	#define RK_GPIO2_C1 81
105	#define RK_GPIO2_C2 82
106	#define RK_GPIO2_C3 83
107	#define RK_GPIO2_C4 84
108	#define RK_GPIO2_C5 85
109	#define RK_GPIO2_C6 86
110	#define RK_GPIO2_C7 87
111	#define RK_GPIO2_D0 88
112	#define RK_GPIO2_D1 89
113	#define RK_GPIO2_D2 90
114	#define RK_GPIO2_D3 91
115	#define RK_GPIO2_D4 92
116	#define RK_GPIO2_D5 93
117	#define RK_GPIO2_D6 94
118	#define RK_GPIO2_D7 95
119
120	#define RK_GPIO3_A0 96
121	#define RK_GPIO3_A1 97
122	#define RK_GPIO3_A2 98
123	#define RK_GPIO3_A3 99
124	#define RK_GPIO3_A4 100
125	#define RK_GPIO3_A5 101
126	#define RK_GPIO3_A6 102
127	#define RK_GPIO3_A7 103
128	#define RK_GPIO3_B0 104
129	#define RK_GPIO3_B1 105
130	#define RK_GPIO3_B2 106
131	#define RK_GPIO3_B3 107
132	#define RK_GPIO3_B4 108
133	#define RK_GPIO3_B5 109
134	#define RK_GPIO3_B6 110
135	#define RK_GPIO3_B7 111
136	#define RK_GPIO3_C0 112
137	#define RK_GPIO3_C1 113
138	#define RK_GPIO3_C2 114
139	#define RK_GPIO3_C3 115
140	#define RK_GPIO3_C4 116
141	#define RK_GPIO3_C5 117
142	#define RK_GPIO3_C6 118
143	#define RK_GPIO3_C7 119
144	#define RK_GPIO3_D0 120
145	#define RK_GPIO3_D1 121
146	#define RK_GPIO3_D2 122
147	#define RK_GPIO3_D3 123
148	#define RK_GPIO3_D4 124
149	#define RK_GPIO3_D5 125
150	#define RK_GPIO3_D6 126
151	#define RK_GPIO3_D7 127
152
153	#define RK_GPIO4_A0 128
154	#define RK_GPIO4_A1 129
155	#define RK_GPIO4_A2 130
156	#define RK_GPIO4_A3 131
157	#define RK_GPIO4_A4 132
158	#define RK_GPIO4_A5 133
159	#define RK_GPIO4_A6 134
160	#define RK_GPIO4_A7 135
161	#define RK_GPIO4_B0 136
162	#define RK_GPIO4_B1 137
163	#define RK_GPIO4_B2 138
164	#define RK_GPIO4_B3 139
165	#define RK_GPIO4_B4 140
166	#define RK_GPIO4_B5 141
167	#define RK_GPIO4_B6 142
168	#define RK_GPIO4_B7 143
169	#define RK_GPIO4_C0 144
170	#define RK_GPIO4_C1 145
171	#define RK_GPIO4_C2 146
172	#define RK_GPIO4_C3 147
173	#define RK_GPIO4_C4 148
174	#define RK_GPIO4_C5 149
175	#define RK_GPIO4_C6 150
176	#define RK_GPIO4_C7 151
177	#define RK_GPIO4_D0 152
178	#define RK_GPIO4_D1 153
179	#define RK_GPIO4_D2 154
180	#define RK_GPIO4_D3 155
181	#define RK_GPIO4_D4 156
182	#define RK_GPIO4_D5 157
183	#define RK_GPIO4_D6 158
184	#define RK_GPIO4_D7 159
185
e1450694 JX	186	enum rockchip_pinctrl_type {
	187	PX30,
	188	RV1108,
	189	RK2928,
	190	RK3066B,
	191	RK3128,
	192	RK3188,
	193	RK3288,
	194	RK3308,
	195	RK3368,
	196	RK3399,
	197	RK3568,
fdc33eba	198	RK3588,
e1450694 JX	199	};
e1450694 JX	200
ff96a8c2 JX	201	/**
	202	* struct rockchip_gpio_regs
	203	* @port_dr: data register
	204	* @port_ddr: data direction register
	205	* @int_en: interrupt enable
	206	* @int_mask: interrupt mask
	207	* @int_type: interrupt trigger type, such as high, low, edge trriger type.
	208	* @int_polarity: interrupt polarity enable register
	209	* @int_bothedge: interrupt bothedge enable register
	210	* @int_status: interrupt status register
	211	* @int_rawstatus: int_status = int_rawstatus & int_mask
	212	* @debounce: enable debounce for interrupt signal
	213	* @dbclk_div_en: enable divider for debounce clock
	214	* @dbclk_div_con: setting for divider of debounce clock
	215	* @port_eoi: end of interrupt of the port
	216	* @ext_port: port data from external
	217	* @version_id: controller version register
	218	*/
	219	struct rockchip_gpio_regs {
	220	u32 port_dr;
	221	u32 port_ddr;
	222	u32 int_en;
	223	u32 int_mask;
	224	u32 int_type;
	225	u32 int_polarity;
	226	u32 int_bothedge;
	227	u32 int_status;
	228	u32 int_rawstatus;
	229	u32 debounce;
	230	u32 dbclk_div_en;
	231	u32 dbclk_div_con;
	232	u32 port_eoi;
	233	u32 ext_port;
	234	u32 version_id;
	235	};
	236
e1450694 JX	237	/**
	238	* struct rockchip_iomux
	239	* @type: iomux variant using IOMUX_* constants
	240	* @offset: if initialized to -1 it will be autocalculated, by specifying
	241	* an initial offset value the relevant source offset can be reset
	242	* to a new value for autocalculating the following iomux registers.
	243	*/
	244	struct rockchip_iomux {
	245	int type;
	246	int offset;
	247	};
	248
	249	/*
	250	* enum type index corresponding to rockchip_perpin_drv_list arrays index.
	251	*/
	252	enum rockchip_pin_drv_type {
	253	DRV_TYPE_IO_DEFAULT = 0,
	254	DRV_TYPE_IO_1V8_OR_3V0,
	255	DRV_TYPE_IO_1V8_ONLY,
	256	DRV_TYPE_IO_1V8_3V0_AUTO,
	257	DRV_TYPE_IO_3V3_ONLY,
	258	DRV_TYPE_MAX
	259	};
	260
	261	/*
	262	* enum type index corresponding to rockchip_pull_list arrays index.
	263	*/
	264	enum rockchip_pin_pull_type {
	265	PULL_TYPE_IO_DEFAULT = 0,
	266	PULL_TYPE_IO_1V8_ONLY,
	267	PULL_TYPE_MAX
	268	};
	269
	270	/**
	271	* struct rockchip_drv
	272	* @drv_type: drive strength variant using rockchip_perpin_drv_type
	273	* @offset: if initialized to -1 it will be autocalculated, by specifying
	274	* an initial offset value the relevant source offset can be reset
	275	* to a new value for autocalculating the following drive strength
	276	* registers. if used chips own cal_drv func instead to calculate
	277	* registers offset, the variant could be ignored.
	278	*/
	279	struct rockchip_drv {
	280	enum rockchip_pin_drv_type drv_type;
	281	int offset;
	282	};
	283
	284	/**
	285	* struct rockchip_pin_bank
5f82afd8	286	* @dev: the pinctrl device bind to the bank
e1450694 JX	287	* @reg_base: register base of the gpio bank
	288	* @regmap_pull: optional separate register for additional pull settings
	289	* @clk: clock of the gpio bank
3bcbd1a8	290	* @db_clk: clock of the gpio debounce
e1450694 JX	291	* @irq: interrupt of the gpio bank
	292	* @saved_masks: Saved content of GPIO_INTEN at suspend time.
	293	* @pin_base: first pin number
	294	* @nr_pins: number of pins in this bank
	295	* @name: name of the bank
	296	* @bank_num: number of the bank, to account for holes
	297	* @iomux: array describing the 4 iomux sources of the bank
	298	* @drv: array describing the 4 drive strength sources of the bank
	299	* @pull_type: array describing the 4 pull type sources of the bank
	300	* @valid: is all necessary information present
	301	* @of_node: dt node of this bank
	302	* @drvdata: common pinctrl basedata
	303	* @domain: irqdomain of the gpio bank
	304	* @gpio_chip: gpiolib chip
	305	* @grange: gpio range
	306	* @slock: spinlock for the gpio bank
	307	* @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
	308	* @recalced_mask: bit mask to indicate a need to recalulate the mask
	309	* @route_mask: bits describing the routing pins of per bank
e7165b1d HS	310	* @deferred_output: gpio output settings to be done after gpio bank probed
e7165b1d HS	311	* @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
e1450694 JX	312	*/
e1450694 JX	313	struct rockchip_pin_bank {
5f82afd8	314	struct device *dev;
e1450694 JX	315	void __iomem *reg_base;
	316	struct regmap *regmap_pull;
	317	struct clk *clk;
3bcbd1a8	318	struct clk *db_clk;
e1450694 JX	319	int irq;
	320	u32 saved_masks;
	321	u32 pin_base;
	322	u8 nr_pins;
	323	char *name;
	324	u8 bank_num;
	325	struct rockchip_iomux iomux[4];
	326	struct rockchip_drv drv[4];
	327	enum rockchip_pin_pull_type pull_type[4];
	328	bool valid;
	329	struct device_node *of_node;
	330	struct rockchip_pinctrl *drvdata;
	331	struct irq_domain *domain;
	332	struct gpio_chip gpio_chip;
	333	struct pinctrl_gpio_range grange;
	334	raw_spinlock_t slock;
ff96a8c2 JX	335	const struct rockchip_gpio_regs *gpio_regs;
ff96a8c2 JX	336	u32 gpio_type;
e1450694 JX	337	u32 toggle_edge_mode;
	338	u32 recalced_mask;
	339	u32 route_mask;
8ce5ef64	340	struct list_head deferred_pins;
e7165b1d	341	struct mutex deferred_lock;
e1450694 JX	342	};
	343
	344	/**
	345	* struct rockchip_mux_recalced_data: represent a pin iomux data.
	346	* @num: bank number.
	347	* @pin: pin number.
	348	* @bit: index at register.
	349	* @reg: register offset.
	350	* @mask: mask bit
	351	*/
	352	struct rockchip_mux_recalced_data {
	353	u8 num;
	354	u8 pin;
	355	u32 reg;
	356	u8 bit;
	357	u8 mask;
	358	};
	359
	360	enum rockchip_mux_route_location {
	361	ROCKCHIP_ROUTE_SAME = 0,
	362	ROCKCHIP_ROUTE_PMU,
	363	ROCKCHIP_ROUTE_GRF,
	364	};
	365
	366	/**
	367	* struct rockchip_mux_recalced_data: represent a pin iomux data.
	368	* @bank_num: bank number.
	369	* @pin: index at register or used to calc index.
	370	* @func: the min pin.
	371	* @route_location: the mux route location (same, pmu, grf).
	372	* @route_offset: the max pin.
	373	* @route_val: the register offset.
	374	*/
	375	struct rockchip_mux_route_data {
	376	u8 bank_num;
	377	u8 pin;
	378	u8 func;
	379	enum rockchip_mux_route_location route_location;
	380	u32 route_offset;
	381	u32 route_val;
	382	};
	383
	384	struct rockchip_pin_ctrl {
	385	struct rockchip_pin_bank *pin_banks;
	386	u32 nr_banks;
	387	u32 nr_pins;
	388	char *label;
	389	enum rockchip_pinctrl_type type;
	390	int grf_mux_offset;
	391	int pmu_mux_offset;
	392	int grf_drv_offset;
	393	int pmu_drv_offset;
	394	struct rockchip_mux_recalced_data *iomux_recalced;
	395	u32 niomux_recalced;
	396	struct rockchip_mux_route_data *iomux_routes;
	397	u32 niomux_routes;
	398
42573ab3	399	int (pull_calc_reg)(struct rockchip_pin_bank bank,
e1450694 JX	400	int pin_num, struct regmap **regmap,
e1450694 JX	401	int reg, u8 bit);
42573ab3	402	int (drv_calc_reg)(struct rockchip_pin_bank bank,
e1450694 JX	403	int pin_num, struct regmap **regmap,
	404	int reg, u8 bit);
	405	int (schmitt_calc_reg)(struct rockchip_pin_bank bank,
	406	int pin_num, struct regmap **regmap,
	407	int reg, u8 bit);
	408	};
	409
	410	struct rockchip_pin_config {
	411	unsigned int func;
	412	unsigned long *configs;
	413	unsigned int nconfigs;
	414	};
	415
8ce5ef64 CC	416	enum pin_config_param;
	417
	418	struct rockchip_pin_deferred {
e7165b1d HS	419	struct list_head head;
e7165b1d HS	420	unsigned int pin;
8ce5ef64	421	enum pin_config_param param;
e7165b1d HS	422	u32 arg;
	423	};
	424
e1450694 JX	425	/**
	426	* struct rockchip_pin_group: represent group of pins of a pinmux function.
	427	* @name: name of the pin group, used to lookup the group.
	428	* @pins: the pins included in this group.
	429	* @npins: number of pins included in this group.
	430	* @data: local pin configuration
	431	*/
	432	struct rockchip_pin_group {
	433	const char *name;
	434	unsigned int npins;
	435	unsigned int *pins;
	436	struct rockchip_pin_config *data;
	437	};
	438
	439	/**
	440	* struct rockchip_pmx_func: represent a pin function.
	441	* @name: name of the pin function, used to lookup the function.
	442	* @groups: one or more names of pin groups that provide this function.
	443	* @ngroups: number of groups included in @groups.
	444	*/
	445	struct rockchip_pmx_func {
	446	const char *name;
	447	const char **groups;
	448	u8 ngroups;
	449	};
	450
	451	struct rockchip_pinctrl {
	452	struct regmap *regmap_base;
	453	int reg_size;
	454	struct regmap *regmap_pull;
	455	struct regmap *regmap_pmu;
	456	struct device *dev;
	457	struct rockchip_pin_ctrl *ctrl;
	458	struct pinctrl_desc pctl;
	459	struct pinctrl_dev *pctl_dev;
	460	struct rockchip_pin_group *groups;
	461	unsigned int ngroups;
	462	struct rockchip_pmx_func *functions;
	463	unsigned int nfunctions;
	464	};
	465
	466	#endif