[linux-block.git] / drivers / pinctrl / pinctrl-rockchip.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
 *
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * With some ideas taken from pinctrl-samsung:
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2012 Linaro Ltd
 *		https://www.linaro.org
 *
 * and pinctrl-at91:
 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */

#ifndef _PINCTRL_ROCKCHIP_H
#define _PINCTRL_ROCKCHIP_H

#define RK_GPIO0_A0	0
#define RK_GPIO0_A1	1
#define RK_GPIO0_A2	2
#define RK_GPIO0_A3	3
#define RK_GPIO0_A4	4
#define RK_GPIO0_A5	5
#define RK_GPIO0_A6	6
#define RK_GPIO0_A7	7
#define RK_GPIO0_B0	8
#define RK_GPIO0_B1	9
#define RK_GPIO0_B2	10
#define RK_GPIO0_B3	11
#define RK_GPIO0_B4	12
#define RK_GPIO0_B5	13
#define RK_GPIO0_B6	14
#define RK_GPIO0_B7	15
#define RK_GPIO0_C0	16
#define RK_GPIO0_C1	17
#define RK_GPIO0_C2	18
#define RK_GPIO0_C3	19
#define RK_GPIO0_C4	20
#define RK_GPIO0_C5	21
#define RK_GPIO0_C6	22
#define RK_GPIO0_C7	23
#define RK_GPIO0_D0	24
#define RK_GPIO0_D1	25
#define RK_GPIO0_D2	26
#define RK_GPIO0_D3	27
#define RK_GPIO0_D4	28
#define RK_GPIO0_D5	29
#define RK_GPIO0_D6	30
#define RK_GPIO0_D7	31

#define RK_GPIO1_A0	32
#define RK_GPIO1_A1	33
#define RK_GPIO1_A2	34
#define RK_GPIO1_A3	35
#define RK_GPIO1_A4	36
#define RK_GPIO1_A5	37
#define RK_GPIO1_A6	38
#define RK_GPIO1_A7	39
#define RK_GPIO1_B0	40
#define RK_GPIO1_B1	41
#define RK_GPIO1_B2	42
#define RK_GPIO1_B3	43
#define RK_GPIO1_B4	44
#define RK_GPIO1_B5	45
#define RK_GPIO1_B6	46
#define RK_GPIO1_B7	47
#define RK_GPIO1_C0	48
#define RK_GPIO1_C1	49
#define RK_GPIO1_C2	50
#define RK_GPIO1_C3	51
#define RK_GPIO1_C4	52
#define RK_GPIO1_C5	53
#define RK_GPIO1_C6	54
#define RK_GPIO1_C7	55
#define RK_GPIO1_D0	56
#define RK_GPIO1_D1	57
#define RK_GPIO1_D2	58
#define RK_GPIO1_D3	59
#define RK_GPIO1_D4	60
#define RK_GPIO1_D5	61
#define RK_GPIO1_D6	62
#define RK_GPIO1_D7	63

#define RK_GPIO2_A0	64
#define RK_GPIO2_A1	65
#define RK_GPIO2_A2	66
#define RK_GPIO2_A3	67
#define RK_GPIO2_A4	68
#define RK_GPIO2_A5	69
#define RK_GPIO2_A6	70
#define RK_GPIO2_A7	71
#define RK_GPIO2_B0	72
#define RK_GPIO2_B1	73
#define RK_GPIO2_B2	74
#define RK_GPIO2_B3	75
#define RK_GPIO2_B4	76
#define RK_GPIO2_B5	77
#define RK_GPIO2_B6	78
#define RK_GPIO2_B7	79
#define RK_GPIO2_C0	80
#define RK_GPIO2_C1	81
#define RK_GPIO2_C2	82
#define RK_GPIO2_C3	83
#define RK_GPIO2_C4	84
#define RK_GPIO2_C5	85
#define RK_GPIO2_C6	86
#define RK_GPIO2_C7	87
#define RK_GPIO2_D0	88
#define RK_GPIO2_D1	89
#define RK_GPIO2_D2	90
#define RK_GPIO2_D3	91
#define RK_GPIO2_D4	92
#define RK_GPIO2_D5	93
#define RK_GPIO2_D6	94
#define RK_GPIO2_D7	95

#define RK_GPIO3_A0	96
#define RK_GPIO3_A1	97
#define RK_GPIO3_A2	98
#define RK_GPIO3_A3	99
#define RK_GPIO3_A4	100
#define RK_GPIO3_A5	101
#define RK_GPIO3_A6	102
#define RK_GPIO3_A7	103
#define RK_GPIO3_B0	104
#define RK_GPIO3_B1	105
#define RK_GPIO3_B2	106
#define RK_GPIO3_B3	107
#define RK_GPIO3_B4	108
#define RK_GPIO3_B5	109
#define RK_GPIO3_B6	110
#define RK_GPIO3_B7	111
#define RK_GPIO3_C0	112
#define RK_GPIO3_C1	113
#define RK_GPIO3_C2	114
#define RK_GPIO3_C3	115
#define RK_GPIO3_C4	116
#define RK_GPIO3_C5	117
#define RK_GPIO3_C6	118
#define RK_GPIO3_C7	119
#define RK_GPIO3_D0	120
#define RK_GPIO3_D1	121
#define RK_GPIO3_D2	122
#define RK_GPIO3_D3	123
#define RK_GPIO3_D4	124
#define RK_GPIO3_D5	125
#define RK_GPIO3_D6	126
#define RK_GPIO3_D7	127

#define RK_GPIO4_A0	128
#define RK_GPIO4_A1	129
#define RK_GPIO4_A2	130
#define RK_GPIO4_A3	131
#define RK_GPIO4_A4	132
#define RK_GPIO4_A5	133
#define RK_GPIO4_A6	134
#define RK_GPIO4_A7	135
#define RK_GPIO4_B0	136
#define RK_GPIO4_B1	137
#define RK_GPIO4_B2	138
#define RK_GPIO4_B3	139
#define RK_GPIO4_B4	140
#define RK_GPIO4_B5	141
#define RK_GPIO4_B6	142
#define RK_GPIO4_B7	143
#define RK_GPIO4_C0	144
#define RK_GPIO4_C1	145
#define RK_GPIO4_C2	146
#define RK_GPIO4_C3	147
#define RK_GPIO4_C4	148
#define RK_GPIO4_C5	149
#define RK_GPIO4_C6	150
#define RK_GPIO4_C7	151
#define RK_GPIO4_D0	152
#define RK_GPIO4_D1	153
#define RK_GPIO4_D2	154
#define RK_GPIO4_D3	155
#define RK_GPIO4_D4	156
#define RK_GPIO4_D5	157
#define RK_GPIO4_D6	158
#define RK_GPIO4_D7	159

enum rockchip_pinctrl_type {
	PX30,
	RV1108,
	RV1126,
	RK2928,
	RK3066B,
	RK3128,
	RK3188,
	RK3288,
	RK3308,
	RK3368,
	RK3399,
	RK3568,
	RK3588,
};

/**
 * struct rockchip_gpio_regs
 * @port_dr: data register
 * @port_ddr: data direction register
 * @int_en: interrupt enable
 * @int_mask: interrupt mask
 * @int_type: interrupt trigger type, such as high, low, edge trriger type.
 * @int_polarity: interrupt polarity enable register
 * @int_bothedge: interrupt bothedge enable register
 * @int_status: interrupt status register
 * @int_rawstatus: int_status = int_rawstatus & int_mask
 * @debounce: enable debounce for interrupt signal
 * @dbclk_div_en: enable divider for debounce clock
 * @dbclk_div_con: setting for divider of debounce clock
 * @port_eoi: end of interrupt of the port
 * @ext_port: port data from external
 * @version_id: controller version register
 */
struct rockchip_gpio_regs {
	u32 port_dr;
	u32 port_ddr;
	u32 int_en;
	u32 int_mask;
	u32 int_type;
	u32 int_polarity;
	u32 int_bothedge;
	u32 int_status;
	u32 int_rawstatus;
	u32 debounce;
	u32 dbclk_div_en;
	u32 dbclk_div_con;
	u32 port_eoi;
	u32 ext_port;
	u32 version_id;
};

/**
 * struct rockchip_iomux
 * @type: iomux variant using IOMUX_* constants
 * @offset: if initialized to -1 it will be autocalculated, by specifying
 *	    an initial offset value the relevant source offset can be reset
 *	    to a new value for autocalculating the following iomux registers.
 */
struct rockchip_iomux {
	int type;
	int offset;
};

/*
 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
 */
enum rockchip_pin_drv_type {
	DRV_TYPE_IO_DEFAULT = 0,
	DRV_TYPE_IO_1V8_OR_3V0,
	DRV_TYPE_IO_1V8_ONLY,
	DRV_TYPE_IO_1V8_3V0_AUTO,
	DRV_TYPE_IO_3V3_ONLY,
	DRV_TYPE_MAX
};

/*
 * enum type index corresponding to rockchip_pull_list arrays index.
 */
enum rockchip_pin_pull_type {
	PULL_TYPE_IO_DEFAULT = 0,
	PULL_TYPE_IO_1V8_ONLY,
	PULL_TYPE_MAX
};

/**
 * struct rockchip_drv
 * @drv_type: drive strength variant using rockchip_perpin_drv_type
 * @offset: if initialized to -1 it will be autocalculated, by specifying
 *	    an initial offset value the relevant source offset can be reset
 *	    to a new value for autocalculating the following drive strength
 *	    registers. if used chips own cal_drv func instead to calculate
 *	    registers offset, the variant could be ignored.
 */
struct rockchip_drv {
	enum rockchip_pin_drv_type	drv_type;
	int				offset;
};

/**
 * struct rockchip_pin_bank
 * @dev: the pinctrl device bind to the bank
 * @reg_base: register base of the gpio bank
 * @regmap_pull: optional separate register for additional pull settings
 * @clk: clock of the gpio bank
 * @db_clk: clock of the gpio debounce
 * @irq: interrupt of the gpio bank
 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 * @pin_base: first pin number
 * @nr_pins: number of pins in this bank
 * @name: name of the bank
 * @bank_num: number of the bank, to account for holes
 * @iomux: array describing the 4 iomux sources of the bank
 * @drv: array describing the 4 drive strength sources of the bank
 * @pull_type: array describing the 4 pull type sources of the bank
 * @valid: is all necessary information present
 * @of_node: dt node of this bank
 * @drvdata: common pinctrl basedata
 * @domain: irqdomain of the gpio bank
 * @gpio_chip: gpiolib chip
 * @grange: gpio range
 * @slock: spinlock for the gpio bank
 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
 * @recalced_mask: bit mask to indicate a need to recalulate the mask
 * @route_mask: bits describing the routing pins of per bank
 * @deferred_output: gpio output settings to be done after gpio bank probed
 * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
 */
struct rockchip_pin_bank {
	struct device			*dev;
	void __iomem			*reg_base;
	struct regmap			*regmap_pull;
	struct clk			*clk;
	struct clk			*db_clk;
	int				irq;
	u32				saved_masks;
	u32				pin_base;
	u8				nr_pins;
	char				*name;
	u8				bank_num;
	struct rockchip_iomux		iomux[4];
	struct rockchip_drv		drv[4];
	enum rockchip_pin_pull_type	pull_type[4];
	bool				valid;
	struct device_node		*of_node;
	struct rockchip_pinctrl		*drvdata;
	struct irq_domain		*domain;
	struct gpio_chip		gpio_chip;
	struct pinctrl_gpio_range	grange;
	raw_spinlock_t			slock;
	const struct rockchip_gpio_regs	*gpio_regs;
	u32				gpio_type;
	u32				toggle_edge_mode;
	u32				recalced_mask;
	u32				route_mask;
	struct list_head		deferred_pins;
	struct mutex			deferred_lock;
};

/**
 * struct rockchip_mux_recalced_data: represent a pin iomux data.
 * @num: bank number.
 * @pin: pin number.
 * @bit: index at register.
 * @reg: register offset.
 * @mask: mask bit
 */
struct rockchip_mux_recalced_data {
	u8 num;
	u8 pin;
	u32 reg;
	u8 bit;
	u8 mask;
};

enum rockchip_mux_route_location {
	ROCKCHIP_ROUTE_SAME = 0,
	ROCKCHIP_ROUTE_PMU,
	ROCKCHIP_ROUTE_GRF,
};

/**
 * struct rockchip_mux_recalced_data: represent a pin iomux data.
 * @bank_num: bank number.
 * @pin: index at register or used to calc index.
 * @func: the min pin.
 * @route_location: the mux route location (same, pmu, grf).
 * @route_offset: the max pin.
 * @route_val: the register offset.
 */
struct rockchip_mux_route_data {
	u8 bank_num;
	u8 pin;
	u8 func;
	enum rockchip_mux_route_location route_location;
	u32 route_offset;
	u32 route_val;
};

struct rockchip_pin_ctrl {
	struct rockchip_pin_bank	*pin_banks;
	u32				nr_banks;
	u32				nr_pins;
	char				*label;
	enum rockchip_pinctrl_type	type;
	int				grf_mux_offset;
	int				pmu_mux_offset;
	int				grf_drv_offset;
	int				pmu_drv_offset;
	struct rockchip_mux_recalced_data *iomux_recalced;
	u32				niomux_recalced;
	struct rockchip_mux_route_data *iomux_routes;
	u32				niomux_routes;

	int	(*pull_calc_reg)(struct rockchip_pin_bank *bank,
				    int pin_num, struct regmap **regmap,
				    int *reg, u8 *bit);
	int	(*drv_calc_reg)(struct rockchip_pin_bank *bank,
				    int pin_num, struct regmap **regmap,
				    int *reg, u8 *bit);
	int	(*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
				    int pin_num, struct regmap **regmap,
				    int *reg, u8 *bit);
};

struct rockchip_pin_config {
	unsigned int		func;
	unsigned long		*configs;
	unsigned int		nconfigs;
};

enum pin_config_param;

struct rockchip_pin_deferred {
	struct list_head head;
	unsigned int pin;
	enum pin_config_param param;
	u32 arg;
};

/**
 * struct rockchip_pin_group: represent group of pins of a pinmux function.
 * @name: name of the pin group, used to lookup the group.
 * @pins: the pins included in this group.
 * @npins: number of pins included in this group.
 * @data: local pin configuration
 */
struct rockchip_pin_group {
	const char			*name;
	unsigned int			npins;
	unsigned int			*pins;
	struct rockchip_pin_config	*data;
};

/**
 * struct rockchip_pmx_func: represent a pin function.
 * @name: name of the pin function, used to lookup the function.
 * @groups: one or more names of pin groups that provide this function.
 * @ngroups: number of groups included in @groups.
 */
struct rockchip_pmx_func {
	const char		*name;
	const char		**groups;
	u8			ngroups;
};

struct rockchip_pinctrl {
	struct regmap			*regmap_base;
	int				reg_size;
	struct regmap			*regmap_pull;
	struct regmap			*regmap_pmu;
	struct device			*dev;
	struct rockchip_pin_ctrl	*ctrl;
	struct pinctrl_desc		pctl;
	struct pinctrl_dev		*pctl_dev;
	struct rockchip_pin_group	*groups;
	unsigned int			ngroups;
	struct rockchip_pmx_func	*functions;
	unsigned int			nfunctions;
};

#endif
Commit	Line	Data
e1450694 JX	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
	4	*
	5	* Copyright (c) 2013 MundoReader S.L.
	6	* Author: Heiko Stuebner <heiko@sntech.de>
	7	*
	8	* With some ideas taken from pinctrl-samsung:
	9	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	10	* http://www.samsung.com
	11	* Copyright (c) 2012 Linaro Ltd
	12	* https://www.linaro.org
	13	*
	14	* and pinctrl-at91:
	15	* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	16	*/
	17
	18	#ifndef _PINCTRL_ROCKCHIP_H
	19	#define _PINCTRL_ROCKCHIP_H
	20
fdc33eba JX	21	#define RK_GPIO0_A0 0
	22	#define RK_GPIO0_A1 1
	23	#define RK_GPIO0_A2 2
	24	#define RK_GPIO0_A3 3
	25	#define RK_GPIO0_A4 4
	26	#define RK_GPIO0_A5 5
	27	#define RK_GPIO0_A6 6
	28	#define RK_GPIO0_A7 7
	29	#define RK_GPIO0_B0 8
	30	#define RK_GPIO0_B1 9
	31	#define RK_GPIO0_B2 10
	32	#define RK_GPIO0_B3 11
	33	#define RK_GPIO0_B4 12
	34	#define RK_GPIO0_B5 13
	35	#define RK_GPIO0_B6 14
	36	#define RK_GPIO0_B7 15
	37	#define RK_GPIO0_C0 16
	38	#define RK_GPIO0_C1 17
	39	#define RK_GPIO0_C2 18
	40	#define RK_GPIO0_C3 19
	41	#define RK_GPIO0_C4 20
	42	#define RK_GPIO0_C5 21
	43	#define RK_GPIO0_C6 22
	44	#define RK_GPIO0_C7 23
	45	#define RK_GPIO0_D0 24
	46	#define RK_GPIO0_D1 25
	47	#define RK_GPIO0_D2 26
	48	#define RK_GPIO0_D3 27
	49	#define RK_GPIO0_D4 28
	50	#define RK_GPIO0_D5 29
	51	#define RK_GPIO0_D6 30
	52	#define RK_GPIO0_D7 31
	53
	54	#define RK_GPIO1_A0 32
	55	#define RK_GPIO1_A1 33
	56	#define RK_GPIO1_A2 34
	57	#define RK_GPIO1_A3 35
	58	#define RK_GPIO1_A4 36
	59	#define RK_GPIO1_A5 37
	60	#define RK_GPIO1_A6 38
	61	#define RK_GPIO1_A7 39
	62	#define RK_GPIO1_B0 40
	63	#define RK_GPIO1_B1 41
	64	#define RK_GPIO1_B2 42
	65	#define RK_GPIO1_B3 43
	66	#define RK_GPIO1_B4 44
	67	#define RK_GPIO1_B5 45
	68	#define RK_GPIO1_B6 46
	69	#define RK_GPIO1_B7 47
	70	#define RK_GPIO1_C0 48
	71	#define RK_GPIO1_C1 49
	72	#define RK_GPIO1_C2 50
	73	#define RK_GPIO1_C3 51
	74	#define RK_GPIO1_C4 52
	75	#define RK_GPIO1_C5 53
	76	#define RK_GPIO1_C6 54
	77	#define RK_GPIO1_C7 55
	78	#define RK_GPIO1_D0 56
	79	#define RK_GPIO1_D1 57
	80	#define RK_GPIO1_D2 58
	81	#define RK_GPIO1_D3 59
	82	#define RK_GPIO1_D4 60
	83	#define RK_GPIO1_D5 61
	84	#define RK_GPIO1_D6 62
85	#define RK_GPIO1_D7 63
86
87	#define RK_GPIO2_A0 64
88	#define RK_GPIO2_A1 65
89	#define RK_GPIO2_A2 66
90	#define RK_GPIO2_A3 67
91	#define RK_GPIO2_A4 68
92	#define RK_GPIO2_A5 69
93	#define RK_GPIO2_A6 70
94	#define RK_GPIO2_A7 71
95	#define RK_GPIO2_B0 72
96	#define RK_GPIO2_B1 73
97	#define RK_GPIO2_B2 74
98	#define RK_GPIO2_B3 75
99	#define RK_GPIO2_B4 76
100	#define RK_GPIO2_B5 77
101	#define RK_GPIO2_B6 78
102	#define RK_GPIO2_B7 79
103	#define RK_GPIO2_C0 80
104	#define RK_GPIO2_C1 81
105	#define RK_GPIO2_C2 82
106	#define RK_GPIO2_C3 83
107	#define RK_GPIO2_C4 84
108	#define RK_GPIO2_C5 85
109	#define RK_GPIO2_C6 86
110	#define RK_GPIO2_C7 87
111	#define RK_GPIO2_D0 88
112	#define RK_GPIO2_D1 89
113	#define RK_GPIO2_D2 90
114	#define RK_GPIO2_D3 91
115	#define RK_GPIO2_D4 92
116	#define RK_GPIO2_D5 93
117	#define RK_GPIO2_D6 94
118	#define RK_GPIO2_D7 95
119
120	#define RK_GPIO3_A0 96
121	#define RK_GPIO3_A1 97
122	#define RK_GPIO3_A2 98
123	#define RK_GPIO3_A3 99
124	#define RK_GPIO3_A4 100
125	#define RK_GPIO3_A5 101
126	#define RK_GPIO3_A6 102
127	#define RK_GPIO3_A7 103
128	#define RK_GPIO3_B0 104
129	#define RK_GPIO3_B1 105
130	#define RK_GPIO3_B2 106
131	#define RK_GPIO3_B3 107
132	#define RK_GPIO3_B4 108
133	#define RK_GPIO3_B5 109
134	#define RK_GPIO3_B6 110
135	#define RK_GPIO3_B7 111
136	#define RK_GPIO3_C0 112
137	#define RK_GPIO3_C1 113
138	#define RK_GPIO3_C2 114
139	#define RK_GPIO3_C3 115
140	#define RK_GPIO3_C4 116
141	#define RK_GPIO3_C5 117
142	#define RK_GPIO3_C6 118
143	#define RK_GPIO3_C7 119
144	#define RK_GPIO3_D0 120
145	#define RK_GPIO3_D1 121
146	#define RK_GPIO3_D2 122
147	#define RK_GPIO3_D3 123
148	#define RK_GPIO3_D4 124
149	#define RK_GPIO3_D5 125
150	#define RK_GPIO3_D6 126
151	#define RK_GPIO3_D7 127
152
153	#define RK_GPIO4_A0 128
154	#define RK_GPIO4_A1 129
155	#define RK_GPIO4_A2 130
156	#define RK_GPIO4_A3 131
157	#define RK_GPIO4_A4 132
158	#define RK_GPIO4_A5 133
159	#define RK_GPIO4_A6 134
160	#define RK_GPIO4_A7 135
161	#define RK_GPIO4_B0 136
162	#define RK_GPIO4_B1 137
163	#define RK_GPIO4_B2 138
164	#define RK_GPIO4_B3 139
165	#define RK_GPIO4_B4 140
166	#define RK_GPIO4_B5 141
167	#define RK_GPIO4_B6 142
168	#define RK_GPIO4_B7 143
169	#define RK_GPIO4_C0 144
170	#define RK_GPIO4_C1 145
171	#define RK_GPIO4_C2 146
172	#define RK_GPIO4_C3 147
173	#define RK_GPIO4_C4 148
174	#define RK_GPIO4_C5 149
175	#define RK_GPIO4_C6 150
176	#define RK_GPIO4_C7 151
177	#define RK_GPIO4_D0 152
178	#define RK_GPIO4_D1 153
179	#define RK_GPIO4_D2 154
180	#define RK_GPIO4_D3 155
181	#define RK_GPIO4_D4 156
182	#define RK_GPIO4_D5 157
183	#define RK_GPIO4_D6 158
184	#define RK_GPIO4_D7 159
185
e1450694 JX	186	enum rockchip_pinctrl_type {
	187	PX30,
	188	RV1108,
fd4ea486	189	RV1126,
e1450694 JX	190	RK2928,
	191	RK3066B,
	192	RK3128,
	193	RK3188,
	194	RK3288,
	195	RK3308,
	196	RK3368,
	197	RK3399,
	198	RK3568,
fdc33eba	199	RK3588,
e1450694 JX	200	};
e1450694 JX	201
ff96a8c2 JX	202	/**
	203	* struct rockchip_gpio_regs
	204	* @port_dr: data register
	205	* @port_ddr: data direction register
	206	* @int_en: interrupt enable
	207	* @int_mask: interrupt mask
	208	* @int_type: interrupt trigger type, such as high, low, edge trriger type.
	209	* @int_polarity: interrupt polarity enable register
	210	* @int_bothedge: interrupt bothedge enable register
	211	* @int_status: interrupt status register
	212	* @int_rawstatus: int_status = int_rawstatus & int_mask
	213	* @debounce: enable debounce for interrupt signal
	214	* @dbclk_div_en: enable divider for debounce clock
	215	* @dbclk_div_con: setting for divider of debounce clock
	216	* @port_eoi: end of interrupt of the port
	217	* @ext_port: port data from external
	218	* @version_id: controller version register
	219	*/
	220	struct rockchip_gpio_regs {
	221	u32 port_dr;
	222	u32 port_ddr;
	223	u32 int_en;
	224	u32 int_mask;
	225	u32 int_type;
	226	u32 int_polarity;
	227	u32 int_bothedge;
	228	u32 int_status;
	229	u32 int_rawstatus;
	230	u32 debounce;
	231	u32 dbclk_div_en;
	232	u32 dbclk_div_con;
	233	u32 port_eoi;
	234	u32 ext_port;
	235	u32 version_id;
	236	};
	237
e1450694 JX	238	/**
	239	* struct rockchip_iomux
	240	* @type: iomux variant using IOMUX_* constants
	241	* @offset: if initialized to -1 it will be autocalculated, by specifying
	242	* an initial offset value the relevant source offset can be reset
	243	* to a new value for autocalculating the following iomux registers.
	244	*/
	245	struct rockchip_iomux {
	246	int type;
	247	int offset;
	248	};
	249
	250	/*
	251	* enum type index corresponding to rockchip_perpin_drv_list arrays index.
	252	*/
	253	enum rockchip_pin_drv_type {
	254	DRV_TYPE_IO_DEFAULT = 0,
	255	DRV_TYPE_IO_1V8_OR_3V0,
	256	DRV_TYPE_IO_1V8_ONLY,
	257	DRV_TYPE_IO_1V8_3V0_AUTO,
	258	DRV_TYPE_IO_3V3_ONLY,
	259	DRV_TYPE_MAX
	260	};
	261
	262	/*
	263	* enum type index corresponding to rockchip_pull_list arrays index.
	264	*/
	265	enum rockchip_pin_pull_type {
	266	PULL_TYPE_IO_DEFAULT = 0,
	267	PULL_TYPE_IO_1V8_ONLY,
	268	PULL_TYPE_MAX
	269	};
	270
	271	/**
	272	* struct rockchip_drv
	273	* @drv_type: drive strength variant using rockchip_perpin_drv_type
	274	* @offset: if initialized to -1 it will be autocalculated, by specifying
	275	* an initial offset value the relevant source offset can be reset
	276	* to a new value for autocalculating the following drive strength
	277	* registers. if used chips own cal_drv func instead to calculate
	278	* registers offset, the variant could be ignored.
	279	*/
	280	struct rockchip_drv {
	281	enum rockchip_pin_drv_type drv_type;
	282	int offset;
	283	};
	284
	285	/**
	286	* struct rockchip_pin_bank
5f82afd8	287	* @dev: the pinctrl device bind to the bank
e1450694 JX	288	* @reg_base: register base of the gpio bank
	289	* @regmap_pull: optional separate register for additional pull settings
	290	* @clk: clock of the gpio bank
3bcbd1a8	291	* @db_clk: clock of the gpio debounce
e1450694 JX	292	* @irq: interrupt of the gpio bank
	293	* @saved_masks: Saved content of GPIO_INTEN at suspend time.
	294	* @pin_base: first pin number
	295	* @nr_pins: number of pins in this bank
	296	* @name: name of the bank
	297	* @bank_num: number of the bank, to account for holes
	298	* @iomux: array describing the 4 iomux sources of the bank
	299	* @drv: array describing the 4 drive strength sources of the bank
	300	* @pull_type: array describing the 4 pull type sources of the bank
	301	* @valid: is all necessary information present
	302	* @of_node: dt node of this bank
	303	* @drvdata: common pinctrl basedata
	304	* @domain: irqdomain of the gpio bank
	305	* @gpio_chip: gpiolib chip
	306	* @grange: gpio range
	307	* @slock: spinlock for the gpio bank
	308	* @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
	309	* @recalced_mask: bit mask to indicate a need to recalulate the mask
	310	* @route_mask: bits describing the routing pins of per bank
e7165b1d HS	311	* @deferred_output: gpio output settings to be done after gpio bank probed
e7165b1d HS	312	* @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
e1450694 JX	313	*/
e1450694 JX	314	struct rockchip_pin_bank {
5f82afd8	315	struct device *dev;
e1450694 JX	316	void __iomem *reg_base;
	317	struct regmap *regmap_pull;
	318	struct clk *clk;
3bcbd1a8	319	struct clk *db_clk;
e1450694 JX	320	int irq;
	321	u32 saved_masks;
	322	u32 pin_base;
	323	u8 nr_pins;
	324	char *name;
	325	u8 bank_num;
	326	struct rockchip_iomux iomux[4];
	327	struct rockchip_drv drv[4];
	328	enum rockchip_pin_pull_type pull_type[4];
	329	bool valid;
	330	struct device_node *of_node;
	331	struct rockchip_pinctrl *drvdata;
	332	struct irq_domain *domain;
	333	struct gpio_chip gpio_chip;
	334	struct pinctrl_gpio_range grange;
	335	raw_spinlock_t slock;
ff96a8c2 JX	336	const struct rockchip_gpio_regs *gpio_regs;
ff96a8c2 JX	337	u32 gpio_type;
e1450694 JX	338	u32 toggle_edge_mode;
	339	u32 recalced_mask;
	340	u32 route_mask;
8ce5ef64	341	struct list_head deferred_pins;
e7165b1d	342	struct mutex deferred_lock;
e1450694 JX	343	};
	344
	345	/**
	346	* struct rockchip_mux_recalced_data: represent a pin iomux data.
	347	* @num: bank number.
	348	* @pin: pin number.
	349	* @bit: index at register.
	350	* @reg: register offset.
	351	* @mask: mask bit
	352	*/
	353	struct rockchip_mux_recalced_data {
	354	u8 num;
	355	u8 pin;
	356	u32 reg;
	357	u8 bit;
	358	u8 mask;
	359	};
	360
	361	enum rockchip_mux_route_location {
	362	ROCKCHIP_ROUTE_SAME = 0,
	363	ROCKCHIP_ROUTE_PMU,
	364	ROCKCHIP_ROUTE_GRF,
	365	};
	366
	367	/**
	368	* struct rockchip_mux_recalced_data: represent a pin iomux data.
	369	* @bank_num: bank number.
	370	* @pin: index at register or used to calc index.
	371	* @func: the min pin.
	372	* @route_location: the mux route location (same, pmu, grf).
	373	* @route_offset: the max pin.
	374	* @route_val: the register offset.
	375	*/
	376	struct rockchip_mux_route_data {
	377	u8 bank_num;
	378	u8 pin;
	379	u8 func;
	380	enum rockchip_mux_route_location route_location;
	381	u32 route_offset;
	382	u32 route_val;
	383	};
	384
	385	struct rockchip_pin_ctrl {
	386	struct rockchip_pin_bank *pin_banks;
	387	u32 nr_banks;
	388	u32 nr_pins;
	389	char *label;
	390	enum rockchip_pinctrl_type type;
	391	int grf_mux_offset;
	392	int pmu_mux_offset;
	393	int grf_drv_offset;
	394	int pmu_drv_offset;
	395	struct rockchip_mux_recalced_data *iomux_recalced;
	396	u32 niomux_recalced;
	397	struct rockchip_mux_route_data *iomux_routes;
	398	u32 niomux_routes;
	399
42573ab3	400	int (pull_calc_reg)(struct rockchip_pin_bank bank,
e1450694 JX	401	int pin_num, struct regmap **regmap,
e1450694 JX	402	int reg, u8 bit);
42573ab3	403	int (drv_calc_reg)(struct rockchip_pin_bank bank,
e1450694 JX	404	int pin_num, struct regmap **regmap,
	405	int reg, u8 bit);
	406	int (schmitt_calc_reg)(struct rockchip_pin_bank bank,
	407	int pin_num, struct regmap **regmap,
	408	int reg, u8 bit);
	409	};
	410
	411	struct rockchip_pin_config {
	412	unsigned int func;
	413	unsigned long *configs;
	414	unsigned int nconfigs;
	415	};
	416
8ce5ef64 CC	417	enum pin_config_param;
	418
	419	struct rockchip_pin_deferred {
e7165b1d HS	420	struct list_head head;
e7165b1d HS	421	unsigned int pin;
8ce5ef64	422	enum pin_config_param param;
e7165b1d HS	423	u32 arg;
	424	};
	425
e1450694 JX	426	/**
	427	* struct rockchip_pin_group: represent group of pins of a pinmux function.
	428	* @name: name of the pin group, used to lookup the group.
	429	* @pins: the pins included in this group.
	430	* @npins: number of pins included in this group.
	431	* @data: local pin configuration
	432	*/
	433	struct rockchip_pin_group {
	434	const char *name;
	435	unsigned int npins;
	436	unsigned int *pins;
	437	struct rockchip_pin_config *data;
	438	};
	439
	440	/**
	441	* struct rockchip_pmx_func: represent a pin function.
	442	* @name: name of the pin function, used to lookup the function.
	443	* @groups: one or more names of pin groups that provide this function.
	444	* @ngroups: number of groups included in @groups.
	445	*/
	446	struct rockchip_pmx_func {
	447	const char *name;
	448	const char **groups;
	449	u8 ngroups;
	450	};
	451
	452	struct rockchip_pinctrl {
	453	struct regmap *regmap_base;
	454	int reg_size;
	455	struct regmap *regmap_pull;
	456	struct regmap *regmap_pmu;
	457	struct device *dev;
	458	struct rockchip_pin_ctrl *ctrl;
	459	struct pinctrl_desc pctl;
	460	struct pinctrl_dev *pctl_dev;
	461	struct rockchip_pin_group *groups;
	462	unsigned int ngroups;
	463	struct rockchip_pmx_func *functions;
	464	unsigned int nfunctions;
	465	};
	466
	467	#endif