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d3e51161 HS |
1 | /* |
2 | * Pinctrl driver for Rockchip SoCs | |
3 | * | |
4 | * Copyright (c) 2013 MundoReader S.L. | |
5 | * Author: Heiko Stuebner <heiko@sntech.de> | |
6 | * | |
7 | * With some ideas taken from pinctrl-samsung: | |
8 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
9 | * http://www.samsung.com | |
10 | * Copyright (c) 2012 Linaro Ltd | |
11 | * http://www.linaro.org | |
12 | * | |
13 | * and pinctrl-at91: | |
14 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as published | |
18 | * by the Free Software Foundation. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | */ | |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/bitops.h> | |
30 | #include <linux/gpio.h> | |
31 | #include <linux/of_address.h> | |
32 | #include <linux/of_irq.h> | |
33 | #include <linux/pinctrl/machine.h> | |
34 | #include <linux/pinctrl/pinconf.h> | |
35 | #include <linux/pinctrl/pinctrl.h> | |
36 | #include <linux/pinctrl/pinmux.h> | |
37 | #include <linux/pinctrl/pinconf-generic.h> | |
38 | #include <linux/irqchip/chained_irq.h> | |
7e865abb | 39 | #include <linux/clk.h> |
751a99ab | 40 | #include <linux/regmap.h> |
14dee867 | 41 | #include <linux/mfd/syscon.h> |
d3e51161 HS |
42 | #include <dt-bindings/pinctrl/rockchip.h> |
43 | ||
44 | #include "core.h" | |
45 | #include "pinconf.h" | |
46 | ||
47 | /* GPIO control registers */ | |
48 | #define GPIO_SWPORT_DR 0x00 | |
49 | #define GPIO_SWPORT_DDR 0x04 | |
50 | #define GPIO_INTEN 0x30 | |
51 | #define GPIO_INTMASK 0x34 | |
52 | #define GPIO_INTTYPE_LEVEL 0x38 | |
53 | #define GPIO_INT_POLARITY 0x3c | |
54 | #define GPIO_INT_STATUS 0x40 | |
55 | #define GPIO_INT_RAWSTATUS 0x44 | |
56 | #define GPIO_DEBOUNCE 0x48 | |
57 | #define GPIO_PORTS_EOI 0x4c | |
58 | #define GPIO_EXT_PORT 0x50 | |
59 | #define GPIO_LS_SYNC 0x60 | |
60 | ||
a282926d HS |
61 | enum rockchip_pinctrl_type { |
62 | RK2928, | |
63 | RK3066B, | |
64 | RK3188, | |
66d750e1 | 65 | RK3288, |
daecdc66 | 66 | RK3368, |
a282926d HS |
67 | }; |
68 | ||
fc72c923 HS |
69 | /** |
70 | * Encode variants of iomux registers into a type variable | |
71 | */ | |
72 | #define IOMUX_GPIO_ONLY BIT(0) | |
03716e1d | 73 | #define IOMUX_WIDTH_4BIT BIT(1) |
95ec8ae4 | 74 | #define IOMUX_SOURCE_PMU BIT(2) |
62f49226 | 75 | #define IOMUX_UNROUTED BIT(3) |
fc72c923 HS |
76 | |
77 | /** | |
78 | * @type: iomux variant using IOMUX_* constants | |
6bc0d121 HS |
79 | * @offset: if initialized to -1 it will be autocalculated, by specifying |
80 | * an initial offset value the relevant source offset can be reset | |
81 | * to a new value for autocalculating the following iomux registers. | |
fc72c923 HS |
82 | */ |
83 | struct rockchip_iomux { | |
84 | int type; | |
6bc0d121 | 85 | int offset; |
65fca613 HS |
86 | }; |
87 | ||
d3e51161 HS |
88 | /** |
89 | * @reg_base: register base of the gpio bank | |
6ca5274d | 90 | * @reg_pull: optional separate register for additional pull settings |
d3e51161 HS |
91 | * @clk: clock of the gpio bank |
92 | * @irq: interrupt of the gpio bank | |
5ae0c7ad | 93 | * @saved_masks: Saved content of GPIO_INTEN at suspend time. |
d3e51161 HS |
94 | * @pin_base: first pin number |
95 | * @nr_pins: number of pins in this bank | |
96 | * @name: name of the bank | |
97 | * @bank_num: number of the bank, to account for holes | |
fc72c923 | 98 | * @iomux: array describing the 4 iomux sources of the bank |
d3e51161 HS |
99 | * @valid: are all necessary informations present |
100 | * @of_node: dt node of this bank | |
101 | * @drvdata: common pinctrl basedata | |
102 | * @domain: irqdomain of the gpio bank | |
103 | * @gpio_chip: gpiolib chip | |
104 | * @grange: gpio range | |
105 | * @slock: spinlock for the gpio bank | |
106 | */ | |
107 | struct rockchip_pin_bank { | |
108 | void __iomem *reg_base; | |
751a99ab | 109 | struct regmap *regmap_pull; |
d3e51161 HS |
110 | struct clk *clk; |
111 | int irq; | |
5ae0c7ad | 112 | u32 saved_masks; |
d3e51161 HS |
113 | u32 pin_base; |
114 | u8 nr_pins; | |
115 | char *name; | |
116 | u8 bank_num; | |
fc72c923 | 117 | struct rockchip_iomux iomux[4]; |
d3e51161 HS |
118 | bool valid; |
119 | struct device_node *of_node; | |
120 | struct rockchip_pinctrl *drvdata; | |
121 | struct irq_domain *domain; | |
122 | struct gpio_chip gpio_chip; | |
123 | struct pinctrl_gpio_range grange; | |
124 | spinlock_t slock; | |
5a927501 | 125 | u32 toggle_edge_mode; |
d3e51161 HS |
126 | }; |
127 | ||
128 | #define PIN_BANK(id, pins, label) \ | |
129 | { \ | |
130 | .bank_num = id, \ | |
131 | .nr_pins = pins, \ | |
132 | .name = label, \ | |
6bc0d121 HS |
133 | .iomux = { \ |
134 | { .offset = -1 }, \ | |
135 | { .offset = -1 }, \ | |
136 | { .offset = -1 }, \ | |
137 | { .offset = -1 }, \ | |
138 | }, \ | |
d3e51161 HS |
139 | } |
140 | ||
fc72c923 HS |
141 | #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ |
142 | { \ | |
143 | .bank_num = id, \ | |
144 | .nr_pins = pins, \ | |
145 | .name = label, \ | |
146 | .iomux = { \ | |
6bc0d121 HS |
147 | { .type = iom0, .offset = -1 }, \ |
148 | { .type = iom1, .offset = -1 }, \ | |
149 | { .type = iom2, .offset = -1 }, \ | |
150 | { .type = iom3, .offset = -1 }, \ | |
fc72c923 HS |
151 | }, \ |
152 | } | |
153 | ||
d3e51161 | 154 | /** |
d3e51161 HS |
155 | */ |
156 | struct rockchip_pin_ctrl { | |
157 | struct rockchip_pin_bank *pin_banks; | |
158 | u32 nr_banks; | |
159 | u32 nr_pins; | |
160 | char *label; | |
a282926d | 161 | enum rockchip_pinctrl_type type; |
95ec8ae4 HS |
162 | int grf_mux_offset; |
163 | int pmu_mux_offset; | |
751a99ab HS |
164 | void (*pull_calc_reg)(struct rockchip_pin_bank *bank, |
165 | int pin_num, struct regmap **regmap, | |
166 | int *reg, u8 *bit); | |
ef17f69f HS |
167 | void (*drv_calc_reg)(struct rockchip_pin_bank *bank, |
168 | int pin_num, struct regmap **regmap, | |
169 | int *reg, u8 *bit); | |
d3e51161 HS |
170 | }; |
171 | ||
172 | struct rockchip_pin_config { | |
173 | unsigned int func; | |
174 | unsigned long *configs; | |
175 | unsigned int nconfigs; | |
176 | }; | |
177 | ||
178 | /** | |
179 | * struct rockchip_pin_group: represent group of pins of a pinmux function. | |
180 | * @name: name of the pin group, used to lookup the group. | |
181 | * @pins: the pins included in this group. | |
182 | * @npins: number of pins included in this group. | |
183 | * @func: the mux function number to be programmed when selected. | |
184 | * @configs: the config values to be set for each pin | |
185 | * @nconfigs: number of configs for each pin | |
186 | */ | |
187 | struct rockchip_pin_group { | |
188 | const char *name; | |
189 | unsigned int npins; | |
190 | unsigned int *pins; | |
191 | struct rockchip_pin_config *data; | |
192 | }; | |
193 | ||
194 | /** | |
195 | * struct rockchip_pmx_func: represent a pin function. | |
196 | * @name: name of the pin function, used to lookup the function. | |
197 | * @groups: one or more names of pin groups that provide this function. | |
198 | * @num_groups: number of groups included in @groups. | |
199 | */ | |
200 | struct rockchip_pmx_func { | |
201 | const char *name; | |
202 | const char **groups; | |
203 | u8 ngroups; | |
204 | }; | |
205 | ||
206 | struct rockchip_pinctrl { | |
751a99ab | 207 | struct regmap *regmap_base; |
bfc7a42a | 208 | int reg_size; |
751a99ab | 209 | struct regmap *regmap_pull; |
14dee867 | 210 | struct regmap *regmap_pmu; |
d3e51161 HS |
211 | struct device *dev; |
212 | struct rockchip_pin_ctrl *ctrl; | |
213 | struct pinctrl_desc pctl; | |
214 | struct pinctrl_dev *pctl_dev; | |
215 | struct rockchip_pin_group *groups; | |
216 | unsigned int ngroups; | |
217 | struct rockchip_pmx_func *functions; | |
218 | unsigned int nfunctions; | |
219 | }; | |
220 | ||
751a99ab HS |
221 | static struct regmap_config rockchip_regmap_config = { |
222 | .reg_bits = 32, | |
223 | .val_bits = 32, | |
224 | .reg_stride = 4, | |
225 | }; | |
226 | ||
d3e51161 HS |
227 | static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) |
228 | { | |
229 | return container_of(gc, struct rockchip_pin_bank, gpio_chip); | |
230 | } | |
231 | ||
232 | static const inline struct rockchip_pin_group *pinctrl_name_to_group( | |
233 | const struct rockchip_pinctrl *info, | |
234 | const char *name) | |
235 | { | |
d3e51161 HS |
236 | int i; |
237 | ||
238 | for (i = 0; i < info->ngroups; i++) { | |
1cb95395 AL |
239 | if (!strcmp(info->groups[i].name, name)) |
240 | return &info->groups[i]; | |
d3e51161 HS |
241 | } |
242 | ||
1cb95395 | 243 | return NULL; |
d3e51161 HS |
244 | } |
245 | ||
246 | /* | |
247 | * given a pin number that is local to a pin controller, find out the pin bank | |
248 | * and the register base of the pin bank. | |
249 | */ | |
250 | static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, | |
251 | unsigned pin) | |
252 | { | |
253 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
254 | ||
51578b9b | 255 | while (pin >= (b->pin_base + b->nr_pins)) |
d3e51161 HS |
256 | b++; |
257 | ||
258 | return b; | |
259 | } | |
260 | ||
261 | static struct rockchip_pin_bank *bank_num_to_bank( | |
262 | struct rockchip_pinctrl *info, | |
263 | unsigned num) | |
264 | { | |
265 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
266 | int i; | |
267 | ||
1cb95395 | 268 | for (i = 0; i < info->ctrl->nr_banks; i++, b++) { |
d3e51161 | 269 | if (b->bank_num == num) |
1cb95395 | 270 | return b; |
d3e51161 HS |
271 | } |
272 | ||
1cb95395 | 273 | return ERR_PTR(-EINVAL); |
d3e51161 HS |
274 | } |
275 | ||
276 | /* | |
277 | * Pinctrl_ops handling | |
278 | */ | |
279 | ||
280 | static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) | |
281 | { | |
282 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
283 | ||
284 | return info->ngroups; | |
285 | } | |
286 | ||
287 | static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, | |
288 | unsigned selector) | |
289 | { | |
290 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
291 | ||
292 | return info->groups[selector].name; | |
293 | } | |
294 | ||
295 | static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, | |
296 | unsigned selector, const unsigned **pins, | |
297 | unsigned *npins) | |
298 | { | |
299 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
300 | ||
301 | if (selector >= info->ngroups) | |
302 | return -EINVAL; | |
303 | ||
304 | *pins = info->groups[selector].pins; | |
305 | *npins = info->groups[selector].npins; | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, | |
311 | struct device_node *np, | |
312 | struct pinctrl_map **map, unsigned *num_maps) | |
313 | { | |
314 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
315 | const struct rockchip_pin_group *grp; | |
316 | struct pinctrl_map *new_map; | |
317 | struct device_node *parent; | |
318 | int map_num = 1; | |
319 | int i; | |
320 | ||
321 | /* | |
322 | * first find the group of this node and check if we need to create | |
323 | * config maps for pins | |
324 | */ | |
325 | grp = pinctrl_name_to_group(info, np->name); | |
326 | if (!grp) { | |
327 | dev_err(info->dev, "unable to find group for node %s\n", | |
328 | np->name); | |
329 | return -EINVAL; | |
330 | } | |
331 | ||
332 | map_num += grp->npins; | |
333 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, | |
334 | GFP_KERNEL); | |
335 | if (!new_map) | |
336 | return -ENOMEM; | |
337 | ||
338 | *map = new_map; | |
339 | *num_maps = map_num; | |
340 | ||
341 | /* create mux map */ | |
342 | parent = of_get_parent(np); | |
343 | if (!parent) { | |
344 | devm_kfree(pctldev->dev, new_map); | |
345 | return -EINVAL; | |
346 | } | |
347 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
348 | new_map[0].data.mux.function = parent->name; | |
349 | new_map[0].data.mux.group = np->name; | |
350 | of_node_put(parent); | |
351 | ||
352 | /* create config map */ | |
353 | new_map++; | |
354 | for (i = 0; i < grp->npins; i++) { | |
355 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
356 | new_map[i].data.configs.group_or_pin = | |
357 | pin_get_name(pctldev, grp->pins[i]); | |
358 | new_map[i].data.configs.configs = grp->data[i].configs; | |
359 | new_map[i].data.configs.num_configs = grp->data[i].nconfigs; | |
360 | } | |
361 | ||
362 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
363 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, | |
369 | struct pinctrl_map *map, unsigned num_maps) | |
370 | { | |
371 | } | |
372 | ||
373 | static const struct pinctrl_ops rockchip_pctrl_ops = { | |
374 | .get_groups_count = rockchip_get_groups_count, | |
375 | .get_group_name = rockchip_get_group_name, | |
376 | .get_group_pins = rockchip_get_group_pins, | |
377 | .dt_node_to_map = rockchip_dt_node_to_map, | |
378 | .dt_free_map = rockchip_dt_free_map, | |
379 | }; | |
380 | ||
381 | /* | |
382 | * Hardware access | |
383 | */ | |
384 | ||
a076e2ed HS |
385 | static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) |
386 | { | |
387 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 388 | int iomux_num = (pin / 8); |
95ec8ae4 | 389 | struct regmap *regmap; |
751a99ab | 390 | unsigned int val; |
03716e1d | 391 | int reg, ret, mask; |
a076e2ed HS |
392 | u8 bit; |
393 | ||
fc72c923 HS |
394 | if (iomux_num > 3) |
395 | return -EINVAL; | |
396 | ||
62f49226 HS |
397 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
398 | dev_err(info->dev, "pin %d is unrouted\n", pin); | |
399 | return -EINVAL; | |
400 | } | |
401 | ||
fc72c923 | 402 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) |
a076e2ed HS |
403 | return RK_FUNC_GPIO; |
404 | ||
95ec8ae4 HS |
405 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
406 | ? info->regmap_pmu : info->regmap_base; | |
407 | ||
a076e2ed | 408 | /* get basic quadrupel of mux registers and the correct reg inside */ |
03716e1d | 409 | mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; |
6bc0d121 | 410 | reg = bank->iomux[iomux_num].offset; |
03716e1d HS |
411 | if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { |
412 | if ((pin % 8) >= 4) | |
413 | reg += 0x4; | |
414 | bit = (pin % 4) * 4; | |
415 | } else { | |
416 | bit = (pin % 8) * 2; | |
417 | } | |
a076e2ed | 418 | |
95ec8ae4 | 419 | ret = regmap_read(regmap, reg, &val); |
751a99ab HS |
420 | if (ret) |
421 | return ret; | |
422 | ||
03716e1d | 423 | return ((val >> bit) & mask); |
a076e2ed HS |
424 | } |
425 | ||
d3e51161 HS |
426 | /* |
427 | * Set a new mux function for a pin. | |
428 | * | |
429 | * The register is divided into the upper and lower 16 bit. When changing | |
430 | * a value, the previous register value is not read and changed. Instead | |
431 | * it seems the changed bits are marked in the upper 16 bit, while the | |
432 | * changed value gets set in the same offset in the lower 16 bit. | |
433 | * All pin settings seem to be 2 bit wide in both the upper and lower | |
434 | * parts. | |
435 | * @bank: pin bank to change | |
436 | * @pin: pin to change | |
437 | * @mux: new mux function to set | |
438 | */ | |
14797189 | 439 | static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) |
d3e51161 HS |
440 | { |
441 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 442 | int iomux_num = (pin / 8); |
95ec8ae4 | 443 | struct regmap *regmap; |
03716e1d | 444 | int reg, ret, mask; |
d3e51161 HS |
445 | unsigned long flags; |
446 | u8 bit; | |
99e872d9 | 447 | u32 data, rmask; |
d3e51161 | 448 | |
fc72c923 HS |
449 | if (iomux_num > 3) |
450 | return -EINVAL; | |
451 | ||
62f49226 HS |
452 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
453 | dev_err(info->dev, "pin %d is unrouted\n", pin); | |
454 | return -EINVAL; | |
455 | } | |
456 | ||
fc72c923 | 457 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { |
c4a532de HS |
458 | if (mux != RK_FUNC_GPIO) { |
459 | dev_err(info->dev, | |
460 | "pin %d only supports a gpio mux\n", pin); | |
461 | return -ENOTSUPP; | |
462 | } else { | |
463 | return 0; | |
464 | } | |
465 | } | |
466 | ||
d3e51161 HS |
467 | dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", |
468 | bank->bank_num, pin, mux); | |
469 | ||
95ec8ae4 HS |
470 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
471 | ? info->regmap_pmu : info->regmap_base; | |
472 | ||
d3e51161 | 473 | /* get basic quadrupel of mux registers and the correct reg inside */ |
03716e1d | 474 | mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; |
6bc0d121 | 475 | reg = bank->iomux[iomux_num].offset; |
03716e1d HS |
476 | if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { |
477 | if ((pin % 8) >= 4) | |
478 | reg += 0x4; | |
479 | bit = (pin % 4) * 4; | |
480 | } else { | |
481 | bit = (pin % 8) * 2; | |
482 | } | |
d3e51161 HS |
483 | |
484 | spin_lock_irqsave(&bank->slock, flags); | |
485 | ||
03716e1d | 486 | data = (mask << (bit + 16)); |
99e872d9 | 487 | rmask = data | (data >> 16); |
03716e1d | 488 | data |= (mux & mask) << bit; |
99e872d9 | 489 | ret = regmap_update_bits(regmap, reg, rmask, data); |
d3e51161 HS |
490 | |
491 | spin_unlock_irqrestore(&bank->slock, flags); | |
14797189 | 492 | |
751a99ab | 493 | return ret; |
d3e51161 HS |
494 | } |
495 | ||
a282926d HS |
496 | #define RK2928_PULL_OFFSET 0x118 |
497 | #define RK2928_PULL_PINS_PER_REG 16 | |
498 | #define RK2928_PULL_BANK_STRIDE 8 | |
499 | ||
500 | static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
501 | int pin_num, struct regmap **regmap, |
502 | int *reg, u8 *bit) | |
a282926d HS |
503 | { |
504 | struct rockchip_pinctrl *info = bank->drvdata; | |
505 | ||
751a99ab HS |
506 | *regmap = info->regmap_base; |
507 | *reg = RK2928_PULL_OFFSET; | |
a282926d HS |
508 | *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; |
509 | *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; | |
510 | ||
511 | *bit = pin_num % RK2928_PULL_PINS_PER_REG; | |
512 | }; | |
513 | ||
bfc7a42a | 514 | #define RK3188_PULL_OFFSET 0x164 |
6ca5274d HS |
515 | #define RK3188_PULL_BITS_PER_PIN 2 |
516 | #define RK3188_PULL_PINS_PER_REG 8 | |
517 | #define RK3188_PULL_BANK_STRIDE 16 | |
14dee867 | 518 | #define RK3188_PULL_PMU_OFFSET 0x64 |
6ca5274d HS |
519 | |
520 | static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
521 | int pin_num, struct regmap **regmap, |
522 | int *reg, u8 *bit) | |
6ca5274d HS |
523 | { |
524 | struct rockchip_pinctrl *info = bank->drvdata; | |
525 | ||
526 | /* The first 12 pins of the first bank are located elsewhere */ | |
fc72c923 | 527 | if (bank->bank_num == 0 && pin_num < 12) { |
14dee867 HS |
528 | *regmap = info->regmap_pmu ? info->regmap_pmu |
529 | : bank->regmap_pull; | |
530 | *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; | |
751a99ab | 531 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
6ca5274d HS |
532 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; |
533 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
534 | } else { | |
751a99ab HS |
535 | *regmap = info->regmap_pull ? info->regmap_pull |
536 | : info->regmap_base; | |
537 | *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; | |
538 | ||
bfc7a42a HS |
539 | /* correct the offset, as it is the 2nd pull register */ |
540 | *reg -= 4; | |
6ca5274d HS |
541 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
542 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
543 | ||
544 | /* | |
545 | * The bits in these registers have an inverse ordering | |
546 | * with the lowest pin being in bits 15:14 and the highest | |
547 | * pin in bits 1:0 | |
548 | */ | |
549 | *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); | |
550 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
551 | } | |
552 | } | |
553 | ||
304f077d HS |
554 | #define RK3288_PULL_OFFSET 0x140 |
555 | static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
556 | int pin_num, struct regmap **regmap, | |
557 | int *reg, u8 *bit) | |
558 | { | |
559 | struct rockchip_pinctrl *info = bank->drvdata; | |
560 | ||
561 | /* The first 24 pins of the first bank are located in PMU */ | |
562 | if (bank->bank_num == 0) { | |
563 | *regmap = info->regmap_pmu; | |
564 | *reg = RK3188_PULL_PMU_OFFSET; | |
565 | ||
566 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
567 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; | |
568 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
569 | } else { | |
570 | *regmap = info->regmap_base; | |
571 | *reg = RK3288_PULL_OFFSET; | |
572 | ||
573 | /* correct the offset, as we're starting with the 2nd bank */ | |
574 | *reg -= 0x10; | |
575 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; | |
576 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
577 | ||
578 | *bit = (pin_num % RK3188_PULL_PINS_PER_REG); | |
579 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
580 | } | |
581 | } | |
582 | ||
b547c800 HS |
583 | #define RK3288_DRV_PMU_OFFSET 0x70 |
584 | #define RK3288_DRV_GRF_OFFSET 0x1c0 | |
585 | #define RK3288_DRV_BITS_PER_PIN 2 | |
586 | #define RK3288_DRV_PINS_PER_REG 8 | |
587 | #define RK3288_DRV_BANK_STRIDE 16 | |
b547c800 HS |
588 | |
589 | static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, | |
590 | int pin_num, struct regmap **regmap, | |
591 | int *reg, u8 *bit) | |
592 | { | |
593 | struct rockchip_pinctrl *info = bank->drvdata; | |
594 | ||
595 | /* The first 24 pins of the first bank are located in PMU */ | |
596 | if (bank->bank_num == 0) { | |
597 | *regmap = info->regmap_pmu; | |
598 | *reg = RK3288_DRV_PMU_OFFSET; | |
599 | ||
600 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); | |
601 | *bit = pin_num % RK3288_DRV_PINS_PER_REG; | |
602 | *bit *= RK3288_DRV_BITS_PER_PIN; | |
603 | } else { | |
604 | *regmap = info->regmap_base; | |
605 | *reg = RK3288_DRV_GRF_OFFSET; | |
606 | ||
607 | /* correct the offset, as we're starting with the 2nd bank */ | |
608 | *reg -= 0x10; | |
609 | *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; | |
610 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); | |
611 | ||
612 | *bit = (pin_num % RK3288_DRV_PINS_PER_REG); | |
613 | *bit *= RK3288_DRV_BITS_PER_PIN; | |
614 | } | |
615 | } | |
616 | ||
daecdc66 HS |
617 | #define RK3368_PULL_GRF_OFFSET 0x100 |
618 | #define RK3368_PULL_PMU_OFFSET 0x10 | |
619 | ||
620 | static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
621 | int pin_num, struct regmap **regmap, | |
622 | int *reg, u8 *bit) | |
623 | { | |
624 | struct rockchip_pinctrl *info = bank->drvdata; | |
625 | ||
626 | /* The first 32 pins of the first bank are located in PMU */ | |
627 | if (bank->bank_num == 0) { | |
628 | *regmap = info->regmap_pmu; | |
629 | *reg = RK3368_PULL_PMU_OFFSET; | |
630 | ||
631 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
632 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; | |
633 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
634 | } else { | |
635 | *regmap = info->regmap_base; | |
636 | *reg = RK3368_PULL_GRF_OFFSET; | |
637 | ||
638 | /* correct the offset, as we're starting with the 2nd bank */ | |
639 | *reg -= 0x10; | |
640 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; | |
641 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
642 | ||
643 | *bit = (pin_num % RK3188_PULL_PINS_PER_REG); | |
644 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
645 | } | |
646 | } | |
647 | ||
648 | #define RK3368_DRV_PMU_OFFSET 0x20 | |
649 | #define RK3368_DRV_GRF_OFFSET 0x200 | |
650 | ||
651 | static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, | |
652 | int pin_num, struct regmap **regmap, | |
653 | int *reg, u8 *bit) | |
654 | { | |
655 | struct rockchip_pinctrl *info = bank->drvdata; | |
656 | ||
657 | /* The first 32 pins of the first bank are located in PMU */ | |
658 | if (bank->bank_num == 0) { | |
659 | *regmap = info->regmap_pmu; | |
660 | *reg = RK3368_DRV_PMU_OFFSET; | |
661 | ||
662 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); | |
663 | *bit = pin_num % RK3288_DRV_PINS_PER_REG; | |
664 | *bit *= RK3288_DRV_BITS_PER_PIN; | |
665 | } else { | |
666 | *regmap = info->regmap_base; | |
667 | *reg = RK3368_DRV_GRF_OFFSET; | |
668 | ||
669 | /* correct the offset, as we're starting with the 2nd bank */ | |
670 | *reg -= 0x10; | |
671 | *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; | |
672 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); | |
673 | ||
674 | *bit = (pin_num % RK3288_DRV_PINS_PER_REG); | |
675 | *bit *= RK3288_DRV_BITS_PER_PIN; | |
676 | } | |
677 | } | |
678 | ||
ef17f69f HS |
679 | static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 }; |
680 | ||
681 | static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, | |
682 | int pin_num) | |
b547c800 | 683 | { |
ef17f69f HS |
684 | struct rockchip_pinctrl *info = bank->drvdata; |
685 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
b547c800 HS |
686 | struct regmap *regmap; |
687 | int reg, ret; | |
688 | u32 data; | |
689 | u8 bit; | |
690 | ||
ef17f69f | 691 | ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); |
b547c800 HS |
692 | |
693 | ret = regmap_read(regmap, reg, &data); | |
694 | if (ret) | |
695 | return ret; | |
696 | ||
697 | data >>= bit; | |
698 | data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1; | |
699 | ||
ef17f69f | 700 | return rockchip_perpin_drv_list[data]; |
b547c800 HS |
701 | } |
702 | ||
ef17f69f HS |
703 | static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, |
704 | int pin_num, int strength) | |
b547c800 HS |
705 | { |
706 | struct rockchip_pinctrl *info = bank->drvdata; | |
ef17f69f | 707 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
b547c800 HS |
708 | struct regmap *regmap; |
709 | unsigned long flags; | |
710 | int reg, ret, i; | |
99e872d9 | 711 | u32 data, rmask; |
b547c800 HS |
712 | u8 bit; |
713 | ||
ef17f69f | 714 | ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); |
b547c800 HS |
715 | |
716 | ret = -EINVAL; | |
ef17f69f HS |
717 | for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) { |
718 | if (rockchip_perpin_drv_list[i] == strength) { | |
b547c800 HS |
719 | ret = i; |
720 | break; | |
721 | } | |
722 | } | |
723 | ||
724 | if (ret < 0) { | |
725 | dev_err(info->dev, "unsupported driver strength %d\n", | |
726 | strength); | |
727 | return ret; | |
728 | } | |
729 | ||
730 | spin_lock_irqsave(&bank->slock, flags); | |
731 | ||
732 | /* enable the write to the equivalent lower bits */ | |
733 | data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16); | |
99e872d9 | 734 | rmask = data | (data >> 16); |
b547c800 HS |
735 | data |= (ret << bit); |
736 | ||
99e872d9 | 737 | ret = regmap_update_bits(regmap, reg, rmask, data); |
b547c800 HS |
738 | spin_unlock_irqrestore(&bank->slock, flags); |
739 | ||
740 | return ret; | |
741 | } | |
742 | ||
d3e51161 HS |
743 | static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) |
744 | { | |
745 | struct rockchip_pinctrl *info = bank->drvdata; | |
746 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
747 | struct regmap *regmap; |
748 | int reg, ret; | |
d3e51161 | 749 | u8 bit; |
6ca5274d | 750 | u32 data; |
d3e51161 HS |
751 | |
752 | /* rk3066b does support any pulls */ | |
a282926d | 753 | if (ctrl->type == RK3066B) |
d3e51161 HS |
754 | return PIN_CONFIG_BIAS_DISABLE; |
755 | ||
751a99ab HS |
756 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
757 | ||
758 | ret = regmap_read(regmap, reg, &data); | |
759 | if (ret) | |
760 | return ret; | |
6ca5274d | 761 | |
a282926d HS |
762 | switch (ctrl->type) { |
763 | case RK2928: | |
751a99ab | 764 | return !(data & BIT(bit)) |
d3e51161 HS |
765 | ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT |
766 | : PIN_CONFIG_BIAS_DISABLE; | |
a282926d | 767 | case RK3188: |
66d750e1 | 768 | case RK3288: |
daecdc66 | 769 | case RK3368: |
751a99ab | 770 | data >>= bit; |
6ca5274d HS |
771 | data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; |
772 | ||
773 | switch (data) { | |
774 | case 0: | |
775 | return PIN_CONFIG_BIAS_DISABLE; | |
776 | case 1: | |
777 | return PIN_CONFIG_BIAS_PULL_UP; | |
778 | case 2: | |
779 | return PIN_CONFIG_BIAS_PULL_DOWN; | |
780 | case 3: | |
781 | return PIN_CONFIG_BIAS_BUS_HOLD; | |
782 | } | |
783 | ||
784 | dev_err(info->dev, "unknown pull setting\n"); | |
d3e51161 | 785 | return -EIO; |
a282926d HS |
786 | default: |
787 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
788 | return -EINVAL; | |
789 | }; | |
d3e51161 HS |
790 | } |
791 | ||
792 | static int rockchip_set_pull(struct rockchip_pin_bank *bank, | |
793 | int pin_num, int pull) | |
794 | { | |
795 | struct rockchip_pinctrl *info = bank->drvdata; | |
796 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
797 | struct regmap *regmap; |
798 | int reg, ret; | |
d3e51161 HS |
799 | unsigned long flags; |
800 | u8 bit; | |
99e872d9 | 801 | u32 data, rmask; |
d3e51161 HS |
802 | |
803 | dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", | |
804 | bank->bank_num, pin_num, pull); | |
805 | ||
806 | /* rk3066b does support any pulls */ | |
a282926d | 807 | if (ctrl->type == RK3066B) |
d3e51161 HS |
808 | return pull ? -EINVAL : 0; |
809 | ||
751a99ab | 810 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
6ca5274d | 811 | |
a282926d HS |
812 | switch (ctrl->type) { |
813 | case RK2928: | |
d3e51161 HS |
814 | spin_lock_irqsave(&bank->slock, flags); |
815 | ||
816 | data = BIT(bit + 16); | |
817 | if (pull == PIN_CONFIG_BIAS_DISABLE) | |
818 | data |= BIT(bit); | |
751a99ab | 819 | ret = regmap_write(regmap, reg, data); |
d3e51161 HS |
820 | |
821 | spin_unlock_irqrestore(&bank->slock, flags); | |
a282926d HS |
822 | break; |
823 | case RK3188: | |
66d750e1 | 824 | case RK3288: |
daecdc66 | 825 | case RK3368: |
6ca5274d HS |
826 | spin_lock_irqsave(&bank->slock, flags); |
827 | ||
828 | /* enable the write to the equivalent lower bits */ | |
829 | data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); | |
99e872d9 | 830 | rmask = data | (data >> 16); |
6ca5274d HS |
831 | |
832 | switch (pull) { | |
833 | case PIN_CONFIG_BIAS_DISABLE: | |
834 | break; | |
835 | case PIN_CONFIG_BIAS_PULL_UP: | |
836 | data |= (1 << bit); | |
837 | break; | |
838 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
839 | data |= (2 << bit); | |
840 | break; | |
841 | case PIN_CONFIG_BIAS_BUS_HOLD: | |
842 | data |= (3 << bit); | |
843 | break; | |
844 | default: | |
d32c3e26 | 845 | spin_unlock_irqrestore(&bank->slock, flags); |
6ca5274d HS |
846 | dev_err(info->dev, "unsupported pull setting %d\n", |
847 | pull); | |
848 | return -EINVAL; | |
849 | } | |
850 | ||
99e872d9 | 851 | ret = regmap_update_bits(regmap, reg, rmask, data); |
6ca5274d HS |
852 | |
853 | spin_unlock_irqrestore(&bank->slock, flags); | |
854 | break; | |
a282926d HS |
855 | default: |
856 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
857 | return -EINVAL; | |
d3e51161 HS |
858 | } |
859 | ||
751a99ab | 860 | return ret; |
d3e51161 HS |
861 | } |
862 | ||
863 | /* | |
864 | * Pinmux_ops handling | |
865 | */ | |
866 | ||
867 | static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
868 | { | |
869 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
870 | ||
871 | return info->nfunctions; | |
872 | } | |
873 | ||
874 | static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
875 | unsigned selector) | |
876 | { | |
877 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
878 | ||
879 | return info->functions[selector].name; | |
880 | } | |
881 | ||
882 | static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, | |
883 | unsigned selector, const char * const **groups, | |
884 | unsigned * const num_groups) | |
885 | { | |
886 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
887 | ||
888 | *groups = info->functions[selector].groups; | |
889 | *num_groups = info->functions[selector].ngroups; | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
03e9f0ca LW |
894 | static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
895 | unsigned group) | |
d3e51161 HS |
896 | { |
897 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
898 | const unsigned int *pins = info->groups[group].pins; | |
899 | const struct rockchip_pin_config *data = info->groups[group].data; | |
900 | struct rockchip_pin_bank *bank; | |
14797189 | 901 | int cnt, ret = 0; |
d3e51161 HS |
902 | |
903 | dev_dbg(info->dev, "enable function %s group %s\n", | |
904 | info->functions[selector].name, info->groups[group].name); | |
905 | ||
906 | /* | |
907 | * for each pin in the pin group selected, program the correspoding pin | |
908 | * pin function number in the config register. | |
909 | */ | |
910 | for (cnt = 0; cnt < info->groups[group].npins; cnt++) { | |
911 | bank = pin_to_bank(info, pins[cnt]); | |
14797189 HS |
912 | ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, |
913 | data[cnt].func); | |
914 | if (ret) | |
915 | break; | |
916 | } | |
917 | ||
918 | if (ret) { | |
919 | /* revert the already done pin settings */ | |
920 | for (cnt--; cnt >= 0; cnt--) | |
921 | rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); | |
922 | ||
923 | return ret; | |
d3e51161 HS |
924 | } |
925 | ||
926 | return 0; | |
927 | } | |
928 | ||
d3e51161 HS |
929 | /* |
930 | * The calls to gpio_direction_output() and gpio_direction_input() | |
931 | * leads to this function call (via the pinctrl_gpio_direction_{input|output}() | |
932 | * function called from the gpiolib interface). | |
933 | */ | |
e5c2c9db DA |
934 | static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, |
935 | int pin, bool input) | |
d3e51161 | 936 | { |
d3e51161 | 937 | struct rockchip_pin_bank *bank; |
e5c2c9db | 938 | int ret; |
fab262f5 | 939 | unsigned long flags; |
d3e51161 HS |
940 | u32 data; |
941 | ||
d3e51161 | 942 | bank = gc_to_pin_bank(chip); |
d3e51161 | 943 | |
14797189 HS |
944 | ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); |
945 | if (ret < 0) | |
946 | return ret; | |
d3e51161 | 947 | |
07a06ae9 | 948 | clk_enable(bank->clk); |
fab262f5 DA |
949 | spin_lock_irqsave(&bank->slock, flags); |
950 | ||
d3e51161 HS |
951 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); |
952 | /* set bit to 1 for output, 0 for input */ | |
953 | if (!input) | |
954 | data |= BIT(pin); | |
955 | else | |
956 | data &= ~BIT(pin); | |
957 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
958 | ||
fab262f5 | 959 | spin_unlock_irqrestore(&bank->slock, flags); |
07a06ae9 | 960 | clk_disable(bank->clk); |
fab262f5 | 961 | |
d3e51161 HS |
962 | return 0; |
963 | } | |
964 | ||
e5c2c9db DA |
965 | static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
966 | struct pinctrl_gpio_range *range, | |
967 | unsigned offset, bool input) | |
968 | { | |
969 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
970 | struct gpio_chip *chip; | |
971 | int pin; | |
972 | ||
973 | chip = range->gc; | |
974 | pin = offset - chip->base; | |
975 | dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", | |
976 | offset, range->name, pin, input ? "input" : "output"); | |
977 | ||
978 | return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, | |
979 | input); | |
980 | } | |
981 | ||
d3e51161 HS |
982 | static const struct pinmux_ops rockchip_pmx_ops = { |
983 | .get_functions_count = rockchip_pmx_get_funcs_count, | |
984 | .get_function_name = rockchip_pmx_get_func_name, | |
985 | .get_function_groups = rockchip_pmx_get_groups, | |
03e9f0ca | 986 | .set_mux = rockchip_pmx_set, |
d3e51161 HS |
987 | .gpio_set_direction = rockchip_pmx_gpio_set_direction, |
988 | }; | |
989 | ||
990 | /* | |
991 | * Pinconf_ops handling | |
992 | */ | |
993 | ||
44b6d930 HS |
994 | static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, |
995 | enum pin_config_param pull) | |
996 | { | |
a282926d HS |
997 | switch (ctrl->type) { |
998 | case RK2928: | |
999 | return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || | |
1000 | pull == PIN_CONFIG_BIAS_DISABLE); | |
1001 | case RK3066B: | |
44b6d930 | 1002 | return pull ? false : true; |
a282926d | 1003 | case RK3188: |
66d750e1 | 1004 | case RK3288: |
daecdc66 | 1005 | case RK3368: |
a282926d | 1006 | return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); |
44b6d930 HS |
1007 | } |
1008 | ||
a282926d | 1009 | return false; |
44b6d930 HS |
1010 | } |
1011 | ||
e5c2c9db | 1012 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); |
a076e2ed HS |
1013 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); |
1014 | ||
d3e51161 HS |
1015 | /* set the pin config settings for a specified pin */ |
1016 | static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
03b054e9 | 1017 | unsigned long *configs, unsigned num_configs) |
d3e51161 HS |
1018 | { |
1019 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
1020 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
03b054e9 SY |
1021 | enum pin_config_param param; |
1022 | u16 arg; | |
1023 | int i; | |
1024 | int rc; | |
1025 | ||
1026 | for (i = 0; i < num_configs; i++) { | |
1027 | param = pinconf_to_config_param(configs[i]); | |
1028 | arg = pinconf_to_config_argument(configs[i]); | |
1029 | ||
1030 | switch (param) { | |
1031 | case PIN_CONFIG_BIAS_DISABLE: | |
1032 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
1033 | param); | |
1034 | if (rc) | |
1035 | return rc; | |
1036 | break; | |
1037 | case PIN_CONFIG_BIAS_PULL_UP: | |
1038 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
1039 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 1040 | case PIN_CONFIG_BIAS_BUS_HOLD: |
03b054e9 SY |
1041 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
1042 | return -ENOTSUPP; | |
1043 | ||
1044 | if (!arg) | |
1045 | return -EINVAL; | |
1046 | ||
1047 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
1048 | param); | |
1049 | if (rc) | |
1050 | return rc; | |
1051 | break; | |
a076e2ed | 1052 | case PIN_CONFIG_OUTPUT: |
e5c2c9db DA |
1053 | rockchip_gpio_set(&bank->gpio_chip, |
1054 | pin - bank->pin_base, arg); | |
1055 | rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, | |
1056 | pin - bank->pin_base, false); | |
a076e2ed HS |
1057 | if (rc) |
1058 | return rc; | |
1059 | break; | |
b547c800 HS |
1060 | case PIN_CONFIG_DRIVE_STRENGTH: |
1061 | /* rk3288 is the first with per-pin drive-strength */ | |
ef17f69f | 1062 | if (!info->ctrl->drv_calc_reg) |
b547c800 HS |
1063 | return -ENOTSUPP; |
1064 | ||
ef17f69f HS |
1065 | rc = rockchip_set_drive_perpin(bank, |
1066 | pin - bank->pin_base, arg); | |
b547c800 HS |
1067 | if (rc < 0) |
1068 | return rc; | |
1069 | break; | |
03b054e9 | 1070 | default: |
44b6d930 | 1071 | return -ENOTSUPP; |
03b054e9 SY |
1072 | break; |
1073 | } | |
1074 | } /* for each config */ | |
d3e51161 HS |
1075 | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | /* get the pin config settings for a specified pin */ | |
1080 | static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
1081 | unsigned long *config) | |
1082 | { | |
1083 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
1084 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
1085 | enum pin_config_param param = pinconf_to_config_param(*config); | |
dab3eba7 | 1086 | u16 arg; |
a076e2ed | 1087 | int rc; |
d3e51161 HS |
1088 | |
1089 | switch (param) { | |
1090 | case PIN_CONFIG_BIAS_DISABLE: | |
44b6d930 HS |
1091 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
1092 | return -EINVAL; | |
1093 | ||
dab3eba7 | 1094 | arg = 0; |
44b6d930 | 1095 | break; |
d3e51161 HS |
1096 | case PIN_CONFIG_BIAS_PULL_UP: |
1097 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
1098 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 1099 | case PIN_CONFIG_BIAS_BUS_HOLD: |
44b6d930 HS |
1100 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
1101 | return -ENOTSUPP; | |
d3e51161 | 1102 | |
44b6d930 | 1103 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
d3e51161 HS |
1104 | return -EINVAL; |
1105 | ||
dab3eba7 | 1106 | arg = 1; |
d3e51161 | 1107 | break; |
a076e2ed HS |
1108 | case PIN_CONFIG_OUTPUT: |
1109 | rc = rockchip_get_mux(bank, pin - bank->pin_base); | |
1110 | if (rc != RK_FUNC_GPIO) | |
1111 | return -EINVAL; | |
1112 | ||
1113 | rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); | |
1114 | if (rc < 0) | |
1115 | return rc; | |
1116 | ||
1117 | arg = rc ? 1 : 0; | |
1118 | break; | |
b547c800 HS |
1119 | case PIN_CONFIG_DRIVE_STRENGTH: |
1120 | /* rk3288 is the first with per-pin drive-strength */ | |
ef17f69f | 1121 | if (!info->ctrl->drv_calc_reg) |
b547c800 HS |
1122 | return -ENOTSUPP; |
1123 | ||
ef17f69f | 1124 | rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); |
b547c800 HS |
1125 | if (rc < 0) |
1126 | return rc; | |
1127 | ||
1128 | arg = rc; | |
1129 | break; | |
d3e51161 HS |
1130 | default: |
1131 | return -ENOTSUPP; | |
1132 | break; | |
1133 | } | |
1134 | ||
dab3eba7 HS |
1135 | *config = pinconf_to_config_packed(param, arg); |
1136 | ||
d3e51161 HS |
1137 | return 0; |
1138 | } | |
1139 | ||
1140 | static const struct pinconf_ops rockchip_pinconf_ops = { | |
1141 | .pin_config_get = rockchip_pinconf_get, | |
1142 | .pin_config_set = rockchip_pinconf_set, | |
ed62f2f2 | 1143 | .is_generic = true, |
d3e51161 HS |
1144 | }; |
1145 | ||
65fca613 HS |
1146 | static const struct of_device_id rockchip_bank_match[] = { |
1147 | { .compatible = "rockchip,gpio-bank" }, | |
6ca5274d | 1148 | { .compatible = "rockchip,rk3188-gpio-bank0" }, |
65fca613 HS |
1149 | {}, |
1150 | }; | |
d3e51161 HS |
1151 | |
1152 | static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, | |
1153 | struct device_node *np) | |
1154 | { | |
1155 | struct device_node *child; | |
1156 | ||
1157 | for_each_child_of_node(np, child) { | |
65fca613 | 1158 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 HS |
1159 | continue; |
1160 | ||
1161 | info->nfunctions++; | |
1162 | info->ngroups += of_get_child_count(child); | |
1163 | } | |
1164 | } | |
1165 | ||
1166 | static int rockchip_pinctrl_parse_groups(struct device_node *np, | |
1167 | struct rockchip_pin_group *grp, | |
1168 | struct rockchip_pinctrl *info, | |
1169 | u32 index) | |
1170 | { | |
1171 | struct rockchip_pin_bank *bank; | |
1172 | int size; | |
1173 | const __be32 *list; | |
1174 | int num; | |
1175 | int i, j; | |
1176 | int ret; | |
1177 | ||
1178 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
1179 | ||
1180 | /* Initialise group */ | |
1181 | grp->name = np->name; | |
1182 | ||
1183 | /* | |
1184 | * the binding format is rockchip,pins = <bank pin mux CONFIG>, | |
1185 | * do sanity check and calculate pins number | |
1186 | */ | |
1187 | list = of_get_property(np, "rockchip,pins", &size); | |
1188 | /* we do not check return since it's safe node passed down */ | |
1189 | size /= sizeof(*list); | |
1190 | if (!size || size % 4) { | |
1191 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
1192 | return -EINVAL; | |
1193 | } | |
1194 | ||
1195 | grp->npins = size / 4; | |
1196 | ||
1197 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
1198 | GFP_KERNEL); | |
1199 | grp->data = devm_kzalloc(info->dev, grp->npins * | |
1200 | sizeof(struct rockchip_pin_config), | |
1201 | GFP_KERNEL); | |
1202 | if (!grp->pins || !grp->data) | |
1203 | return -ENOMEM; | |
1204 | ||
1205 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
1206 | const __be32 *phandle; | |
1207 | struct device_node *np_config; | |
1208 | ||
1209 | num = be32_to_cpu(*list++); | |
1210 | bank = bank_num_to_bank(info, num); | |
1211 | if (IS_ERR(bank)) | |
1212 | return PTR_ERR(bank); | |
1213 | ||
1214 | grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); | |
1215 | grp->data[j].func = be32_to_cpu(*list++); | |
1216 | ||
1217 | phandle = list++; | |
1218 | if (!phandle) | |
1219 | return -EINVAL; | |
1220 | ||
1221 | np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); | |
dd4d01f7 | 1222 | ret = pinconf_generic_parse_dt_config(np_config, NULL, |
d3e51161 HS |
1223 | &grp->data[j].configs, &grp->data[j].nconfigs); |
1224 | if (ret) | |
1225 | return ret; | |
1226 | } | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
1231 | static int rockchip_pinctrl_parse_functions(struct device_node *np, | |
1232 | struct rockchip_pinctrl *info, | |
1233 | u32 index) | |
1234 | { | |
1235 | struct device_node *child; | |
1236 | struct rockchip_pmx_func *func; | |
1237 | struct rockchip_pin_group *grp; | |
1238 | int ret; | |
1239 | static u32 grp_index; | |
1240 | u32 i = 0; | |
1241 | ||
1242 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
1243 | ||
1244 | func = &info->functions[index]; | |
1245 | ||
1246 | /* Initialise function */ | |
1247 | func->name = np->name; | |
1248 | func->ngroups = of_get_child_count(np); | |
1249 | if (func->ngroups <= 0) | |
1250 | return 0; | |
1251 | ||
1252 | func->groups = devm_kzalloc(info->dev, | |
1253 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
1254 | if (!func->groups) | |
1255 | return -ENOMEM; | |
1256 | ||
1257 | for_each_child_of_node(np, child) { | |
1258 | func->groups[i] = child->name; | |
1259 | grp = &info->groups[grp_index++]; | |
1260 | ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); | |
1261 | if (ret) | |
1262 | return ret; | |
1263 | } | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, | |
1269 | struct rockchip_pinctrl *info) | |
1270 | { | |
1271 | struct device *dev = &pdev->dev; | |
1272 | struct device_node *np = dev->of_node; | |
1273 | struct device_node *child; | |
1274 | int ret; | |
1275 | int i; | |
1276 | ||
1277 | rockchip_pinctrl_child_count(info, np); | |
1278 | ||
1279 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1280 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1281 | ||
1282 | info->functions = devm_kzalloc(dev, info->nfunctions * | |
1283 | sizeof(struct rockchip_pmx_func), | |
1284 | GFP_KERNEL); | |
1285 | if (!info->functions) { | |
1286 | dev_err(dev, "failed to allocate memory for function list\n"); | |
1287 | return -EINVAL; | |
1288 | } | |
1289 | ||
1290 | info->groups = devm_kzalloc(dev, info->ngroups * | |
1291 | sizeof(struct rockchip_pin_group), | |
1292 | GFP_KERNEL); | |
1293 | if (!info->groups) { | |
1294 | dev_err(dev, "failed allocate memory for ping group list\n"); | |
1295 | return -EINVAL; | |
1296 | } | |
1297 | ||
1298 | i = 0; | |
1299 | ||
1300 | for_each_child_of_node(np, child) { | |
65fca613 | 1301 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 | 1302 | continue; |
65fca613 | 1303 | |
d3e51161 HS |
1304 | ret = rockchip_pinctrl_parse_functions(child, info, i++); |
1305 | if (ret) { | |
1306 | dev_err(&pdev->dev, "failed to parse function\n"); | |
1307 | return ret; | |
1308 | } | |
1309 | } | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
1314 | static int rockchip_pinctrl_register(struct platform_device *pdev, | |
1315 | struct rockchip_pinctrl *info) | |
1316 | { | |
1317 | struct pinctrl_desc *ctrldesc = &info->pctl; | |
1318 | struct pinctrl_pin_desc *pindesc, *pdesc; | |
1319 | struct rockchip_pin_bank *pin_bank; | |
1320 | int pin, bank, ret; | |
1321 | int k; | |
1322 | ||
1323 | ctrldesc->name = "rockchip-pinctrl"; | |
1324 | ctrldesc->owner = THIS_MODULE; | |
1325 | ctrldesc->pctlops = &rockchip_pctrl_ops; | |
1326 | ctrldesc->pmxops = &rockchip_pmx_ops; | |
1327 | ctrldesc->confops = &rockchip_pinconf_ops; | |
1328 | ||
1329 | pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * | |
1330 | info->ctrl->nr_pins, GFP_KERNEL); | |
1331 | if (!pindesc) { | |
1332 | dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); | |
1333 | return -ENOMEM; | |
1334 | } | |
1335 | ctrldesc->pins = pindesc; | |
1336 | ctrldesc->npins = info->ctrl->nr_pins; | |
1337 | ||
1338 | pdesc = pindesc; | |
1339 | for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { | |
1340 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1341 | for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { | |
1342 | pdesc->number = k; | |
1343 | pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", | |
1344 | pin_bank->name, pin); | |
1345 | pdesc++; | |
1346 | } | |
1347 | } | |
1348 | ||
0fb7dcb1 DA |
1349 | ret = rockchip_pinctrl_parse_dt(pdev, info); |
1350 | if (ret) | |
1351 | return ret; | |
1352 | ||
d3e51161 | 1353 | info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); |
323de9ef | 1354 | if (IS_ERR(info->pctl_dev)) { |
d3e51161 | 1355 | dev_err(&pdev->dev, "could not register pinctrl driver\n"); |
323de9ef | 1356 | return PTR_ERR(info->pctl_dev); |
d3e51161 HS |
1357 | } |
1358 | ||
1359 | for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { | |
1360 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1361 | pin_bank->grange.name = pin_bank->name; | |
1362 | pin_bank->grange.id = bank; | |
1363 | pin_bank->grange.pin_base = pin_bank->pin_base; | |
1364 | pin_bank->grange.base = pin_bank->gpio_chip.base; | |
1365 | pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; | |
1366 | pin_bank->grange.gc = &pin_bank->gpio_chip; | |
1367 | pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); | |
1368 | } | |
1369 | ||
d3e51161 HS |
1370 | return 0; |
1371 | } | |
1372 | ||
1373 | /* | |
1374 | * GPIO handling | |
1375 | */ | |
1376 | ||
1377 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) | |
1378 | { | |
1379 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1380 | void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; | |
1381 | unsigned long flags; | |
1382 | u32 data; | |
1383 | ||
07a06ae9 | 1384 | clk_enable(bank->clk); |
d3e51161 HS |
1385 | spin_lock_irqsave(&bank->slock, flags); |
1386 | ||
1387 | data = readl(reg); | |
1388 | data &= ~BIT(offset); | |
1389 | if (value) | |
1390 | data |= BIT(offset); | |
1391 | writel(data, reg); | |
1392 | ||
1393 | spin_unlock_irqrestore(&bank->slock, flags); | |
07a06ae9 | 1394 | clk_disable(bank->clk); |
d3e51161 HS |
1395 | } |
1396 | ||
1397 | /* | |
1398 | * Returns the level of the pin for input direction and setting of the DR | |
1399 | * register for output gpios. | |
1400 | */ | |
1401 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) | |
1402 | { | |
1403 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1404 | u32 data; | |
1405 | ||
07a06ae9 | 1406 | clk_enable(bank->clk); |
d3e51161 | 1407 | data = readl(bank->reg_base + GPIO_EXT_PORT); |
07a06ae9 | 1408 | clk_disable(bank->clk); |
d3e51161 HS |
1409 | data >>= offset; |
1410 | data &= 1; | |
1411 | return data; | |
1412 | } | |
1413 | ||
1414 | /* | |
1415 | * gpiolib gpio_direction_input callback function. The setting of the pin | |
1416 | * mux function as 'gpio input' will be handled by the pinctrl susbsystem | |
1417 | * interface. | |
1418 | */ | |
1419 | static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) | |
1420 | { | |
1421 | return pinctrl_gpio_direction_input(gc->base + offset); | |
1422 | } | |
1423 | ||
1424 | /* | |
1425 | * gpiolib gpio_direction_output callback function. The setting of the pin | |
1426 | * mux function as 'gpio output' will be handled by the pinctrl susbsystem | |
1427 | * interface. | |
1428 | */ | |
1429 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, | |
1430 | unsigned offset, int value) | |
1431 | { | |
1432 | rockchip_gpio_set(gc, offset, value); | |
1433 | return pinctrl_gpio_direction_output(gc->base + offset); | |
1434 | } | |
1435 | ||
1436 | /* | |
1437 | * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin | |
1438 | * and a virtual IRQ, if not already present. | |
1439 | */ | |
1440 | static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
1441 | { | |
1442 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1443 | unsigned int virq; | |
1444 | ||
1445 | if (!bank->domain) | |
1446 | return -ENXIO; | |
1447 | ||
1448 | virq = irq_create_mapping(bank->domain, offset); | |
1449 | ||
1450 | return (virq) ? : -ENXIO; | |
1451 | } | |
1452 | ||
1453 | static const struct gpio_chip rockchip_gpiolib_chip = { | |
98c85d58 JG |
1454 | .request = gpiochip_generic_request, |
1455 | .free = gpiochip_generic_free, | |
d3e51161 HS |
1456 | .set = rockchip_gpio_set, |
1457 | .get = rockchip_gpio_get, | |
1458 | .direction_input = rockchip_gpio_direction_input, | |
1459 | .direction_output = rockchip_gpio_direction_output, | |
1460 | .to_irq = rockchip_gpio_to_irq, | |
1461 | .owner = THIS_MODULE, | |
1462 | }; | |
1463 | ||
1464 | /* | |
1465 | * Interrupt handling | |
1466 | */ | |
1467 | ||
bd0b9ac4 | 1468 | static void rockchip_irq_demux(struct irq_desc *desc) |
d3e51161 | 1469 | { |
5663bb27 JL |
1470 | struct irq_chip *chip = irq_desc_get_chip(desc); |
1471 | struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); | |
d3e51161 HS |
1472 | u32 pend; |
1473 | ||
1474 | dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); | |
1475 | ||
1476 | chained_irq_enter(chip, desc); | |
1477 | ||
1478 | pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); | |
1479 | ||
1480 | while (pend) { | |
415f748c | 1481 | unsigned int irq, virq; |
d3e51161 HS |
1482 | |
1483 | irq = __ffs(pend); | |
1484 | pend &= ~BIT(irq); | |
1485 | virq = irq_linear_revmap(bank->domain, irq); | |
1486 | ||
1487 | if (!virq) { | |
1488 | dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); | |
1489 | continue; | |
1490 | } | |
1491 | ||
1492 | dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); | |
1493 | ||
5a927501 HS |
1494 | /* |
1495 | * Triggering IRQ on both rising and falling edge | |
1496 | * needs manual intervention. | |
1497 | */ | |
1498 | if (bank->toggle_edge_mode & BIT(irq)) { | |
53b1bfc7 DA |
1499 | u32 data, data_old, polarity; |
1500 | unsigned long flags; | |
1501 | ||
1502 | data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); | |
1503 | do { | |
1504 | spin_lock_irqsave(&bank->slock, flags); | |
1505 | ||
1506 | polarity = readl_relaxed(bank->reg_base + | |
1507 | GPIO_INT_POLARITY); | |
1508 | if (data & BIT(irq)) | |
1509 | polarity &= ~BIT(irq); | |
1510 | else | |
1511 | polarity |= BIT(irq); | |
1512 | writel(polarity, | |
1513 | bank->reg_base + GPIO_INT_POLARITY); | |
1514 | ||
1515 | spin_unlock_irqrestore(&bank->slock, flags); | |
1516 | ||
1517 | data_old = data; | |
1518 | data = readl_relaxed(bank->reg_base + | |
1519 | GPIO_EXT_PORT); | |
1520 | } while ((data & BIT(irq)) != (data_old & BIT(irq))); | |
5a927501 HS |
1521 | } |
1522 | ||
d3e51161 HS |
1523 | generic_handle_irq(virq); |
1524 | } | |
1525 | ||
1526 | chained_irq_exit(chip, desc); | |
1527 | } | |
1528 | ||
1529 | static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) | |
1530 | { | |
1531 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
1532 | struct rockchip_pin_bank *bank = gc->private; | |
1533 | u32 mask = BIT(d->hwirq); | |
1534 | u32 polarity; | |
1535 | u32 level; | |
1536 | u32 data; | |
fab262f5 | 1537 | unsigned long flags; |
14797189 | 1538 | int ret; |
d3e51161 | 1539 | |
5a927501 | 1540 | /* make sure the pin is configured as gpio input */ |
14797189 HS |
1541 | ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); |
1542 | if (ret < 0) | |
1543 | return ret; | |
1544 | ||
07a06ae9 | 1545 | clk_enable(bank->clk); |
fab262f5 DA |
1546 | spin_lock_irqsave(&bank->slock, flags); |
1547 | ||
5a927501 HS |
1548 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); |
1549 | data &= ~mask; | |
1550 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
1551 | ||
fab262f5 DA |
1552 | spin_unlock_irqrestore(&bank->slock, flags); |
1553 | ||
d3e51161 | 1554 | if (type & IRQ_TYPE_EDGE_BOTH) |
2dbf1bc5 | 1555 | irq_set_handler_locked(d, handle_edge_irq); |
d3e51161 | 1556 | else |
2dbf1bc5 | 1557 | irq_set_handler_locked(d, handle_level_irq); |
d3e51161 | 1558 | |
fab262f5 | 1559 | spin_lock_irqsave(&bank->slock, flags); |
d3e51161 HS |
1560 | irq_gc_lock(gc); |
1561 | ||
1562 | level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1563 | polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); | |
1564 | ||
1565 | switch (type) { | |
5a927501 HS |
1566 | case IRQ_TYPE_EDGE_BOTH: |
1567 | bank->toggle_edge_mode |= mask; | |
1568 | level |= mask; | |
1569 | ||
1570 | /* | |
1571 | * Determine gpio state. If 1 next interrupt should be falling | |
1572 | * otherwise rising. | |
1573 | */ | |
1574 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
1575 | if (data & mask) | |
1576 | polarity &= ~mask; | |
1577 | else | |
1578 | polarity |= mask; | |
1579 | break; | |
d3e51161 | 1580 | case IRQ_TYPE_EDGE_RISING: |
5a927501 | 1581 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1582 | level |= mask; |
1583 | polarity |= mask; | |
1584 | break; | |
1585 | case IRQ_TYPE_EDGE_FALLING: | |
5a927501 | 1586 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1587 | level |= mask; |
1588 | polarity &= ~mask; | |
1589 | break; | |
1590 | case IRQ_TYPE_LEVEL_HIGH: | |
5a927501 | 1591 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1592 | level &= ~mask; |
1593 | polarity |= mask; | |
1594 | break; | |
1595 | case IRQ_TYPE_LEVEL_LOW: | |
5a927501 | 1596 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1597 | level &= ~mask; |
1598 | polarity &= ~mask; | |
1599 | break; | |
1600 | default: | |
7cc5f970 | 1601 | irq_gc_unlock(gc); |
fab262f5 | 1602 | spin_unlock_irqrestore(&bank->slock, flags); |
07a06ae9 | 1603 | clk_disable(bank->clk); |
d3e51161 HS |
1604 | return -EINVAL; |
1605 | } | |
1606 | ||
1607 | writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1608 | writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); | |
1609 | ||
1610 | irq_gc_unlock(gc); | |
fab262f5 | 1611 | spin_unlock_irqrestore(&bank->slock, flags); |
07a06ae9 | 1612 | clk_disable(bank->clk); |
d3e51161 | 1613 | |
d3e51161 HS |
1614 | return 0; |
1615 | } | |
1616 | ||
68bda47c DA |
1617 | static void rockchip_irq_suspend(struct irq_data *d) |
1618 | { | |
1619 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
1620 | struct rockchip_pin_bank *bank = gc->private; | |
1621 | ||
07a06ae9 | 1622 | clk_enable(bank->clk); |
5ae0c7ad DA |
1623 | bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); |
1624 | irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); | |
07a06ae9 | 1625 | clk_disable(bank->clk); |
68bda47c DA |
1626 | } |
1627 | ||
1628 | static void rockchip_irq_resume(struct irq_data *d) | |
1629 | { | |
1630 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
1631 | struct rockchip_pin_bank *bank = gc->private; | |
1632 | ||
07a06ae9 | 1633 | clk_enable(bank->clk); |
5ae0c7ad | 1634 | irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); |
07a06ae9 LH |
1635 | clk_disable(bank->clk); |
1636 | } | |
1637 | ||
1638 | static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d) | |
1639 | { | |
1640 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
1641 | struct rockchip_pin_bank *bank = gc->private; | |
1642 | ||
1643 | clk_enable(bank->clk); | |
1644 | irq_gc_mask_clr_bit(d); | |
1645 | } | |
1646 | ||
1647 | void rockchip_irq_gc_mask_set_bit(struct irq_data *d) | |
1648 | { | |
1649 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
1650 | struct rockchip_pin_bank *bank = gc->private; | |
1651 | ||
1652 | irq_gc_mask_set_bit(d); | |
1653 | clk_disable(bank->clk); | |
f2dd028c DA |
1654 | } |
1655 | ||
d3e51161 HS |
1656 | static int rockchip_interrupts_register(struct platform_device *pdev, |
1657 | struct rockchip_pinctrl *info) | |
1658 | { | |
1659 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1660 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1661 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
1662 | struct irq_chip_generic *gc; | |
1663 | int ret; | |
07a06ae9 | 1664 | int i, j; |
d3e51161 HS |
1665 | |
1666 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1667 | if (!bank->valid) { | |
1668 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1669 | bank->name); | |
1670 | continue; | |
1671 | } | |
1672 | ||
07a06ae9 LH |
1673 | ret = clk_enable(bank->clk); |
1674 | if (ret) { | |
1675 | dev_err(&pdev->dev, "failed to enable clock for bank %s\n", | |
1676 | bank->name); | |
1677 | continue; | |
1678 | } | |
1679 | ||
d3e51161 HS |
1680 | bank->domain = irq_domain_add_linear(bank->of_node, 32, |
1681 | &irq_generic_chip_ops, NULL); | |
1682 | if (!bank->domain) { | |
1683 | dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", | |
1684 | bank->name); | |
07a06ae9 | 1685 | clk_disable(bank->clk); |
d3e51161 HS |
1686 | continue; |
1687 | } | |
1688 | ||
1689 | ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, | |
1690 | "rockchip_gpio_irq", handle_level_irq, | |
1691 | clr, 0, IRQ_GC_INIT_MASK_CACHE); | |
1692 | if (ret) { | |
1693 | dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", | |
1694 | bank->name); | |
1695 | irq_domain_remove(bank->domain); | |
07a06ae9 | 1696 | clk_disable(bank->clk); |
d3e51161 HS |
1697 | continue; |
1698 | } | |
1699 | ||
5ae0c7ad DA |
1700 | /* |
1701 | * Linux assumes that all interrupts start out disabled/masked. | |
1702 | * Our driver only uses the concept of masked and always keeps | |
1703 | * things enabled, so for us that's all masked and all enabled. | |
1704 | */ | |
1705 | writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); | |
1706 | writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); | |
1707 | ||
d3e51161 HS |
1708 | gc = irq_get_domain_generic_chip(bank->domain, 0); |
1709 | gc->reg_base = bank->reg_base; | |
1710 | gc->private = bank; | |
f2dd028c | 1711 | gc->chip_types[0].regs.mask = GPIO_INTMASK; |
d3e51161 HS |
1712 | gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; |
1713 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; | |
07a06ae9 LH |
1714 | gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit; |
1715 | gc->chip_types[0].chip.irq_unmask = | |
1716 | rockchip_irq_gc_mask_clr_bit; | |
d3e51161 | 1717 | gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; |
68bda47c DA |
1718 | gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; |
1719 | gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; | |
d3e51161 | 1720 | gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; |
876d716b | 1721 | gc->wake_enabled = IRQ_MSK(bank->nr_pins); |
d3e51161 | 1722 | |
03051bc2 TG |
1723 | irq_set_chained_handler_and_data(bank->irq, |
1724 | rockchip_irq_demux, bank); | |
07a06ae9 LH |
1725 | |
1726 | /* map the gpio irqs here, when the clock is still running */ | |
1727 | for (j = 0 ; j < 32 ; j++) | |
1728 | irq_create_mapping(bank->domain, j); | |
1729 | ||
1730 | clk_disable(bank->clk); | |
d3e51161 HS |
1731 | } |
1732 | ||
1733 | return 0; | |
1734 | } | |
1735 | ||
1736 | static int rockchip_gpiolib_register(struct platform_device *pdev, | |
1737 | struct rockchip_pinctrl *info) | |
1738 | { | |
1739 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1740 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1741 | struct gpio_chip *gc; | |
1742 | int ret; | |
1743 | int i; | |
1744 | ||
1745 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1746 | if (!bank->valid) { | |
1747 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1748 | bank->name); | |
1749 | continue; | |
1750 | } | |
1751 | ||
1752 | bank->gpio_chip = rockchip_gpiolib_chip; | |
1753 | ||
1754 | gc = &bank->gpio_chip; | |
1755 | gc->base = bank->pin_base; | |
1756 | gc->ngpio = bank->nr_pins; | |
1757 | gc->dev = &pdev->dev; | |
1758 | gc->of_node = bank->of_node; | |
1759 | gc->label = bank->name; | |
1760 | ||
1761 | ret = gpiochip_add(gc); | |
1762 | if (ret) { | |
1763 | dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", | |
1764 | gc->label, ret); | |
1765 | goto fail; | |
1766 | } | |
1767 | } | |
1768 | ||
1769 | rockchip_interrupts_register(pdev, info); | |
1770 | ||
1771 | return 0; | |
1772 | ||
1773 | fail: | |
1774 | for (--i, --bank; i >= 0; --i, --bank) { | |
1775 | if (!bank->valid) | |
1776 | continue; | |
b4e7c55d | 1777 | gpiochip_remove(&bank->gpio_chip); |
d3e51161 HS |
1778 | } |
1779 | return ret; | |
1780 | } | |
1781 | ||
1782 | static int rockchip_gpiolib_unregister(struct platform_device *pdev, | |
1783 | struct rockchip_pinctrl *info) | |
1784 | { | |
1785 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1786 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
d3e51161 HS |
1787 | int i; |
1788 | ||
b4e7c55d | 1789 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { |
d3e51161 HS |
1790 | if (!bank->valid) |
1791 | continue; | |
b4e7c55d | 1792 | gpiochip_remove(&bank->gpio_chip); |
d3e51161 HS |
1793 | } |
1794 | ||
b4e7c55d | 1795 | return 0; |
d3e51161 HS |
1796 | } |
1797 | ||
1798 | static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, | |
622f3237 | 1799 | struct rockchip_pinctrl *info) |
d3e51161 HS |
1800 | { |
1801 | struct resource res; | |
751a99ab | 1802 | void __iomem *base; |
d3e51161 HS |
1803 | |
1804 | if (of_address_to_resource(bank->of_node, 0, &res)) { | |
622f3237 | 1805 | dev_err(info->dev, "cannot find IO resource for bank\n"); |
d3e51161 HS |
1806 | return -ENOENT; |
1807 | } | |
1808 | ||
622f3237 | 1809 | bank->reg_base = devm_ioremap_resource(info->dev, &res); |
d3e51161 HS |
1810 | if (IS_ERR(bank->reg_base)) |
1811 | return PTR_ERR(bank->reg_base); | |
1812 | ||
6ca5274d HS |
1813 | /* |
1814 | * special case, where parts of the pull setting-registers are | |
1815 | * part of the PMU register space | |
1816 | */ | |
1817 | if (of_device_is_compatible(bank->of_node, | |
1818 | "rockchip,rk3188-gpio-bank0")) { | |
a658efaa | 1819 | struct device_node *node; |
bfc7a42a | 1820 | |
a658efaa HS |
1821 | node = of_parse_phandle(bank->of_node->parent, |
1822 | "rockchip,pmu", 0); | |
1823 | if (!node) { | |
1824 | if (of_address_to_resource(bank->of_node, 1, &res)) { | |
1825 | dev_err(info->dev, "cannot find IO resource for bank\n"); | |
1826 | return -ENOENT; | |
1827 | } | |
1828 | ||
1829 | base = devm_ioremap_resource(info->dev, &res); | |
1830 | if (IS_ERR(base)) | |
1831 | return PTR_ERR(base); | |
1832 | rockchip_regmap_config.max_register = | |
1833 | resource_size(&res) - 4; | |
1834 | rockchip_regmap_config.name = | |
1835 | "rockchip,rk3188-gpio-bank0-pull"; | |
1836 | bank->regmap_pull = devm_regmap_init_mmio(info->dev, | |
1837 | base, | |
1838 | &rockchip_regmap_config); | |
6ca5274d | 1839 | } |
6ca5274d | 1840 | } |
65fca613 | 1841 | |
d3e51161 HS |
1842 | bank->irq = irq_of_parse_and_map(bank->of_node, 0); |
1843 | ||
1844 | bank->clk = of_clk_get(bank->of_node, 0); | |
1845 | if (IS_ERR(bank->clk)) | |
1846 | return PTR_ERR(bank->clk); | |
1847 | ||
07a06ae9 | 1848 | return clk_prepare(bank->clk); |
d3e51161 HS |
1849 | } |
1850 | ||
1851 | static const struct of_device_id rockchip_pinctrl_dt_match[]; | |
1852 | ||
1853 | /* retrieve the soc specific data */ | |
1854 | static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( | |
1855 | struct rockchip_pinctrl *d, | |
1856 | struct platform_device *pdev) | |
1857 | { | |
1858 | const struct of_device_id *match; | |
1859 | struct device_node *node = pdev->dev.of_node; | |
1860 | struct device_node *np; | |
1861 | struct rockchip_pin_ctrl *ctrl; | |
1862 | struct rockchip_pin_bank *bank; | |
95ec8ae4 | 1863 | int grf_offs, pmu_offs, i, j; |
d3e51161 HS |
1864 | |
1865 | match = of_match_node(rockchip_pinctrl_dt_match, node); | |
1866 | ctrl = (struct rockchip_pin_ctrl *)match->data; | |
1867 | ||
1868 | for_each_child_of_node(node, np) { | |
1869 | if (!of_find_property(np, "gpio-controller", NULL)) | |
1870 | continue; | |
1871 | ||
1872 | bank = ctrl->pin_banks; | |
1873 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1874 | if (!strcmp(bank->name, np->name)) { | |
1875 | bank->of_node = np; | |
1876 | ||
622f3237 | 1877 | if (!rockchip_get_bank_data(bank, d)) |
d3e51161 HS |
1878 | bank->valid = true; |
1879 | ||
1880 | break; | |
1881 | } | |
1882 | } | |
1883 | } | |
1884 | ||
95ec8ae4 HS |
1885 | grf_offs = ctrl->grf_mux_offset; |
1886 | pmu_offs = ctrl->pmu_mux_offset; | |
d3e51161 HS |
1887 | bank = ctrl->pin_banks; |
1888 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
6bc0d121 HS |
1889 | int bank_pins = 0; |
1890 | ||
d3e51161 HS |
1891 | spin_lock_init(&bank->slock); |
1892 | bank->drvdata = d; | |
1893 | bank->pin_base = ctrl->nr_pins; | |
1894 | ctrl->nr_pins += bank->nr_pins; | |
6bc0d121 HS |
1895 | |
1896 | /* calculate iomux offsets */ | |
1897 | for (j = 0; j < 4; j++) { | |
1898 | struct rockchip_iomux *iom = &bank->iomux[j]; | |
03716e1d | 1899 | int inc; |
6bc0d121 HS |
1900 | |
1901 | if (bank_pins >= bank->nr_pins) | |
1902 | break; | |
1903 | ||
1904 | /* preset offset value, set new start value */ | |
1905 | if (iom->offset >= 0) { | |
95ec8ae4 HS |
1906 | if (iom->type & IOMUX_SOURCE_PMU) |
1907 | pmu_offs = iom->offset; | |
1908 | else | |
1909 | grf_offs = iom->offset; | |
6bc0d121 | 1910 | } else { /* set current offset */ |
95ec8ae4 HS |
1911 | iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? |
1912 | pmu_offs : grf_offs; | |
6bc0d121 HS |
1913 | } |
1914 | ||
1915 | dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", | |
1916 | i, j, iom->offset); | |
1917 | ||
1918 | /* | |
1919 | * Increase offset according to iomux width. | |
03716e1d | 1920 | * 4bit iomux'es are spread over two registers. |
6bc0d121 | 1921 | */ |
03716e1d | 1922 | inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; |
95ec8ae4 HS |
1923 | if (iom->type & IOMUX_SOURCE_PMU) |
1924 | pmu_offs += inc; | |
1925 | else | |
1926 | grf_offs += inc; | |
6bc0d121 HS |
1927 | |
1928 | bank_pins += 8; | |
1929 | } | |
d3e51161 HS |
1930 | } |
1931 | ||
1932 | return ctrl; | |
1933 | } | |
1934 | ||
8dca9331 CZ |
1935 | #define RK3288_GRF_GPIO6C_IOMUX 0x64 |
1936 | #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) | |
1937 | ||
1938 | static u32 rk3288_grf_gpio6c_iomux; | |
1939 | ||
9198f509 CZ |
1940 | static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) |
1941 | { | |
1942 | struct rockchip_pinctrl *info = dev_get_drvdata(dev); | |
8dca9331 CZ |
1943 | int ret = pinctrl_force_sleep(info->pctl_dev); |
1944 | ||
1945 | if (ret) | |
1946 | return ret; | |
1947 | ||
1948 | /* | |
1949 | * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save | |
1950 | * the setting here, and restore it at resume. | |
1951 | */ | |
1952 | if (info->ctrl->type == RK3288) { | |
1953 | ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, | |
1954 | &rk3288_grf_gpio6c_iomux); | |
1955 | if (ret) { | |
1956 | pinctrl_force_default(info->pctl_dev); | |
1957 | return ret; | |
1958 | } | |
1959 | } | |
9198f509 | 1960 | |
8dca9331 | 1961 | return 0; |
9198f509 CZ |
1962 | } |
1963 | ||
1964 | static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) | |
1965 | { | |
1966 | struct rockchip_pinctrl *info = dev_get_drvdata(dev); | |
8dca9331 CZ |
1967 | int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, |
1968 | rk3288_grf_gpio6c_iomux | | |
1969 | GPIO6C6_SEL_WRITE_ENABLE); | |
1970 | ||
1971 | if (ret) | |
1972 | return ret; | |
9198f509 CZ |
1973 | |
1974 | return pinctrl_force_default(info->pctl_dev); | |
1975 | } | |
1976 | ||
1977 | static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, | |
1978 | rockchip_pinctrl_resume); | |
1979 | ||
d3e51161 HS |
1980 | static int rockchip_pinctrl_probe(struct platform_device *pdev) |
1981 | { | |
1982 | struct rockchip_pinctrl *info; | |
1983 | struct device *dev = &pdev->dev; | |
1984 | struct rockchip_pin_ctrl *ctrl; | |
14dee867 | 1985 | struct device_node *np = pdev->dev.of_node, *node; |
d3e51161 | 1986 | struct resource *res; |
751a99ab | 1987 | void __iomem *base; |
d3e51161 HS |
1988 | int ret; |
1989 | ||
1990 | if (!dev->of_node) { | |
1991 | dev_err(dev, "device tree node not found\n"); | |
1992 | return -ENODEV; | |
1993 | } | |
1994 | ||
1995 | info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); | |
1996 | if (!info) | |
1997 | return -ENOMEM; | |
1998 | ||
622f3237 HS |
1999 | info->dev = dev; |
2000 | ||
d3e51161 HS |
2001 | ctrl = rockchip_pinctrl_get_soc_data(info, pdev); |
2002 | if (!ctrl) { | |
2003 | dev_err(dev, "driver data not available\n"); | |
2004 | return -EINVAL; | |
2005 | } | |
2006 | info->ctrl = ctrl; | |
d3e51161 | 2007 | |
1e747e59 HS |
2008 | node = of_parse_phandle(np, "rockchip,grf", 0); |
2009 | if (node) { | |
2010 | info->regmap_base = syscon_node_to_regmap(node); | |
2011 | if (IS_ERR(info->regmap_base)) | |
2012 | return PTR_ERR(info->regmap_base); | |
2013 | } else { | |
2014 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
751a99ab HS |
2015 | base = devm_ioremap_resource(&pdev->dev, res); |
2016 | if (IS_ERR(base)) | |
2017 | return PTR_ERR(base); | |
2018 | ||
2019 | rockchip_regmap_config.max_register = resource_size(res) - 4; | |
1e747e59 HS |
2020 | rockchip_regmap_config.name = "rockchip,pinctrl"; |
2021 | info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, | |
2022 | &rockchip_regmap_config); | |
2023 | ||
2024 | /* to check for the old dt-bindings */ | |
2025 | info->reg_size = resource_size(res); | |
2026 | ||
2027 | /* Honor the old binding, with pull registers as 2nd resource */ | |
2028 | if (ctrl->type == RK3188 && info->reg_size < 0x200) { | |
2029 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
2030 | base = devm_ioremap_resource(&pdev->dev, res); | |
2031 | if (IS_ERR(base)) | |
2032 | return PTR_ERR(base); | |
2033 | ||
2034 | rockchip_regmap_config.max_register = | |
2035 | resource_size(res) - 4; | |
2036 | rockchip_regmap_config.name = "rockchip,pinctrl-pull"; | |
2037 | info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, | |
2038 | base, | |
2039 | &rockchip_regmap_config); | |
2040 | } | |
6ca5274d HS |
2041 | } |
2042 | ||
14dee867 HS |
2043 | /* try to find the optional reference to the pmu syscon */ |
2044 | node = of_parse_phandle(np, "rockchip,pmu", 0); | |
2045 | if (node) { | |
2046 | info->regmap_pmu = syscon_node_to_regmap(node); | |
2047 | if (IS_ERR(info->regmap_pmu)) | |
2048 | return PTR_ERR(info->regmap_pmu); | |
2049 | } | |
2050 | ||
d3e51161 HS |
2051 | ret = rockchip_gpiolib_register(pdev, info); |
2052 | if (ret) | |
2053 | return ret; | |
2054 | ||
2055 | ret = rockchip_pinctrl_register(pdev, info); | |
2056 | if (ret) { | |
2057 | rockchip_gpiolib_unregister(pdev, info); | |
2058 | return ret; | |
2059 | } | |
2060 | ||
2061 | platform_set_drvdata(pdev, info); | |
2062 | ||
2063 | return 0; | |
2064 | } | |
2065 | ||
2066 | static struct rockchip_pin_bank rk2928_pin_banks[] = { | |
2067 | PIN_BANK(0, 32, "gpio0"), | |
2068 | PIN_BANK(1, 32, "gpio1"), | |
2069 | PIN_BANK(2, 32, "gpio2"), | |
2070 | PIN_BANK(3, 32, "gpio3"), | |
2071 | }; | |
2072 | ||
2073 | static struct rockchip_pin_ctrl rk2928_pin_ctrl = { | |
2074 | .pin_banks = rk2928_pin_banks, | |
2075 | .nr_banks = ARRAY_SIZE(rk2928_pin_banks), | |
2076 | .label = "RK2928-GPIO", | |
a282926d | 2077 | .type = RK2928, |
95ec8ae4 | 2078 | .grf_mux_offset = 0xa8, |
a282926d | 2079 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
2080 | }; |
2081 | ||
c5ce7670 XZ |
2082 | static struct rockchip_pin_bank rk3036_pin_banks[] = { |
2083 | PIN_BANK(0, 32, "gpio0"), | |
2084 | PIN_BANK(1, 32, "gpio1"), | |
2085 | PIN_BANK(2, 32, "gpio2"), | |
2086 | }; | |
2087 | ||
2088 | static struct rockchip_pin_ctrl rk3036_pin_ctrl = { | |
2089 | .pin_banks = rk3036_pin_banks, | |
2090 | .nr_banks = ARRAY_SIZE(rk3036_pin_banks), | |
2091 | .label = "RK3036-GPIO", | |
2092 | .type = RK2928, | |
2093 | .grf_mux_offset = 0xa8, | |
2094 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, | |
2095 | }; | |
2096 | ||
d3e51161 HS |
2097 | static struct rockchip_pin_bank rk3066a_pin_banks[] = { |
2098 | PIN_BANK(0, 32, "gpio0"), | |
2099 | PIN_BANK(1, 32, "gpio1"), | |
2100 | PIN_BANK(2, 32, "gpio2"), | |
2101 | PIN_BANK(3, 32, "gpio3"), | |
2102 | PIN_BANK(4, 32, "gpio4"), | |
2103 | PIN_BANK(6, 16, "gpio6"), | |
2104 | }; | |
2105 | ||
2106 | static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { | |
2107 | .pin_banks = rk3066a_pin_banks, | |
2108 | .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), | |
2109 | .label = "RK3066a-GPIO", | |
a282926d | 2110 | .type = RK2928, |
95ec8ae4 | 2111 | .grf_mux_offset = 0xa8, |
a282926d | 2112 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
2113 | }; |
2114 | ||
2115 | static struct rockchip_pin_bank rk3066b_pin_banks[] = { | |
2116 | PIN_BANK(0, 32, "gpio0"), | |
2117 | PIN_BANK(1, 32, "gpio1"), | |
2118 | PIN_BANK(2, 32, "gpio2"), | |
2119 | PIN_BANK(3, 32, "gpio3"), | |
2120 | }; | |
2121 | ||
2122 | static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { | |
2123 | .pin_banks = rk3066b_pin_banks, | |
2124 | .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), | |
2125 | .label = "RK3066b-GPIO", | |
a282926d | 2126 | .type = RK3066B, |
95ec8ae4 | 2127 | .grf_mux_offset = 0x60, |
d3e51161 HS |
2128 | }; |
2129 | ||
2130 | static struct rockchip_pin_bank rk3188_pin_banks[] = { | |
fc72c923 | 2131 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), |
d3e51161 HS |
2132 | PIN_BANK(1, 32, "gpio1"), |
2133 | PIN_BANK(2, 32, "gpio2"), | |
2134 | PIN_BANK(3, 32, "gpio3"), | |
2135 | }; | |
2136 | ||
2137 | static struct rockchip_pin_ctrl rk3188_pin_ctrl = { | |
2138 | .pin_banks = rk3188_pin_banks, | |
2139 | .nr_banks = ARRAY_SIZE(rk3188_pin_banks), | |
2140 | .label = "RK3188-GPIO", | |
a282926d | 2141 | .type = RK3188, |
95ec8ae4 | 2142 | .grf_mux_offset = 0x60, |
6ca5274d | 2143 | .pull_calc_reg = rk3188_calc_pull_reg_and_bit, |
d3e51161 HS |
2144 | }; |
2145 | ||
304f077d HS |
2146 | static struct rockchip_pin_bank rk3288_pin_banks[] = { |
2147 | PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, | |
2148 | IOMUX_SOURCE_PMU, | |
2149 | IOMUX_SOURCE_PMU, | |
2150 | IOMUX_UNROUTED | |
2151 | ), | |
2152 | PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, | |
2153 | IOMUX_UNROUTED, | |
2154 | IOMUX_UNROUTED, | |
2155 | 0 | |
2156 | ), | |
2157 | PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), | |
2158 | PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), | |
2159 | PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, | |
2160 | IOMUX_WIDTH_4BIT, | |
2161 | 0, | |
2162 | 0 | |
2163 | ), | |
2164 | PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, | |
2165 | 0, | |
2166 | 0, | |
2167 | IOMUX_UNROUTED | |
2168 | ), | |
2169 | PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), | |
2170 | PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, | |
2171 | 0, | |
2172 | IOMUX_WIDTH_4BIT, | |
2173 | IOMUX_UNROUTED | |
2174 | ), | |
2175 | PIN_BANK(8, 16, "gpio8"), | |
2176 | }; | |
2177 | ||
2178 | static struct rockchip_pin_ctrl rk3288_pin_ctrl = { | |
2179 | .pin_banks = rk3288_pin_banks, | |
2180 | .nr_banks = ARRAY_SIZE(rk3288_pin_banks), | |
2181 | .label = "RK3288-GPIO", | |
66d750e1 | 2182 | .type = RK3288, |
304f077d HS |
2183 | .grf_mux_offset = 0x0, |
2184 | .pmu_mux_offset = 0x84, | |
2185 | .pull_calc_reg = rk3288_calc_pull_reg_and_bit, | |
ef17f69f | 2186 | .drv_calc_reg = rk3288_calc_drv_reg_and_bit, |
304f077d HS |
2187 | }; |
2188 | ||
daecdc66 HS |
2189 | static struct rockchip_pin_bank rk3368_pin_banks[] = { |
2190 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, | |
2191 | IOMUX_SOURCE_PMU, | |
2192 | IOMUX_SOURCE_PMU, | |
2193 | IOMUX_SOURCE_PMU | |
2194 | ), | |
2195 | PIN_BANK(1, 32, "gpio1"), | |
2196 | PIN_BANK(2, 32, "gpio2"), | |
2197 | PIN_BANK(3, 32, "gpio3"), | |
2198 | }; | |
2199 | ||
2200 | static struct rockchip_pin_ctrl rk3368_pin_ctrl = { | |
2201 | .pin_banks = rk3368_pin_banks, | |
2202 | .nr_banks = ARRAY_SIZE(rk3368_pin_banks), | |
2203 | .label = "RK3368-GPIO", | |
2204 | .type = RK3368, | |
2205 | .grf_mux_offset = 0x0, | |
2206 | .pmu_mux_offset = 0x0, | |
2207 | .pull_calc_reg = rk3368_calc_pull_reg_and_bit, | |
2208 | .drv_calc_reg = rk3368_calc_drv_reg_and_bit, | |
2209 | }; | |
2210 | ||
2211 | ||
d3e51161 HS |
2212 | static const struct of_device_id rockchip_pinctrl_dt_match[] = { |
2213 | { .compatible = "rockchip,rk2928-pinctrl", | |
2214 | .data = (void *)&rk2928_pin_ctrl }, | |
c5ce7670 XZ |
2215 | { .compatible = "rockchip,rk3036-pinctrl", |
2216 | .data = (void *)&rk3036_pin_ctrl }, | |
d3e51161 HS |
2217 | { .compatible = "rockchip,rk3066a-pinctrl", |
2218 | .data = (void *)&rk3066a_pin_ctrl }, | |
2219 | { .compatible = "rockchip,rk3066b-pinctrl", | |
2220 | .data = (void *)&rk3066b_pin_ctrl }, | |
2221 | { .compatible = "rockchip,rk3188-pinctrl", | |
2222 | .data = (void *)&rk3188_pin_ctrl }, | |
304f077d HS |
2223 | { .compatible = "rockchip,rk3288-pinctrl", |
2224 | .data = (void *)&rk3288_pin_ctrl }, | |
daecdc66 HS |
2225 | { .compatible = "rockchip,rk3368-pinctrl", |
2226 | .data = (void *)&rk3368_pin_ctrl }, | |
d3e51161 HS |
2227 | {}, |
2228 | }; | |
2229 | MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); | |
2230 | ||
2231 | static struct platform_driver rockchip_pinctrl_driver = { | |
2232 | .probe = rockchip_pinctrl_probe, | |
2233 | .driver = { | |
2234 | .name = "rockchip-pinctrl", | |
9198f509 | 2235 | .pm = &rockchip_pinctrl_dev_pm_ops, |
0be9e70d | 2236 | .of_match_table = rockchip_pinctrl_dt_match, |
d3e51161 HS |
2237 | }, |
2238 | }; | |
2239 | ||
2240 | static int __init rockchip_pinctrl_drv_register(void) | |
2241 | { | |
2242 | return platform_driver_register(&rockchip_pinctrl_driver); | |
2243 | } | |
2244 | postcore_initcall(rockchip_pinctrl_drv_register); | |
2245 | ||
2246 | MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); | |
2247 | MODULE_DESCRIPTION("Rockchip pinctrl driver"); | |
2248 | MODULE_LICENSE("GPL v2"); |