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pinctrl: rockchip：Add input schmitt support
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
d3e51161
HS		 1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
2f436204 26#include <linux/init.h>
d3e51161
HS		 27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
7e865abb 39#include <linux/clk.h>
751a99ab 40#include <linux/regmap.h>
14dee867 41#include <linux/mfd/syscon.h>
d3e51161
HS		 42#include <dt-bindings/pinctrl/rockchip.h>
43
44#include "core.h"
45#include "pinconf.h"
46
47/* GPIO control registers */
48#define GPIO_SWPORT_DR 0x00
49#define GPIO_SWPORT_DDR 0x04
50#define GPIO_INTEN 0x30
51#define GPIO_INTMASK 0x34
52#define GPIO_INTTYPE_LEVEL 0x38
53#define GPIO_INT_POLARITY 0x3c
54#define GPIO_INT_STATUS 0x40
55#define GPIO_INT_RAWSTATUS 0x44
56#define GPIO_DEBOUNCE 0x48
57#define GPIO_PORTS_EOI 0x4c
58#define GPIO_EXT_PORT 0x50
59#define GPIO_LS_SYNC 0x60
60
a282926d 61enum rockchip_pinctrl_type {
688daf23 62 RK1108,
a282926d
HS		 63 RK2928,
64 RK3066B,
65 RK3188,
66d750e1 66 RK3288,
daecdc66 67 RK3368,
b6c23275 68 RK3399,
a282926d
HS		 69};
70
fc72c923
HS		 71/**
72 * Encode variants of iomux registers into a type variable
73 */
74#define IOMUX_GPIO_ONLY BIT(0)
03716e1d 75#define IOMUX_WIDTH_4BIT BIT(1)
95ec8ae4 76#define IOMUX_SOURCE_PMU BIT(2)
62f49226 77#define IOMUX_UNROUTED BIT(3)
8b6c6f93 78#define IOMUX_WIDTH_3BIT BIT(4)
ea262ad6 79#define IOMUX_RECALCED BIT(5)
fc72c923
HS		 80
81/**
82 * @type: iomux variant using IOMUX_* constants
6bc0d121
HS		 83 * @offset: if initialized to -1 it will be autocalculated, by specifying
84 * an initial offset value the relevant source offset can be reset
85 * to a new value for autocalculating the following iomux registers.
fc72c923
HS		 86 */
87struct rockchip_iomux {
88 int type;
6bc0d121 89 int offset;
65fca613
HS		 90};
91
b6c23275
DW		 92/**
93 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
94 */
95enum rockchip_pin_drv_type {
96 DRV_TYPE_IO_DEFAULT = 0,
97 DRV_TYPE_IO_1V8_OR_3V0,
98 DRV_TYPE_IO_1V8_ONLY,
99 DRV_TYPE_IO_1V8_3V0_AUTO,
100 DRV_TYPE_IO_3V3_ONLY,
101 DRV_TYPE_MAX
102};
103
3ba6767a
DW		 104/**
105 * enum type index corresponding to rockchip_pull_list arrays index.
106 */
107enum rockchip_pin_pull_type {
108 PULL_TYPE_IO_DEFAULT = 0,
109 PULL_TYPE_IO_1V8_ONLY,
110 PULL_TYPE_MAX
111};
112
b6c23275
DW		 113/**
114 * @drv_type: drive strength variant using rockchip_perpin_drv_type
115 * @offset: if initialized to -1 it will be autocalculated, by specifying
116 * an initial offset value the relevant source offset can be reset
117 * to a new value for autocalculating the following drive strength
118 * registers. if used chips own cal_drv func instead to calculate
119 * registers offset, the variant could be ignored.
120 */
121struct rockchip_drv {
122 enum rockchip_pin_drv_type drv_type;
123 int offset;
124};
125
d3e51161
HS		 126/**
127 * @reg_base: register base of the gpio bank
6ca5274d 128 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 129 * @clk: clock of the gpio bank
130 * @irq: interrupt of the gpio bank
5ae0c7ad 131 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
d3e51161
HS		 132 * @pin_base: first pin number
133 * @nr_pins: number of pins in this bank
134 * @name: name of the bank
135 * @bank_num: number of the bank, to account for holes
fc72c923 136 * @iomux: array describing the 4 iomux sources of the bank
b6c23275 137 * @drv: array describing the 4 drive strength sources of the bank
3ba6767a 138 * @pull_type: array describing the 4 pull type sources of the bank
d3e51161
HS		 139 * @valid: are all necessary informations present
140 * @of_node: dt node of this bank
141 * @drvdata: common pinctrl basedata
142 * @domain: irqdomain of the gpio bank
143 * @gpio_chip: gpiolib chip
144 * @grange: gpio range
145 * @slock: spinlock for the gpio bank
146 */
147struct rockchip_pin_bank {
148 void __iomem *reg_base;
751a99ab 149 struct regmap *regmap_pull;
d3e51161
HS		 150 struct clk *clk;
151 int irq;
5ae0c7ad 152 u32 saved_masks;
d3e51161
HS		 153 u32 pin_base;
154 u8 nr_pins;
155 char *name;
156 u8 bank_num;
fc72c923 157 struct rockchip_iomux iomux[4];
b6c23275 158 struct rockchip_drv drv[4];
3ba6767a 159 enum rockchip_pin_pull_type pull_type[4];
d3e51161
HS		 160 bool valid;
161 struct device_node *of_node;
162 struct rockchip_pinctrl *drvdata;
163 struct irq_domain *domain;
164 struct gpio_chip gpio_chip;
165 struct pinctrl_gpio_range grange;
166 spinlock_t slock;
5a927501 167 u32 toggle_edge_mode;
d3e51161
HS		 168};
169
170#define PIN_BANK(id, pins, label) \
171 { \
172 .bank_num = id, \
173 .nr_pins = pins, \
174 .name = label, \
6bc0d121
HS		 175 .iomux = { \
176 { .offset = -1 }, \
177 { .offset = -1 }, \
178 { .offset = -1 }, \
179 { .offset = -1 }, \
180 }, \
d3e51161
HS		 181 }
182
fc72c923
HS		 183#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
184 { \
185 .bank_num = id, \
186 .nr_pins = pins, \
187 .name = label, \
188 .iomux = { \
6bc0d121
HS		 189 { .type = iom0, .offset = -1 }, \
190 { .type = iom1, .offset = -1 }, \
191 { .type = iom2, .offset = -1 }, \
192 { .type = iom3, .offset = -1 }, \
fc72c923
HS		 193 }, \
194 }
195
b6c23275
DW		 196#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
197 { \
198 .bank_num = id, \
199 .nr_pins = pins, \
200 .name = label, \
201 .iomux = { \
202 { .offset = -1 }, \
203 { .offset = -1 }, \
204 { .offset = -1 }, \
205 { .offset = -1 }, \
206 }, \
207 .drv = { \
208 { .drv_type = type0, .offset = -1 }, \
209 { .drv_type = type1, .offset = -1 }, \
210 { .drv_type = type2, .offset = -1 }, \
211 { .drv_type = type3, .offset = -1 }, \
212 }, \
213 }
214
3ba6767a
DW		 215#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
216 drv2, drv3, pull0, pull1, \
217 pull2, pull3) \
218 { \
219 .bank_num = id, \
220 .nr_pins = pins, \
221 .name = label, \
222 .iomux = { \
223 { .offset = -1 }, \
224 { .offset = -1 }, \
225 { .offset = -1 }, \
226 { .offset = -1 }, \
227 }, \
228 .drv = { \
229 { .drv_type = drv0, .offset = -1 }, \
230 { .drv_type = drv1, .offset = -1 }, \
231 { .drv_type = drv2, .offset = -1 }, \
232 { .drv_type = drv3, .offset = -1 }, \
233 }, \
234 .pull_type[0] = pull0, \
235 .pull_type[1] = pull1, \
236 .pull_type[2] = pull2, \
237 .pull_type[3] = pull3, \
238 }
239
b6c23275
DW		 240#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
241 iom2, iom3, drv0, drv1, drv2, \
242 drv3, offset0, offset1, \
243 offset2, offset3) \
244 { \
245 .bank_num = id, \
246 .nr_pins = pins, \
247 .name = label, \
248 .iomux = { \
249 { .type = iom0, .offset = -1 }, \
250 { .type = iom1, .offset = -1 }, \
251 { .type = iom2, .offset = -1 }, \
252 { .type = iom3, .offset = -1 }, \
253 }, \
254 .drv = { \
255 { .drv_type = drv0, .offset = offset0 }, \
256 { .drv_type = drv1, .offset = offset1 }, \
257 { .drv_type = drv2, .offset = offset2 }, \
258 { .drv_type = drv3, .offset = offset3 }, \
259 }, \
260 }
261
3ba6767a
DW		 262#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
263 label, iom0, iom1, iom2, \
264 iom3, drv0, drv1, drv2, \
265 drv3, offset0, offset1, \
266 offset2, offset3, pull0, \
267 pull1, pull2, pull3) \
268 { \
269 .bank_num = id, \
270 .nr_pins = pins, \
271 .name = label, \
272 .iomux = { \
273 { .type = iom0, .offset = -1 }, \
274 { .type = iom1, .offset = -1 }, \
275 { .type = iom2, .offset = -1 }, \
276 { .type = iom3, .offset = -1 }, \
277 }, \
278 .drv = { \
279 { .drv_type = drv0, .offset = offset0 }, \
280 { .drv_type = drv1, .offset = offset1 }, \
281 { .drv_type = drv2, .offset = offset2 }, \
282 { .drv_type = drv3, .offset = offset3 }, \
283 }, \
284 .pull_type[0] = pull0, \
285 .pull_type[1] = pull1, \
286 .pull_type[2] = pull2, \
287 .pull_type[3] = pull3, \
288 }
289
d3e51161 290/**
d3e51161
HS		 291 */
292struct rockchip_pin_ctrl {
293 struct rockchip_pin_bank *pin_banks;
294 u32 nr_banks;
295 u32 nr_pins;
296 char *label;
a282926d 297 enum rockchip_pinctrl_type type;
95ec8ae4
HS		 298 int grf_mux_offset;
299 int pmu_mux_offset;
b6c23275
DW		 300 int grf_drv_offset;
301 int pmu_drv_offset;
302
751a99ab
HS		 303 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
304 int pin_num, struct regmap **regmap,
305 int *reg, u8 *bit);
ef17f69f
HS		 306 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
307 int pin_num, struct regmap **regmap,
308 int *reg, u8 *bit);
ea262ad6 309 void (*iomux_recalc)(u8 bank_num, int pin, int *reg,
310 u8 *bit, int *mask);
e3b357d7 311 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
312 int pin_num, struct regmap **regmap,
313 int *reg, u8 *bit);
d3e51161
HS		 314};
315
316struct rockchip_pin_config {
317 unsigned int func;
318 unsigned long *configs;
319 unsigned int nconfigs;
320};
321
322/**
323 * struct rockchip_pin_group: represent group of pins of a pinmux function.
324 * @name: name of the pin group, used to lookup the group.
325 * @pins: the pins included in this group.
326 * @npins: number of pins included in this group.
327 * @func: the mux function number to be programmed when selected.
328 * @configs: the config values to be set for each pin
329 * @nconfigs: number of configs for each pin
330 */
331struct rockchip_pin_group {
332 const char *name;
333 unsigned int npins;
334 unsigned int *pins;
335 struct rockchip_pin_config *data;
336};
337
338/**
339 * struct rockchip_pmx_func: represent a pin function.
340 * @name: name of the pin function, used to lookup the function.
341 * @groups: one or more names of pin groups that provide this function.
342 * @num_groups: number of groups included in @groups.
343 */
344struct rockchip_pmx_func {
345 const char *name;
346 const char **groups;
347 u8 ngroups;
348};
349
350struct rockchip_pinctrl {
751a99ab 351 struct regmap *regmap_base;
bfc7a42a 352 int reg_size;
751a99ab 353 struct regmap *regmap_pull;
14dee867 354 struct regmap *regmap_pmu;
d3e51161
HS		 355 struct device *dev;
356 struct rockchip_pin_ctrl *ctrl;
357 struct pinctrl_desc pctl;
358 struct pinctrl_dev *pctl_dev;
359 struct rockchip_pin_group *groups;
360 unsigned int ngroups;
361 struct rockchip_pmx_func *functions;
362 unsigned int nfunctions;
363};
364
ea262ad6 365/**
366 * struct rockchip_mux_recalced_data: represent a pin iomux data.
367 * @num: bank number.
368 * @pin: pin number.
369 * @bit: index at register.
370 * @reg: register offset.
371 * @mask: mask bit
372 */
373struct rockchip_mux_recalced_data {
374 u8 num;
375 u8 pin;
376 u8 reg;
377 u8 bit;
378 u8 mask;
379};
380
751a99ab
HS		 381static struct regmap_config rockchip_regmap_config = {
382 .reg_bits = 32,
383 .val_bits = 32,
384 .reg_stride = 4,
385};
386
56411f3c 387static inline const struct rockchip_pin_group *pinctrl_name_to_group(
d3e51161
HS		 388 const struct rockchip_pinctrl *info,
389 const char *name)
390{
d3e51161
HS		 391 int i;
392
393 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 394 if (!strcmp(info->groups[i].name, name))
395 return &info->groups[i];
d3e51161
HS		 396 }
397
1cb95395 398 return NULL;
d3e51161
HS		 399}
400
401/*
402 * given a pin number that is local to a pin controller, find out the pin bank
403 * and the register base of the pin bank.
404 */
405static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
406 unsigned pin)
407{
408 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
409
51578b9b 410 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 411 b++;
412
413 return b;
414}
415
416static struct rockchip_pin_bank *bank_num_to_bank(
417 struct rockchip_pinctrl *info,
418 unsigned num)
419{
420 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
421 int i;
422
1cb95395 423 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 424 if (b->bank_num == num)
1cb95395 425 return b;
d3e51161
HS		 426 }
427
1cb95395 428 return ERR_PTR(-EINVAL);
d3e51161
HS		 429}
430
431/*
432 * Pinctrl_ops handling
433 */
434
435static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
436{
437 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
438
439 return info->ngroups;
440}
441
442static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
443 unsigned selector)
444{
445 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
446
447 return info->groups[selector].name;
448}
449
450static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
451 unsigned selector, const unsigned **pins,
452 unsigned *npins)
453{
454 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
455
456 if (selector >= info->ngroups)
457 return -EINVAL;
458
459 *pins = info->groups[selector].pins;
460 *npins = info->groups[selector].npins;
461
462 return 0;
463}
464
465static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
466 struct device_node *np,
467 struct pinctrl_map **map, unsigned *num_maps)
468{
469 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
470 const struct rockchip_pin_group *grp;
471 struct pinctrl_map *new_map;
472 struct device_node *parent;
473 int map_num = 1;
474 int i;
475
476 /*
477 * first find the group of this node and check if we need to create
478 * config maps for pins
479 */
480 grp = pinctrl_name_to_group(info, np->name);
481 if (!grp) {
482 dev_err(info->dev, "unable to find group for node %s\n",
483 np->name);
484 return -EINVAL;
485 }
486
487 map_num += grp->npins;
488 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
489 GFP_KERNEL);
490 if (!new_map)
491 return -ENOMEM;
492
493 *map = new_map;
494 *num_maps = map_num;
495
496 /* create mux map */
497 parent = of_get_parent(np);
498 if (!parent) {
499 devm_kfree(pctldev->dev, new_map);
500 return -EINVAL;
501 }
502 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
503 new_map[0].data.mux.function = parent->name;
504 new_map[0].data.mux.group = np->name;
505 of_node_put(parent);
506
507 /* create config map */
508 new_map++;
509 for (i = 0; i < grp->npins; i++) {
510 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
511 new_map[i].data.configs.group_or_pin =
512 pin_get_name(pctldev, grp->pins[i]);
513 new_map[i].data.configs.configs = grp->data[i].configs;
514 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
515 }
516
517 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
518 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
519
520 return 0;
521}
522
523static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
524 struct pinctrl_map *map, unsigned num_maps)
525{
526}
527
528static const struct pinctrl_ops rockchip_pctrl_ops = {
529 .get_groups_count = rockchip_get_groups_count,
530 .get_group_name = rockchip_get_group_name,
531 .get_group_pins = rockchip_get_group_pins,
532 .dt_node_to_map = rockchip_dt_node_to_map,
533 .dt_free_map = rockchip_dt_free_map,
534};
535
536/*
537 * Hardware access
538 */
539
3818e4a7 540static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
541 {
542 .num = 2,
543 .pin = 12,
544 .reg = 0x24,
545 .bit = 8,
546 .mask = 0x3
547 }, {
548 .num = 2,
549 .pin = 15,
550 .reg = 0x28,
551 .bit = 0,
552 .mask = 0x7
553 }, {
554 .num = 2,
555 .pin = 23,
556 .reg = 0x30,
557 .bit = 14,
558 .mask = 0x3
559 },
560};
561
562static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
563 u8 *bit, int *mask)
564{
565 const struct rockchip_mux_recalced_data *data = NULL;
566 int i;
567
568 for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++)
569 if (rk3328_mux_recalced_data[i].num == bank_num &&
570 rk3328_mux_recalced_data[i].pin == pin) {
571 data = &rk3328_mux_recalced_data[i];
572 break;
573 }
574
575 if (!data)
576 return;
577
578 *reg = data->reg;
579 *mask = data->mask;
580 *bit = data->bit;
581}
582
a076e2ed
HS		 583static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
584{
585 struct rockchip_pinctrl *info = bank->drvdata;
ea262ad6 586 struct rockchip_pin_ctrl *ctrl = info->ctrl;
fc72c923 587 int iomux_num = (pin / 8);
95ec8ae4 588 struct regmap *regmap;
751a99ab 589 unsigned int val;
ea262ad6 590 int reg, ret, mask, mux_type;
a076e2ed
HS		 591 u8 bit;
592
fc72c923
HS		 593 if (iomux_num > 3)
594 return -EINVAL;
595
62f49226
HS		 596 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
597 dev_err(info->dev, "pin %d is unrouted\n", pin);
598 return -EINVAL;
599 }
600
fc72c923 601 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
a076e2ed
HS		 602 return RK_FUNC_GPIO;
603
95ec8ae4
HS		 604 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
605 ? info->regmap_pmu : info->regmap_base;
606
a076e2ed 607 /* get basic quadrupel of mux registers and the correct reg inside */
ea262ad6 608 mux_type = bank->iomux[iomux_num].type;
6bc0d121 609 reg = bank->iomux[iomux_num].offset;
ea262ad6 610 if (mux_type & IOMUX_WIDTH_4BIT) {
03716e1d
HS		 611 if ((pin % 8) >= 4)
612 reg += 0x4;
613 bit = (pin % 4) * 4;
8b6c6f93 614 mask = 0xf;
ea262ad6 615 } else if (mux_type & IOMUX_WIDTH_3BIT) {
8b6c6f93 616 if ((pin % 8) >= 5)
617 reg += 0x4;
618 bit = (pin % 8 % 5) * 3;
619 mask = 0x7;
03716e1d
HS		 620 } else {
621 bit = (pin % 8) * 2;
8b6c6f93 622 mask = 0x3;
03716e1d 623 }
a076e2ed 624
ea262ad6 625 if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
626 ctrl->iomux_recalc(bank->bank_num, pin, &reg, &bit, &mask);
627
95ec8ae4 628 ret = regmap_read(regmap, reg, &val);
751a99ab
HS		 629 if (ret)
630 return ret;
631
03716e1d 632 return ((val >> bit) & mask);
a076e2ed
HS		 633}
634
d3e51161
HS		 635/*
636 * Set a new mux function for a pin.
637 *
638 * The register is divided into the upper and lower 16 bit. When changing
639 * a value, the previous register value is not read and changed. Instead
640 * it seems the changed bits are marked in the upper 16 bit, while the
641 * changed value gets set in the same offset in the lower 16 bit.
642 * All pin settings seem to be 2 bit wide in both the upper and lower
643 * parts.
644 * @bank: pin bank to change
645 * @pin: pin to change
646 * @mux: new mux function to set
647 */
14797189 648static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 649{
650 struct rockchip_pinctrl *info = bank->drvdata;
ea262ad6 651 struct rockchip_pin_ctrl *ctrl = info->ctrl;
fc72c923 652 int iomux_num = (pin / 8);
95ec8ae4 653 struct regmap *regmap;
ea262ad6 654 int reg, ret, mask, mux_type;
d3e51161
HS		 655 unsigned long flags;
656 u8 bit;
99e872d9 657 u32 data, rmask;
d3e51161 658
fc72c923
HS		 659 if (iomux_num > 3)
660 return -EINVAL;
661
62f49226
HS		 662 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
663 dev_err(info->dev, "pin %d is unrouted\n", pin);
664 return -EINVAL;
665 }
666
fc72c923 667 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
c4a532de
HS		 668 if (mux != RK_FUNC_GPIO) {
669 dev_err(info->dev,
670 "pin %d only supports a gpio mux\n", pin);
671 return -ENOTSUPP;
672 } else {
673 return 0;
674 }
675 }
676
d3e51161
HS		 677 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
678 bank->bank_num, pin, mux);
679
95ec8ae4
HS		 680 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
681 ? info->regmap_pmu : info->regmap_base;
682
d3e51161 683 /* get basic quadrupel of mux registers and the correct reg inside */
ea262ad6 684 mux_type = bank->iomux[iomux_num].type;
6bc0d121 685 reg = bank->iomux[iomux_num].offset;
ea262ad6 686 if (mux_type & IOMUX_WIDTH_4BIT) {
03716e1d
HS		 687 if ((pin % 8) >= 4)
688 reg += 0x4;
689 bit = (pin % 4) * 4;
8b6c6f93 690 mask = 0xf;
ea262ad6 691 } else if (mux_type & IOMUX_WIDTH_3BIT) {
8b6c6f93 692 if ((pin % 8) >= 5)
693 reg += 0x4;
694 bit = (pin % 8 % 5) * 3;
695 mask = 0x7;
03716e1d
HS		 696 } else {
697 bit = (pin % 8) * 2;
8b6c6f93 698 mask = 0x3;
03716e1d 699 }
d3e51161 700
ea262ad6 701 if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
702 ctrl->iomux_recalc(bank->bank_num, pin, &reg, &bit, &mask);
703
d3e51161
HS		 704 spin_lock_irqsave(&bank->slock, flags);
705
03716e1d 706 data = (mask << (bit + 16));
99e872d9 707 rmask = data | (data >> 16);
03716e1d 708 data |= (mux & mask) << bit;
99e872d9 709 ret = regmap_update_bits(regmap, reg, rmask, data);
d3e51161
HS		 710
711 spin_unlock_irqrestore(&bank->slock, flags);
14797189 712
751a99ab 713 return ret;
d3e51161
HS		 714}
715
688daf23
AY		 716#define RK1108_PULL_PMU_OFFSET 0x10
717#define RK1108_PULL_OFFSET 0x110
718#define RK1108_PULL_PINS_PER_REG 8
719#define RK1108_PULL_BITS_PER_PIN 2
720#define RK1108_PULL_BANK_STRIDE 16
721
722static void rk1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
723 int pin_num, struct regmap **regmap,
724 int *reg, u8 *bit)
725{
726 struct rockchip_pinctrl *info = bank->drvdata;
727
728 /* The first 24 pins of the first bank are located in PMU */
729 if (bank->bank_num == 0) {
730 *regmap = info->regmap_pmu;
731 *reg = RK1108_PULL_PMU_OFFSET;
732 } else {
733 *reg = RK1108_PULL_OFFSET;
734 *regmap = info->regmap_base;
735 /* correct the offset, as we're starting with the 2nd bank */
736 *reg -= 0x10;
737 *reg += bank->bank_num * RK1108_PULL_BANK_STRIDE;
738 }
739
740 *reg += ((pin_num / RK1108_PULL_PINS_PER_REG) * 4);
741 *bit = (pin_num % RK1108_PULL_PINS_PER_REG);
742 *bit *= RK1108_PULL_BITS_PER_PIN;
743}
744
745#define RK1108_DRV_PMU_OFFSET 0x20
746#define RK1108_DRV_GRF_OFFSET 0x210
747#define RK1108_DRV_BITS_PER_PIN 2
748#define RK1108_DRV_PINS_PER_REG 8
749#define RK1108_DRV_BANK_STRIDE 16
750
751static void rk1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
752 int pin_num, struct regmap **regmap,
753 int *reg, u8 *bit)
754{
755 struct rockchip_pinctrl *info = bank->drvdata;
756
757 /* The first 24 pins of the first bank are located in PMU */
758 if (bank->bank_num == 0) {
759 *regmap = info->regmap_pmu;
760 *reg = RK1108_DRV_PMU_OFFSET;
761 } else {
762 *regmap = info->regmap_base;
763 *reg = RK1108_DRV_GRF_OFFSET;
764
765 /* correct the offset, as we're starting with the 2nd bank */
766 *reg -= 0x10;
767 *reg += bank->bank_num * RK1108_DRV_BANK_STRIDE;
768 }
769
770 *reg += ((pin_num / RK1108_DRV_PINS_PER_REG) * 4);
771 *bit = pin_num % RK1108_DRV_PINS_PER_REG;
772 *bit *= RK1108_DRV_BITS_PER_PIN;
773}
774
a282926d
HS		 775#define RK2928_PULL_OFFSET 0x118
776#define RK2928_PULL_PINS_PER_REG 16
777#define RK2928_PULL_BANK_STRIDE 8
778
779static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 780 int pin_num, struct regmap **regmap,
781 int *reg, u8 *bit)
a282926d
HS		 782{
783 struct rockchip_pinctrl *info = bank->drvdata;
784
751a99ab
HS		 785 *regmap = info->regmap_base;
786 *reg = RK2928_PULL_OFFSET;
a282926d
HS		 787 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
788 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
789
790 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
791};
792
bfc7a42a 793#define RK3188_PULL_OFFSET 0x164
6ca5274d
HS		 794#define RK3188_PULL_BITS_PER_PIN 2
795#define RK3188_PULL_PINS_PER_REG 8
796#define RK3188_PULL_BANK_STRIDE 16
14dee867 797#define RK3188_PULL_PMU_OFFSET 0x64
6ca5274d
HS		 798
799static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 800 int pin_num, struct regmap **regmap,
801 int *reg, u8 *bit)
6ca5274d
HS		 802{
803 struct rockchip_pinctrl *info = bank->drvdata;
804
805 /* The first 12 pins of the first bank are located elsewhere */
fc72c923 806 if (bank->bank_num == 0 && pin_num < 12) {
14dee867
HS		 807 *regmap = info->regmap_pmu ? info->regmap_pmu
808 : bank->regmap_pull;
809 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
751a99ab 810 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
6ca5274d
HS		 811 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
812 *bit *= RK3188_PULL_BITS_PER_PIN;
813 } else {
751a99ab
HS		 814 *regmap = info->regmap_pull ? info->regmap_pull
815 : info->regmap_base;
816 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
817
bfc7a42a
HS		 818 /* correct the offset, as it is the 2nd pull register */
819 *reg -= 4;
6ca5274d
HS		 820 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
821 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
822
823 /*
824 * The bits in these registers have an inverse ordering
825 * with the lowest pin being in bits 15:14 and the highest
826 * pin in bits 1:0
827 */
828 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
829 *bit *= RK3188_PULL_BITS_PER_PIN;
830 }
831}
832
304f077d
HS		 833#define RK3288_PULL_OFFSET 0x140
834static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
835 int pin_num, struct regmap **regmap,
836 int *reg, u8 *bit)
837{
838 struct rockchip_pinctrl *info = bank->drvdata;
839
840 /* The first 24 pins of the first bank are located in PMU */
841 if (bank->bank_num == 0) {
842 *regmap = info->regmap_pmu;
843 *reg = RK3188_PULL_PMU_OFFSET;
844
845 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
846 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
847 *bit *= RK3188_PULL_BITS_PER_PIN;
848 } else {
849 *regmap = info->regmap_base;
850 *reg = RK3288_PULL_OFFSET;
851
852 /* correct the offset, as we're starting with the 2nd bank */
853 *reg -= 0x10;
854 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
855 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
856
857 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
858 *bit *= RK3188_PULL_BITS_PER_PIN;
859 }
860}
861
b547c800
HS		 862#define RK3288_DRV_PMU_OFFSET 0x70
863#define RK3288_DRV_GRF_OFFSET 0x1c0
864#define RK3288_DRV_BITS_PER_PIN 2
865#define RK3288_DRV_PINS_PER_REG 8
866#define RK3288_DRV_BANK_STRIDE 16
b547c800
HS		 867
868static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
869 int pin_num, struct regmap **regmap,
870 int *reg, u8 *bit)
871{
872 struct rockchip_pinctrl *info = bank->drvdata;
873
874 /* The first 24 pins of the first bank are located in PMU */
875 if (bank->bank_num == 0) {
876 *regmap = info->regmap_pmu;
877 *reg = RK3288_DRV_PMU_OFFSET;
878
879 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
880 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
881 *bit *= RK3288_DRV_BITS_PER_PIN;
882 } else {
883 *regmap = info->regmap_base;
884 *reg = RK3288_DRV_GRF_OFFSET;
885
886 /* correct the offset, as we're starting with the 2nd bank */
887 *reg -= 0x10;
888 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
889 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
890
891 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
892 *bit *= RK3288_DRV_BITS_PER_PIN;
893 }
894}
895
fea0fe60
JC		 896#define RK3228_PULL_OFFSET 0x100
897
898static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
899 int pin_num, struct regmap **regmap,
900 int *reg, u8 *bit)
901{
902 struct rockchip_pinctrl *info = bank->drvdata;
903
904 *regmap = info->regmap_base;
905 *reg = RK3228_PULL_OFFSET;
906 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
907 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
908
909 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
910 *bit *= RK3188_PULL_BITS_PER_PIN;
911}
912
913#define RK3228_DRV_GRF_OFFSET 0x200
914
915static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
916 int pin_num, struct regmap **regmap,
917 int *reg, u8 *bit)
918{
919 struct rockchip_pinctrl *info = bank->drvdata;
920
921 *regmap = info->regmap_base;
922 *reg = RK3228_DRV_GRF_OFFSET;
923 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
924 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
925
926 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
927 *bit *= RK3288_DRV_BITS_PER_PIN;
928}
929
daecdc66
HS		 930#define RK3368_PULL_GRF_OFFSET 0x100
931#define RK3368_PULL_PMU_OFFSET 0x10
932
933static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
934 int pin_num, struct regmap **regmap,
935 int *reg, u8 *bit)
936{
937 struct rockchip_pinctrl *info = bank->drvdata;
938
939 /* The first 32 pins of the first bank are located in PMU */
940 if (bank->bank_num == 0) {
941 *regmap = info->regmap_pmu;
942 *reg = RK3368_PULL_PMU_OFFSET;
943
944 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
945 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
946 *bit *= RK3188_PULL_BITS_PER_PIN;
947 } else {
948 *regmap = info->regmap_base;
949 *reg = RK3368_PULL_GRF_OFFSET;
950
951 /* correct the offset, as we're starting with the 2nd bank */
952 *reg -= 0x10;
953 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
954 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
955
956 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
957 *bit *= RK3188_PULL_BITS_PER_PIN;
958 }
959}
960
961#define RK3368_DRV_PMU_OFFSET 0x20
962#define RK3368_DRV_GRF_OFFSET 0x200
963
964static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
965 int pin_num, struct regmap **regmap,
966 int *reg, u8 *bit)
967{
968 struct rockchip_pinctrl *info = bank->drvdata;
969
970 /* The first 32 pins of the first bank are located in PMU */
971 if (bank->bank_num == 0) {
972 *regmap = info->regmap_pmu;
973 *reg = RK3368_DRV_PMU_OFFSET;
974
975 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
976 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
977 *bit *= RK3288_DRV_BITS_PER_PIN;
978 } else {
979 *regmap = info->regmap_base;
980 *reg = RK3368_DRV_GRF_OFFSET;
981
982 /* correct the offset, as we're starting with the 2nd bank */
983 *reg -= 0x10;
984 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
985 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
986
987 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
988 *bit *= RK3288_DRV_BITS_PER_PIN;
989 }
990}
991
b6c23275
DW		 992#define RK3399_PULL_GRF_OFFSET 0xe040
993#define RK3399_PULL_PMU_OFFSET 0x40
994#define RK3399_DRV_3BITS_PER_PIN 3
995
996static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
997 int pin_num, struct regmap **regmap,
998 int *reg, u8 *bit)
999{
1000 struct rockchip_pinctrl *info = bank->drvdata;
1001
1002 /* The bank0:16 and bank1:32 pins are located in PMU */
1003 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1004 *regmap = info->regmap_pmu;
1005 *reg = RK3399_PULL_PMU_OFFSET;
1006
1007 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1008
1009 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1010 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1011 *bit *= RK3188_PULL_BITS_PER_PIN;
1012 } else {
1013 *regmap = info->regmap_base;
1014 *reg = RK3399_PULL_GRF_OFFSET;
1015
1016 /* correct the offset, as we're starting with the 3rd bank */
1017 *reg -= 0x20;
1018 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1019 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1020
1021 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1022 *bit *= RK3188_PULL_BITS_PER_PIN;
1023 }
1024}
1025
1026static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1027 int pin_num, struct regmap **regmap,
1028 int *reg, u8 *bit)
1029{
1030 struct rockchip_pinctrl *info = bank->drvdata;
1031 int drv_num = (pin_num / 8);
1032
1033 /* The bank0:16 and bank1:32 pins are located in PMU */
1034 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1035 *regmap = info->regmap_pmu;
1036 else
1037 *regmap = info->regmap_base;
1038
1039 *reg = bank->drv[drv_num].offset;
1040 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1041 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1042 *bit = (pin_num % 8) * 3;
1043 else
1044 *bit = (pin_num % 8) * 2;
1045}
1046
1047static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1048 { 2, 4, 8, 12, -1, -1, -1, -1 },
1049 { 3, 6, 9, 12, -1, -1, -1, -1 },
1050 { 5, 10, 15, 20, -1, -1, -1, -1 },
1051 { 4, 6, 8, 10, 12, 14, 16, 18 },
1052 { 4, 7, 10, 13, 16, 19, 22, 26 }
1053};
ef17f69f
HS		 1054
1055static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1056 int pin_num)
b547c800 1057{
ef17f69f
HS		 1058 struct rockchip_pinctrl *info = bank->drvdata;
1059 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 1060 struct regmap *regmap;
1061 int reg, ret;
b6c23275 1062 u32 data, temp, rmask_bits;
b547c800 1063 u8 bit;
b6c23275 1064 int drv_type = bank->drv[pin_num / 8].drv_type;
b547c800 1065
ef17f69f 1066 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800 1067
b6c23275
DW		 1068 switch (drv_type) {
1069 case DRV_TYPE_IO_1V8_3V0_AUTO:
1070 case DRV_TYPE_IO_3V3_ONLY:
1071 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1072 switch (bit) {
1073 case 0 ... 12:
1074 /* regular case, nothing to do */
1075 break;
1076 case 15:
1077 /*
1078 * drive-strength offset is special, as it is
1079 * spread over 2 registers
1080 */
1081 ret = regmap_read(regmap, reg, &data);
1082 if (ret)
1083 return ret;
1084
1085 ret = regmap_read(regmap, reg + 0x4, &temp);
1086 if (ret)
1087 return ret;
1088
1089 /*
1090 * the bit data[15] contains bit 0 of the value
1091 * while temp[1:0] contains bits 2 and 1
1092 */
1093 data >>= 15;
1094 temp &= 0x3;
1095 temp <<= 1;
1096 data |= temp;
1097
1098 return rockchip_perpin_drv_list[drv_type][data];
1099 case 18 ... 21:
1100 /* setting fully enclosed in the second register */
1101 reg += 4;
1102 bit -= 16;
1103 break;
1104 default:
1105 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1106 bit, drv_type);
1107 return -EINVAL;
1108 }
1109
1110 break;
1111 case DRV_TYPE_IO_DEFAULT:
1112 case DRV_TYPE_IO_1V8_OR_3V0:
1113 case DRV_TYPE_IO_1V8_ONLY:
1114 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1115 break;
1116 default:
1117 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1118 drv_type);
1119 return -EINVAL;
1120 }
1121
b547c800
HS		 1122 ret = regmap_read(regmap, reg, &data);
1123 if (ret)
1124 return ret;
1125
1126 data >>= bit;
b6c23275 1127 data &= (1 << rmask_bits) - 1;
b547c800 1128
b6c23275 1129 return rockchip_perpin_drv_list[drv_type][data];
b547c800
HS		 1130}
1131
ef17f69f
HS		 1132static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1133 int pin_num, int strength)
b547c800
HS		 1134{
1135 struct rockchip_pinctrl *info = bank->drvdata;
ef17f69f 1136 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 1137 struct regmap *regmap;
1138 unsigned long flags;
1139 int reg, ret, i;
b6c23275 1140 u32 data, rmask, rmask_bits, temp;
b547c800 1141 u8 bit;
b6c23275
DW		 1142 int drv_type = bank->drv[pin_num / 8].drv_type;
1143
1144 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1145 bank->bank_num, pin_num, strength);
b547c800 1146
ef17f69f 1147 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800
HS		 1148
1149 ret = -EINVAL;
b6c23275
DW		 1150 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1151 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
b547c800
HS		 1152 ret = i;
1153 break;
b6c23275
DW		 1154 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1155 ret = rockchip_perpin_drv_list[drv_type][i];
1156 break;
b547c800
HS		 1157 }
1158 }
1159
1160 if (ret < 0) {
1161 dev_err(info->dev, "unsupported driver strength %d\n",
1162 strength);
1163 return ret;
1164 }
1165
1166 spin_lock_irqsave(&bank->slock, flags);
1167
b6c23275
DW		 1168 switch (drv_type) {
1169 case DRV_TYPE_IO_1V8_3V0_AUTO:
1170 case DRV_TYPE_IO_3V3_ONLY:
1171 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1172 switch (bit) {
1173 case 0 ... 12:
1174 /* regular case, nothing to do */
1175 break;
1176 case 15:
1177 /*
1178 * drive-strength offset is special, as it is spread
1179 * over 2 registers, the bit data[15] contains bit 0
1180 * of the value while temp[1:0] contains bits 2 and 1
1181 */
1182 data = (ret & 0x1) << 15;
1183 temp = (ret >> 0x1) & 0x3;
1184
1185 rmask = BIT(15) | BIT(31);
1186 data |= BIT(31);
1187 ret = regmap_update_bits(regmap, reg, rmask, data);
1188 if (ret) {
1189 spin_unlock_irqrestore(&bank->slock, flags);
1190 return ret;
1191 }
1192
1193 rmask = 0x3 | (0x3 << 16);
1194 temp |= (0x3 << 16);
1195 reg += 0x4;
1196 ret = regmap_update_bits(regmap, reg, rmask, temp);
1197
1198 spin_unlock_irqrestore(&bank->slock, flags);
1199 return ret;
1200 case 18 ... 21:
1201 /* setting fully enclosed in the second register */
1202 reg += 4;
1203 bit -= 16;
1204 break;
1205 default:
1206 spin_unlock_irqrestore(&bank->slock, flags);
1207 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1208 bit, drv_type);
1209 return -EINVAL;
1210 }
1211 break;
1212 case DRV_TYPE_IO_DEFAULT:
1213 case DRV_TYPE_IO_1V8_OR_3V0:
1214 case DRV_TYPE_IO_1V8_ONLY:
1215 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1216 break;
1217 default:
1218 spin_unlock_irqrestore(&bank->slock, flags);
1219 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1220 drv_type);
1221 return -EINVAL;
1222 }
1223
b547c800 1224 /* enable the write to the equivalent lower bits */
b6c23275 1225 data = ((1 << rmask_bits) - 1) << (bit + 16);
99e872d9 1226 rmask = data | (data >> 16);
b547c800
HS		 1227 data |= (ret << bit);
1228
99e872d9 1229 ret = regmap_update_bits(regmap, reg, rmask, data);
b547c800
HS		 1230 spin_unlock_irqrestore(&bank->slock, flags);
1231
1232 return ret;
1233}
1234
3ba6767a
DW		 1235static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1236 {
1237 PIN_CONFIG_BIAS_DISABLE,
1238 PIN_CONFIG_BIAS_PULL_UP,
1239 PIN_CONFIG_BIAS_PULL_DOWN,
1240 PIN_CONFIG_BIAS_BUS_HOLD
1241 },
1242 {
1243 PIN_CONFIG_BIAS_DISABLE,
1244 PIN_CONFIG_BIAS_PULL_DOWN,
1245 PIN_CONFIG_BIAS_DISABLE,
1246 PIN_CONFIG_BIAS_PULL_UP
1247 },
1248};
1249
d3e51161
HS		 1250static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1251{
1252 struct rockchip_pinctrl *info = bank->drvdata;
1253 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 1254 struct regmap *regmap;
3ba6767a 1255 int reg, ret, pull_type;
d3e51161 1256 u8 bit;
6ca5274d 1257 u32 data;
d3e51161
HS		 1258
1259 /* rk3066b does support any pulls */
a282926d 1260 if (ctrl->type == RK3066B)
d3e51161
HS		 1261 return PIN_CONFIG_BIAS_DISABLE;
1262
751a99ab
HS		 1263 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1264
1265 ret = regmap_read(regmap, reg, &data);
1266 if (ret)
1267 return ret;
6ca5274d 1268
a282926d
HS		 1269 switch (ctrl->type) {
1270 case RK2928:
751a99ab 1271 return !(data & BIT(bit))
d3e51161
HS		 1272 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1273 : PIN_CONFIG_BIAS_DISABLE;
688daf23 1274 case RK1108:
a282926d 1275 case RK3188:
66d750e1 1276 case RK3288:
daecdc66 1277 case RK3368:
b6c23275 1278 case RK3399:
3ba6767a 1279 pull_type = bank->pull_type[pin_num / 8];
751a99ab 1280 data >>= bit;
6ca5274d
HS		 1281 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1282
3ba6767a 1283 return rockchip_pull_list[pull_type][data];
a282926d
HS		 1284 default:
1285 dev_err(info->dev, "unsupported pinctrl type\n");
1286 return -EINVAL;
1287 };
d3e51161
HS		 1288}
1289
1290static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1291 int pin_num, int pull)
1292{
1293 struct rockchip_pinctrl *info = bank->drvdata;
1294 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 1295 struct regmap *regmap;
3ba6767a 1296 int reg, ret, i, pull_type;
d3e51161
HS		 1297 unsigned long flags;
1298 u8 bit;
99e872d9 1299 u32 data, rmask;
d3e51161
HS		 1300
1301 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1302 bank->bank_num, pin_num, pull);
1303
1304 /* rk3066b does support any pulls */
a282926d 1305 if (ctrl->type == RK3066B)
d3e51161
HS		 1306 return pull ? -EINVAL : 0;
1307
751a99ab 1308 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
6ca5274d 1309
a282926d
HS		 1310 switch (ctrl->type) {
1311 case RK2928:
d3e51161
HS		 1312 spin_lock_irqsave(&bank->slock, flags);
1313
1314 data = BIT(bit + 16);
1315 if (pull == PIN_CONFIG_BIAS_DISABLE)
1316 data |= BIT(bit);
751a99ab 1317 ret = regmap_write(regmap, reg, data);
d3e51161
HS		 1318
1319 spin_unlock_irqrestore(&bank->slock, flags);
a282926d 1320 break;
688daf23 1321 case RK1108:
a282926d 1322 case RK3188:
66d750e1 1323 case RK3288:
daecdc66 1324 case RK3368:
b6c23275 1325 case RK3399:
3ba6767a
DW		 1326 pull_type = bank->pull_type[pin_num / 8];
1327 ret = -EINVAL;
1328 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1329 i++) {
1330 if (rockchip_pull_list[pull_type][i] == pull) {
1331 ret = i;
1332 break;
1333 }
1334 }
1335
1336 if (ret < 0) {
1337 dev_err(info->dev, "unsupported pull setting %d\n",
1338 pull);
1339 return ret;
1340 }
1341
6ca5274d
HS		 1342 spin_lock_irqsave(&bank->slock, flags);
1343
1344 /* enable the write to the equivalent lower bits */
1345 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
99e872d9 1346 rmask = data | (data >> 16);
3ba6767a 1347 data |= (ret << bit);
6ca5274d 1348
99e872d9 1349 ret = regmap_update_bits(regmap, reg, rmask, data);
6ca5274d
HS		 1350
1351 spin_unlock_irqrestore(&bank->slock, flags);
1352 break;
a282926d
HS		 1353 default:
1354 dev_err(info->dev, "unsupported pinctrl type\n");
1355 return -EINVAL;
d3e51161
HS		 1356 }
1357
751a99ab 1358 return ret;
d3e51161
HS		 1359}
1360
e3b357d7 1361static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1362{
1363 struct rockchip_pinctrl *info = bank->drvdata;
1364 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1365 struct regmap *regmap;
1366 int reg, ret;
1367 u8 bit;
1368 u32 data;
1369
1370 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1371 if (ret)
1372 return ret;
1373
1374 ret = regmap_read(regmap, reg, &data);
1375 if (ret)
1376 return ret;
1377
1378 data >>= bit;
1379 return data & 0x1;
1380}
1381
1382static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1383 int pin_num, int enable)
1384{
1385 struct rockchip_pinctrl *info = bank->drvdata;
1386 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1387 struct regmap *regmap;
1388 int reg, ret;
1389 unsigned long flags;
1390 u8 bit;
1391 u32 data, rmask;
1392
1393 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1394 bank->bank_num, pin_num, enable);
1395
1396 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1397 if (ret)
1398 return ret;
1399
1400 spin_lock_irqsave(&bank->slock, flags);
1401
1402 /* enable the write to the equivalent lower bits */
1403 data = BIT(bit + 16) | (enable << bit);
1404 rmask = BIT(bit + 16) | BIT(bit);
1405
1406 ret = regmap_update_bits(regmap, reg, rmask, data);
1407 spin_unlock_irqrestore(&bank->slock, flags);
1408
1409 return ret;
1410}
1411
d3e51161
HS		 1412/*
1413 * Pinmux_ops handling
1414 */
1415
1416static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1417{
1418 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1419
1420 return info->nfunctions;
1421}
1422
1423static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1424 unsigned selector)
1425{
1426 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1427
1428 return info->functions[selector].name;
1429}
1430
1431static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1432 unsigned selector, const char * const **groups,
1433 unsigned * const num_groups)
1434{
1435 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1436
1437 *groups = info->functions[selector].groups;
1438 *num_groups = info->functions[selector].ngroups;
1439
1440 return 0;
1441}
1442
03e9f0ca
LW		 1443static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1444 unsigned group)
d3e51161
HS		 1445{
1446 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1447 const unsigned int *pins = info->groups[group].pins;
1448 const struct rockchip_pin_config *data = info->groups[group].data;
1449 struct rockchip_pin_bank *bank;
14797189 1450 int cnt, ret = 0;
d3e51161
HS		 1451
1452 dev_dbg(info->dev, "enable function %s group %s\n",
1453 info->functions[selector].name, info->groups[group].name);
1454
1455 /*
1456 * for each pin in the pin group selected, program the correspoding pin
1457 * pin function number in the config register.
1458 */
1459 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1460 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 1461 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1462 data[cnt].func);
1463 if (ret)
1464 break;
1465 }
1466
1467 if (ret) {
1468 /* revert the already done pin settings */
1469 for (cnt--; cnt >= 0; cnt--)
1470 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1471
1472 return ret;
d3e51161
HS		 1473 }
1474
1475 return 0;
1476}
1477
6ba20a00
CW		 1478static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1479{
1480 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1481 u32 data;
1482
1483 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1484
1485 return !(data & BIT(offset));
1486}
1487
d3e51161
HS		 1488/*
1489 * The calls to gpio_direction_output() and gpio_direction_input()
1490 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1491 * function called from the gpiolib interface).
1492 */
e5c2c9db
DA		 1493static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1494 int pin, bool input)
d3e51161 1495{
d3e51161 1496 struct rockchip_pin_bank *bank;
e5c2c9db 1497 int ret;
fab262f5 1498 unsigned long flags;
d3e51161
HS		 1499 u32 data;
1500
03bf81f1 1501 bank = gpiochip_get_data(chip);
d3e51161 1502
14797189
HS		 1503 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1504 if (ret < 0)
1505 return ret;
d3e51161 1506
07a06ae9 1507 clk_enable(bank->clk);
fab262f5
DA		 1508 spin_lock_irqsave(&bank->slock, flags);
1509
d3e51161
HS		 1510 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1511 /* set bit to 1 for output, 0 for input */
1512 if (!input)
1513 data |= BIT(pin);
1514 else
1515 data &= ~BIT(pin);
1516 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1517
fab262f5 1518 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1519 clk_disable(bank->clk);
fab262f5 1520
d3e51161
HS		 1521 return 0;
1522}
1523
e5c2c9db
DA		 1524static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1525 struct pinctrl_gpio_range *range,
1526 unsigned offset, bool input)
1527{
1528 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1529 struct gpio_chip *chip;
1530 int pin;
1531
1532 chip = range->gc;
1533 pin = offset - chip->base;
1534 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1535 offset, range->name, pin, input ? "input" : "output");
1536
1537 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1538 input);
1539}
1540
d3e51161
HS		 1541static const struct pinmux_ops rockchip_pmx_ops = {
1542 .get_functions_count = rockchip_pmx_get_funcs_count,
1543 .get_function_name = rockchip_pmx_get_func_name,
1544 .get_function_groups = rockchip_pmx_get_groups,
03e9f0ca 1545 .set_mux = rockchip_pmx_set,
d3e51161
HS		 1546 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1547};
1548
1549/*
1550 * Pinconf_ops handling
1551 */
1552
44b6d930
HS		 1553static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1554 enum pin_config_param pull)
1555{
a282926d
HS		 1556 switch (ctrl->type) {
1557 case RK2928:
1558 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1559 pull == PIN_CONFIG_BIAS_DISABLE);
1560 case RK3066B:
44b6d930 1561 return pull ? false : true;
688daf23 1562 case RK1108:
a282926d 1563 case RK3188:
66d750e1 1564 case RK3288:
daecdc66 1565 case RK3368:
b6c23275 1566 case RK3399:
a282926d 1567 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 1568 }
1569
a282926d 1570 return false;
44b6d930
HS		 1571}
1572
e5c2c9db 1573static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
a076e2ed
HS		 1574static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1575
d3e51161
HS		 1576/* set the pin config settings for a specified pin */
1577static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 1578 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 1579{
1580 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1581 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9 1582 enum pin_config_param param;
58957d2e 1583 u32 arg;
03b054e9
SY		 1584 int i;
1585 int rc;
1586
1587 for (i = 0; i < num_configs; i++) {
1588 param = pinconf_to_config_param(configs[i]);
1589 arg = pinconf_to_config_argument(configs[i]);
1590
1591 switch (param) {
1592 case PIN_CONFIG_BIAS_DISABLE:
1593 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1594 param);
1595 if (rc)
1596 return rc;
1597 break;
1598 case PIN_CONFIG_BIAS_PULL_UP:
1599 case PIN_CONFIG_BIAS_PULL_DOWN:
1600 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 1601 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 1602 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1603 return -ENOTSUPP;
1604
1605 if (!arg)
1606 return -EINVAL;
1607
1608 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1609 param);
1610 if (rc)
1611 return rc;
1612 break;
a076e2ed 1613 case PIN_CONFIG_OUTPUT:
e5c2c9db
DA		 1614 rockchip_gpio_set(&bank->gpio_chip,
1615 pin - bank->pin_base, arg);
1616 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1617 pin - bank->pin_base, false);
a076e2ed
HS		 1618 if (rc)
1619 return rc;
1620 break;
b547c800
HS		 1621 case PIN_CONFIG_DRIVE_STRENGTH:
1622 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 1623 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 1624 return -ENOTSUPP;
1625
ef17f69f
HS		 1626 rc = rockchip_set_drive_perpin(bank,
1627 pin - bank->pin_base, arg);
b547c800
HS		 1628 if (rc < 0)
1629 return rc;
1630 break;
e3b357d7 1631 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1632 if (!info->ctrl->schmitt_calc_reg)
1633 return -ENOTSUPP;
1634
1635 rc = rockchip_set_schmitt(bank,
1636 pin - bank->pin_base, arg);
1637 if (rc < 0)
1638 return rc;
1639 break;
03b054e9 1640 default:
44b6d930 1641 return -ENOTSUPP;
03b054e9
SY		 1642 break;
1643 }
1644 } /* for each config */
d3e51161
HS		 1645
1646 return 0;
1647}
1648
1649/* get the pin config settings for a specified pin */
1650static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1651 unsigned long *config)
1652{
1653 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1654 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1655 enum pin_config_param param = pinconf_to_config_param(*config);
dab3eba7 1656 u16 arg;
a076e2ed 1657 int rc;
d3e51161
HS		 1658
1659 switch (param) {
1660 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 1661 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1662 return -EINVAL;
1663
dab3eba7 1664 arg = 0;
44b6d930 1665 break;
d3e51161
HS		 1666 case PIN_CONFIG_BIAS_PULL_UP:
1667 case PIN_CONFIG_BIAS_PULL_DOWN:
1668 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 1669 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 1670 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1671 return -ENOTSUPP;
d3e51161 1672
44b6d930 1673 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 1674 return -EINVAL;
1675
dab3eba7 1676 arg = 1;
d3e51161 1677 break;
a076e2ed
HS		 1678 case PIN_CONFIG_OUTPUT:
1679 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1680 if (rc != RK_FUNC_GPIO)
1681 return -EINVAL;
1682
1683 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1684 if (rc < 0)
1685 return rc;
1686
1687 arg = rc ? 1 : 0;
1688 break;
b547c800
HS		 1689 case PIN_CONFIG_DRIVE_STRENGTH:
1690 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 1691 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 1692 return -ENOTSUPP;
1693
ef17f69f 1694 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
b547c800
HS		 1695 if (rc < 0)
1696 return rc;
1697
e3b357d7 1698 arg = rc;
1699 break;
1700 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1701 if (!info->ctrl->schmitt_calc_reg)
1702 return -ENOTSUPP;
1703
1704 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
1705 if (rc < 0)
1706 return rc;
1707
b547c800
HS		 1708 arg = rc;
1709 break;
d3e51161
HS		 1710 default:
1711 return -ENOTSUPP;
1712 break;
1713 }
1714
dab3eba7
HS		 1715 *config = pinconf_to_config_packed(param, arg);
1716
d3e51161
HS		 1717 return 0;
1718}
1719
1720static const struct pinconf_ops rockchip_pinconf_ops = {
1721 .pin_config_get = rockchip_pinconf_get,
1722 .pin_config_set = rockchip_pinconf_set,
ed62f2f2 1723 .is_generic = true,
d3e51161
HS		 1724};
1725
65fca613
HS		 1726static const struct of_device_id rockchip_bank_match[] = {
1727 { .compatible = "rockchip,gpio-bank" },
6ca5274d 1728 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 1729 {},
1730};
d3e51161
HS		 1731
1732static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1733 struct device_node *np)
1734{
1735 struct device_node *child;
1736
1737 for_each_child_of_node(np, child) {
65fca613 1738 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 1739 continue;
1740
1741 info->nfunctions++;
1742 info->ngroups += of_get_child_count(child);
1743 }
1744}
1745
1746static int rockchip_pinctrl_parse_groups(struct device_node *np,
1747 struct rockchip_pin_group *grp,
1748 struct rockchip_pinctrl *info,
1749 u32 index)
1750{
1751 struct rockchip_pin_bank *bank;
1752 int size;
1753 const __be32 *list;
1754 int num;
1755 int i, j;
1756 int ret;
1757
1758 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1759
1760 /* Initialise group */
1761 grp->name = np->name;
1762
1763 /*
1764 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1765 * do sanity check and calculate pins number
1766 */
1767 list = of_get_property(np, "rockchip,pins", &size);
1768 /* we do not check return since it's safe node passed down */
1769 size /= sizeof(*list);
1770 if (!size || size % 4) {
1771 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1772 return -EINVAL;
1773 }
1774
1775 grp->npins = size / 4;
1776
1777 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1778 GFP_KERNEL);
1779 grp->data = devm_kzalloc(info->dev, grp->npins *
1780 sizeof(struct rockchip_pin_config),
1781 GFP_KERNEL);
1782 if (!grp->pins || !grp->data)
1783 return -ENOMEM;
1784
1785 for (i = 0, j = 0; i < size; i += 4, j++) {
1786 const __be32 *phandle;
1787 struct device_node *np_config;
1788
1789 num = be32_to_cpu(*list++);
1790 bank = bank_num_to_bank(info, num);
1791 if (IS_ERR(bank))
1792 return PTR_ERR(bank);
1793
1794 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1795 grp->data[j].func = be32_to_cpu(*list++);
1796
1797 phandle = list++;
1798 if (!phandle)
1799 return -EINVAL;
1800
1801 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
dd4d01f7 1802 ret = pinconf_generic_parse_dt_config(np_config, NULL,
d3e51161
HS		 1803 &grp->data[j].configs, &grp->data[j].nconfigs);
1804 if (ret)
1805 return ret;
1806 }
1807
1808 return 0;
1809}
1810
1811static int rockchip_pinctrl_parse_functions(struct device_node *np,
1812 struct rockchip_pinctrl *info,
1813 u32 index)
1814{
1815 struct device_node *child;
1816 struct rockchip_pmx_func *func;
1817 struct rockchip_pin_group *grp;
1818 int ret;
1819 static u32 grp_index;
1820 u32 i = 0;
1821
1822 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1823
1824 func = &info->functions[index];
1825
1826 /* Initialise function */
1827 func->name = np->name;
1828 func->ngroups = of_get_child_count(np);
1829 if (func->ngroups <= 0)
1830 return 0;
1831
1832 func->groups = devm_kzalloc(info->dev,
1833 func->ngroups * sizeof(char *), GFP_KERNEL);
1834 if (!func->groups)
1835 return -ENOMEM;
1836
1837 for_each_child_of_node(np, child) {
1838 func->groups[i] = child->name;
1839 grp = &info->groups[grp_index++];
1840 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
f7a81b7f
JL		 1841 if (ret) {
1842 of_node_put(child);
d3e51161 1843 return ret;
f7a81b7f 1844 }
d3e51161
HS		 1845 }
1846
1847 return 0;
1848}
1849
1850static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1851 struct rockchip_pinctrl *info)
1852{
1853 struct device *dev = &pdev->dev;
1854 struct device_node *np = dev->of_node;
1855 struct device_node *child;
1856 int ret;
1857 int i;
1858
1859 rockchip_pinctrl_child_count(info, np);
1860
1861 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1862 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1863
1864 info->functions = devm_kzalloc(dev, info->nfunctions *
1865 sizeof(struct rockchip_pmx_func),
1866 GFP_KERNEL);
1867 if (!info->functions) {
1868 dev_err(dev, "failed to allocate memory for function list\n");
1869 return -EINVAL;
1870 }
1871
1872 info->groups = devm_kzalloc(dev, info->ngroups *
1873 sizeof(struct rockchip_pin_group),
1874 GFP_KERNEL);
1875 if (!info->groups) {
1876 dev_err(dev, "failed allocate memory for ping group list\n");
1877 return -EINVAL;
1878 }
1879
1880 i = 0;
1881
1882 for_each_child_of_node(np, child) {
65fca613 1883 if (of_match_node(rockchip_bank_match, child))
d3e51161 1884 continue;
65fca613 1885
d3e51161
HS		 1886 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1887 if (ret) {
1888 dev_err(&pdev->dev, "failed to parse function\n");
f7a81b7f 1889 of_node_put(child);
d3e51161
HS		 1890 return ret;
1891 }
1892 }
1893
1894 return 0;
1895}
1896
1897static int rockchip_pinctrl_register(struct platform_device *pdev,
1898 struct rockchip_pinctrl *info)
1899{
1900 struct pinctrl_desc *ctrldesc = &info->pctl;
1901 struct pinctrl_pin_desc *pindesc, *pdesc;
1902 struct rockchip_pin_bank *pin_bank;
1903 int pin, bank, ret;
1904 int k;
1905
1906 ctrldesc->name = "rockchip-pinctrl";
1907 ctrldesc->owner = THIS_MODULE;
1908 ctrldesc->pctlops = &rockchip_pctrl_ops;
1909 ctrldesc->pmxops = &rockchip_pmx_ops;
1910 ctrldesc->confops = &rockchip_pinconf_ops;
1911
1912 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1913 info->ctrl->nr_pins, GFP_KERNEL);
1914 if (!pindesc) {
1915 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1916 return -ENOMEM;
1917 }
1918 ctrldesc->pins = pindesc;
1919 ctrldesc->npins = info->ctrl->nr_pins;
1920
1921 pdesc = pindesc;
1922 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1923 pin_bank = &info->ctrl->pin_banks[bank];
1924 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1925 pdesc->number = k;
1926 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1927 pin_bank->name, pin);
1928 pdesc++;
1929 }
1930 }
1931
0fb7dcb1
DA		 1932 ret = rockchip_pinctrl_parse_dt(pdev, info);
1933 if (ret)
1934 return ret;
1935
0085a2b4 1936 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
323de9ef 1937 if (IS_ERR(info->pctl_dev)) {
d3e51161 1938 dev_err(&pdev->dev, "could not register pinctrl driver\n");
323de9ef 1939 return PTR_ERR(info->pctl_dev);
d3e51161
HS		 1940 }
1941
1942 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1943 pin_bank = &info->ctrl->pin_banks[bank];
1944 pin_bank->grange.name = pin_bank->name;
1945 pin_bank->grange.id = bank;
1946 pin_bank->grange.pin_base = pin_bank->pin_base;
1947 pin_bank->grange.base = pin_bank->gpio_chip.base;
1948 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1949 pin_bank->grange.gc = &pin_bank->gpio_chip;
1950 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1951 }
1952
d3e51161
HS		 1953 return 0;
1954}
1955
1956/*
1957 * GPIO handling
1958 */
1959
1960static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1961{
03bf81f1 1962 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 1963 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1964 unsigned long flags;
1965 u32 data;
1966
07a06ae9 1967 clk_enable(bank->clk);
d3e51161
HS		 1968 spin_lock_irqsave(&bank->slock, flags);
1969
1970 data = readl(reg);
1971 data &= ~BIT(offset);
1972 if (value)
1973 data |= BIT(offset);
1974 writel(data, reg);
1975
1976 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1977 clk_disable(bank->clk);
d3e51161
HS		 1978}
1979
1980/*
1981 * Returns the level of the pin for input direction and setting of the DR
1982 * register for output gpios.
1983 */
1984static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1985{
03bf81f1 1986 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 1987 u32 data;
1988
07a06ae9 1989 clk_enable(bank->clk);
d3e51161 1990 data = readl(bank->reg_base + GPIO_EXT_PORT);
07a06ae9 1991 clk_disable(bank->clk);
d3e51161
HS		 1992 data >>= offset;
1993 data &= 1;
1994 return data;
1995}
1996
1997/*
1998 * gpiolib gpio_direction_input callback function. The setting of the pin
1999 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2000 * interface.
2001 */
2002static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2003{
2004 return pinctrl_gpio_direction_input(gc->base + offset);
2005}
2006
2007/*
2008 * gpiolib gpio_direction_output callback function. The setting of the pin
2009 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2010 * interface.
2011 */
2012static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2013 unsigned offset, int value)
2014{
2015 rockchip_gpio_set(gc, offset, value);
2016 return pinctrl_gpio_direction_output(gc->base + offset);
2017}
2018
2019/*
2020 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2021 * and a virtual IRQ, if not already present.
2022 */
2023static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2024{
03bf81f1 2025 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2026 unsigned int virq;
2027
2028 if (!bank->domain)
2029 return -ENXIO;
2030
2031 virq = irq_create_mapping(bank->domain, offset);
2032
2033 return (virq) ? : -ENXIO;
2034}
2035
2036static const struct gpio_chip rockchip_gpiolib_chip = {
98c85d58
JG		 2037 .request = gpiochip_generic_request,
2038 .free = gpiochip_generic_free,
d3e51161
HS		 2039 .set = rockchip_gpio_set,
2040 .get = rockchip_gpio_get,
6ba20a00 2041 .get_direction = rockchip_gpio_get_direction,
d3e51161
HS		 2042 .direction_input = rockchip_gpio_direction_input,
2043 .direction_output = rockchip_gpio_direction_output,
2044 .to_irq = rockchip_gpio_to_irq,
2045 .owner = THIS_MODULE,
2046};
2047
2048/*
2049 * Interrupt handling
2050 */
2051
bd0b9ac4 2052static void rockchip_irq_demux(struct irq_desc *desc)
d3e51161 2053{
5663bb27
JL		 2054 struct irq_chip *chip = irq_desc_get_chip(desc);
2055 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
d3e51161
HS		 2056 u32 pend;
2057
2058 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2059
2060 chained_irq_enter(chip, desc);
2061
2062 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2063
2064 while (pend) {
415f748c 2065 unsigned int irq, virq;
d3e51161
HS		 2066
2067 irq = __ffs(pend);
2068 pend &= ~BIT(irq);
2069 virq = irq_linear_revmap(bank->domain, irq);
2070
2071 if (!virq) {
2072 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2073 continue;
2074 }
2075
2076 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2077
5a927501
HS		 2078 /*
2079 * Triggering IRQ on both rising and falling edge
2080 * needs manual intervention.
2081 */
2082 if (bank->toggle_edge_mode & BIT(irq)) {
53b1bfc7
DA		 2083 u32 data, data_old, polarity;
2084 unsigned long flags;
2085
2086 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2087 do {
2088 spin_lock_irqsave(&bank->slock, flags);
2089
2090 polarity = readl_relaxed(bank->reg_base +
2091 GPIO_INT_POLARITY);
2092 if (data & BIT(irq))
2093 polarity &= ~BIT(irq);
2094 else
2095 polarity |= BIT(irq);
2096 writel(polarity,
2097 bank->reg_base + GPIO_INT_POLARITY);
2098
2099 spin_unlock_irqrestore(&bank->slock, flags);
2100
2101 data_old = data;
2102 data = readl_relaxed(bank->reg_base +
2103 GPIO_EXT_PORT);
2104 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
5a927501
HS		 2105 }
2106
d3e51161
HS		 2107 generic_handle_irq(virq);
2108 }
2109
2110 chained_irq_exit(chip, desc);
2111}
2112
2113static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2114{
2115 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2116 struct rockchip_pin_bank *bank = gc->private;
2117 u32 mask = BIT(d->hwirq);
2118 u32 polarity;
2119 u32 level;
2120 u32 data;
fab262f5 2121 unsigned long flags;
14797189 2122 int ret;
d3e51161 2123
5a927501 2124 /* make sure the pin is configured as gpio input */
14797189
HS		 2125 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2126 if (ret < 0)
2127 return ret;
2128
07a06ae9 2129 clk_enable(bank->clk);
fab262f5
DA		 2130 spin_lock_irqsave(&bank->slock, flags);
2131
5a927501
HS		 2132 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2133 data &= ~mask;
2134 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2135
fab262f5
DA		 2136 spin_unlock_irqrestore(&bank->slock, flags);
2137
d3e51161 2138 if (type & IRQ_TYPE_EDGE_BOTH)
2dbf1bc5 2139 irq_set_handler_locked(d, handle_edge_irq);
d3e51161 2140 else
2dbf1bc5 2141 irq_set_handler_locked(d, handle_level_irq);
d3e51161 2142
fab262f5 2143 spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 2144 irq_gc_lock(gc);
2145
2146 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2147 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2148
2149 switch (type) {
5a927501
HS		 2150 case IRQ_TYPE_EDGE_BOTH:
2151 bank->toggle_edge_mode |= mask;
2152 level |= mask;
2153
2154 /*
2155 * Determine gpio state. If 1 next interrupt should be falling
2156 * otherwise rising.
2157 */
2158 data = readl(bank->reg_base + GPIO_EXT_PORT);
2159 if (data & mask)
2160 polarity &= ~mask;
2161 else
2162 polarity |= mask;
2163 break;
d3e51161 2164 case IRQ_TYPE_EDGE_RISING:
5a927501 2165 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2166 level |= mask;
2167 polarity |= mask;
2168 break;
2169 case IRQ_TYPE_EDGE_FALLING:
5a927501 2170 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2171 level |= mask;
2172 polarity &= ~mask;
2173 break;
2174 case IRQ_TYPE_LEVEL_HIGH:
5a927501 2175 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2176 level &= ~mask;
2177 polarity |= mask;
2178 break;
2179 case IRQ_TYPE_LEVEL_LOW:
5a927501 2180 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2181 level &= ~mask;
2182 polarity &= ~mask;
2183 break;
2184 default:
7cc5f970 2185 irq_gc_unlock(gc);
fab262f5 2186 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 2187 clk_disable(bank->clk);
d3e51161
HS		 2188 return -EINVAL;
2189 }
2190
2191 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2192 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2193
2194 irq_gc_unlock(gc);
fab262f5 2195 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 2196 clk_disable(bank->clk);
d3e51161 2197
d3e51161
HS		 2198 return 0;
2199}
2200
68bda47c
DA		 2201static void rockchip_irq_suspend(struct irq_data *d)
2202{
2203 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2204 struct rockchip_pin_bank *bank = gc->private;
2205
07a06ae9 2206 clk_enable(bank->clk);
5ae0c7ad
DA		 2207 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2208 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
07a06ae9 2209 clk_disable(bank->clk);
68bda47c
DA		 2210}
2211
2212static void rockchip_irq_resume(struct irq_data *d)
2213{
2214 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2215 struct rockchip_pin_bank *bank = gc->private;
2216
07a06ae9 2217 clk_enable(bank->clk);
5ae0c7ad 2218 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
07a06ae9
LH		 2219 clk_disable(bank->clk);
2220}
2221
2222static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
2223{
2224 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2225 struct rockchip_pin_bank *bank = gc->private;
2226
2227 clk_enable(bank->clk);
2228 irq_gc_mask_clr_bit(d);
2229}
2230
a688e351 2231static void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
07a06ae9
LH		 2232{
2233 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2234 struct rockchip_pin_bank *bank = gc->private;
2235
2236 irq_gc_mask_set_bit(d);
2237 clk_disable(bank->clk);
f2dd028c
DA		 2238}
2239
d3e51161
HS		 2240static int rockchip_interrupts_register(struct platform_device *pdev,
2241 struct rockchip_pinctrl *info)
2242{
2243 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2244 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2245 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2246 struct irq_chip_generic *gc;
2247 int ret;
07a06ae9 2248 int i, j;
d3e51161
HS		 2249
2250 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2251 if (!bank->valid) {
2252 dev_warn(&pdev->dev, "bank %s is not valid\n",
2253 bank->name);
2254 continue;
2255 }
2256
07a06ae9
LH		 2257 ret = clk_enable(bank->clk);
2258 if (ret) {
2259 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2260 bank->name);
2261 continue;
2262 }
2263
d3e51161
HS		 2264 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2265 &irq_generic_chip_ops, NULL);
2266 if (!bank->domain) {
2267 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2268 bank->name);
07a06ae9 2269 clk_disable(bank->clk);
d3e51161
HS		 2270 continue;
2271 }
2272
2273 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2274 "rockchip_gpio_irq", handle_level_irq,
2275 clr, 0, IRQ_GC_INIT_MASK_CACHE);
2276 if (ret) {
2277 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2278 bank->name);
2279 irq_domain_remove(bank->domain);
07a06ae9 2280 clk_disable(bank->clk);
d3e51161
HS		 2281 continue;
2282 }
2283
5ae0c7ad
DA		 2284 /*
2285 * Linux assumes that all interrupts start out disabled/masked.
2286 * Our driver only uses the concept of masked and always keeps
2287 * things enabled, so for us that's all masked and all enabled.
2288 */
2289 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2290 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2291
d3e51161
HS		 2292 gc = irq_get_domain_generic_chip(bank->domain, 0);
2293 gc->reg_base = bank->reg_base;
2294 gc->private = bank;
f2dd028c 2295 gc->chip_types[0].regs.mask = GPIO_INTMASK;
d3e51161
HS		 2296 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2297 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
07a06ae9
LH		 2298 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2299 gc->chip_types[0].chip.irq_unmask =
2300 rockchip_irq_gc_mask_clr_bit;
d3e51161 2301 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
68bda47c
DA		 2302 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2303 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
d3e51161 2304 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
876d716b 2305 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
d3e51161 2306
03051bc2
TG		 2307 irq_set_chained_handler_and_data(bank->irq,
2308 rockchip_irq_demux, bank);
07a06ae9
LH		 2309
2310 /* map the gpio irqs here, when the clock is still running */
2311 for (j = 0 ; j < 32 ; j++)
2312 irq_create_mapping(bank->domain, j);
2313
2314 clk_disable(bank->clk);
d3e51161
HS		 2315 }
2316
2317 return 0;
2318}
2319
2320static int rockchip_gpiolib_register(struct platform_device *pdev,
2321 struct rockchip_pinctrl *info)
2322{
2323 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2324 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2325 struct gpio_chip *gc;
2326 int ret;
2327 int i;
2328
2329 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2330 if (!bank->valid) {
2331 dev_warn(&pdev->dev, "bank %s is not valid\n",
2332 bank->name);
2333 continue;
2334 }
2335
2336 bank->gpio_chip = rockchip_gpiolib_chip;
2337
2338 gc = &bank->gpio_chip;
2339 gc->base = bank->pin_base;
2340 gc->ngpio = bank->nr_pins;
58383c78 2341 gc->parent = &pdev->dev;
d3e51161
HS		 2342 gc->of_node = bank->of_node;
2343 gc->label = bank->name;
2344
03bf81f1 2345 ret = gpiochip_add_data(gc, bank);
d3e51161
HS		 2346 if (ret) {
2347 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2348 gc->label, ret);
2349 goto fail;
2350 }
2351 }
2352
2353 rockchip_interrupts_register(pdev, info);
2354
2355 return 0;
2356
2357fail:
2358 for (--i, --bank; i >= 0; --i, --bank) {
2359 if (!bank->valid)
2360 continue;
b4e7c55d 2361 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 2362 }
2363 return ret;
2364}
2365
2366static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2367 struct rockchip_pinctrl *info)
2368{
2369 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2370 struct rockchip_pin_bank *bank = ctrl->pin_banks;
d3e51161
HS		 2371 int i;
2372
b4e7c55d 2373 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
d3e51161
HS		 2374 if (!bank->valid)
2375 continue;
b4e7c55d 2376 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 2377 }
2378
b4e7c55d 2379 return 0;
d3e51161
HS		 2380}
2381
2382static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
622f3237 2383 struct rockchip_pinctrl *info)
d3e51161
HS		 2384{
2385 struct resource res;
751a99ab 2386 void __iomem *base;
d3e51161
HS		 2387
2388 if (of_address_to_resource(bank->of_node, 0, &res)) {
622f3237 2389 dev_err(info->dev, "cannot find IO resource for bank\n");
d3e51161
HS		 2390 return -ENOENT;
2391 }
2392
622f3237 2393 bank->reg_base = devm_ioremap_resource(info->dev, &res);
d3e51161
HS		 2394 if (IS_ERR(bank->reg_base))
2395 return PTR_ERR(bank->reg_base);
2396
6ca5274d
HS		 2397 /*
2398 * special case, where parts of the pull setting-registers are
2399 * part of the PMU register space
2400 */
2401 if (of_device_is_compatible(bank->of_node,
2402 "rockchip,rk3188-gpio-bank0")) {
a658efaa 2403 struct device_node *node;
bfc7a42a 2404
a658efaa
HS		 2405 node = of_parse_phandle(bank->of_node->parent,
2406 "rockchip,pmu", 0);
2407 if (!node) {
2408 if (of_address_to_resource(bank->of_node, 1, &res)) {
2409 dev_err(info->dev, "cannot find IO resource for bank\n");
2410 return -ENOENT;
2411 }
2412
2413 base = devm_ioremap_resource(info->dev, &res);
2414 if (IS_ERR(base))
2415 return PTR_ERR(base);
2416 rockchip_regmap_config.max_register =
2417 resource_size(&res) - 4;
2418 rockchip_regmap_config.name =
2419 "rockchip,rk3188-gpio-bank0-pull";
2420 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2421 base,
2422 &rockchip_regmap_config);
6ca5274d 2423 }
6ca5274d 2424 }
65fca613 2425
d3e51161
HS		 2426 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2427
2428 bank->clk = of_clk_get(bank->of_node, 0);
2429 if (IS_ERR(bank->clk))
2430 return PTR_ERR(bank->clk);
2431
07a06ae9 2432 return clk_prepare(bank->clk);
d3e51161
HS		 2433}
2434
2435static const struct of_device_id rockchip_pinctrl_dt_match[];
2436
2437/* retrieve the soc specific data */
2438static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2439 struct rockchip_pinctrl *d,
2440 struct platform_device *pdev)
2441{
2442 const struct of_device_id *match;
2443 struct device_node *node = pdev->dev.of_node;
2444 struct device_node *np;
2445 struct rockchip_pin_ctrl *ctrl;
2446 struct rockchip_pin_bank *bank;
b6c23275 2447 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
d3e51161
HS		 2448
2449 match = of_match_node(rockchip_pinctrl_dt_match, node);
2450 ctrl = (struct rockchip_pin_ctrl *)match->data;
2451
2452 for_each_child_of_node(node, np) {
2453 if (!of_find_property(np, "gpio-controller", NULL))
2454 continue;
2455
2456 bank = ctrl->pin_banks;
2457 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2458 if (!strcmp(bank->name, np->name)) {
2459 bank->of_node = np;
2460
622f3237 2461 if (!rockchip_get_bank_data(bank, d))
d3e51161
HS		 2462 bank->valid = true;
2463
2464 break;
2465 }
2466 }
2467 }
2468
95ec8ae4
HS		 2469 grf_offs = ctrl->grf_mux_offset;
2470 pmu_offs = ctrl->pmu_mux_offset;
b6c23275
DW		 2471 drv_pmu_offs = ctrl->pmu_drv_offset;
2472 drv_grf_offs = ctrl->grf_drv_offset;
d3e51161
HS		 2473 bank = ctrl->pin_banks;
2474 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
6bc0d121
HS		 2475 int bank_pins = 0;
2476
d3e51161
HS		 2477 spin_lock_init(&bank->slock);
2478 bank->drvdata = d;
2479 bank->pin_base = ctrl->nr_pins;
2480 ctrl->nr_pins += bank->nr_pins;
6bc0d121 2481
b6c23275 2482 /* calculate iomux and drv offsets */
6bc0d121
HS		 2483 for (j = 0; j < 4; j++) {
2484 struct rockchip_iomux *iom = &bank->iomux[j];
b6c23275 2485 struct rockchip_drv *drv = &bank->drv[j];
03716e1d 2486 int inc;
6bc0d121
HS		 2487
2488 if (bank_pins >= bank->nr_pins)
2489 break;
2490
b6c23275 2491 /* preset iomux offset value, set new start value */
6bc0d121 2492 if (iom->offset >= 0) {
95ec8ae4
HS		 2493 if (iom->type & IOMUX_SOURCE_PMU)
2494 pmu_offs = iom->offset;
2495 else
2496 grf_offs = iom->offset;
b6c23275 2497 } else { /* set current iomux offset */
95ec8ae4
HS		 2498 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2499 pmu_offs : grf_offs;
6bc0d121
HS		 2500 }
2501
b6c23275
DW		 2502 /* preset drv offset value, set new start value */
2503 if (drv->offset >= 0) {
2504 if (iom->type & IOMUX_SOURCE_PMU)
2505 drv_pmu_offs = drv->offset;
2506 else
2507 drv_grf_offs = drv->offset;
2508 } else { /* set current drv offset */
2509 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2510 drv_pmu_offs : drv_grf_offs;
2511 }
2512
2513 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2514 i, j, iom->offset, drv->offset);
6bc0d121
HS		 2515
2516 /*
2517 * Increase offset according to iomux width.
03716e1d 2518 * 4bit iomux'es are spread over two registers.
6bc0d121 2519 */
8b6c6f93 2520 inc = (iom->type & (IOMUX_WIDTH_4BIT |
2521 IOMUX_WIDTH_3BIT)) ? 8 : 4;
95ec8ae4
HS		 2522 if (iom->type & IOMUX_SOURCE_PMU)
2523 pmu_offs += inc;
2524 else
2525 grf_offs += inc;
6bc0d121 2526
b6c23275
DW		 2527 /*
2528 * Increase offset according to drv width.
2529 * 3bit drive-strenth'es are spread over two registers.
2530 */
2531 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2532 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2533 inc = 8;
2534 else
2535 inc = 4;
2536
2537 if (iom->type & IOMUX_SOURCE_PMU)
2538 drv_pmu_offs += inc;
2539 else
2540 drv_grf_offs += inc;
2541
6bc0d121
HS		 2542 bank_pins += 8;
2543 }
d3e51161
HS		 2544 }
2545
2546 return ctrl;
2547}
2548
8dca9331
CZ		 2549#define RK3288_GRF_GPIO6C_IOMUX 0x64
2550#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2551
2552static u32 rk3288_grf_gpio6c_iomux;
2553
9198f509
CZ		 2554static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2555{
2556 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 2557 int ret = pinctrl_force_sleep(info->pctl_dev);
2558
2559 if (ret)
2560 return ret;
2561
2562 /*
2563 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2564 * the setting here, and restore it at resume.
2565 */
2566 if (info->ctrl->type == RK3288) {
2567 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2568 &rk3288_grf_gpio6c_iomux);
2569 if (ret) {
2570 pinctrl_force_default(info->pctl_dev);
2571 return ret;
2572 }
2573 }
9198f509 2574
8dca9331 2575 return 0;
9198f509
CZ		 2576}
2577
2578static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2579{
2580 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 2581 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2582 rk3288_grf_gpio6c_iomux |
2583 GPIO6C6_SEL_WRITE_ENABLE);
2584
2585 if (ret)
2586 return ret;
9198f509
CZ		 2587
2588 return pinctrl_force_default(info->pctl_dev);
2589}
2590
2591static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2592 rockchip_pinctrl_resume);
2593
d3e51161
HS		 2594static int rockchip_pinctrl_probe(struct platform_device *pdev)
2595{
2596 struct rockchip_pinctrl *info;
2597 struct device *dev = &pdev->dev;
2598 struct rockchip_pin_ctrl *ctrl;
14dee867 2599 struct device_node *np = pdev->dev.of_node, *node;
d3e51161 2600 struct resource *res;
751a99ab 2601 void __iomem *base;
d3e51161
HS		 2602 int ret;
2603
2604 if (!dev->of_node) {
2605 dev_err(dev, "device tree node not found\n");
2606 return -ENODEV;
2607 }
2608
2609 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2610 if (!info)
2611 return -ENOMEM;
2612
622f3237
HS		 2613 info->dev = dev;
2614
d3e51161
HS		 2615 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2616 if (!ctrl) {
2617 dev_err(dev, "driver data not available\n");
2618 return -EINVAL;
2619 }
2620 info->ctrl = ctrl;
d3e51161 2621
1e747e59
HS		 2622 node = of_parse_phandle(np, "rockchip,grf", 0);
2623 if (node) {
2624 info->regmap_base = syscon_node_to_regmap(node);
2625 if (IS_ERR(info->regmap_base))
2626 return PTR_ERR(info->regmap_base);
2627 } else {
2628 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751a99ab
HS		 2629 base = devm_ioremap_resource(&pdev->dev, res);
2630 if (IS_ERR(base))
2631 return PTR_ERR(base);
2632
2633 rockchip_regmap_config.max_register = resource_size(res) - 4;
1e747e59
HS		 2634 rockchip_regmap_config.name = "rockchip,pinctrl";
2635 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2636 &rockchip_regmap_config);
2637
2638 /* to check for the old dt-bindings */
2639 info->reg_size = resource_size(res);
2640
2641 /* Honor the old binding, with pull registers as 2nd resource */
2642 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2643 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2644 base = devm_ioremap_resource(&pdev->dev, res);
2645 if (IS_ERR(base))
2646 return PTR_ERR(base);
2647
2648 rockchip_regmap_config.max_register =
2649 resource_size(res) - 4;
2650 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2651 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2652 base,
2653 &rockchip_regmap_config);
2654 }
6ca5274d
HS		 2655 }
2656
14dee867
HS		 2657 /* try to find the optional reference to the pmu syscon */
2658 node = of_parse_phandle(np, "rockchip,pmu", 0);
2659 if (node) {
2660 info->regmap_pmu = syscon_node_to_regmap(node);
2661 if (IS_ERR(info->regmap_pmu))
2662 return PTR_ERR(info->regmap_pmu);
2663 }
2664
d3e51161
HS		 2665 ret = rockchip_gpiolib_register(pdev, info);
2666 if (ret)
2667 return ret;
2668
2669 ret = rockchip_pinctrl_register(pdev, info);
2670 if (ret) {
2671 rockchip_gpiolib_unregister(pdev, info);
2672 return ret;
2673 }
2674
2675 platform_set_drvdata(pdev, info);
2676
2677 return 0;
2678}
2679
688daf23
AY		 2680static struct rockchip_pin_bank rk1108_pin_banks[] = {
2681 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2682 IOMUX_SOURCE_PMU,
2683 IOMUX_SOURCE_PMU,
2684 IOMUX_SOURCE_PMU),
2685 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2686 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2687 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2688};
2689
2690static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
2691 .pin_banks = rk1108_pin_banks,
2692 .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
2693 .label = "RK1108-GPIO",
2694 .type = RK1108,
2695 .grf_mux_offset = 0x10,
2696 .pmu_mux_offset = 0x0,
2697 .pull_calc_reg = rk1108_calc_pull_reg_and_bit,
2698 .drv_calc_reg = rk1108_calc_drv_reg_and_bit,
2699};
2700
d3e51161
HS		 2701static struct rockchip_pin_bank rk2928_pin_banks[] = {
2702 PIN_BANK(0, 32, "gpio0"),
2703 PIN_BANK(1, 32, "gpio1"),
2704 PIN_BANK(2, 32, "gpio2"),
2705 PIN_BANK(3, 32, "gpio3"),
2706};
2707
2708static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2709 .pin_banks = rk2928_pin_banks,
2710 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2711 .label = "RK2928-GPIO",
a282926d 2712 .type = RK2928,
95ec8ae4 2713 .grf_mux_offset = 0xa8,
a282926d 2714 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 2715};
2716
c5ce7670
XZ		 2717static struct rockchip_pin_bank rk3036_pin_banks[] = {
2718 PIN_BANK(0, 32, "gpio0"),
2719 PIN_BANK(1, 32, "gpio1"),
2720 PIN_BANK(2, 32, "gpio2"),
2721};
2722
2723static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2724 .pin_banks = rk3036_pin_banks,
2725 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2726 .label = "RK3036-GPIO",
2727 .type = RK2928,
2728 .grf_mux_offset = 0xa8,
2729 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2730};
2731
d3e51161
HS		 2732static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2733 PIN_BANK(0, 32, "gpio0"),
2734 PIN_BANK(1, 32, "gpio1"),
2735 PIN_BANK(2, 32, "gpio2"),
2736 PIN_BANK(3, 32, "gpio3"),
2737 PIN_BANK(4, 32, "gpio4"),
2738 PIN_BANK(6, 16, "gpio6"),
2739};
2740
2741static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2742 .pin_banks = rk3066a_pin_banks,
2743 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2744 .label = "RK3066a-GPIO",
a282926d 2745 .type = RK2928,
95ec8ae4 2746 .grf_mux_offset = 0xa8,
a282926d 2747 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 2748};
2749
2750static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2751 PIN_BANK(0, 32, "gpio0"),
2752 PIN_BANK(1, 32, "gpio1"),
2753 PIN_BANK(2, 32, "gpio2"),
2754 PIN_BANK(3, 32, "gpio3"),
2755};
2756
2757static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2758 .pin_banks = rk3066b_pin_banks,
2759 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2760 .label = "RK3066b-GPIO",
a282926d 2761 .type = RK3066B,
95ec8ae4 2762 .grf_mux_offset = 0x60,
d3e51161
HS		 2763};
2764
2765static struct rockchip_pin_bank rk3188_pin_banks[] = {
fc72c923 2766 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
d3e51161
HS		 2767 PIN_BANK(1, 32, "gpio1"),
2768 PIN_BANK(2, 32, "gpio2"),
2769 PIN_BANK(3, 32, "gpio3"),
2770};
2771
2772static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2773 .pin_banks = rk3188_pin_banks,
2774 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2775 .label = "RK3188-GPIO",
a282926d 2776 .type = RK3188,
95ec8ae4 2777 .grf_mux_offset = 0x60,
6ca5274d 2778 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 2779};
2780
fea0fe60
JC		 2781static struct rockchip_pin_bank rk3228_pin_banks[] = {
2782 PIN_BANK(0, 32, "gpio0"),
2783 PIN_BANK(1, 32, "gpio1"),
2784 PIN_BANK(2, 32, "gpio2"),
2785 PIN_BANK(3, 32, "gpio3"),
2786};
2787
2788static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2789 .pin_banks = rk3228_pin_banks,
2790 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2791 .label = "RK3228-GPIO",
2792 .type = RK3288,
2793 .grf_mux_offset = 0x0,
2794 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2795 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2796};
2797
304f077d
HS		 2798static struct rockchip_pin_bank rk3288_pin_banks[] = {
2799 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2800 IOMUX_SOURCE_PMU,
2801 IOMUX_SOURCE_PMU,
2802 IOMUX_UNROUTED
2803 ),
2804 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2805 IOMUX_UNROUTED,
2806 IOMUX_UNROUTED,
2807 0
2808 ),
2809 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2810 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2811 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2812 IOMUX_WIDTH_4BIT,
2813 0,
2814 0
2815 ),
2816 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2817 0,
2818 0,
2819 IOMUX_UNROUTED
2820 ),
2821 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2822 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2823 0,
2824 IOMUX_WIDTH_4BIT,
2825 IOMUX_UNROUTED
2826 ),
2827 PIN_BANK(8, 16, "gpio8"),
2828};
2829
2830static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2831 .pin_banks = rk3288_pin_banks,
2832 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2833 .label = "RK3288-GPIO",
66d750e1 2834 .type = RK3288,
304f077d
HS		 2835 .grf_mux_offset = 0x0,
2836 .pmu_mux_offset = 0x84,
2837 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
ef17f69f 2838 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
304f077d
HS		 2839};
2840
3818e4a7 2841static struct rockchip_pin_bank rk3328_pin_banks[] = {
2842 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
2843 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2844 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
2845 IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
2846 IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
2847 0),
2848 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
2849 IOMUX_WIDTH_3BIT,
2850 IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
2851 0,
2852 0),
2853};
2854
2855static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
2856 .pin_banks = rk3328_pin_banks,
2857 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
2858 .label = "RK3328-GPIO",
2859 .type = RK3288,
2860 .grf_mux_offset = 0x0,
2861 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2862 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2863 .iomux_recalc = rk3328_recalc_mux,
2864};
2865
daecdc66
HS		 2866static struct rockchip_pin_bank rk3368_pin_banks[] = {
2867 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2868 IOMUX_SOURCE_PMU,
2869 IOMUX_SOURCE_PMU,
2870 IOMUX_SOURCE_PMU
2871 ),
2872 PIN_BANK(1, 32, "gpio1"),
2873 PIN_BANK(2, 32, "gpio2"),
2874 PIN_BANK(3, 32, "gpio3"),
2875};
2876
2877static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2878 .pin_banks = rk3368_pin_banks,
2879 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2880 .label = "RK3368-GPIO",
2881 .type = RK3368,
2882 .grf_mux_offset = 0x0,
2883 .pmu_mux_offset = 0x0,
2884 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
2885 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
2886};
2887
b6c23275 2888static struct rockchip_pin_bank rk3399_pin_banks[] = {
3ba6767a
DW		 2889 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
2890 IOMUX_SOURCE_PMU,
2891 IOMUX_SOURCE_PMU,
2892 IOMUX_SOURCE_PMU,
2893 IOMUX_SOURCE_PMU,
2894 DRV_TYPE_IO_1V8_ONLY,
2895 DRV_TYPE_IO_1V8_ONLY,
2896 DRV_TYPE_IO_DEFAULT,
2897 DRV_TYPE_IO_DEFAULT,
2898 0x0,
2899 0x8,
2900 -1,
2901 -1,
2902 PULL_TYPE_IO_1V8_ONLY,
2903 PULL_TYPE_IO_1V8_ONLY,
2904 PULL_TYPE_IO_DEFAULT,
2905 PULL_TYPE_IO_DEFAULT
2906 ),
b6c23275
DW		 2907 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2908 IOMUX_SOURCE_PMU,
2909 IOMUX_SOURCE_PMU,
2910 IOMUX_SOURCE_PMU,
2911 DRV_TYPE_IO_1V8_OR_3V0,
2912 DRV_TYPE_IO_1V8_OR_3V0,
2913 DRV_TYPE_IO_1V8_OR_3V0,
2914 DRV_TYPE_IO_1V8_OR_3V0,
2915 0x20,
2916 0x28,
2917 0x30,
2918 0x38
2919 ),
3ba6767a
DW		 2920 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2921 DRV_TYPE_IO_1V8_OR_3V0,
2922 DRV_TYPE_IO_1V8_ONLY,
2923 DRV_TYPE_IO_1V8_ONLY,
2924 PULL_TYPE_IO_DEFAULT,
2925 PULL_TYPE_IO_DEFAULT,
2926 PULL_TYPE_IO_1V8_ONLY,
2927 PULL_TYPE_IO_1V8_ONLY
2928 ),
b6c23275
DW		 2929 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2930 DRV_TYPE_IO_3V3_ONLY,
2931 DRV_TYPE_IO_3V3_ONLY,
2932 DRV_TYPE_IO_1V8_OR_3V0
2933 ),
2934 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2935 DRV_TYPE_IO_1V8_3V0_AUTO,
2936 DRV_TYPE_IO_1V8_OR_3V0,
2937 DRV_TYPE_IO_1V8_OR_3V0
2938 ),
2939};
2940
2941static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2942 .pin_banks = rk3399_pin_banks,
2943 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
2944 .label = "RK3399-GPIO",
2945 .type = RK3399,
2946 .grf_mux_offset = 0xe000,
2947 .pmu_mux_offset = 0x0,
2948 .grf_drv_offset = 0xe100,
2949 .pmu_drv_offset = 0x80,
2950 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
2951 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
2952};
daecdc66 2953
d3e51161 2954static const struct of_device_id rockchip_pinctrl_dt_match[] = {
688daf23
AY		 2955 { .compatible = "rockchip,rk1108-pinctrl",
2956 .data = (void *)&rk1108_pin_ctrl },
d3e51161
HS		 2957 { .compatible = "rockchip,rk2928-pinctrl",
2958 .data = (void *)&rk2928_pin_ctrl },
c5ce7670
XZ		 2959 { .compatible = "rockchip,rk3036-pinctrl",
2960 .data = (void *)&rk3036_pin_ctrl },
d3e51161
HS		 2961 { .compatible = "rockchip,rk3066a-pinctrl",
2962 .data = (void *)&rk3066a_pin_ctrl },
2963 { .compatible = "rockchip,rk3066b-pinctrl",
2964 .data = (void *)&rk3066b_pin_ctrl },
2965 { .compatible = "rockchip,rk3188-pinctrl",
2966 .data = (void *)&rk3188_pin_ctrl },
fea0fe60
JC		 2967 { .compatible = "rockchip,rk3228-pinctrl",
2968 .data = (void *)&rk3228_pin_ctrl },
304f077d
HS		 2969 { .compatible = "rockchip,rk3288-pinctrl",
2970 .data = (void *)&rk3288_pin_ctrl },
3818e4a7 2971 { .compatible = "rockchip,rk3328-pinctrl",
2972 .data = (void *)&rk3328_pin_ctrl },
daecdc66
HS		 2973 { .compatible = "rockchip,rk3368-pinctrl",
2974 .data = (void *)&rk3368_pin_ctrl },
b6c23275
DW		 2975 { .compatible = "rockchip,rk3399-pinctrl",
2976 .data = (void *)&rk3399_pin_ctrl },
d3e51161
HS		 2977 {},
2978};
d3e51161
HS		 2979
2980static struct platform_driver rockchip_pinctrl_driver = {
2981 .probe = rockchip_pinctrl_probe,
2982 .driver = {
2983 .name = "rockchip-pinctrl",
9198f509 2984 .pm = &rockchip_pinctrl_dev_pm_ops,
0be9e70d 2985 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 2986 },
2987};
2988
2989static int __init rockchip_pinctrl_drv_register(void)
2990{
2991 return platform_driver_register(&rockchip_pinctrl_driver);
2992}
2993postcore_initcall(rockchip_pinctrl_drv_register);
Linux 6.x block layer and io_uring tree(s)