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pinctrl: qcom: ssbi-gpio: fix gpio-hog related boot issues
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
d3e51161
HS		 1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
2f436204 26#include <linux/init.h>
d3e51161
HS		 27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
1c5fb66a 30#include <linux/gpio/driver.h>
d3e51161
HS		 31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
7e865abb 39#include <linux/clk.h>
751a99ab 40#include <linux/regmap.h>
14dee867 41#include <linux/mfd/syscon.h>
d3e51161
HS		 42#include <dt-bindings/pinctrl/rockchip.h>
43
44#include "core.h"
45#include "pinconf.h"
46
47/* GPIO control registers */
48#define GPIO_SWPORT_DR 0x00
49#define GPIO_SWPORT_DDR 0x04
50#define GPIO_INTEN 0x30
51#define GPIO_INTMASK 0x34
52#define GPIO_INTTYPE_LEVEL 0x38
53#define GPIO_INT_POLARITY 0x3c
54#define GPIO_INT_STATUS 0x40
55#define GPIO_INT_RAWSTATUS 0x44
56#define GPIO_DEBOUNCE 0x48
57#define GPIO_PORTS_EOI 0x4c
58#define GPIO_EXT_PORT 0x50
59#define GPIO_LS_SYNC 0x60
60
a282926d 61enum rockchip_pinctrl_type {
87065ca9 62 PX30,
b9c6dcab 63 RV1108,
a282926d
HS		 64 RK2928,
65 RK3066B,
d23c66df 66 RK3128,
a282926d 67 RK3188,
66d750e1 68 RK3288,
daecdc66 69 RK3368,
b6c23275 70 RK3399,
a282926d
HS		 71};
72
fc72c923
HS		 73/**
74 * Encode variants of iomux registers into a type variable
75 */
76#define IOMUX_GPIO_ONLY BIT(0)
03716e1d 77#define IOMUX_WIDTH_4BIT BIT(1)
95ec8ae4 78#define IOMUX_SOURCE_PMU BIT(2)
62f49226 79#define IOMUX_UNROUTED BIT(3)
8b6c6f93 80#define IOMUX_WIDTH_3BIT BIT(4)
fc72c923
HS		 81
82/**
83 * @type: iomux variant using IOMUX_* constants
6bc0d121
HS		 84 * @offset: if initialized to -1 it will be autocalculated, by specifying
85 * an initial offset value the relevant source offset can be reset
86 * to a new value for autocalculating the following iomux registers.
fc72c923
HS		 87 */
88struct rockchip_iomux {
89 int type;
6bc0d121 90 int offset;
65fca613
HS		 91};
92
b6c23275
DW		 93/**
94 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
95 */
96enum rockchip_pin_drv_type {
97 DRV_TYPE_IO_DEFAULT = 0,
98 DRV_TYPE_IO_1V8_OR_3V0,
99 DRV_TYPE_IO_1V8_ONLY,
100 DRV_TYPE_IO_1V8_3V0_AUTO,
101 DRV_TYPE_IO_3V3_ONLY,
102 DRV_TYPE_MAX
103};
104
3ba6767a
DW		 105/**
106 * enum type index corresponding to rockchip_pull_list arrays index.
107 */
108enum rockchip_pin_pull_type {
109 PULL_TYPE_IO_DEFAULT = 0,
110 PULL_TYPE_IO_1V8_ONLY,
111 PULL_TYPE_MAX
112};
113
b6c23275
DW		 114/**
115 * @drv_type: drive strength variant using rockchip_perpin_drv_type
116 * @offset: if initialized to -1 it will be autocalculated, by specifying
117 * an initial offset value the relevant source offset can be reset
118 * to a new value for autocalculating the following drive strength
119 * registers. if used chips own cal_drv func instead to calculate
120 * registers offset, the variant could be ignored.
121 */
122struct rockchip_drv {
123 enum rockchip_pin_drv_type drv_type;
124 int offset;
125};
126
d3e51161
HS		 127/**
128 * @reg_base: register base of the gpio bank
6ca5274d 129 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 130 * @clk: clock of the gpio bank
131 * @irq: interrupt of the gpio bank
5ae0c7ad 132 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
d3e51161
HS		 133 * @pin_base: first pin number
134 * @nr_pins: number of pins in this bank
135 * @name: name of the bank
136 * @bank_num: number of the bank, to account for holes
fc72c923 137 * @iomux: array describing the 4 iomux sources of the bank
b6c23275 138 * @drv: array describing the 4 drive strength sources of the bank
3ba6767a 139 * @pull_type: array describing the 4 pull type sources of the bank
85dc397a 140 * @valid: is all necessary information present
d3e51161
HS		 141 * @of_node: dt node of this bank
142 * @drvdata: common pinctrl basedata
143 * @domain: irqdomain of the gpio bank
144 * @gpio_chip: gpiolib chip
145 * @grange: gpio range
146 * @slock: spinlock for the gpio bank
bd35b9bf 147 * @route_mask: bits describing the routing pins of per bank
d3e51161
HS		 148 */
149struct rockchip_pin_bank {
150 void __iomem *reg_base;
751a99ab 151 struct regmap *regmap_pull;
d3e51161
HS		 152 struct clk *clk;
153 int irq;
5ae0c7ad 154 u32 saved_masks;
d3e51161
HS		 155 u32 pin_base;
156 u8 nr_pins;
157 char *name;
158 u8 bank_num;
fc72c923 159 struct rockchip_iomux iomux[4];
b6c23275 160 struct rockchip_drv drv[4];
3ba6767a 161 enum rockchip_pin_pull_type pull_type[4];
d3e51161
HS		 162 bool valid;
163 struct device_node *of_node;
164 struct rockchip_pinctrl *drvdata;
165 struct irq_domain *domain;
166 struct gpio_chip gpio_chip;
167 struct pinctrl_gpio_range grange;
70b7aa7a 168 raw_spinlock_t slock;
5a927501 169 u32 toggle_edge_mode;
c04c3fa6 170 u32 recalced_mask;
bd35b9bf 171 u32 route_mask;
d3e51161
HS		 172};
173
174#define PIN_BANK(id, pins, label) \
175 { \
176 .bank_num = id, \
177 .nr_pins = pins, \
178 .name = label, \
6bc0d121
HS		 179 .iomux = { \
180 { .offset = -1 }, \
181 { .offset = -1 }, \
182 { .offset = -1 }, \
183 { .offset = -1 }, \
184 }, \
d3e51161
HS		 185 }
186
fc72c923
HS		 187#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
188 { \
189 .bank_num = id, \
190 .nr_pins = pins, \
191 .name = label, \
192 .iomux = { \
6bc0d121
HS		 193 { .type = iom0, .offset = -1 }, \
194 { .type = iom1, .offset = -1 }, \
195 { .type = iom2, .offset = -1 }, \
196 { .type = iom3, .offset = -1 }, \
fc72c923
HS		 197 }, \
198 }
199
b6c23275
DW		 200#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
201 { \
202 .bank_num = id, \
203 .nr_pins = pins, \
204 .name = label, \
205 .iomux = { \
206 { .offset = -1 }, \
207 { .offset = -1 }, \
208 { .offset = -1 }, \
209 { .offset = -1 }, \
210 }, \
211 .drv = { \
212 { .drv_type = type0, .offset = -1 }, \
213 { .drv_type = type1, .offset = -1 }, \
214 { .drv_type = type2, .offset = -1 }, \
215 { .drv_type = type3, .offset = -1 }, \
216 }, \
217 }
218
3ba6767a
DW		 219#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
220 drv2, drv3, pull0, pull1, \
221 pull2, pull3) \
222 { \
223 .bank_num = id, \
224 .nr_pins = pins, \
225 .name = label, \
226 .iomux = { \
227 { .offset = -1 }, \
228 { .offset = -1 }, \
229 { .offset = -1 }, \
230 { .offset = -1 }, \
231 }, \
232 .drv = { \
233 { .drv_type = drv0, .offset = -1 }, \
234 { .drv_type = drv1, .offset = -1 }, \
235 { .drv_type = drv2, .offset = -1 }, \
236 { .drv_type = drv3, .offset = -1 }, \
237 }, \
238 .pull_type[0] = pull0, \
239 .pull_type[1] = pull1, \
240 .pull_type[2] = pull2, \
241 .pull_type[3] = pull3, \
242 }
243
b6c23275
DW		 244#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
245 iom2, iom3, drv0, drv1, drv2, \
246 drv3, offset0, offset1, \
247 offset2, offset3) \
248 { \
249 .bank_num = id, \
250 .nr_pins = pins, \
251 .name = label, \
252 .iomux = { \
253 { .type = iom0, .offset = -1 }, \
254 { .type = iom1, .offset = -1 }, \
255 { .type = iom2, .offset = -1 }, \
256 { .type = iom3, .offset = -1 }, \
257 }, \
258 .drv = { \
259 { .drv_type = drv0, .offset = offset0 }, \
260 { .drv_type = drv1, .offset = offset1 }, \
261 { .drv_type = drv2, .offset = offset2 }, \
262 { .drv_type = drv3, .offset = offset3 }, \
263 }, \
264 }
265
3ba6767a
DW		 266#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
267 label, iom0, iom1, iom2, \
268 iom3, drv0, drv1, drv2, \
269 drv3, offset0, offset1, \
270 offset2, offset3, pull0, \
271 pull1, pull2, pull3) \
272 { \
273 .bank_num = id, \
274 .nr_pins = pins, \
275 .name = label, \
276 .iomux = { \
277 { .type = iom0, .offset = -1 }, \
278 { .type = iom1, .offset = -1 }, \
279 { .type = iom2, .offset = -1 }, \
280 { .type = iom3, .offset = -1 }, \
281 }, \
282 .drv = { \
283 { .drv_type = drv0, .offset = offset0 }, \
284 { .drv_type = drv1, .offset = offset1 }, \
285 { .drv_type = drv2, .offset = offset2 }, \
286 { .drv_type = drv3, .offset = offset3 }, \
287 }, \
288 .pull_type[0] = pull0, \
289 .pull_type[1] = pull1, \
290 .pull_type[2] = pull2, \
291 .pull_type[3] = pull3, \
292 }
293
c04c3fa6
DW		 294/**
295 * struct rockchip_mux_recalced_data: represent a pin iomux data.
296 * @num: bank number.
297 * @pin: pin number.
298 * @bit: index at register.
299 * @reg: register offset.
300 * @mask: mask bit
301 */
302struct rockchip_mux_recalced_data {
303 u8 num;
304 u8 pin;
12b8f018 305 u32 reg;
c04c3fa6
DW		 306 u8 bit;
307 u8 mask;
308};
309
bd35b9bf
DW		 310/**
311 * struct rockchip_mux_recalced_data: represent a pin iomux data.
312 * @bank_num: bank number.
313 * @pin: index at register or used to calc index.
314 * @func: the min pin.
315 * @route_offset: the max pin.
316 * @route_val: the register offset.
317 */
318struct rockchip_mux_route_data {
319 u8 bank_num;
320 u8 pin;
321 u8 func;
322 u32 route_offset;
323 u32 route_val;
324};
325
d3e51161 326/**
d3e51161
HS		 327 */
328struct rockchip_pin_ctrl {
329 struct rockchip_pin_bank *pin_banks;
330 u32 nr_banks;
331 u32 nr_pins;
332 char *label;
a282926d 333 enum rockchip_pinctrl_type type;
95ec8ae4
HS		 334 int grf_mux_offset;
335 int pmu_mux_offset;
b6c23275
DW		 336 int grf_drv_offset;
337 int pmu_drv_offset;
c04c3fa6
DW		 338 struct rockchip_mux_recalced_data *iomux_recalced;
339 u32 niomux_recalced;
bd35b9bf
DW		 340 struct rockchip_mux_route_data *iomux_routes;
341 u32 niomux_routes;
b6c23275 342
751a99ab
HS		 343 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
344 int pin_num, struct regmap **regmap,
345 int *reg, u8 *bit);
ef17f69f
HS		 346 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
347 int pin_num, struct regmap **regmap,
348 int *reg, u8 *bit);
e3b357d7 349 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
350 int pin_num, struct regmap **regmap,
351 int *reg, u8 *bit);
d3e51161
HS		 352};
353
354struct rockchip_pin_config {
355 unsigned int func;
356 unsigned long *configs;
357 unsigned int nconfigs;
358};
359
360/**
361 * struct rockchip_pin_group: represent group of pins of a pinmux function.
362 * @name: name of the pin group, used to lookup the group.
363 * @pins: the pins included in this group.
364 * @npins: number of pins included in this group.
365 * @func: the mux function number to be programmed when selected.
366 * @configs: the config values to be set for each pin
367 * @nconfigs: number of configs for each pin
368 */
369struct rockchip_pin_group {
370 const char *name;
371 unsigned int npins;
372 unsigned int *pins;
373 struct rockchip_pin_config *data;
374};
375
376/**
377 * struct rockchip_pmx_func: represent a pin function.
378 * @name: name of the pin function, used to lookup the function.
379 * @groups: one or more names of pin groups that provide this function.
380 * @num_groups: number of groups included in @groups.
381 */
382struct rockchip_pmx_func {
383 const char *name;
384 const char **groups;
385 u8 ngroups;
386};
387
388struct rockchip_pinctrl {
751a99ab 389 struct regmap *regmap_base;
bfc7a42a 390 int reg_size;
751a99ab 391 struct regmap *regmap_pull;
14dee867 392 struct regmap *regmap_pmu;
d3e51161
HS		 393 struct device *dev;
394 struct rockchip_pin_ctrl *ctrl;
395 struct pinctrl_desc pctl;
396 struct pinctrl_dev *pctl_dev;
397 struct rockchip_pin_group *groups;
398 unsigned int ngroups;
399 struct rockchip_pmx_func *functions;
400 unsigned int nfunctions;
401};
402
751a99ab
HS		 403static struct regmap_config rockchip_regmap_config = {
404 .reg_bits = 32,
405 .val_bits = 32,
406 .reg_stride = 4,
407};
408
56411f3c 409static inline const struct rockchip_pin_group *pinctrl_name_to_group(
d3e51161
HS		 410 const struct rockchip_pinctrl *info,
411 const char *name)
412{
d3e51161
HS		 413 int i;
414
415 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 416 if (!strcmp(info->groups[i].name, name))
417 return &info->groups[i];
d3e51161
HS		 418 }
419
1cb95395 420 return NULL;
d3e51161
HS		 421}
422
423/*
424 * given a pin number that is local to a pin controller, find out the pin bank
425 * and the register base of the pin bank.
426 */
427static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
428 unsigned pin)
429{
430 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
431
51578b9b 432 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 433 b++;
434
435 return b;
436}
437
438static struct rockchip_pin_bank *bank_num_to_bank(
439 struct rockchip_pinctrl *info,
440 unsigned num)
441{
442 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
443 int i;
444
1cb95395 445 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 446 if (b->bank_num == num)
1cb95395 447 return b;
d3e51161
HS		 448 }
449
1cb95395 450 return ERR_PTR(-EINVAL);
d3e51161
HS		 451}
452
453/*
454 * Pinctrl_ops handling
455 */
456
457static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
458{
459 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
460
461 return info->ngroups;
462}
463
464static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
465 unsigned selector)
466{
467 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
468
469 return info->groups[selector].name;
470}
471
472static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
473 unsigned selector, const unsigned **pins,
474 unsigned *npins)
475{
476 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
477
478 if (selector >= info->ngroups)
479 return -EINVAL;
480
481 *pins = info->groups[selector].pins;
482 *npins = info->groups[selector].npins;
483
484 return 0;
485}
486
487static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
488 struct device_node *np,
489 struct pinctrl_map **map, unsigned *num_maps)
490{
491 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
492 const struct rockchip_pin_group *grp;
493 struct pinctrl_map *new_map;
494 struct device_node *parent;
495 int map_num = 1;
496 int i;
497
498 /*
499 * first find the group of this node and check if we need to create
500 * config maps for pins
501 */
502 grp = pinctrl_name_to_group(info, np->name);
503 if (!grp) {
94f4e54c
RH		 504 dev_err(info->dev, "unable to find group for node %pOFn\n",
505 np);
d3e51161
HS		 506 return -EINVAL;
507 }
508
509 map_num += grp->npins;
a86854d0 510 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
d3e51161
HS		 511 GFP_KERNEL);
512 if (!new_map)
513 return -ENOMEM;
514
515 *map = new_map;
516 *num_maps = map_num;
517
518 /* create mux map */
519 parent = of_get_parent(np);
520 if (!parent) {
521 devm_kfree(pctldev->dev, new_map);
522 return -EINVAL;
523 }
524 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
525 new_map[0].data.mux.function = parent->name;
526 new_map[0].data.mux.group = np->name;
527 of_node_put(parent);
528
529 /* create config map */
530 new_map++;
531 for (i = 0; i < grp->npins; i++) {
532 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
533 new_map[i].data.configs.group_or_pin =
534 pin_get_name(pctldev, grp->pins[i]);
535 new_map[i].data.configs.configs = grp->data[i].configs;
536 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
537 }
538
539 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
540 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
541
542 return 0;
543}
544
545static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
546 struct pinctrl_map *map, unsigned num_maps)
547{
548}
549
550static const struct pinctrl_ops rockchip_pctrl_ops = {
551 .get_groups_count = rockchip_get_groups_count,
552 .get_group_name = rockchip_get_group_name,
553 .get_group_pins = rockchip_get_group_pins,
554 .dt_node_to_map = rockchip_dt_node_to_map,
555 .dt_free_map = rockchip_dt_free_map,
556};
557
558/*
559 * Hardware access
560 */
561
12b8f018
DW		 562static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
563 {
564 .num = 1,
565 .pin = 0,
566 .reg = 0x418,
567 .bit = 0,
568 .mask = 0x3
569 }, {
570 .num = 1,
571 .pin = 1,
572 .reg = 0x418,
573 .bit = 2,
574 .mask = 0x3
575 }, {
576 .num = 1,
577 .pin = 2,
578 .reg = 0x418,
579 .bit = 4,
580 .mask = 0x3
581 }, {
582 .num = 1,
583 .pin = 3,
584 .reg = 0x418,
585 .bit = 6,
586 .mask = 0x3
587 }, {
588 .num = 1,
589 .pin = 4,
590 .reg = 0x418,
591 .bit = 8,
592 .mask = 0x3
593 }, {
594 .num = 1,
595 .pin = 5,
596 .reg = 0x418,
597 .bit = 10,
598 .mask = 0x3
599 }, {
600 .num = 1,
601 .pin = 6,
602 .reg = 0x418,
603 .bit = 12,
604 .mask = 0x3
605 }, {
606 .num = 1,
607 .pin = 7,
608 .reg = 0x418,
609 .bit = 14,
610 .mask = 0x3
611 }, {
612 .num = 1,
613 .pin = 8,
614 .reg = 0x41c,
615 .bit = 0,
616 .mask = 0x3
617 }, {
618 .num = 1,
619 .pin = 9,
620 .reg = 0x41c,
621 .bit = 2,
622 .mask = 0x3
623 },
624};
625
d23c66df
DW		 626static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
627 {
628 .num = 2,
629 .pin = 20,
630 .reg = 0xe8,
631 .bit = 0,
632 .mask = 0x7
633 }, {
634 .num = 2,
635 .pin = 21,
636 .reg = 0xe8,
637 .bit = 4,
638 .mask = 0x7
639 }, {
640 .num = 2,
641 .pin = 22,
642 .reg = 0xe8,
643 .bit = 8,
644 .mask = 0x7
645 }, {
646 .num = 2,
647 .pin = 23,
648 .reg = 0xe8,
649 .bit = 12,
650 .mask = 0x7
651 }, {
652 .num = 2,
653 .pin = 24,
654 .reg = 0xd4,
655 .bit = 12,
656 .mask = 0x7
657 },
658};
659
c04c3fa6 660static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
3818e4a7 661 {
662 .num = 2,
663 .pin = 12,
664 .reg = 0x24,
665 .bit = 8,
666 .mask = 0x3
667 }, {
668 .num = 2,
669 .pin = 15,
670 .reg = 0x28,
671 .bit = 0,
672 .mask = 0x7
673 }, {
674 .num = 2,
675 .pin = 23,
676 .reg = 0x30,
677 .bit = 14,
678 .mask = 0x3
679 },
680};
681
c04c3fa6
DW		 682static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
683 int *reg, u8 *bit, int *mask)
3818e4a7 684{
c04c3fa6
DW		 685 struct rockchip_pinctrl *info = bank->drvdata;
686 struct rockchip_pin_ctrl *ctrl = info->ctrl;
687 struct rockchip_mux_recalced_data *data;
3818e4a7 688 int i;
689
c04c3fa6
DW		 690 for (i = 0; i < ctrl->niomux_recalced; i++) {
691 data = &ctrl->iomux_recalced[i];
692 if (data->num == bank->bank_num &&
693 data->pin == pin)
3818e4a7 694 break;
c04c3fa6 695 }
3818e4a7 696
c04c3fa6 697 if (i >= ctrl->niomux_recalced)
3818e4a7 698 return;
699
700 *reg = data->reg;
701 *mask = data->mask;
702 *bit = data->bit;
703}
704
87065ca9
DW		 705static struct rockchip_mux_route_data px30_mux_route_data[] = {
706 {
707 /* cif-d2m0 */
708 .bank_num = 2,
709 .pin = 0,
710 .func = 1,
711 .route_offset = 0x184,
712 .route_val = BIT(16 + 7),
713 }, {
714 /* cif-d2m1 */
715 .bank_num = 3,
716 .pin = 3,
717 .func = 3,
718 .route_offset = 0x184,
719 .route_val = BIT(16 + 7) | BIT(7),
720 }, {
721 /* pdm-m0 */
722 .bank_num = 3,
723 .pin = 22,
724 .func = 2,
725 .route_offset = 0x184,
726 .route_val = BIT(16 + 8),
727 }, {
728 /* pdm-m1 */
729 .bank_num = 2,
730 .pin = 22,
731 .func = 1,
732 .route_offset = 0x184,
733 .route_val = BIT(16 + 8) | BIT(8),
734 }, {
735 /* uart2-rxm0 */
736 .bank_num = 1,
737 .pin = 27,
738 .func = 2,
739 .route_offset = 0x184,
740 .route_val = BIT(16 + 10),
741 }, {
742 /* uart2-rxm1 */
743 .bank_num = 2,
744 .pin = 14,
745 .func = 2,
746 .route_offset = 0x184,
747 .route_val = BIT(16 + 10) | BIT(10),
748 }, {
749 /* uart3-rxm0 */
750 .bank_num = 0,
751 .pin = 17,
752 .func = 2,
753 .route_offset = 0x184,
754 .route_val = BIT(16 + 9),
755 }, {
756 /* uart3-rxm1 */
757 .bank_num = 1,
758 .pin = 15,
759 .func = 2,
760 .route_offset = 0x184,
761 .route_val = BIT(16 + 9) | BIT(9),
762 },
763};
764
d23c66df
DW		 765static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
766 {
767 /* spi-0 */
768 .bank_num = 1,
769 .pin = 10,
770 .func = 1,
771 .route_offset = 0x144,
772 .route_val = BIT(16 + 3) | BIT(16 + 4),
773 }, {
774 /* spi-1 */
775 .bank_num = 1,
776 .pin = 27,
777 .func = 3,
778 .route_offset = 0x144,
779 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
780 }, {
781 /* spi-2 */
782 .bank_num = 0,
783 .pin = 13,
784 .func = 2,
785 .route_offset = 0x144,
786 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
787 }, {
788 /* i2s-0 */
789 .bank_num = 1,
790 .pin = 5,
791 .func = 1,
792 .route_offset = 0x144,
793 .route_val = BIT(16 + 5),
794 }, {
795 /* i2s-1 */
796 .bank_num = 0,
797 .pin = 14,
798 .func = 1,
799 .route_offset = 0x144,
800 .route_val = BIT(16 + 5) | BIT(5),
801 }, {
802 /* emmc-0 */
803 .bank_num = 1,
804 .pin = 22,
805 .func = 2,
806 .route_offset = 0x144,
807 .route_val = BIT(16 + 6),
808 }, {
809 /* emmc-1 */
810 .bank_num = 2,
811 .pin = 4,
812 .func = 2,
813 .route_offset = 0x144,
814 .route_val = BIT(16 + 6) | BIT(6),
815 },
816};
817
d4970ee0
DW		 818static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
819 {
820 /* pwm0-0 */
821 .bank_num = 0,
822 .pin = 26,
823 .func = 1,
824 .route_offset = 0x50,
825 .route_val = BIT(16),
826 }, {
827 /* pwm0-1 */
828 .bank_num = 3,
829 .pin = 21,
830 .func = 1,
831 .route_offset = 0x50,
832 .route_val = BIT(16) | BIT(0),
833 }, {
834 /* pwm1-0 */
835 .bank_num = 0,
836 .pin = 27,
837 .func = 1,
838 .route_offset = 0x50,
839 .route_val = BIT(16 + 1),
840 }, {
841 /* pwm1-1 */
842 .bank_num = 0,
843 .pin = 30,
844 .func = 2,
845 .route_offset = 0x50,
846 .route_val = BIT(16 + 1) | BIT(1),
847 }, {
848 /* pwm2-0 */
849 .bank_num = 0,
850 .pin = 28,
851 .func = 1,
852 .route_offset = 0x50,
853 .route_val = BIT(16 + 2),
854 }, {
855 /* pwm2-1 */
856 .bank_num = 1,
857 .pin = 12,
858 .func = 2,
859 .route_offset = 0x50,
860 .route_val = BIT(16 + 2) | BIT(2),
861 }, {
862 /* pwm3-0 */
863 .bank_num = 3,
864 .pin = 26,
865 .func = 1,
866 .route_offset = 0x50,
867 .route_val = BIT(16 + 3),
868 }, {
869 /* pwm3-1 */
870 .bank_num = 1,
871 .pin = 11,
872 .func = 2,
873 .route_offset = 0x50,
874 .route_val = BIT(16 + 3) | BIT(3),
875 }, {
876 /* sdio-0_d0 */
877 .bank_num = 1,
878 .pin = 1,
879 .func = 1,
880 .route_offset = 0x50,
881 .route_val = BIT(16 + 4),
882 }, {
883 /* sdio-1_d0 */
884 .bank_num = 3,
885 .pin = 2,
886 .func = 1,
887 .route_offset = 0x50,
888 .route_val = BIT(16 + 4) | BIT(4),
889 }, {
890 /* spi-0_rx */
891 .bank_num = 0,
892 .pin = 13,
893 .func = 2,
894 .route_offset = 0x50,
895 .route_val = BIT(16 + 5),
896 }, {
897 /* spi-1_rx */
898 .bank_num = 2,
899 .pin = 0,
900 .func = 2,
901 .route_offset = 0x50,
902 .route_val = BIT(16 + 5) | BIT(5),
903 }, {
904 /* emmc-0_cmd */
905 .bank_num = 1,
906 .pin = 22,
907 .func = 2,
908 .route_offset = 0x50,
909 .route_val = BIT(16 + 7),
910 }, {
911 /* emmc-1_cmd */
912 .bank_num = 2,
913 .pin = 4,
914 .func = 2,
915 .route_offset = 0x50,
916 .route_val = BIT(16 + 7) | BIT(7),
917 }, {
918 /* uart2-0_rx */
919 .bank_num = 1,
920 .pin = 19,
921 .func = 2,
922 .route_offset = 0x50,
923 .route_val = BIT(16 + 8),
924 }, {
925 /* uart2-1_rx */
926 .bank_num = 1,
927 .pin = 10,
928 .func = 2,
929 .route_offset = 0x50,
930 .route_val = BIT(16 + 8) | BIT(8),
931 }, {
932 /* uart1-0_rx */
933 .bank_num = 1,
934 .pin = 10,
935 .func = 1,
936 .route_offset = 0x50,
937 .route_val = BIT(16 + 11),
938 }, {
939 /* uart1-1_rx */
940 .bank_num = 3,
941 .pin = 13,
942 .func = 1,
943 .route_offset = 0x50,
944 .route_val = BIT(16 + 11) | BIT(11),
945 },
946};
947
4e96fd30
HS		 948static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
949 {
950 /* edphdmi_cecinoutt1 */
951 .bank_num = 7,
952 .pin = 16,
953 .func = 2,
954 .route_offset = 0x264,
955 .route_val = BIT(16 + 12) | BIT(12),
956 }, {
957 /* edphdmi_cecinout */
958 .bank_num = 7,
959 .pin = 23,
960 .func = 4,
961 .route_offset = 0x264,
962 .route_val = BIT(16 + 12),
963 },
964};
965
cedc964a
DW		 966static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
967 {
968 /* uart2dbg_rxm0 */
969 .bank_num = 1,
970 .pin = 1,
971 .func = 2,
972 .route_offset = 0x50,
973 .route_val = BIT(16) | BIT(16 + 1),
974 }, {
975 /* uart2dbg_rxm1 */
976 .bank_num = 2,
977 .pin = 1,
978 .func = 1,
979 .route_offset = 0x50,
980 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
981 }, {
a976d7b1 982 /* gmac-m1_rxd0 */
cedc964a
DW		 983 .bank_num = 1,
984 .pin = 11,
985 .func = 2,
986 .route_offset = 0x50,
a976d7b1
DW		 987 .route_val = BIT(16 + 2) | BIT(2),
988 }, {
989 /* gmac-m1-optimized_rxd3 */
990 .bank_num = 1,
991 .pin = 14,
992 .func = 2,
993 .route_offset = 0x50,
994 .route_val = BIT(16 + 10) | BIT(10),
cedc964a
DW		 995 }, {
996 /* pdm_sdi0m0 */
997 .bank_num = 2,
998 .pin = 19,
999 .func = 2,
1000 .route_offset = 0x50,
1001 .route_val = BIT(16 + 3),
1002 }, {
1003 /* pdm_sdi0m1 */
1004 .bank_num = 1,
1005 .pin = 23,
1006 .func = 3,
1007 .route_offset = 0x50,
1008 .route_val = BIT(16 + 3) | BIT(3),
1009 }, {
1010 /* spi_rxdm2 */
1011 .bank_num = 3,
1012 .pin = 2,
1013 .func = 4,
1014 .route_offset = 0x50,
1015 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1016 }, {
1017 /* i2s2_sdim0 */
1018 .bank_num = 1,
1019 .pin = 24,
1020 .func = 1,
1021 .route_offset = 0x50,
1022 .route_val = BIT(16 + 6),
1023 }, {
1024 /* i2s2_sdim1 */
1025 .bank_num = 3,
1026 .pin = 2,
1027 .func = 6,
1028 .route_offset = 0x50,
1029 .route_val = BIT(16 + 6) | BIT(6),
1030 }, {
1031 /* card_iom1 */
1032 .bank_num = 2,
1033 .pin = 22,
1034 .func = 3,
1035 .route_offset = 0x50,
1036 .route_val = BIT(16 + 7) | BIT(7),
1037 }, {
1038 /* tsp_d5m1 */
1039 .bank_num = 2,
1040 .pin = 16,
1041 .func = 3,
1042 .route_offset = 0x50,
1043 .route_val = BIT(16 + 8) | BIT(8),
1044 }, {
1045 /* cif_data5m1 */
1046 .bank_num = 2,
1047 .pin = 16,
1048 .func = 4,
1049 .route_offset = 0x50,
1050 .route_val = BIT(16 + 9) | BIT(9),
1051 },
1052};
1053
accc1ce7
DW		 1054static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1055 {
1056 /* uart2dbga_rx */
1057 .bank_num = 4,
1058 .pin = 8,
1059 .func = 2,
1060 .route_offset = 0xe21c,
1061 .route_val = BIT(16 + 10) | BIT(16 + 11),
1062 }, {
1063 /* uart2dbgb_rx */
1064 .bank_num = 4,
1065 .pin = 16,
1066 .func = 2,
1067 .route_offset = 0xe21c,
1068 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1069 }, {
1070 /* uart2dbgc_rx */
1071 .bank_num = 4,
1072 .pin = 19,
1073 .func = 1,
1074 .route_offset = 0xe21c,
1075 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1076 }, {
1077 /* pcie_clkreqn */
1078 .bank_num = 2,
1079 .pin = 26,
1080 .func = 2,
1081 .route_offset = 0xe21c,
1082 .route_val = BIT(16 + 14),
1083 }, {
1084 /* pcie_clkreqnb */
1085 .bank_num = 4,
1086 .pin = 24,
1087 .func = 1,
1088 .route_offset = 0xe21c,
1089 .route_val = BIT(16 + 14) | BIT(14),
1090 },
1091};
1092
bd35b9bf
DW		 1093static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1094 int mux, u32 *reg, u32 *value)
1095{
1096 struct rockchip_pinctrl *info = bank->drvdata;
1097 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1098 struct rockchip_mux_route_data *data;
1099 int i;
1100
1101 for (i = 0; i < ctrl->niomux_routes; i++) {
1102 data = &ctrl->iomux_routes[i];
1103 if ((data->bank_num == bank->bank_num) &&
1104 (data->pin == pin) && (data->func == mux))
1105 break;
1106 }
1107
1108 if (i >= ctrl->niomux_routes)
1109 return false;
1110
1111 *reg = data->route_offset;
1112 *value = data->route_val;
1113
1114 return true;
1115}
1116
a076e2ed
HS		 1117static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1118{
1119 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 1120 int iomux_num = (pin / 8);
95ec8ae4 1121 struct regmap *regmap;
751a99ab 1122 unsigned int val;
ea262ad6 1123 int reg, ret, mask, mux_type;
a076e2ed
HS		 1124 u8 bit;
1125
fc72c923
HS		 1126 if (iomux_num > 3)
1127 return -EINVAL;
1128
62f49226
HS		 1129 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1130 dev_err(info->dev, "pin %d is unrouted\n", pin);
1131 return -EINVAL;
1132 }
1133
fc72c923 1134 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
a076e2ed
HS		 1135 return RK_FUNC_GPIO;
1136
95ec8ae4
HS		 1137 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1138 ? info->regmap_pmu : info->regmap_base;
1139
a076e2ed 1140 /* get basic quadrupel of mux registers and the correct reg inside */
ea262ad6 1141 mux_type = bank->iomux[iomux_num].type;
6bc0d121 1142 reg = bank->iomux[iomux_num].offset;
ea262ad6 1143 if (mux_type & IOMUX_WIDTH_4BIT) {
03716e1d
HS		 1144 if ((pin % 8) >= 4)
1145 reg += 0x4;
1146 bit = (pin % 4) * 4;
8b6c6f93 1147 mask = 0xf;
ea262ad6 1148 } else if (mux_type & IOMUX_WIDTH_3BIT) {
8b6c6f93 1149 if ((pin % 8) >= 5)
1150 reg += 0x4;
1151 bit = (pin % 8 % 5) * 3;
1152 mask = 0x7;
03716e1d
HS		 1153 } else {
1154 bit = (pin % 8) * 2;
8b6c6f93 1155 mask = 0x3;
03716e1d 1156 }
a076e2ed 1157
c04c3fa6
DW		 1158 if (bank->recalced_mask & BIT(pin))
1159 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
ea262ad6 1160
95ec8ae4 1161 ret = regmap_read(regmap, reg, &val);
751a99ab
HS		 1162 if (ret)
1163 return ret;
1164
03716e1d 1165 return ((val >> bit) & mask);
a076e2ed
HS		 1166}
1167
05709c3e
JK		 1168static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1169 int pin, int mux)
1170{
1171 struct rockchip_pinctrl *info = bank->drvdata;
1172 int iomux_num = (pin / 8);
1173
1174 if (iomux_num > 3)
1175 return -EINVAL;
1176
1177 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1178 dev_err(info->dev, "pin %d is unrouted\n", pin);
1179 return -EINVAL;
1180 }
1181
1182 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1183 if (mux != RK_FUNC_GPIO) {
1184 dev_err(info->dev,
1185 "pin %d only supports a gpio mux\n", pin);
1186 return -ENOTSUPP;
1187 }
1188 }
1189
1190 return 0;
1191}
1192
d3e51161
HS		 1193/*
1194 * Set a new mux function for a pin.
1195 *
1196 * The register is divided into the upper and lower 16 bit. When changing
1197 * a value, the previous register value is not read and changed. Instead
1198 * it seems the changed bits are marked in the upper 16 bit, while the
1199 * changed value gets set in the same offset in the lower 16 bit.
1200 * All pin settings seem to be 2 bit wide in both the upper and lower
1201 * parts.
1202 * @bank: pin bank to change
1203 * @pin: pin to change
1204 * @mux: new mux function to set
1205 */
14797189 1206static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 1207{
1208 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 1209 int iomux_num = (pin / 8);
95ec8ae4 1210 struct regmap *regmap;
ea262ad6 1211 int reg, ret, mask, mux_type;
d3e51161 1212 u8 bit;
bd35b9bf 1213 u32 data, rmask, route_reg, route_val;
d3e51161 1214
05709c3e
JK		 1215 ret = rockchip_verify_mux(bank, pin, mux);
1216 if (ret < 0)
1217 return ret;
62f49226 1218
05709c3e
JK		 1219 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1220 return 0;
c4a532de 1221
d3e51161
HS		 1222 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1223 bank->bank_num, pin, mux);
1224
95ec8ae4
HS		 1225 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1226 ? info->regmap_pmu : info->regmap_base;
1227
d3e51161 1228 /* get basic quadrupel of mux registers and the correct reg inside */
ea262ad6 1229 mux_type = bank->iomux[iomux_num].type;
6bc0d121 1230 reg = bank->iomux[iomux_num].offset;
ea262ad6 1231 if (mux_type & IOMUX_WIDTH_4BIT) {
03716e1d
HS		 1232 if ((pin % 8) >= 4)
1233 reg += 0x4;
1234 bit = (pin % 4) * 4;
8b6c6f93 1235 mask = 0xf;
ea262ad6 1236 } else if (mux_type & IOMUX_WIDTH_3BIT) {
8b6c6f93 1237 if ((pin % 8) >= 5)
1238 reg += 0x4;
1239 bit = (pin % 8 % 5) * 3;
1240 mask = 0x7;
03716e1d
HS		 1241 } else {
1242 bit = (pin % 8) * 2;
8b6c6f93 1243 mask = 0x3;
03716e1d 1244 }
d3e51161 1245
c04c3fa6
DW		 1246 if (bank->recalced_mask & BIT(pin))
1247 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
ea262ad6 1248
bd35b9bf
DW		 1249 if (bank->route_mask & BIT(pin)) {
1250 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
1251 &route_val)) {
1252 ret = regmap_write(regmap, route_reg, route_val);
1253 if (ret)
1254 return ret;
1255 }
1256 }
1257
03716e1d 1258 data = (mask << (bit + 16));
99e872d9 1259 rmask = data | (data >> 16);
03716e1d 1260 data |= (mux & mask) << bit;
99e872d9 1261 ret = regmap_update_bits(regmap, reg, rmask, data);
d3e51161 1262
751a99ab 1263 return ret;
d3e51161
HS		 1264}
1265
87065ca9
DW		 1266#define PX30_PULL_PMU_OFFSET 0x10
1267#define PX30_PULL_GRF_OFFSET 0x60
1268#define PX30_PULL_BITS_PER_PIN 2
1269#define PX30_PULL_PINS_PER_REG 8
1270#define PX30_PULL_BANK_STRIDE 16
1271
1272static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1273 int pin_num, struct regmap **regmap,
1274 int *reg, u8 *bit)
1275{
1276 struct rockchip_pinctrl *info = bank->drvdata;
1277
1278 /* The first 32 pins of the first bank are located in PMU */
1279 if (bank->bank_num == 0) {
1280 *regmap = info->regmap_pmu;
1281 *reg = PX30_PULL_PMU_OFFSET;
1282 } else {
1283 *regmap = info->regmap_base;
1284 *reg = PX30_PULL_GRF_OFFSET;
1285
1286 /* correct the offset, as we're starting with the 2nd bank */
1287 *reg -= 0x10;
1288 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1289 }
1290
1291 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1292 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1293 *bit *= PX30_PULL_BITS_PER_PIN;
1294}
1295
1296#define PX30_DRV_PMU_OFFSET 0x20
1297#define PX30_DRV_GRF_OFFSET 0xf0
1298#define PX30_DRV_BITS_PER_PIN 2
1299#define PX30_DRV_PINS_PER_REG 8
1300#define PX30_DRV_BANK_STRIDE 16
1301
1302static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1303 int pin_num, struct regmap **regmap,
1304 int *reg, u8 *bit)
1305{
1306 struct rockchip_pinctrl *info = bank->drvdata;
1307
1308 /* The first 32 pins of the first bank are located in PMU */
1309 if (bank->bank_num == 0) {
1310 *regmap = info->regmap_pmu;
1311 *reg = PX30_DRV_PMU_OFFSET;
1312 } else {
1313 *regmap = info->regmap_base;
1314 *reg = PX30_DRV_GRF_OFFSET;
1315
1316 /* correct the offset, as we're starting with the 2nd bank */
1317 *reg -= 0x10;
1318 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1319 }
1320
1321 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1322 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1323 *bit *= PX30_DRV_BITS_PER_PIN;
1324}
1325
1326#define PX30_SCHMITT_PMU_OFFSET 0x38
1327#define PX30_SCHMITT_GRF_OFFSET 0xc0
1328#define PX30_SCHMITT_PINS_PER_PMU_REG 16
1329#define PX30_SCHMITT_BANK_STRIDE 16
1330#define PX30_SCHMITT_PINS_PER_GRF_REG 8
1331
1332static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1333 int pin_num,
1334 struct regmap **regmap,
1335 int *reg, u8 *bit)
1336{
1337 struct rockchip_pinctrl *info = bank->drvdata;
1338 int pins_per_reg;
1339
1340 if (bank->bank_num == 0) {
1341 *regmap = info->regmap_pmu;
1342 *reg = PX30_SCHMITT_PMU_OFFSET;
1343 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1344 } else {
1345 *regmap = info->regmap_base;
1346 *reg = PX30_SCHMITT_GRF_OFFSET;
1347 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1348 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1349 }
1350
1351 *reg += ((pin_num / pins_per_reg) * 4);
1352 *bit = pin_num % pins_per_reg;
1353
1354 return 0;
1355}
1356
b9c6dcab
AY		 1357#define RV1108_PULL_PMU_OFFSET 0x10
1358#define RV1108_PULL_OFFSET 0x110
1359#define RV1108_PULL_PINS_PER_REG 8
1360#define RV1108_PULL_BITS_PER_PIN 2
1361#define RV1108_PULL_BANK_STRIDE 16
688daf23 1362
b9c6dcab 1363static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
688daf23
AY		 1364 int pin_num, struct regmap **regmap,
1365 int *reg, u8 *bit)
1366{
1367 struct rockchip_pinctrl *info = bank->drvdata;
1368
1369 /* The first 24 pins of the first bank are located in PMU */
1370 if (bank->bank_num == 0) {
1371 *regmap = info->regmap_pmu;
b9c6dcab 1372 *reg = RV1108_PULL_PMU_OFFSET;
688daf23 1373 } else {
b9c6dcab 1374 *reg = RV1108_PULL_OFFSET;
688daf23
AY		 1375 *regmap = info->regmap_base;
1376 /* correct the offset, as we're starting with the 2nd bank */
1377 *reg -= 0x10;
b9c6dcab 1378 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
688daf23
AY		 1379 }
1380
b9c6dcab
AY		 1381 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1382 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1383 *bit *= RV1108_PULL_BITS_PER_PIN;
688daf23
AY		 1384}
1385
b9c6dcab
AY		 1386#define RV1108_DRV_PMU_OFFSET 0x20
1387#define RV1108_DRV_GRF_OFFSET 0x210
1388#define RV1108_DRV_BITS_PER_PIN 2
1389#define RV1108_DRV_PINS_PER_REG 8
1390#define RV1108_DRV_BANK_STRIDE 16
688daf23 1391
b9c6dcab 1392static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
688daf23
AY		 1393 int pin_num, struct regmap **regmap,
1394 int *reg, u8 *bit)
1395{
1396 struct rockchip_pinctrl *info = bank->drvdata;
1397
1398 /* The first 24 pins of the first bank are located in PMU */
1399 if (bank->bank_num == 0) {
1400 *regmap = info->regmap_pmu;
b9c6dcab 1401 *reg = RV1108_DRV_PMU_OFFSET;
688daf23
AY		 1402 } else {
1403 *regmap = info->regmap_base;
b9c6dcab 1404 *reg = RV1108_DRV_GRF_OFFSET;
688daf23
AY		 1405
1406 /* correct the offset, as we're starting with the 2nd bank */
1407 *reg -= 0x10;
b9c6dcab 1408 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
688daf23
AY		 1409 }
1410
b9c6dcab
AY		 1411 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1412 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1413 *bit *= RV1108_DRV_BITS_PER_PIN;
688daf23
AY		 1414}
1415
5caff7ea
AY		 1416#define RV1108_SCHMITT_PMU_OFFSET 0x30
1417#define RV1108_SCHMITT_GRF_OFFSET 0x388
1418#define RV1108_SCHMITT_BANK_STRIDE 8
1419#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1420#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1421
1422static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1423 int pin_num,
1424 struct regmap **regmap,
1425 int *reg, u8 *bit)
1426{
1427 struct rockchip_pinctrl *info = bank->drvdata;
1428 int pins_per_reg;
1429
1430 if (bank->bank_num == 0) {
1431 *regmap = info->regmap_pmu;
1432 *reg = RV1108_SCHMITT_PMU_OFFSET;
1433 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1434 } else {
1435 *regmap = info->regmap_base;
1436 *reg = RV1108_SCHMITT_GRF_OFFSET;
1437 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1438 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1439 }
1440 *reg += ((pin_num / pins_per_reg) * 4);
1441 *bit = pin_num % pins_per_reg;
1442
1443 return 0;
1444}
1445
a282926d
HS		 1446#define RK2928_PULL_OFFSET 0x118
1447#define RK2928_PULL_PINS_PER_REG 16
1448#define RK2928_PULL_BANK_STRIDE 8
1449
1450static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 1451 int pin_num, struct regmap **regmap,
1452 int *reg, u8 *bit)
a282926d
HS		 1453{
1454 struct rockchip_pinctrl *info = bank->drvdata;
1455
751a99ab
HS		 1456 *regmap = info->regmap_base;
1457 *reg = RK2928_PULL_OFFSET;
a282926d
HS		 1458 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1459 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1460
1461 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1462};
1463
d23c66df
DW		 1464#define RK3128_PULL_OFFSET 0x118
1465
1466static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1467 int pin_num, struct regmap **regmap,
1468 int *reg, u8 *bit)
1469{
1470 struct rockchip_pinctrl *info = bank->drvdata;
1471
1472 *regmap = info->regmap_base;
1473 *reg = RK3128_PULL_OFFSET;
1474 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1475 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1476
1477 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1478}
1479
bfc7a42a 1480#define RK3188_PULL_OFFSET 0x164
6ca5274d
HS		 1481#define RK3188_PULL_BITS_PER_PIN 2
1482#define RK3188_PULL_PINS_PER_REG 8
1483#define RK3188_PULL_BANK_STRIDE 16
14dee867 1484#define RK3188_PULL_PMU_OFFSET 0x64
6ca5274d
HS		 1485
1486static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 1487 int pin_num, struct regmap **regmap,
1488 int *reg, u8 *bit)
6ca5274d
HS		 1489{
1490 struct rockchip_pinctrl *info = bank->drvdata;
1491
1492 /* The first 12 pins of the first bank are located elsewhere */
fc72c923 1493 if (bank->bank_num == 0 && pin_num < 12) {
14dee867
HS		 1494 *regmap = info->regmap_pmu ? info->regmap_pmu
1495 : bank->regmap_pull;
1496 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
751a99ab 1497 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
6ca5274d
HS		 1498 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1499 *bit *= RK3188_PULL_BITS_PER_PIN;
1500 } else {
751a99ab
HS		 1501 *regmap = info->regmap_pull ? info->regmap_pull
1502 : info->regmap_base;
1503 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1504
bfc7a42a
HS		 1505 /* correct the offset, as it is the 2nd pull register */
1506 *reg -= 4;
6ca5274d
HS		 1507 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1508 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1509
1510 /*
1511 * The bits in these registers have an inverse ordering
1512 * with the lowest pin being in bits 15:14 and the highest
1513 * pin in bits 1:0
1514 */
1515 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1516 *bit *= RK3188_PULL_BITS_PER_PIN;
1517 }
1518}
1519
304f077d
HS		 1520#define RK3288_PULL_OFFSET 0x140
1521static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1522 int pin_num, struct regmap **regmap,
1523 int *reg, u8 *bit)
1524{
1525 struct rockchip_pinctrl *info = bank->drvdata;
1526
1527 /* The first 24 pins of the first bank are located in PMU */
1528 if (bank->bank_num == 0) {
1529 *regmap = info->regmap_pmu;
1530 *reg = RK3188_PULL_PMU_OFFSET;
1531
1532 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1533 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1534 *bit *= RK3188_PULL_BITS_PER_PIN;
1535 } else {
1536 *regmap = info->regmap_base;
1537 *reg = RK3288_PULL_OFFSET;
1538
1539 /* correct the offset, as we're starting with the 2nd bank */
1540 *reg -= 0x10;
1541 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1542 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1543
1544 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1545 *bit *= RK3188_PULL_BITS_PER_PIN;
1546 }
1547}
1548
b547c800
HS		 1549#define RK3288_DRV_PMU_OFFSET 0x70
1550#define RK3288_DRV_GRF_OFFSET 0x1c0
1551#define RK3288_DRV_BITS_PER_PIN 2
1552#define RK3288_DRV_PINS_PER_REG 8
1553#define RK3288_DRV_BANK_STRIDE 16
b547c800
HS		 1554
1555static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1556 int pin_num, struct regmap **regmap,
1557 int *reg, u8 *bit)
1558{
1559 struct rockchip_pinctrl *info = bank->drvdata;
1560
1561 /* The first 24 pins of the first bank are located in PMU */
1562 if (bank->bank_num == 0) {
1563 *regmap = info->regmap_pmu;
1564 *reg = RK3288_DRV_PMU_OFFSET;
1565
1566 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1567 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1568 *bit *= RK3288_DRV_BITS_PER_PIN;
1569 } else {
1570 *regmap = info->regmap_base;
1571 *reg = RK3288_DRV_GRF_OFFSET;
1572
1573 /* correct the offset, as we're starting with the 2nd bank */
1574 *reg -= 0x10;
1575 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1576 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1577
1578 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1579 *bit *= RK3288_DRV_BITS_PER_PIN;
1580 }
1581}
1582
fea0fe60
JC		 1583#define RK3228_PULL_OFFSET 0x100
1584
1585static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1586 int pin_num, struct regmap **regmap,
1587 int *reg, u8 *bit)
1588{
1589 struct rockchip_pinctrl *info = bank->drvdata;
1590
1591 *regmap = info->regmap_base;
1592 *reg = RK3228_PULL_OFFSET;
1593 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1594 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1595
1596 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1597 *bit *= RK3188_PULL_BITS_PER_PIN;
1598}
1599
1600#define RK3228_DRV_GRF_OFFSET 0x200
1601
1602static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1603 int pin_num, struct regmap **regmap,
1604 int *reg, u8 *bit)
1605{
1606 struct rockchip_pinctrl *info = bank->drvdata;
1607
1608 *regmap = info->regmap_base;
1609 *reg = RK3228_DRV_GRF_OFFSET;
1610 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1611 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1612
1613 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1614 *bit *= RK3288_DRV_BITS_PER_PIN;
1615}
1616
daecdc66
HS		 1617#define RK3368_PULL_GRF_OFFSET 0x100
1618#define RK3368_PULL_PMU_OFFSET 0x10
1619
1620static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1621 int pin_num, struct regmap **regmap,
1622 int *reg, u8 *bit)
1623{
1624 struct rockchip_pinctrl *info = bank->drvdata;
1625
1626 /* The first 32 pins of the first bank are located in PMU */
1627 if (bank->bank_num == 0) {
1628 *regmap = info->regmap_pmu;
1629 *reg = RK3368_PULL_PMU_OFFSET;
1630
1631 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1632 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1633 *bit *= RK3188_PULL_BITS_PER_PIN;
1634 } else {
1635 *regmap = info->regmap_base;
1636 *reg = RK3368_PULL_GRF_OFFSET;
1637
1638 /* correct the offset, as we're starting with the 2nd bank */
1639 *reg -= 0x10;
1640 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1641 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1642
1643 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1644 *bit *= RK3188_PULL_BITS_PER_PIN;
1645 }
1646}
1647
1648#define RK3368_DRV_PMU_OFFSET 0x20
1649#define RK3368_DRV_GRF_OFFSET 0x200
1650
1651static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1652 int pin_num, struct regmap **regmap,
1653 int *reg, u8 *bit)
1654{
1655 struct rockchip_pinctrl *info = bank->drvdata;
1656
1657 /* The first 32 pins of the first bank are located in PMU */
1658 if (bank->bank_num == 0) {
1659 *regmap = info->regmap_pmu;
1660 *reg = RK3368_DRV_PMU_OFFSET;
1661
1662 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1663 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1664 *bit *= RK3288_DRV_BITS_PER_PIN;
1665 } else {
1666 *regmap = info->regmap_base;
1667 *reg = RK3368_DRV_GRF_OFFSET;
1668
1669 /* correct the offset, as we're starting with the 2nd bank */
1670 *reg -= 0x10;
1671 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1672 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1673
1674 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1675 *bit *= RK3288_DRV_BITS_PER_PIN;
1676 }
1677}
1678
b6c23275
DW		 1679#define RK3399_PULL_GRF_OFFSET 0xe040
1680#define RK3399_PULL_PMU_OFFSET 0x40
1681#define RK3399_DRV_3BITS_PER_PIN 3
1682
1683static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1684 int pin_num, struct regmap **regmap,
1685 int *reg, u8 *bit)
1686{
1687 struct rockchip_pinctrl *info = bank->drvdata;
1688
1689 /* The bank0:16 and bank1:32 pins are located in PMU */
1690 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1691 *regmap = info->regmap_pmu;
1692 *reg = RK3399_PULL_PMU_OFFSET;
1693
1694 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1695
1696 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1697 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1698 *bit *= RK3188_PULL_BITS_PER_PIN;
1699 } else {
1700 *regmap = info->regmap_base;
1701 *reg = RK3399_PULL_GRF_OFFSET;
1702
1703 /* correct the offset, as we're starting with the 3rd bank */
1704 *reg -= 0x20;
1705 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1706 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1707
1708 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1709 *bit *= RK3188_PULL_BITS_PER_PIN;
1710 }
1711}
1712
1713static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1714 int pin_num, struct regmap **regmap,
1715 int *reg, u8 *bit)
1716{
1717 struct rockchip_pinctrl *info = bank->drvdata;
1718 int drv_num = (pin_num / 8);
1719
1720 /* The bank0:16 and bank1:32 pins are located in PMU */
1721 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1722 *regmap = info->regmap_pmu;
1723 else
1724 *regmap = info->regmap_base;
1725
1726 *reg = bank->drv[drv_num].offset;
1727 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1728 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1729 *bit = (pin_num % 8) * 3;
1730 else
1731 *bit = (pin_num % 8) * 2;
1732}
1733
1734static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1735 { 2, 4, 8, 12, -1, -1, -1, -1 },
1736 { 3, 6, 9, 12, -1, -1, -1, -1 },
1737 { 5, 10, 15, 20, -1, -1, -1, -1 },
1738 { 4, 6, 8, 10, 12, 14, 16, 18 },
1739 { 4, 7, 10, 13, 16, 19, 22, 26 }
1740};
ef17f69f
HS		 1741
1742static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1743 int pin_num)
b547c800 1744{
ef17f69f
HS		 1745 struct rockchip_pinctrl *info = bank->drvdata;
1746 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 1747 struct regmap *regmap;
1748 int reg, ret;
b6c23275 1749 u32 data, temp, rmask_bits;
b547c800 1750 u8 bit;
b6c23275 1751 int drv_type = bank->drv[pin_num / 8].drv_type;
b547c800 1752
ef17f69f 1753 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800 1754
b6c23275
DW		 1755 switch (drv_type) {
1756 case DRV_TYPE_IO_1V8_3V0_AUTO:
1757 case DRV_TYPE_IO_3V3_ONLY:
1758 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1759 switch (bit) {
1760 case 0 ... 12:
1761 /* regular case, nothing to do */
1762 break;
1763 case 15:
1764 /*
1765 * drive-strength offset is special, as it is
1766 * spread over 2 registers
1767 */
1768 ret = regmap_read(regmap, reg, &data);
1769 if (ret)
1770 return ret;
1771
1772 ret = regmap_read(regmap, reg + 0x4, &temp);
1773 if (ret)
1774 return ret;
1775
1776 /*
1777 * the bit data[15] contains bit 0 of the value
1778 * while temp[1:0] contains bits 2 and 1
1779 */
1780 data >>= 15;
1781 temp &= 0x3;
1782 temp <<= 1;
1783 data |= temp;
1784
1785 return rockchip_perpin_drv_list[drv_type][data];
1786 case 18 ... 21:
1787 /* setting fully enclosed in the second register */
1788 reg += 4;
1789 bit -= 16;
1790 break;
1791 default:
1792 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1793 bit, drv_type);
1794 return -EINVAL;
1795 }
1796
1797 break;
1798 case DRV_TYPE_IO_DEFAULT:
1799 case DRV_TYPE_IO_1V8_OR_3V0:
1800 case DRV_TYPE_IO_1V8_ONLY:
1801 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1802 break;
1803 default:
1804 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1805 drv_type);
1806 return -EINVAL;
1807 }
1808
b547c800
HS		 1809 ret = regmap_read(regmap, reg, &data);
1810 if (ret)
1811 return ret;
1812
1813 data >>= bit;
b6c23275 1814 data &= (1 << rmask_bits) - 1;
b547c800 1815
b6c23275 1816 return rockchip_perpin_drv_list[drv_type][data];
b547c800
HS		 1817}
1818
ef17f69f
HS		 1819static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1820 int pin_num, int strength)
b547c800
HS		 1821{
1822 struct rockchip_pinctrl *info = bank->drvdata;
ef17f69f 1823 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800 1824 struct regmap *regmap;
b547c800 1825 int reg, ret, i;
b6c23275 1826 u32 data, rmask, rmask_bits, temp;
b547c800 1827 u8 bit;
b6c23275
DW		 1828 int drv_type = bank->drv[pin_num / 8].drv_type;
1829
1830 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1831 bank->bank_num, pin_num, strength);
b547c800 1832
ef17f69f 1833 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800
HS		 1834
1835 ret = -EINVAL;
b6c23275
DW		 1836 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1837 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
b547c800
HS		 1838 ret = i;
1839 break;
b6c23275
DW		 1840 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1841 ret = rockchip_perpin_drv_list[drv_type][i];
1842 break;
b547c800
HS		 1843 }
1844 }
1845
1846 if (ret < 0) {
1847 dev_err(info->dev, "unsupported driver strength %d\n",
1848 strength);
1849 return ret;
1850 }
1851
b6c23275
DW		 1852 switch (drv_type) {
1853 case DRV_TYPE_IO_1V8_3V0_AUTO:
1854 case DRV_TYPE_IO_3V3_ONLY:
1855 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1856 switch (bit) {
1857 case 0 ... 12:
1858 /* regular case, nothing to do */
1859 break;
1860 case 15:
1861 /*
1862 * drive-strength offset is special, as it is spread
1863 * over 2 registers, the bit data[15] contains bit 0
1864 * of the value while temp[1:0] contains bits 2 and 1
1865 */
1866 data = (ret & 0x1) << 15;
1867 temp = (ret >> 0x1) & 0x3;
1868
1869 rmask = BIT(15) | BIT(31);
1870 data |= BIT(31);
1871 ret = regmap_update_bits(regmap, reg, rmask, data);
f07bedc3 1872 if (ret)
b6c23275 1873 return ret;
b6c23275
DW		 1874
1875 rmask = 0x3 | (0x3 << 16);
1876 temp |= (0x3 << 16);
1877 reg += 0x4;
1878 ret = regmap_update_bits(regmap, reg, rmask, temp);
1879
b6c23275
DW		 1880 return ret;
1881 case 18 ... 21:
1882 /* setting fully enclosed in the second register */
1883 reg += 4;
1884 bit -= 16;
1885 break;
1886 default:
b6c23275
DW		 1887 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1888 bit, drv_type);
1889 return -EINVAL;
1890 }
1891 break;
1892 case DRV_TYPE_IO_DEFAULT:
1893 case DRV_TYPE_IO_1V8_OR_3V0:
1894 case DRV_TYPE_IO_1V8_ONLY:
1895 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1896 break;
1897 default:
b6c23275
DW		 1898 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1899 drv_type);
1900 return -EINVAL;
1901 }
1902
b547c800 1903 /* enable the write to the equivalent lower bits */
b6c23275 1904 data = ((1 << rmask_bits) - 1) << (bit + 16);
99e872d9 1905 rmask = data | (data >> 16);
b547c800
HS		 1906 data |= (ret << bit);
1907
99e872d9 1908 ret = regmap_update_bits(regmap, reg, rmask, data);
b547c800
HS		 1909
1910 return ret;
1911}
1912
3ba6767a
DW		 1913static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1914 {
1915 PIN_CONFIG_BIAS_DISABLE,
1916 PIN_CONFIG_BIAS_PULL_UP,
1917 PIN_CONFIG_BIAS_PULL_DOWN,
1918 PIN_CONFIG_BIAS_BUS_HOLD
1919 },
1920 {
1921 PIN_CONFIG_BIAS_DISABLE,
1922 PIN_CONFIG_BIAS_PULL_DOWN,
1923 PIN_CONFIG_BIAS_DISABLE,
1924 PIN_CONFIG_BIAS_PULL_UP
1925 },
1926};
1927
d3e51161
HS		 1928static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1929{
1930 struct rockchip_pinctrl *info = bank->drvdata;
1931 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 1932 struct regmap *regmap;
3ba6767a 1933 int reg, ret, pull_type;
d3e51161 1934 u8 bit;
6ca5274d 1935 u32 data;
d3e51161
HS		 1936
1937 /* rk3066b does support any pulls */
a282926d 1938 if (ctrl->type == RK3066B)
d3e51161
HS		 1939 return PIN_CONFIG_BIAS_DISABLE;
1940
751a99ab
HS		 1941 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1942
1943 ret = regmap_read(regmap, reg, &data);
1944 if (ret)
1945 return ret;
6ca5274d 1946
a282926d
HS		 1947 switch (ctrl->type) {
1948 case RK2928:
d23c66df 1949 case RK3128:
751a99ab 1950 return !(data & BIT(bit))
d3e51161
HS		 1951 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1952 : PIN_CONFIG_BIAS_DISABLE;
87065ca9 1953 case PX30:
b9c6dcab 1954 case RV1108:
a282926d 1955 case RK3188:
66d750e1 1956 case RK3288:
daecdc66 1957 case RK3368:
b6c23275 1958 case RK3399:
3ba6767a 1959 pull_type = bank->pull_type[pin_num / 8];
751a99ab 1960 data >>= bit;
6ca5274d
HS		 1961 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1962
3ba6767a 1963 return rockchip_pull_list[pull_type][data];
a282926d
HS		 1964 default:
1965 dev_err(info->dev, "unsupported pinctrl type\n");
1966 return -EINVAL;
1967 };
d3e51161
HS		 1968}
1969
1970static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1971 int pin_num, int pull)
1972{
1973 struct rockchip_pinctrl *info = bank->drvdata;
1974 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 1975 struct regmap *regmap;
3ba6767a 1976 int reg, ret, i, pull_type;
d3e51161 1977 u8 bit;
99e872d9 1978 u32 data, rmask;
d3e51161
HS		 1979
1980 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1981 bank->bank_num, pin_num, pull);
1982
1983 /* rk3066b does support any pulls */
a282926d 1984 if (ctrl->type == RK3066B)
d3e51161
HS		 1985 return pull ? -EINVAL : 0;
1986
751a99ab 1987 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
6ca5274d 1988
a282926d
HS		 1989 switch (ctrl->type) {
1990 case RK2928:
d23c66df 1991 case RK3128:
d3e51161
HS		 1992 data = BIT(bit + 16);
1993 if (pull == PIN_CONFIG_BIAS_DISABLE)
1994 data |= BIT(bit);
751a99ab 1995 ret = regmap_write(regmap, reg, data);
a282926d 1996 break;
87065ca9 1997 case PX30:
b9c6dcab 1998 case RV1108:
a282926d 1999 case RK3188:
66d750e1 2000 case RK3288:
daecdc66 2001 case RK3368:
b6c23275 2002 case RK3399:
3ba6767a
DW		 2003 pull_type = bank->pull_type[pin_num / 8];
2004 ret = -EINVAL;
2005 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2006 i++) {
2007 if (rockchip_pull_list[pull_type][i] == pull) {
2008 ret = i;
2009 break;
2010 }
2011 }
2012
2013 if (ret < 0) {
2014 dev_err(info->dev, "unsupported pull setting %d\n",
2015 pull);
2016 return ret;
2017 }
2018
6ca5274d
HS		 2019 /* enable the write to the equivalent lower bits */
2020 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
99e872d9 2021 rmask = data | (data >> 16);
3ba6767a 2022 data |= (ret << bit);
6ca5274d 2023
99e872d9 2024 ret = regmap_update_bits(regmap, reg, rmask, data);
6ca5274d 2025 break;
a282926d
HS		 2026 default:
2027 dev_err(info->dev, "unsupported pinctrl type\n");
2028 return -EINVAL;
d3e51161
HS		 2029 }
2030
751a99ab 2031 return ret;
d3e51161
HS		 2032}
2033
728d3f5a 2034#define RK3328_SCHMITT_BITS_PER_PIN 1
2035#define RK3328_SCHMITT_PINS_PER_REG 16
2036#define RK3328_SCHMITT_BANK_STRIDE 8
2037#define RK3328_SCHMITT_GRF_OFFSET 0x380
2038
2039static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2040 int pin_num,
2041 struct regmap **regmap,
2042 int *reg, u8 *bit)
2043{
2044 struct rockchip_pinctrl *info = bank->drvdata;
2045
2046 *regmap = info->regmap_base;
2047 *reg = RK3328_SCHMITT_GRF_OFFSET;
2048
2049 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2050 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2051 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2052
2053 return 0;
2054}
2055
e3b357d7 2056static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2057{
2058 struct rockchip_pinctrl *info = bank->drvdata;
2059 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2060 struct regmap *regmap;
2061 int reg, ret;
2062 u8 bit;
2063 u32 data;
2064
2065 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2066 if (ret)
2067 return ret;
2068
2069 ret = regmap_read(regmap, reg, &data);
2070 if (ret)
2071 return ret;
2072
2073 data >>= bit;
2074 return data & 0x1;
2075}
2076
2077static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2078 int pin_num, int enable)
2079{
2080 struct rockchip_pinctrl *info = bank->drvdata;
2081 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2082 struct regmap *regmap;
2083 int reg, ret;
e3b357d7 2084 u8 bit;
2085 u32 data, rmask;
2086
2087 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2088 bank->bank_num, pin_num, enable);
2089
2090 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2091 if (ret)
2092 return ret;
2093
e3b357d7 2094 /* enable the write to the equivalent lower bits */
2095 data = BIT(bit + 16) | (enable << bit);
2096 rmask = BIT(bit + 16) | BIT(bit);
2097
f07bedc3 2098 return regmap_update_bits(regmap, reg, rmask, data);
e3b357d7 2099}
2100
d3e51161
HS		 2101/*
2102 * Pinmux_ops handling
2103 */
2104
2105static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2106{
2107 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2108
2109 return info->nfunctions;
2110}
2111
2112static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2113 unsigned selector)
2114{
2115 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2116
2117 return info->functions[selector].name;
2118}
2119
2120static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2121 unsigned selector, const char * const **groups,
2122 unsigned * const num_groups)
2123{
2124 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2125
2126 *groups = info->functions[selector].groups;
2127 *num_groups = info->functions[selector].ngroups;
2128
2129 return 0;
2130}
2131
03e9f0ca
LW		 2132static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2133 unsigned group)
d3e51161
HS		 2134{
2135 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2136 const unsigned int *pins = info->groups[group].pins;
2137 const struct rockchip_pin_config *data = info->groups[group].data;
2138 struct rockchip_pin_bank *bank;
14797189 2139 int cnt, ret = 0;
d3e51161
HS		 2140
2141 dev_dbg(info->dev, "enable function %s group %s\n",
2142 info->functions[selector].name, info->groups[group].name);
2143
2144 /*
85dc397a 2145 * for each pin in the pin group selected, program the corresponding
d3e51161
HS		 2146 * pin function number in the config register.
2147 */
2148 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2149 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 2150 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2151 data[cnt].func);
2152 if (ret)
2153 break;
2154 }
2155
2156 if (ret) {
2157 /* revert the already done pin settings */
2158 for (cnt--; cnt >= 0; cnt--)
2159 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2160
2161 return ret;
d3e51161
HS		 2162 }
2163
2164 return 0;
2165}
2166
6ba20a00
CW		 2167static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2168{
2169 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2170 u32 data;
5c9d8c4f 2171 int ret;
6ba20a00 2172
5c9d8c4f
BN		 2173 ret = clk_enable(bank->clk);
2174 if (ret < 0) {
2175 dev_err(bank->drvdata->dev,
2176 "failed to enable clock for bank %s\n", bank->name);
2177 return ret;
2178 }
6ba20a00 2179 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
5c9d8c4f 2180 clk_disable(bank->clk);
6ba20a00
CW		 2181
2182 return !(data & BIT(offset));
2183}
2184
d3e51161
HS		 2185/*
2186 * The calls to gpio_direction_output() and gpio_direction_input()
2187 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2188 * function called from the gpiolib interface).
2189 */
e5c2c9db
DA		 2190static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2191 int pin, bool input)
d3e51161 2192{
d3e51161 2193 struct rockchip_pin_bank *bank;
e5c2c9db 2194 int ret;
fab262f5 2195 unsigned long flags;
d3e51161
HS		 2196 u32 data;
2197
03bf81f1 2198 bank = gpiochip_get_data(chip);
d3e51161 2199
14797189
HS		 2200 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2201 if (ret < 0)
2202 return ret;
d3e51161 2203
07a06ae9 2204 clk_enable(bank->clk);
70b7aa7a 2205 raw_spin_lock_irqsave(&bank->slock, flags);
fab262f5 2206
d3e51161
HS		 2207 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2208 /* set bit to 1 for output, 0 for input */
2209 if (!input)
2210 data |= BIT(pin);
2211 else
2212 data &= ~BIT(pin);
2213 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2214
70b7aa7a 2215 raw_spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 2216 clk_disable(bank->clk);
fab262f5 2217
d3e51161
HS		 2218 return 0;
2219}
2220
e5c2c9db
DA		 2221static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2222 struct pinctrl_gpio_range *range,
2223 unsigned offset, bool input)
2224{
2225 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2226 struct gpio_chip *chip;
2227 int pin;
2228
2229 chip = range->gc;
2230 pin = offset - chip->base;
2231 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2232 offset, range->name, pin, input ? "input" : "output");
2233
2234 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2235 input);
2236}
2237
d3e51161
HS		 2238static const struct pinmux_ops rockchip_pmx_ops = {
2239 .get_functions_count = rockchip_pmx_get_funcs_count,
2240 .get_function_name = rockchip_pmx_get_func_name,
2241 .get_function_groups = rockchip_pmx_get_groups,
03e9f0ca 2242 .set_mux = rockchip_pmx_set,
d3e51161
HS		 2243 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2244};
2245
2246/*
2247 * Pinconf_ops handling
2248 */
2249
44b6d930
HS		 2250static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2251 enum pin_config_param pull)
2252{
a282926d
HS		 2253 switch (ctrl->type) {
2254 case RK2928:
d23c66df 2255 case RK3128:
a282926d
HS		 2256 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2257 pull == PIN_CONFIG_BIAS_DISABLE);
2258 case RK3066B:
44b6d930 2259 return pull ? false : true;
87065ca9 2260 case PX30:
b9c6dcab 2261 case RV1108:
a282926d 2262 case RK3188:
66d750e1 2263 case RK3288:
daecdc66 2264 case RK3368:
b6c23275 2265 case RK3399:
a282926d 2266 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 2267 }
2268
a282926d 2269 return false;
44b6d930
HS		 2270}
2271
e5c2c9db 2272static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
a076e2ed
HS		 2273static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2274
d3e51161
HS		 2275/* set the pin config settings for a specified pin */
2276static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 2277 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 2278{
2279 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2280 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9 2281 enum pin_config_param param;
58957d2e 2282 u32 arg;
03b054e9
SY		 2283 int i;
2284 int rc;
2285
2286 for (i = 0; i < num_configs; i++) {
2287 param = pinconf_to_config_param(configs[i]);
2288 arg = pinconf_to_config_argument(configs[i]);
2289
2290 switch (param) {
2291 case PIN_CONFIG_BIAS_DISABLE:
2292 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2293 param);
2294 if (rc)
2295 return rc;
2296 break;
2297 case PIN_CONFIG_BIAS_PULL_UP:
2298 case PIN_CONFIG_BIAS_PULL_DOWN:
2299 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 2300 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 2301 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2302 return -ENOTSUPP;
2303
2304 if (!arg)
2305 return -EINVAL;
2306
2307 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2308 param);
2309 if (rc)
2310 return rc;
2311 break;
a076e2ed 2312 case PIN_CONFIG_OUTPUT:
e5c2c9db
DA		 2313 rockchip_gpio_set(&bank->gpio_chip,
2314 pin - bank->pin_base, arg);
2315 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2316 pin - bank->pin_base, false);
a076e2ed
HS		 2317 if (rc)
2318 return rc;
2319 break;
b547c800
HS		 2320 case PIN_CONFIG_DRIVE_STRENGTH:
2321 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 2322 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 2323 return -ENOTSUPP;
2324
ef17f69f
HS		 2325 rc = rockchip_set_drive_perpin(bank,
2326 pin - bank->pin_base, arg);
b547c800
HS		 2327 if (rc < 0)
2328 return rc;
2329 break;
e3b357d7 2330 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2331 if (!info->ctrl->schmitt_calc_reg)
2332 return -ENOTSUPP;
2333
2334 rc = rockchip_set_schmitt(bank,
2335 pin - bank->pin_base, arg);
2336 if (rc < 0)
2337 return rc;
2338 break;
03b054e9 2339 default:
44b6d930 2340 return -ENOTSUPP;
03b054e9
SY		 2341 break;
2342 }
2343 } /* for each config */
d3e51161
HS		 2344
2345 return 0;
2346}
2347
2348/* get the pin config settings for a specified pin */
2349static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2350 unsigned long *config)
2351{
2352 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2353 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2354 enum pin_config_param param = pinconf_to_config_param(*config);
dab3eba7 2355 u16 arg;
a076e2ed 2356 int rc;
d3e51161
HS		 2357
2358 switch (param) {
2359 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 2360 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2361 return -EINVAL;
2362
dab3eba7 2363 arg = 0;
44b6d930 2364 break;
d3e51161
HS		 2365 case PIN_CONFIG_BIAS_PULL_UP:
2366 case PIN_CONFIG_BIAS_PULL_DOWN:
2367 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 2368 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 2369 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2370 return -ENOTSUPP;
d3e51161 2371
44b6d930 2372 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 2373 return -EINVAL;
2374
dab3eba7 2375 arg = 1;
d3e51161 2376 break;
a076e2ed
HS		 2377 case PIN_CONFIG_OUTPUT:
2378 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2379 if (rc != RK_FUNC_GPIO)
2380 return -EINVAL;
2381
2382 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2383 if (rc < 0)
2384 return rc;
2385
2386 arg = rc ? 1 : 0;
2387 break;
b547c800
HS		 2388 case PIN_CONFIG_DRIVE_STRENGTH:
2389 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 2390 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 2391 return -ENOTSUPP;
2392
ef17f69f 2393 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
b547c800
HS		 2394 if (rc < 0)
2395 return rc;
2396
e3b357d7 2397 arg = rc;
2398 break;
2399 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2400 if (!info->ctrl->schmitt_calc_reg)
2401 return -ENOTSUPP;
2402
2403 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2404 if (rc < 0)
2405 return rc;
2406
b547c800
HS		 2407 arg = rc;
2408 break;
d3e51161
HS		 2409 default:
2410 return -ENOTSUPP;
2411 break;
2412 }
2413
dab3eba7
HS		 2414 *config = pinconf_to_config_packed(param, arg);
2415
d3e51161
HS		 2416 return 0;
2417}
2418
2419static const struct pinconf_ops rockchip_pinconf_ops = {
2420 .pin_config_get = rockchip_pinconf_get,
2421 .pin_config_set = rockchip_pinconf_set,
ed62f2f2 2422 .is_generic = true,
d3e51161
HS		 2423};
2424
65fca613
HS		 2425static const struct of_device_id rockchip_bank_match[] = {
2426 { .compatible = "rockchip,gpio-bank" },
6ca5274d 2427 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 2428 {},
2429};
d3e51161
HS		 2430
2431static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2432 struct device_node *np)
2433{
2434 struct device_node *child;
2435
2436 for_each_child_of_node(np, child) {
65fca613 2437 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 2438 continue;
2439
2440 info->nfunctions++;
2441 info->ngroups += of_get_child_count(child);
2442 }
2443}
2444
2445static int rockchip_pinctrl_parse_groups(struct device_node *np,
2446 struct rockchip_pin_group *grp,
2447 struct rockchip_pinctrl *info,
2448 u32 index)
2449{
2450 struct rockchip_pin_bank *bank;
2451 int size;
2452 const __be32 *list;
2453 int num;
2454 int i, j;
2455 int ret;
2456
94f4e54c 2457 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
d3e51161
HS		 2458
2459 /* Initialise group */
2460 grp->name = np->name;
2461
2462 /*
2463 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2464 * do sanity check and calculate pins number
2465 */
2466 list = of_get_property(np, "rockchip,pins", &size);
2467 /* we do not check return since it's safe node passed down */
2468 size /= sizeof(*list);
2469 if (!size || size % 4) {
2470 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2471 return -EINVAL;
2472 }
2473
2474 grp->npins = size / 4;
2475
a86854d0 2476 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
d3e51161 2477 GFP_KERNEL);
a86854d0
KC		 2478 grp->data = devm_kcalloc(info->dev,
2479 grp->npins,
2480 sizeof(struct rockchip_pin_config),
d3e51161
HS		 2481 GFP_KERNEL);
2482 if (!grp->pins || !grp->data)
2483 return -ENOMEM;
2484
2485 for (i = 0, j = 0; i < size; i += 4, j++) {
2486 const __be32 *phandle;
2487 struct device_node *np_config;
2488
2489 num = be32_to_cpu(*list++);
2490 bank = bank_num_to_bank(info, num);
2491 if (IS_ERR(bank))
2492 return PTR_ERR(bank);
2493
2494 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2495 grp->data[j].func = be32_to_cpu(*list++);
2496
2497 phandle = list++;
2498 if (!phandle)
2499 return -EINVAL;
2500
2501 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
dd4d01f7 2502 ret = pinconf_generic_parse_dt_config(np_config, NULL,
d3e51161
HS		 2503 &grp->data[j].configs, &grp->data[j].nconfigs);
2504 if (ret)
2505 return ret;
2506 }
2507
2508 return 0;
2509}
2510
2511static int rockchip_pinctrl_parse_functions(struct device_node *np,
2512 struct rockchip_pinctrl *info,
2513 u32 index)
2514{
2515 struct device_node *child;
2516 struct rockchip_pmx_func *func;
2517 struct rockchip_pin_group *grp;
2518 int ret;
2519 static u32 grp_index;
2520 u32 i = 0;
2521
94f4e54c 2522 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
d3e51161
HS		 2523
2524 func = &info->functions[index];
2525
2526 /* Initialise function */
2527 func->name = np->name;
2528 func->ngroups = of_get_child_count(np);
2529 if (func->ngroups <= 0)
2530 return 0;
2531
a86854d0
KC		 2532 func->groups = devm_kcalloc(info->dev,
2533 func->ngroups, sizeof(char *), GFP_KERNEL);
d3e51161
HS		 2534 if (!func->groups)
2535 return -ENOMEM;
2536
2537 for_each_child_of_node(np, child) {
2538 func->groups[i] = child->name;
2539 grp = &info->groups[grp_index++];
2540 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
f7a81b7f
JL		 2541 if (ret) {
2542 of_node_put(child);
d3e51161 2543 return ret;
f7a81b7f 2544 }
d3e51161
HS		 2545 }
2546
2547 return 0;
2548}
2549
2550static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2551 struct rockchip_pinctrl *info)
2552{
2553 struct device *dev = &pdev->dev;
2554 struct device_node *np = dev->of_node;
2555 struct device_node *child;
2556 int ret;
2557 int i;
2558
2559 rockchip_pinctrl_child_count(info, np);
2560
2561 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2562 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2563
a86854d0
KC		 2564 info->functions = devm_kcalloc(dev,
2565 info->nfunctions,
d3e51161
HS		 2566 sizeof(struct rockchip_pmx_func),
2567 GFP_KERNEL);
98c8ee73 2568 if (!info->functions)
d3e51161 2569 return -EINVAL;
d3e51161 2570
a86854d0
KC		 2571 info->groups = devm_kcalloc(dev,
2572 info->ngroups,
d3e51161
HS		 2573 sizeof(struct rockchip_pin_group),
2574 GFP_KERNEL);
98c8ee73 2575 if (!info->groups)
d3e51161 2576 return -EINVAL;
d3e51161
HS		 2577
2578 i = 0;
2579
2580 for_each_child_of_node(np, child) {
65fca613 2581 if (of_match_node(rockchip_bank_match, child))
d3e51161 2582 continue;
65fca613 2583
d3e51161
HS		 2584 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2585 if (ret) {
2586 dev_err(&pdev->dev, "failed to parse function\n");
f7a81b7f 2587 of_node_put(child);
d3e51161
HS		 2588 return ret;
2589 }
2590 }
2591
2592 return 0;
2593}
2594
2595static int rockchip_pinctrl_register(struct platform_device *pdev,
2596 struct rockchip_pinctrl *info)
2597{
2598 struct pinctrl_desc *ctrldesc = &info->pctl;
2599 struct pinctrl_pin_desc *pindesc, *pdesc;
2600 struct rockchip_pin_bank *pin_bank;
2601 int pin, bank, ret;
2602 int k;
2603
2604 ctrldesc->name = "rockchip-pinctrl";
2605 ctrldesc->owner = THIS_MODULE;
2606 ctrldesc->pctlops = &rockchip_pctrl_ops;
2607 ctrldesc->pmxops = &rockchip_pmx_ops;
2608 ctrldesc->confops = &rockchip_pinconf_ops;
2609
a86854d0
KC		 2610 pindesc = devm_kcalloc(&pdev->dev,
2611 info->ctrl->nr_pins, sizeof(*pindesc),
2612 GFP_KERNEL);
98c8ee73 2613 if (!pindesc)
d3e51161 2614 return -ENOMEM;
98c8ee73 2615
d3e51161
HS		 2616 ctrldesc->pins = pindesc;
2617 ctrldesc->npins = info->ctrl->nr_pins;
2618
2619 pdesc = pindesc;
2620 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2621 pin_bank = &info->ctrl->pin_banks[bank];
2622 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2623 pdesc->number = k;
2624 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2625 pin_bank->name, pin);
2626 pdesc++;
2627 }
2628 }
2629
0fb7dcb1
DA		 2630 ret = rockchip_pinctrl_parse_dt(pdev, info);
2631 if (ret)
2632 return ret;
2633
0085a2b4 2634 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
323de9ef 2635 if (IS_ERR(info->pctl_dev)) {
d3e51161 2636 dev_err(&pdev->dev, "could not register pinctrl driver\n");
323de9ef 2637 return PTR_ERR(info->pctl_dev);
d3e51161
HS		 2638 }
2639
2640 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2641 pin_bank = &info->ctrl->pin_banks[bank];
2642 pin_bank->grange.name = pin_bank->name;
2643 pin_bank->grange.id = bank;
2644 pin_bank->grange.pin_base = pin_bank->pin_base;
2645 pin_bank->grange.base = pin_bank->gpio_chip.base;
2646 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2647 pin_bank->grange.gc = &pin_bank->gpio_chip;
2648 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2649 }
2650
d3e51161
HS		 2651 return 0;
2652}
2653
2654/*
2655 * GPIO handling
2656 */
2657
2658static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2659{
03bf81f1 2660 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2661 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2662 unsigned long flags;
2663 u32 data;
2664
07a06ae9 2665 clk_enable(bank->clk);
70b7aa7a 2666 raw_spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 2667
2668 data = readl(reg);
2669 data &= ~BIT(offset);
2670 if (value)
2671 data |= BIT(offset);
2672 writel(data, reg);
2673
70b7aa7a 2674 raw_spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 2675 clk_disable(bank->clk);
d3e51161
HS		 2676}
2677
2678/*
2679 * Returns the level of the pin for input direction and setting of the DR
2680 * register for output gpios.
2681 */
2682static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2683{
03bf81f1 2684 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2685 u32 data;
2686
07a06ae9 2687 clk_enable(bank->clk);
d3e51161 2688 data = readl(bank->reg_base + GPIO_EXT_PORT);
07a06ae9 2689 clk_disable(bank->clk);
d3e51161
HS		 2690 data >>= offset;
2691 data &= 1;
2692 return data;
2693}
2694
2695/*
2696 * gpiolib gpio_direction_input callback function. The setting of the pin
85dc397a 2697 * mux function as 'gpio input' will be handled by the pinctrl subsystem
d3e51161
HS		 2698 * interface.
2699 */
2700static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2701{
2702 return pinctrl_gpio_direction_input(gc->base + offset);
2703}
2704
2705/*
2706 * gpiolib gpio_direction_output callback function. The setting of the pin
85dc397a 2707 * mux function as 'gpio output' will be handled by the pinctrl subsystem
d3e51161
HS		 2708 * interface.
2709 */
2710static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2711 unsigned offset, int value)
2712{
2713 rockchip_gpio_set(gc, offset, value);
2714 return pinctrl_gpio_direction_output(gc->base + offset);
2715}
2716
b97038af
SL		 2717static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2718 unsigned int offset, bool enable)
2719{
2720 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2721 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2722 unsigned long flags;
2723 u32 data;
2724
2725 clk_enable(bank->clk);
2726 raw_spin_lock_irqsave(&bank->slock, flags);
2727
2728 data = readl(reg);
2729 if (enable)
2730 data |= BIT(offset);
2731 else
2732 data &= ~BIT(offset);
2733 writel(data, reg);
2734
2735 raw_spin_unlock_irqrestore(&bank->slock, flags);
2736 clk_disable(bank->clk);
2737}
2738
2739/*
2740 * gpiolib set_config callback function. The setting of the pin
2741 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2742 * interface.
2743 */
2744static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2745 unsigned long config)
2746{
2747 enum pin_config_param param = pinconf_to_config_param(config);
2748
2749 switch (param) {
2750 case PIN_CONFIG_INPUT_DEBOUNCE:
2751 rockchip_gpio_set_debounce(gc, offset, true);
2752 /*
2753 * Rockchip's gpio could only support up to one period
2754 * of the debounce clock(pclk), which is far away from
2755 * satisftying the requirement, as pclk is usually near
2756 * 100MHz shared by all peripherals. So the fact is it
2757 * has crippled debounce capability could only be useful
2758 * to prevent any spurious glitches from waking up the system
2759 * if the gpio is conguired as wakeup interrupt source. Let's
2760 * still return -ENOTSUPP as before, to make sure the caller
2761 * of gpiod_set_debounce won't change its behaviour.
2762 */
2763 default:
2764 return -ENOTSUPP;
2765 }
2766}
2767
d3e51161
HS		 2768/*
2769 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2770 * and a virtual IRQ, if not already present.
2771 */
2772static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2773{
03bf81f1 2774 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2775 unsigned int virq;
2776
2777 if (!bank->domain)
2778 return -ENXIO;
2779
2780 virq = irq_create_mapping(bank->domain, offset);
2781
2782 return (virq) ? : -ENXIO;
2783}
2784
2785static const struct gpio_chip rockchip_gpiolib_chip = {
98c85d58
JG		 2786 .request = gpiochip_generic_request,
2787 .free = gpiochip_generic_free,
d3e51161
HS		 2788 .set = rockchip_gpio_set,
2789 .get = rockchip_gpio_get,
6ba20a00 2790 .get_direction = rockchip_gpio_get_direction,
d3e51161
HS		 2791 .direction_input = rockchip_gpio_direction_input,
2792 .direction_output = rockchip_gpio_direction_output,
b97038af 2793 .set_config = rockchip_gpio_set_config,
d3e51161
HS		 2794 .to_irq = rockchip_gpio_to_irq,
2795 .owner = THIS_MODULE,
2796};
2797
2798/*
2799 * Interrupt handling
2800 */
2801
bd0b9ac4 2802static void rockchip_irq_demux(struct irq_desc *desc)
d3e51161 2803{
5663bb27
JL		 2804 struct irq_chip *chip = irq_desc_get_chip(desc);
2805 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
d3e51161
HS		 2806 u32 pend;
2807
2808 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2809
2810 chained_irq_enter(chip, desc);
2811
2812 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2813
2814 while (pend) {
415f748c 2815 unsigned int irq, virq;
d3e51161
HS		 2816
2817 irq = __ffs(pend);
2818 pend &= ~BIT(irq);
2819 virq = irq_linear_revmap(bank->domain, irq);
2820
2821 if (!virq) {
2822 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2823 continue;
2824 }
2825
2826 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2827
5a927501
HS		 2828 /*
2829 * Triggering IRQ on both rising and falling edge
2830 * needs manual intervention.
2831 */
2832 if (bank->toggle_edge_mode & BIT(irq)) {
53b1bfc7
DA		 2833 u32 data, data_old, polarity;
2834 unsigned long flags;
2835
2836 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2837 do {
70b7aa7a 2838 raw_spin_lock_irqsave(&bank->slock, flags);
53b1bfc7
DA		 2839
2840 polarity = readl_relaxed(bank->reg_base +
2841 GPIO_INT_POLARITY);
2842 if (data & BIT(irq))
2843 polarity &= ~BIT(irq);
2844 else
2845 polarity |= BIT(irq);
2846 writel(polarity,
2847 bank->reg_base + GPIO_INT_POLARITY);
2848
70b7aa7a 2849 raw_spin_unlock_irqrestore(&bank->slock, flags);
53b1bfc7
DA		 2850
2851 data_old = data;
2852 data = readl_relaxed(bank->reg_base +
2853 GPIO_EXT_PORT);
2854 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
5a927501
HS		 2855 }
2856
d3e51161
HS		 2857 generic_handle_irq(virq);
2858 }
2859
2860 chained_irq_exit(chip, desc);
2861}
2862
2863static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2864{
2865 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2866 struct rockchip_pin_bank *bank = gc->private;
2867 u32 mask = BIT(d->hwirq);
2868 u32 polarity;
2869 u32 level;
2870 u32 data;
fab262f5 2871 unsigned long flags;
14797189 2872 int ret;
d3e51161 2873
5a927501 2874 /* make sure the pin is configured as gpio input */
1d80df93 2875 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
14797189
HS		 2876 if (ret < 0)
2877 return ret;
2878
1d80df93 2879 clk_enable(bank->clk);
70b7aa7a 2880 raw_spin_lock_irqsave(&bank->slock, flags);
fab262f5 2881
5a927501
HS		 2882 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2883 data &= ~mask;
2884 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2885
70b7aa7a 2886 raw_spin_unlock_irqrestore(&bank->slock, flags);
fab262f5 2887
d3e51161 2888 if (type & IRQ_TYPE_EDGE_BOTH)
2dbf1bc5 2889 irq_set_handler_locked(d, handle_edge_irq);
d3e51161 2890 else
2dbf1bc5 2891 irq_set_handler_locked(d, handle_level_irq);
d3e51161 2892
70b7aa7a 2893 raw_spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 2894 irq_gc_lock(gc);
2895
2896 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2897 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2898
2899 switch (type) {
5a927501
HS		 2900 case IRQ_TYPE_EDGE_BOTH:
2901 bank->toggle_edge_mode |= mask;
2902 level |= mask;
2903
2904 /*
2905 * Determine gpio state. If 1 next interrupt should be falling
2906 * otherwise rising.
2907 */
2908 data = readl(bank->reg_base + GPIO_EXT_PORT);
2909 if (data & mask)
2910 polarity &= ~mask;
2911 else
2912 polarity |= mask;
2913 break;
d3e51161 2914 case IRQ_TYPE_EDGE_RISING:
5a927501 2915 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2916 level |= mask;
2917 polarity |= mask;
2918 break;
2919 case IRQ_TYPE_EDGE_FALLING:
5a927501 2920 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2921 level |= mask;
2922 polarity &= ~mask;
2923 break;
2924 case IRQ_TYPE_LEVEL_HIGH:
5a927501 2925 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2926 level &= ~mask;
2927 polarity |= mask;
2928 break;
2929 case IRQ_TYPE_LEVEL_LOW:
5a927501 2930 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2931 level &= ~mask;
2932 polarity &= ~mask;
2933 break;
2934 default:
7cc5f970 2935 irq_gc_unlock(gc);
70b7aa7a 2936 raw_spin_unlock_irqrestore(&bank->slock, flags);
1d80df93 2937 clk_disable(bank->clk);
d3e51161
HS		 2938 return -EINVAL;
2939 }
2940
2941 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2942 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2943
2944 irq_gc_unlock(gc);
70b7aa7a 2945 raw_spin_unlock_irqrestore(&bank->slock, flags);
1d80df93 2946 clk_disable(bank->clk);
d3e51161 2947
d3e51161
HS		 2948 return 0;
2949}
2950
68bda47c
DA		 2951static void rockchip_irq_suspend(struct irq_data *d)
2952{
2953 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2954 struct rockchip_pin_bank *bank = gc->private;
2955
07a06ae9 2956 clk_enable(bank->clk);
5ae0c7ad
DA		 2957 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2958 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
07a06ae9 2959 clk_disable(bank->clk);
68bda47c
DA		 2960}
2961
2962static void rockchip_irq_resume(struct irq_data *d)
2963{
2964 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2965 struct rockchip_pin_bank *bank = gc->private;
2966
07a06ae9 2967 clk_enable(bank->clk);
5ae0c7ad 2968 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
07a06ae9
LH		 2969 clk_disable(bank->clk);
2970}
2971
d468289a 2972static void rockchip_irq_enable(struct irq_data *d)
07a06ae9
LH		 2973{
2974 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2975 struct rockchip_pin_bank *bank = gc->private;
2976
2977 clk_enable(bank->clk);
2978 irq_gc_mask_clr_bit(d);
2979}
2980
d468289a 2981static void rockchip_irq_disable(struct irq_data *d)
07a06ae9
LH		 2982{
2983 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2984 struct rockchip_pin_bank *bank = gc->private;
2985
2986 irq_gc_mask_set_bit(d);
2987 clk_disable(bank->clk);
f2dd028c
DA		 2988}
2989
d3e51161
HS		 2990static int rockchip_interrupts_register(struct platform_device *pdev,
2991 struct rockchip_pinctrl *info)
2992{
2993 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2994 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2995 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2996 struct irq_chip_generic *gc;
2997 int ret;
07a06ae9 2998 int i, j;
d3e51161
HS		 2999
3000 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3001 if (!bank->valid) {
3002 dev_warn(&pdev->dev, "bank %s is not valid\n",
3003 bank->name);
3004 continue;
3005 }
3006
07a06ae9
LH		 3007 ret = clk_enable(bank->clk);
3008 if (ret) {
3009 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3010 bank->name);
3011 continue;
3012 }
3013
d3e51161
HS		 3014 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3015 &irq_generic_chip_ops, NULL);
3016 if (!bank->domain) {
3017 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3018 bank->name);
07a06ae9 3019 clk_disable(bank->clk);
d3e51161
HS		 3020 continue;
3021 }
3022
3023 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3024 "rockchip_gpio_irq", handle_level_irq,
3025 clr, 0, IRQ_GC_INIT_MASK_CACHE);
3026 if (ret) {
3027 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3028 bank->name);
3029 irq_domain_remove(bank->domain);
07a06ae9 3030 clk_disable(bank->clk);
d3e51161
HS		 3031 continue;
3032 }
3033
5ae0c7ad
DA		 3034 /*
3035 * Linux assumes that all interrupts start out disabled/masked.
3036 * Our driver only uses the concept of masked and always keeps
3037 * things enabled, so for us that's all masked and all enabled.
3038 */
3039 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3040 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3041
d3e51161
HS		 3042 gc = irq_get_domain_generic_chip(bank->domain, 0);
3043 gc->reg_base = bank->reg_base;
3044 gc->private = bank;
f2dd028c 3045 gc->chip_types[0].regs.mask = GPIO_INTMASK;
d3e51161
HS		 3046 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3047 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
d468289a
JC		 3048 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3049 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3050 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3051 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
d3e51161 3052 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
68bda47c
DA		 3053 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3054 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
d3e51161 3055 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
876d716b 3056 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
d3e51161 3057
03051bc2
TG		 3058 irq_set_chained_handler_and_data(bank->irq,
3059 rockchip_irq_demux, bank);
07a06ae9
LH		 3060
3061 /* map the gpio irqs here, when the clock is still running */
3062 for (j = 0 ; j < 32 ; j++)
3063 irq_create_mapping(bank->domain, j);
3064
3065 clk_disable(bank->clk);
d3e51161
HS		 3066 }
3067
3068 return 0;
3069}
3070
3071static int rockchip_gpiolib_register(struct platform_device *pdev,
3072 struct rockchip_pinctrl *info)
3073{
3074 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3075 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3076 struct gpio_chip *gc;
3077 int ret;
3078 int i;
3079
3080 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3081 if (!bank->valid) {
3082 dev_warn(&pdev->dev, "bank %s is not valid\n",
3083 bank->name);
3084 continue;
3085 }
3086
3087 bank->gpio_chip = rockchip_gpiolib_chip;
3088
3089 gc = &bank->gpio_chip;
3090 gc->base = bank->pin_base;
3091 gc->ngpio = bank->nr_pins;
58383c78 3092 gc->parent = &pdev->dev;
d3e51161
HS		 3093 gc->of_node = bank->of_node;
3094 gc->label = bank->name;
3095
03bf81f1 3096 ret = gpiochip_add_data(gc, bank);
d3e51161
HS		 3097 if (ret) {
3098 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3099 gc->label, ret);
3100 goto fail;
3101 }
3102 }
3103
3104 rockchip_interrupts_register(pdev, info);
3105
3106 return 0;
3107
3108fail:
3109 for (--i, --bank; i >= 0; --i, --bank) {
3110 if (!bank->valid)
3111 continue;
b4e7c55d 3112 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 3113 }
3114 return ret;
3115}
3116
3117static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3118 struct rockchip_pinctrl *info)
3119{
3120 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3121 struct rockchip_pin_bank *bank = ctrl->pin_banks;
d3e51161
HS		 3122 int i;
3123
b4e7c55d 3124 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
d3e51161
HS		 3125 if (!bank->valid)
3126 continue;
b4e7c55d 3127 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 3128 }
3129
b4e7c55d 3130 return 0;
d3e51161
HS		 3131}
3132
3133static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
622f3237 3134 struct rockchip_pinctrl *info)
d3e51161
HS		 3135{
3136 struct resource res;
751a99ab 3137 void __iomem *base;
d3e51161
HS		 3138
3139 if (of_address_to_resource(bank->of_node, 0, &res)) {
622f3237 3140 dev_err(info->dev, "cannot find IO resource for bank\n");
d3e51161
HS		 3141 return -ENOENT;
3142 }
3143
622f3237 3144 bank->reg_base = devm_ioremap_resource(info->dev, &res);
d3e51161
HS		 3145 if (IS_ERR(bank->reg_base))
3146 return PTR_ERR(bank->reg_base);
3147
6ca5274d
HS		 3148 /*
3149 * special case, where parts of the pull setting-registers are
3150 * part of the PMU register space
3151 */
3152 if (of_device_is_compatible(bank->of_node,
3153 "rockchip,rk3188-gpio-bank0")) {
a658efaa 3154 struct device_node *node;
bfc7a42a 3155
a658efaa
HS		 3156 node = of_parse_phandle(bank->of_node->parent,
3157 "rockchip,pmu", 0);
3158 if (!node) {
3159 if (of_address_to_resource(bank->of_node, 1, &res)) {
3160 dev_err(info->dev, "cannot find IO resource for bank\n");
3161 return -ENOENT;
3162 }
3163
3164 base = devm_ioremap_resource(info->dev, &res);
3165 if (IS_ERR(base))
3166 return PTR_ERR(base);
3167 rockchip_regmap_config.max_register =
3168 resource_size(&res) - 4;
3169 rockchip_regmap_config.name =
3170 "rockchip,rk3188-gpio-bank0-pull";
3171 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3172 base,
3173 &rockchip_regmap_config);
6ca5274d 3174 }
6ca5274d 3175 }
65fca613 3176
d3e51161
HS		 3177 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3178
3179 bank->clk = of_clk_get(bank->of_node, 0);
3180 if (IS_ERR(bank->clk))
3181 return PTR_ERR(bank->clk);
3182
07a06ae9 3183 return clk_prepare(bank->clk);
d3e51161
HS		 3184}
3185
3186static const struct of_device_id rockchip_pinctrl_dt_match[];
3187
3188/* retrieve the soc specific data */
3189static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3190 struct rockchip_pinctrl *d,
3191 struct platform_device *pdev)
3192{
3193 const struct of_device_id *match;
3194 struct device_node *node = pdev->dev.of_node;
3195 struct device_node *np;
3196 struct rockchip_pin_ctrl *ctrl;
3197 struct rockchip_pin_bank *bank;
b6c23275 3198 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
d3e51161
HS		 3199
3200 match = of_match_node(rockchip_pinctrl_dt_match, node);
3201 ctrl = (struct rockchip_pin_ctrl *)match->data;
3202
3203 for_each_child_of_node(node, np) {
3204 if (!of_find_property(np, "gpio-controller", NULL))
3205 continue;
3206
3207 bank = ctrl->pin_banks;
3208 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3209 if (!strcmp(bank->name, np->name)) {
3210 bank->of_node = np;
3211
622f3237 3212 if (!rockchip_get_bank_data(bank, d))
d3e51161
HS		 3213 bank->valid = true;
3214
3215 break;
3216 }
3217 }
3218 }
3219
95ec8ae4
HS		 3220 grf_offs = ctrl->grf_mux_offset;
3221 pmu_offs = ctrl->pmu_mux_offset;
b6c23275
DW		 3222 drv_pmu_offs = ctrl->pmu_drv_offset;
3223 drv_grf_offs = ctrl->grf_drv_offset;
d3e51161
HS		 3224 bank = ctrl->pin_banks;
3225 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
6bc0d121
HS		 3226 int bank_pins = 0;
3227
70b7aa7a 3228 raw_spin_lock_init(&bank->slock);
d3e51161
HS		 3229 bank->drvdata = d;
3230 bank->pin_base = ctrl->nr_pins;
3231 ctrl->nr_pins += bank->nr_pins;
6bc0d121 3232
b6c23275 3233 /* calculate iomux and drv offsets */
6bc0d121
HS		 3234 for (j = 0; j < 4; j++) {
3235 struct rockchip_iomux *iom = &bank->iomux[j];
b6c23275 3236 struct rockchip_drv *drv = &bank->drv[j];
03716e1d 3237 int inc;
6bc0d121
HS		 3238
3239 if (bank_pins >= bank->nr_pins)
3240 break;
3241
b6c23275 3242 /* preset iomux offset value, set new start value */
6bc0d121 3243 if (iom->offset >= 0) {
95ec8ae4
HS		 3244 if (iom->type & IOMUX_SOURCE_PMU)
3245 pmu_offs = iom->offset;
3246 else
3247 grf_offs = iom->offset;
b6c23275 3248 } else { /* set current iomux offset */
95ec8ae4
HS		 3249 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3250 pmu_offs : grf_offs;
6bc0d121
HS		 3251 }
3252
b6c23275
DW		 3253 /* preset drv offset value, set new start value */
3254 if (drv->offset >= 0) {
3255 if (iom->type & IOMUX_SOURCE_PMU)
3256 drv_pmu_offs = drv->offset;
3257 else
3258 drv_grf_offs = drv->offset;
3259 } else { /* set current drv offset */
3260 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3261 drv_pmu_offs : drv_grf_offs;
3262 }
3263
3264 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3265 i, j, iom->offset, drv->offset);
6bc0d121
HS		 3266
3267 /*
3268 * Increase offset according to iomux width.
03716e1d 3269 * 4bit iomux'es are spread over two registers.
6bc0d121 3270 */
8b6c6f93 3271 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3272 IOMUX_WIDTH_3BIT)) ? 8 : 4;
95ec8ae4
HS		 3273 if (iom->type & IOMUX_SOURCE_PMU)
3274 pmu_offs += inc;
3275 else
3276 grf_offs += inc;
6bc0d121 3277
b6c23275
DW		 3278 /*
3279 * Increase offset according to drv width.
3280 * 3bit drive-strenth'es are spread over two registers.
3281 */
3282 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3283 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3284 inc = 8;
3285 else
3286 inc = 4;
3287
3288 if (iom->type & IOMUX_SOURCE_PMU)
3289 drv_pmu_offs += inc;
3290 else
3291 drv_grf_offs += inc;
3292
6bc0d121
HS		 3293 bank_pins += 8;
3294 }
bd35b9bf 3295
c04c3fa6
DW		 3296 /* calculate the per-bank recalced_mask */
3297 for (j = 0; j < ctrl->niomux_recalced; j++) {
3298 int pin = 0;
3299
3300 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3301 pin = ctrl->iomux_recalced[j].pin;
3302 bank->recalced_mask |= BIT(pin);
3303 }
3304 }
3305
bd35b9bf
DW		 3306 /* calculate the per-bank route_mask */
3307 for (j = 0; j < ctrl->niomux_routes; j++) {
3308 int pin = 0;
3309
3310 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3311 pin = ctrl->iomux_routes[j].pin;
3312 bank->route_mask |= BIT(pin);
3313 }
3314 }
d3e51161
HS		 3315 }
3316
3317 return ctrl;
3318}
3319
8dca9331
CZ		 3320#define RK3288_GRF_GPIO6C_IOMUX 0x64
3321#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3322
3323static u32 rk3288_grf_gpio6c_iomux;
3324
9198f509
CZ		 3325static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3326{
3327 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 3328 int ret = pinctrl_force_sleep(info->pctl_dev);
3329
3330 if (ret)
3331 return ret;
3332
3333 /*
3334 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3335 * the setting here, and restore it at resume.
3336 */
3337 if (info->ctrl->type == RK3288) {
3338 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3339 &rk3288_grf_gpio6c_iomux);
3340 if (ret) {
3341 pinctrl_force_default(info->pctl_dev);
3342 return ret;
3343 }
3344 }
9198f509 3345
8dca9331 3346 return 0;
9198f509
CZ		 3347}
3348
3349static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3350{
3351 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 3352 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3353 rk3288_grf_gpio6c_iomux |
3354 GPIO6C6_SEL_WRITE_ENABLE);
3355
3356 if (ret)
3357 return ret;
9198f509
CZ		 3358
3359 return pinctrl_force_default(info->pctl_dev);
3360}
3361
3362static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3363 rockchip_pinctrl_resume);
3364
d3e51161
HS		 3365static int rockchip_pinctrl_probe(struct platform_device *pdev)
3366{
3367 struct rockchip_pinctrl *info;
3368 struct device *dev = &pdev->dev;
3369 struct rockchip_pin_ctrl *ctrl;
14dee867 3370 struct device_node *np = pdev->dev.of_node, *node;
d3e51161 3371 struct resource *res;
751a99ab 3372 void __iomem *base;
d3e51161
HS		 3373 int ret;
3374
3375 if (!dev->of_node) {
3376 dev_err(dev, "device tree node not found\n");
3377 return -ENODEV;
3378 }
3379
283b7ac9 3380 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
d3e51161
HS		 3381 if (!info)
3382 return -ENOMEM;
3383
622f3237
HS		 3384 info->dev = dev;
3385
d3e51161
HS		 3386 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3387 if (!ctrl) {
3388 dev_err(dev, "driver data not available\n");
3389 return -EINVAL;
3390 }
3391 info->ctrl = ctrl;
d3e51161 3392
1e747e59
HS		 3393 node = of_parse_phandle(np, "rockchip,grf", 0);
3394 if (node) {
3395 info->regmap_base = syscon_node_to_regmap(node);
3396 if (IS_ERR(info->regmap_base))
3397 return PTR_ERR(info->regmap_base);
3398 } else {
3399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751a99ab
HS		 3400 base = devm_ioremap_resource(&pdev->dev, res);
3401 if (IS_ERR(base))
3402 return PTR_ERR(base);
3403
3404 rockchip_regmap_config.max_register = resource_size(res) - 4;
1e747e59
HS		 3405 rockchip_regmap_config.name = "rockchip,pinctrl";
3406 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3407 &rockchip_regmap_config);
3408
3409 /* to check for the old dt-bindings */
3410 info->reg_size = resource_size(res);
3411
3412 /* Honor the old binding, with pull registers as 2nd resource */
3413 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3414 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3415 base = devm_ioremap_resource(&pdev->dev, res);
3416 if (IS_ERR(base))
3417 return PTR_ERR(base);
3418
3419 rockchip_regmap_config.max_register =
3420 resource_size(res) - 4;
3421 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3422 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3423 base,
3424 &rockchip_regmap_config);
3425 }
6ca5274d
HS		 3426 }
3427
14dee867
HS		 3428 /* try to find the optional reference to the pmu syscon */
3429 node = of_parse_phandle(np, "rockchip,pmu", 0);
3430 if (node) {
3431 info->regmap_pmu = syscon_node_to_regmap(node);
3432 if (IS_ERR(info->regmap_pmu))
3433 return PTR_ERR(info->regmap_pmu);
3434 }
3435
d3e51161
HS		 3436 ret = rockchip_gpiolib_register(pdev, info);
3437 if (ret)
3438 return ret;
3439
3440 ret = rockchip_pinctrl_register(pdev, info);
3441 if (ret) {
3442 rockchip_gpiolib_unregister(pdev, info);
3443 return ret;
3444 }
3445
3446 platform_set_drvdata(pdev, info);
3447
3448 return 0;
3449}
3450
87065ca9
DW		 3451static struct rockchip_pin_bank px30_pin_banks[] = {
3452 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3453 IOMUX_SOURCE_PMU,
3454 IOMUX_SOURCE_PMU,
3455 IOMUX_SOURCE_PMU
3456 ),
3457 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3458 IOMUX_WIDTH_4BIT,
3459 IOMUX_WIDTH_4BIT,
3460 IOMUX_WIDTH_4BIT
3461 ),
3462 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3463 IOMUX_WIDTH_4BIT,
3464 IOMUX_WIDTH_4BIT,
3465 IOMUX_WIDTH_4BIT
3466 ),
3467 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3468 IOMUX_WIDTH_4BIT,
3469 IOMUX_WIDTH_4BIT,
3470 IOMUX_WIDTH_4BIT
3471 ),
3472};
3473
3474static struct rockchip_pin_ctrl px30_pin_ctrl = {
3475 .pin_banks = px30_pin_banks,
3476 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3477 .label = "PX30-GPIO",
3478 .type = PX30,
3479 .grf_mux_offset = 0x0,
3480 .pmu_mux_offset = 0x0,
3481 .iomux_routes = px30_mux_route_data,
3482 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3483 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3484 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3485 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3486};
3487
b9c6dcab 3488static struct rockchip_pin_bank rv1108_pin_banks[] = {
688daf23
AY		 3489 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3490 IOMUX_SOURCE_PMU,
3491 IOMUX_SOURCE_PMU,
3492 IOMUX_SOURCE_PMU),
3493 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3494 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3495 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3496};
3497
b9c6dcab
AY		 3498static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3499 .pin_banks = rv1108_pin_banks,
3500 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3501 .label = "RV1108-GPIO",
3502 .type = RV1108,
688daf23
AY		 3503 .grf_mux_offset = 0x10,
3504 .pmu_mux_offset = 0x0,
12b8f018
DW		 3505 .iomux_recalced = rv1108_mux_recalced_data,
3506 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
b9c6dcab
AY		 3507 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3508 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
5caff7ea 3509 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
688daf23
AY		 3510};
3511
d3e51161
HS		 3512static struct rockchip_pin_bank rk2928_pin_banks[] = {
3513 PIN_BANK(0, 32, "gpio0"),
3514 PIN_BANK(1, 32, "gpio1"),
3515 PIN_BANK(2, 32, "gpio2"),
3516 PIN_BANK(3, 32, "gpio3"),
3517};
3518
3519static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3520 .pin_banks = rk2928_pin_banks,
3521 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3522 .label = "RK2928-GPIO",
a282926d 3523 .type = RK2928,
95ec8ae4 3524 .grf_mux_offset = 0xa8,
a282926d 3525 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 3526};
3527
c5ce7670
XZ		 3528static struct rockchip_pin_bank rk3036_pin_banks[] = {
3529 PIN_BANK(0, 32, "gpio0"),
3530 PIN_BANK(1, 32, "gpio1"),
3531 PIN_BANK(2, 32, "gpio2"),
3532};
3533
3534static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3535 .pin_banks = rk3036_pin_banks,
3536 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3537 .label = "RK3036-GPIO",
3538 .type = RK2928,
3539 .grf_mux_offset = 0xa8,
3540 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3541};
3542
d3e51161
HS		 3543static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3544 PIN_BANK(0, 32, "gpio0"),
3545 PIN_BANK(1, 32, "gpio1"),
3546 PIN_BANK(2, 32, "gpio2"),
3547 PIN_BANK(3, 32, "gpio3"),
3548 PIN_BANK(4, 32, "gpio4"),
3549 PIN_BANK(6, 16, "gpio6"),
3550};
3551
3552static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3553 .pin_banks = rk3066a_pin_banks,
3554 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3555 .label = "RK3066a-GPIO",
a282926d 3556 .type = RK2928,
95ec8ae4 3557 .grf_mux_offset = 0xa8,
a282926d 3558 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 3559};
3560
3561static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3562 PIN_BANK(0, 32, "gpio0"),
3563 PIN_BANK(1, 32, "gpio1"),
3564 PIN_BANK(2, 32, "gpio2"),
3565 PIN_BANK(3, 32, "gpio3"),
3566};
3567
3568static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3569 .pin_banks = rk3066b_pin_banks,
3570 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3571 .label = "RK3066b-GPIO",
a282926d 3572 .type = RK3066B,
95ec8ae4 3573 .grf_mux_offset = 0x60,
d3e51161
HS		 3574};
3575
d23c66df
DW		 3576static struct rockchip_pin_bank rk3128_pin_banks[] = {
3577 PIN_BANK(0, 32, "gpio0"),
3578 PIN_BANK(1, 32, "gpio1"),
3579 PIN_BANK(2, 32, "gpio2"),
3580 PIN_BANK(3, 32, "gpio3"),
3581};
3582
3583static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3584 .pin_banks = rk3128_pin_banks,
3585 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3586 .label = "RK3128-GPIO",
3587 .type = RK3128,
3588 .grf_mux_offset = 0xa8,
3589 .iomux_recalced = rk3128_mux_recalced_data,
3590 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3591 .iomux_routes = rk3128_mux_route_data,
3592 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3593 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3594};
3595
d3e51161 3596static struct rockchip_pin_bank rk3188_pin_banks[] = {
fc72c923 3597 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
d3e51161
HS		 3598 PIN_BANK(1, 32, "gpio1"),
3599 PIN_BANK(2, 32, "gpio2"),
3600 PIN_BANK(3, 32, "gpio3"),
3601};
3602
3603static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3604 .pin_banks = rk3188_pin_banks,
3605 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3606 .label = "RK3188-GPIO",
a282926d 3607 .type = RK3188,
95ec8ae4 3608 .grf_mux_offset = 0x60,
6ca5274d 3609 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 3610};
3611
fea0fe60
JC		 3612static struct rockchip_pin_bank rk3228_pin_banks[] = {
3613 PIN_BANK(0, 32, "gpio0"),
3614 PIN_BANK(1, 32, "gpio1"),
3615 PIN_BANK(2, 32, "gpio2"),
3616 PIN_BANK(3, 32, "gpio3"),
3617};
3618
3619static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3620 .pin_banks = rk3228_pin_banks,
3621 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3622 .label = "RK3228-GPIO",
3623 .type = RK3288,
3624 .grf_mux_offset = 0x0,
d4970ee0
DW		 3625 .iomux_routes = rk3228_mux_route_data,
3626 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
fea0fe60
JC		 3627 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3628 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3629};
3630
304f077d
HS		 3631static struct rockchip_pin_bank rk3288_pin_banks[] = {
3632 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3633 IOMUX_SOURCE_PMU,
3634 IOMUX_SOURCE_PMU,
3635 IOMUX_UNROUTED
3636 ),
3637 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3638 IOMUX_UNROUTED,
3639 IOMUX_UNROUTED,
3640 0
3641 ),
3642 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3643 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3644 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3645 IOMUX_WIDTH_4BIT,
3646 0,
3647 0
3648 ),
3649 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3650 0,
3651 0,
3652 IOMUX_UNROUTED
3653 ),
3654 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3655 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3656 0,
3657 IOMUX_WIDTH_4BIT,
3658 IOMUX_UNROUTED
3659 ),
3660 PIN_BANK(8, 16, "gpio8"),
3661};
3662
3663static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3664 .pin_banks = rk3288_pin_banks,
3665 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3666 .label = "RK3288-GPIO",
66d750e1 3667 .type = RK3288,
304f077d
HS		 3668 .grf_mux_offset = 0x0,
3669 .pmu_mux_offset = 0x84,
4e96fd30
HS		 3670 .iomux_routes = rk3288_mux_route_data,
3671 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
304f077d 3672 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
ef17f69f 3673 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
304f077d
HS		 3674};
3675
3818e4a7 3676static struct rockchip_pin_bank rk3328_pin_banks[] = {
3677 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3678 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3679 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
c04c3fa6
DW		 3680 IOMUX_WIDTH_3BIT,
3681 IOMUX_WIDTH_3BIT,
3818e4a7 3682 0),
3683 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3684 IOMUX_WIDTH_3BIT,
c04c3fa6 3685 IOMUX_WIDTH_3BIT,
3818e4a7 3686 0,
3687 0),
3688};
3689
3690static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3691 .pin_banks = rk3328_pin_banks,
3692 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3693 .label = "RK3328-GPIO",
3694 .type = RK3288,
3695 .grf_mux_offset = 0x0,
c04c3fa6
DW		 3696 .iomux_recalced = rk3328_mux_recalced_data,
3697 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
cedc964a
DW		 3698 .iomux_routes = rk3328_mux_route_data,
3699 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3818e4a7 3700 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3701 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
728d3f5a 3702 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3818e4a7 3703};
3704
daecdc66
HS		 3705static struct rockchip_pin_bank rk3368_pin_banks[] = {
3706 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3707 IOMUX_SOURCE_PMU,
3708 IOMUX_SOURCE_PMU,
3709 IOMUX_SOURCE_PMU
3710 ),
3711 PIN_BANK(1, 32, "gpio1"),
3712 PIN_BANK(2, 32, "gpio2"),
3713 PIN_BANK(3, 32, "gpio3"),
3714};
3715
3716static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3717 .pin_banks = rk3368_pin_banks,
3718 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3719 .label = "RK3368-GPIO",
3720 .type = RK3368,
3721 .grf_mux_offset = 0x0,
3722 .pmu_mux_offset = 0x0,
3723 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3724 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3725};
3726
b6c23275 3727static struct rockchip_pin_bank rk3399_pin_banks[] = {
3ba6767a
DW		 3728 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3729 IOMUX_SOURCE_PMU,
3730 IOMUX_SOURCE_PMU,
3731 IOMUX_SOURCE_PMU,
3732 IOMUX_SOURCE_PMU,
3733 DRV_TYPE_IO_1V8_ONLY,
3734 DRV_TYPE_IO_1V8_ONLY,
3735 DRV_TYPE_IO_DEFAULT,
3736 DRV_TYPE_IO_DEFAULT,
c437f65c
DW		 3737 0x80,
3738 0x88,
3ba6767a
DW		 3739 -1,
3740 -1,
3741 PULL_TYPE_IO_1V8_ONLY,
3742 PULL_TYPE_IO_1V8_ONLY,
3743 PULL_TYPE_IO_DEFAULT,
3744 PULL_TYPE_IO_DEFAULT
3745 ),
b6c23275
DW		 3746 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3747 IOMUX_SOURCE_PMU,
3748 IOMUX_SOURCE_PMU,
3749 IOMUX_SOURCE_PMU,
3750 DRV_TYPE_IO_1V8_OR_3V0,
3751 DRV_TYPE_IO_1V8_OR_3V0,
3752 DRV_TYPE_IO_1V8_OR_3V0,
3753 DRV_TYPE_IO_1V8_OR_3V0,
c437f65c
DW		 3754 0xa0,
3755 0xa8,
3756 0xb0,
3757 0xb8
b6c23275 3758 ),
3ba6767a
DW		 3759 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3760 DRV_TYPE_IO_1V8_OR_3V0,
3761 DRV_TYPE_IO_1V8_ONLY,
3762 DRV_TYPE_IO_1V8_ONLY,
3763 PULL_TYPE_IO_DEFAULT,
3764 PULL_TYPE_IO_DEFAULT,
3765 PULL_TYPE_IO_1V8_ONLY,
3766 PULL_TYPE_IO_1V8_ONLY
3767 ),
b6c23275
DW		 3768 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3769 DRV_TYPE_IO_3V3_ONLY,
3770 DRV_TYPE_IO_3V3_ONLY,
3771 DRV_TYPE_IO_1V8_OR_3V0
3772 ),
3773 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3774 DRV_TYPE_IO_1V8_3V0_AUTO,
3775 DRV_TYPE_IO_1V8_OR_3V0,
3776 DRV_TYPE_IO_1V8_OR_3V0
3777 ),
3778};
3779
3780static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3781 .pin_banks = rk3399_pin_banks,
3782 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3783 .label = "RK3399-GPIO",
3784 .type = RK3399,
3785 .grf_mux_offset = 0xe000,
3786 .pmu_mux_offset = 0x0,
3787 .grf_drv_offset = 0xe100,
3788 .pmu_drv_offset = 0x80,
accc1ce7
DW		 3789 .iomux_routes = rk3399_mux_route_data,
3790 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
b6c23275
DW		 3791 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3792 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3793};
daecdc66 3794
d3e51161 3795static const struct of_device_id rockchip_pinctrl_dt_match[] = {
87065ca9
DW		 3796 { .compatible = "rockchip,px30-pinctrl",
3797 .data = &px30_pin_ctrl },
b9c6dcab 3798 { .compatible = "rockchip,rv1108-pinctrl",
cdbbd26f 3799 .data = &rv1108_pin_ctrl },
d3e51161 3800 { .compatible = "rockchip,rk2928-pinctrl",
cdbbd26f 3801 .data = &rk2928_pin_ctrl },
c5ce7670 3802 { .compatible = "rockchip,rk3036-pinctrl",
cdbbd26f 3803 .data = &rk3036_pin_ctrl },
d3e51161 3804 { .compatible = "rockchip,rk3066a-pinctrl",
cdbbd26f 3805 .data = &rk3066a_pin_ctrl },
d3e51161 3806 { .compatible = "rockchip,rk3066b-pinctrl",
cdbbd26f 3807 .data = &rk3066b_pin_ctrl },
d23c66df
DW		 3808 { .compatible = "rockchip,rk3128-pinctrl",
3809 .data = (void *)&rk3128_pin_ctrl },
d3e51161 3810 { .compatible = "rockchip,rk3188-pinctrl",
cdbbd26f 3811 .data = &rk3188_pin_ctrl },
fea0fe60 3812 { .compatible = "rockchip,rk3228-pinctrl",
cdbbd26f 3813 .data = &rk3228_pin_ctrl },
304f077d 3814 { .compatible = "rockchip,rk3288-pinctrl",
cdbbd26f 3815 .data = &rk3288_pin_ctrl },
3818e4a7 3816 { .compatible = "rockchip,rk3328-pinctrl",
cdbbd26f 3817 .data = &rk3328_pin_ctrl },
daecdc66 3818 { .compatible = "rockchip,rk3368-pinctrl",
cdbbd26f 3819 .data = &rk3368_pin_ctrl },
b6c23275 3820 { .compatible = "rockchip,rk3399-pinctrl",
cdbbd26f 3821 .data = &rk3399_pin_ctrl },
d3e51161
HS		 3822 {},
3823};
d3e51161
HS		 3824
3825static struct platform_driver rockchip_pinctrl_driver = {
3826 .probe = rockchip_pinctrl_probe,
3827 .driver = {
3828 .name = "rockchip-pinctrl",
9198f509 3829 .pm = &rockchip_pinctrl_dev_pm_ops,
0be9e70d 3830 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 3831 },
3832};
3833
3834static int __init rockchip_pinctrl_drv_register(void)
3835{
3836 return platform_driver_register(&rockchip_pinctrl_driver);
3837}
3838postcore_initcall(rockchip_pinctrl_drv_register);
Linux 6.x block layer and io_uring tree(s)