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pinctrl: rockchip: add support for 4bit wide iomux settings
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
d3e51161
HS		 1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
7e865abb 39#include <linux/clk.h>
751a99ab 40#include <linux/regmap.h>
14dee867 41#include <linux/mfd/syscon.h>
d3e51161
HS		 42#include <dt-bindings/pinctrl/rockchip.h>
43
44#include "core.h"
45#include "pinconf.h"
46
47/* GPIO control registers */
48#define GPIO_SWPORT_DR 0x00
49#define GPIO_SWPORT_DDR 0x04
50#define GPIO_INTEN 0x30
51#define GPIO_INTMASK 0x34
52#define GPIO_INTTYPE_LEVEL 0x38
53#define GPIO_INT_POLARITY 0x3c
54#define GPIO_INT_STATUS 0x40
55#define GPIO_INT_RAWSTATUS 0x44
56#define GPIO_DEBOUNCE 0x48
57#define GPIO_PORTS_EOI 0x4c
58#define GPIO_EXT_PORT 0x50
59#define GPIO_LS_SYNC 0x60
60
a282926d
HS		 61enum rockchip_pinctrl_type {
62 RK2928,
63 RK3066B,
64 RK3188,
65};
66
fc72c923
HS		 67/**
68 * Encode variants of iomux registers into a type variable
69 */
70#define IOMUX_GPIO_ONLY BIT(0)
03716e1d 71#define IOMUX_WIDTH_4BIT BIT(1)
fc72c923
HS		 72
73/**
74 * @type: iomux variant using IOMUX_* constants
6bc0d121
HS		 75 * @offset: if initialized to -1 it will be autocalculated, by specifying
76 * an initial offset value the relevant source offset can be reset
77 * to a new value for autocalculating the following iomux registers.
fc72c923
HS		 78 */
79struct rockchip_iomux {
80 int type;
6bc0d121 81 int offset;
65fca613
HS		 82};
83
d3e51161
HS		 84/**
85 * @reg_base: register base of the gpio bank
6ca5274d 86 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 87 * @clk: clock of the gpio bank
88 * @irq: interrupt of the gpio bank
89 * @pin_base: first pin number
90 * @nr_pins: number of pins in this bank
91 * @name: name of the bank
92 * @bank_num: number of the bank, to account for holes
fc72c923 93 * @iomux: array describing the 4 iomux sources of the bank
d3e51161
HS		 94 * @valid: are all necessary informations present
95 * @of_node: dt node of this bank
96 * @drvdata: common pinctrl basedata
97 * @domain: irqdomain of the gpio bank
98 * @gpio_chip: gpiolib chip
99 * @grange: gpio range
100 * @slock: spinlock for the gpio bank
101 */
102struct rockchip_pin_bank {
103 void __iomem *reg_base;
751a99ab 104 struct regmap *regmap_pull;
d3e51161
HS		 105 struct clk *clk;
106 int irq;
107 u32 pin_base;
108 u8 nr_pins;
109 char *name;
110 u8 bank_num;
fc72c923 111 struct rockchip_iomux iomux[4];
d3e51161
HS		 112 bool valid;
113 struct device_node *of_node;
114 struct rockchip_pinctrl *drvdata;
115 struct irq_domain *domain;
116 struct gpio_chip gpio_chip;
117 struct pinctrl_gpio_range grange;
118 spinlock_t slock;
5a927501 119 u32 toggle_edge_mode;
d3e51161
HS		 120};
121
122#define PIN_BANK(id, pins, label) \
123 { \
124 .bank_num = id, \
125 .nr_pins = pins, \
126 .name = label, \
6bc0d121
HS		 127 .iomux = { \
128 { .offset = -1 }, \
129 { .offset = -1 }, \
130 { .offset = -1 }, \
131 { .offset = -1 }, \
132 }, \
d3e51161
HS		 133 }
134
fc72c923
HS		 135#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
136 { \
137 .bank_num = id, \
138 .nr_pins = pins, \
139 .name = label, \
140 .iomux = { \
6bc0d121
HS		 141 { .type = iom0, .offset = -1 }, \
142 { .type = iom1, .offset = -1 }, \
143 { .type = iom2, .offset = -1 }, \
144 { .type = iom3, .offset = -1 }, \
fc72c923
HS		 145 }, \
146 }
147
d3e51161 148/**
d3e51161
HS		 149 */
150struct rockchip_pin_ctrl {
151 struct rockchip_pin_bank *pin_banks;
152 u32 nr_banks;
153 u32 nr_pins;
154 char *label;
a282926d 155 enum rockchip_pinctrl_type type;
d3e51161 156 int mux_offset;
751a99ab
HS		 157 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
158 int pin_num, struct regmap **regmap,
159 int *reg, u8 *bit);
d3e51161
HS		 160};
161
162struct rockchip_pin_config {
163 unsigned int func;
164 unsigned long *configs;
165 unsigned int nconfigs;
166};
167
168/**
169 * struct rockchip_pin_group: represent group of pins of a pinmux function.
170 * @name: name of the pin group, used to lookup the group.
171 * @pins: the pins included in this group.
172 * @npins: number of pins included in this group.
173 * @func: the mux function number to be programmed when selected.
174 * @configs: the config values to be set for each pin
175 * @nconfigs: number of configs for each pin
176 */
177struct rockchip_pin_group {
178 const char *name;
179 unsigned int npins;
180 unsigned int *pins;
181 struct rockchip_pin_config *data;
182};
183
184/**
185 * struct rockchip_pmx_func: represent a pin function.
186 * @name: name of the pin function, used to lookup the function.
187 * @groups: one or more names of pin groups that provide this function.
188 * @num_groups: number of groups included in @groups.
189 */
190struct rockchip_pmx_func {
191 const char *name;
192 const char **groups;
193 u8 ngroups;
194};
195
196struct rockchip_pinctrl {
751a99ab 197 struct regmap *regmap_base;
bfc7a42a 198 int reg_size;
751a99ab 199 struct regmap *regmap_pull;
14dee867 200 struct regmap *regmap_pmu;
d3e51161
HS		 201 struct device *dev;
202 struct rockchip_pin_ctrl *ctrl;
203 struct pinctrl_desc pctl;
204 struct pinctrl_dev *pctl_dev;
205 struct rockchip_pin_group *groups;
206 unsigned int ngroups;
207 struct rockchip_pmx_func *functions;
208 unsigned int nfunctions;
209};
210
751a99ab
HS		 211static struct regmap_config rockchip_regmap_config = {
212 .reg_bits = 32,
213 .val_bits = 32,
214 .reg_stride = 4,
215};
216
d3e51161
HS		 217static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
218{
219 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
220}
221
222static const inline struct rockchip_pin_group *pinctrl_name_to_group(
223 const struct rockchip_pinctrl *info,
224 const char *name)
225{
d3e51161
HS		 226 int i;
227
228 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 229 if (!strcmp(info->groups[i].name, name))
230 return &info->groups[i];
d3e51161
HS		 231 }
232
1cb95395 233 return NULL;
d3e51161
HS		 234}
235
236/*
237 * given a pin number that is local to a pin controller, find out the pin bank
238 * and the register base of the pin bank.
239 */
240static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
241 unsigned pin)
242{
243 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
244
51578b9b 245 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 246 b++;
247
248 return b;
249}
250
251static struct rockchip_pin_bank *bank_num_to_bank(
252 struct rockchip_pinctrl *info,
253 unsigned num)
254{
255 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
256 int i;
257
1cb95395 258 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 259 if (b->bank_num == num)
1cb95395 260 return b;
d3e51161
HS		 261 }
262
1cb95395 263 return ERR_PTR(-EINVAL);
d3e51161
HS		 264}
265
266/*
267 * Pinctrl_ops handling
268 */
269
270static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
271{
272 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
273
274 return info->ngroups;
275}
276
277static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
278 unsigned selector)
279{
280 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
281
282 return info->groups[selector].name;
283}
284
285static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
286 unsigned selector, const unsigned **pins,
287 unsigned *npins)
288{
289 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
290
291 if (selector >= info->ngroups)
292 return -EINVAL;
293
294 *pins = info->groups[selector].pins;
295 *npins = info->groups[selector].npins;
296
297 return 0;
298}
299
300static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
301 struct device_node *np,
302 struct pinctrl_map **map, unsigned *num_maps)
303{
304 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
305 const struct rockchip_pin_group *grp;
306 struct pinctrl_map *new_map;
307 struct device_node *parent;
308 int map_num = 1;
309 int i;
310
311 /*
312 * first find the group of this node and check if we need to create
313 * config maps for pins
314 */
315 grp = pinctrl_name_to_group(info, np->name);
316 if (!grp) {
317 dev_err(info->dev, "unable to find group for node %s\n",
318 np->name);
319 return -EINVAL;
320 }
321
322 map_num += grp->npins;
323 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
324 GFP_KERNEL);
325 if (!new_map)
326 return -ENOMEM;
327
328 *map = new_map;
329 *num_maps = map_num;
330
331 /* create mux map */
332 parent = of_get_parent(np);
333 if (!parent) {
334 devm_kfree(pctldev->dev, new_map);
335 return -EINVAL;
336 }
337 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
338 new_map[0].data.mux.function = parent->name;
339 new_map[0].data.mux.group = np->name;
340 of_node_put(parent);
341
342 /* create config map */
343 new_map++;
344 for (i = 0; i < grp->npins; i++) {
345 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
346 new_map[i].data.configs.group_or_pin =
347 pin_get_name(pctldev, grp->pins[i]);
348 new_map[i].data.configs.configs = grp->data[i].configs;
349 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
350 }
351
352 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
353 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
354
355 return 0;
356}
357
358static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
359 struct pinctrl_map *map, unsigned num_maps)
360{
361}
362
363static const struct pinctrl_ops rockchip_pctrl_ops = {
364 .get_groups_count = rockchip_get_groups_count,
365 .get_group_name = rockchip_get_group_name,
366 .get_group_pins = rockchip_get_group_pins,
367 .dt_node_to_map = rockchip_dt_node_to_map,
368 .dt_free_map = rockchip_dt_free_map,
369};
370
371/*
372 * Hardware access
373 */
374
a076e2ed
HS		 375static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
376{
377 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 378 int iomux_num = (pin / 8);
751a99ab 379 unsigned int val;
03716e1d 380 int reg, ret, mask;
a076e2ed
HS		 381 u8 bit;
382
fc72c923
HS		 383 if (iomux_num > 3)
384 return -EINVAL;
385
386 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
a076e2ed
HS		 387 return RK_FUNC_GPIO;
388
389 /* get basic quadrupel of mux registers and the correct reg inside */
03716e1d 390 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
6bc0d121 391 reg = bank->iomux[iomux_num].offset;
03716e1d
HS		 392 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
393 if ((pin % 8) >= 4)
394 reg += 0x4;
395 bit = (pin % 4) * 4;
396 } else {
397 bit = (pin % 8) * 2;
398 }
a076e2ed 399
751a99ab
HS		 400 ret = regmap_read(info->regmap_base, reg, &val);
401 if (ret)
402 return ret;
403
03716e1d 404 return ((val >> bit) & mask);
a076e2ed
HS		 405}
406
d3e51161
HS		 407/*
408 * Set a new mux function for a pin.
409 *
410 * The register is divided into the upper and lower 16 bit. When changing
411 * a value, the previous register value is not read and changed. Instead
412 * it seems the changed bits are marked in the upper 16 bit, while the
413 * changed value gets set in the same offset in the lower 16 bit.
414 * All pin settings seem to be 2 bit wide in both the upper and lower
415 * parts.
416 * @bank: pin bank to change
417 * @pin: pin to change
418 * @mux: new mux function to set
419 */
14797189 420static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 421{
422 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 423 int iomux_num = (pin / 8);
03716e1d 424 int reg, ret, mask;
d3e51161
HS		 425 unsigned long flags;
426 u8 bit;
427 u32 data;
428
fc72c923
HS		 429 if (iomux_num > 3)
430 return -EINVAL;
431
432 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
c4a532de
HS		 433 if (mux != RK_FUNC_GPIO) {
434 dev_err(info->dev,
435 "pin %d only supports a gpio mux\n", pin);
436 return -ENOTSUPP;
437 } else {
438 return 0;
439 }
440 }
441
d3e51161
HS		 442 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
443 bank->bank_num, pin, mux);
444
445 /* get basic quadrupel of mux registers and the correct reg inside */
03716e1d 446 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
6bc0d121 447 reg = bank->iomux[iomux_num].offset;
03716e1d
HS		 448 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
449 if ((pin % 8) >= 4)
450 reg += 0x4;
451 bit = (pin % 4) * 4;
452 } else {
453 bit = (pin % 8) * 2;
454 }
d3e51161
HS		 455
456 spin_lock_irqsave(&bank->slock, flags);
457
03716e1d
HS		 458 data = (mask << (bit + 16));
459 data |= (mux & mask) << bit;
751a99ab 460 ret = regmap_write(info->regmap_base, reg, data);
d3e51161
HS		 461
462 spin_unlock_irqrestore(&bank->slock, flags);
14797189 463
751a99ab 464 return ret;
d3e51161
HS		 465}
466
a282926d
HS		 467#define RK2928_PULL_OFFSET 0x118
468#define RK2928_PULL_PINS_PER_REG 16
469#define RK2928_PULL_BANK_STRIDE 8
470
471static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 472 int pin_num, struct regmap **regmap,
473 int *reg, u8 *bit)
a282926d
HS		 474{
475 struct rockchip_pinctrl *info = bank->drvdata;
476
751a99ab
HS		 477 *regmap = info->regmap_base;
478 *reg = RK2928_PULL_OFFSET;
a282926d
HS		 479 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
480 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
481
482 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
483};
484
bfc7a42a 485#define RK3188_PULL_OFFSET 0x164
6ca5274d
HS		 486#define RK3188_PULL_BITS_PER_PIN 2
487#define RK3188_PULL_PINS_PER_REG 8
488#define RK3188_PULL_BANK_STRIDE 16
14dee867 489#define RK3188_PULL_PMU_OFFSET 0x64
6ca5274d
HS		 490
491static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 492 int pin_num, struct regmap **regmap,
493 int *reg, u8 *bit)
6ca5274d
HS		 494{
495 struct rockchip_pinctrl *info = bank->drvdata;
496
497 /* The first 12 pins of the first bank are located elsewhere */
fc72c923 498 if (bank->bank_num == 0 && pin_num < 12) {
14dee867
HS		 499 *regmap = info->regmap_pmu ? info->regmap_pmu
500 : bank->regmap_pull;
501 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
751a99ab 502 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
6ca5274d
HS		 503 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
504 *bit *= RK3188_PULL_BITS_PER_PIN;
505 } else {
751a99ab
HS		 506 *regmap = info->regmap_pull ? info->regmap_pull
507 : info->regmap_base;
508 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
509
bfc7a42a
HS		 510 /* correct the offset, as it is the 2nd pull register */
511 *reg -= 4;
6ca5274d
HS		 512 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
513 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
514
515 /*
516 * The bits in these registers have an inverse ordering
517 * with the lowest pin being in bits 15:14 and the highest
518 * pin in bits 1:0
519 */
520 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
521 *bit *= RK3188_PULL_BITS_PER_PIN;
522 }
523}
524
d3e51161
HS		 525static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
526{
527 struct rockchip_pinctrl *info = bank->drvdata;
528 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab
HS		 529 struct regmap *regmap;
530 int reg, ret;
d3e51161 531 u8 bit;
6ca5274d 532 u32 data;
d3e51161
HS		 533
534 /* rk3066b does support any pulls */
a282926d 535 if (ctrl->type == RK3066B)
d3e51161
HS		 536 return PIN_CONFIG_BIAS_DISABLE;
537
751a99ab
HS		 538 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
539
540 ret = regmap_read(regmap, reg, &data);
541 if (ret)
542 return ret;
6ca5274d 543
a282926d
HS		 544 switch (ctrl->type) {
545 case RK2928:
751a99ab 546 return !(data & BIT(bit))
d3e51161
HS		 547 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
548 : PIN_CONFIG_BIAS_DISABLE;
a282926d 549 case RK3188:
751a99ab 550 data >>= bit;
6ca5274d
HS		 551 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
552
553 switch (data) {
554 case 0:
555 return PIN_CONFIG_BIAS_DISABLE;
556 case 1:
557 return PIN_CONFIG_BIAS_PULL_UP;
558 case 2:
559 return PIN_CONFIG_BIAS_PULL_DOWN;
560 case 3:
561 return PIN_CONFIG_BIAS_BUS_HOLD;
562 }
563
564 dev_err(info->dev, "unknown pull setting\n");
d3e51161 565 return -EIO;
a282926d
HS		 566 default:
567 dev_err(info->dev, "unsupported pinctrl type\n");
568 return -EINVAL;
569 };
d3e51161
HS		 570}
571
572static int rockchip_set_pull(struct rockchip_pin_bank *bank,
573 int pin_num, int pull)
574{
575 struct rockchip_pinctrl *info = bank->drvdata;
576 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab
HS		 577 struct regmap *regmap;
578 int reg, ret;
d3e51161
HS		 579 unsigned long flags;
580 u8 bit;
581 u32 data;
582
583 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
584 bank->bank_num, pin_num, pull);
585
586 /* rk3066b does support any pulls */
a282926d 587 if (ctrl->type == RK3066B)
d3e51161
HS		 588 return pull ? -EINVAL : 0;
589
751a99ab 590 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
6ca5274d 591
a282926d
HS		 592 switch (ctrl->type) {
593 case RK2928:
d3e51161
HS		 594 spin_lock_irqsave(&bank->slock, flags);
595
596 data = BIT(bit + 16);
597 if (pull == PIN_CONFIG_BIAS_DISABLE)
598 data |= BIT(bit);
751a99ab 599 ret = regmap_write(regmap, reg, data);
d3e51161
HS		 600
601 spin_unlock_irqrestore(&bank->slock, flags);
a282926d
HS		 602 break;
603 case RK3188:
6ca5274d
HS		 604 spin_lock_irqsave(&bank->slock, flags);
605
606 /* enable the write to the equivalent lower bits */
607 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
608
609 switch (pull) {
610 case PIN_CONFIG_BIAS_DISABLE:
611 break;
612 case PIN_CONFIG_BIAS_PULL_UP:
613 data |= (1 << bit);
614 break;
615 case PIN_CONFIG_BIAS_PULL_DOWN:
616 data |= (2 << bit);
617 break;
618 case PIN_CONFIG_BIAS_BUS_HOLD:
619 data |= (3 << bit);
620 break;
621 default:
d32c3e26 622 spin_unlock_irqrestore(&bank->slock, flags);
6ca5274d
HS		 623 dev_err(info->dev, "unsupported pull setting %d\n",
624 pull);
625 return -EINVAL;
626 }
627
751a99ab 628 ret = regmap_write(regmap, reg, data);
6ca5274d
HS		 629
630 spin_unlock_irqrestore(&bank->slock, flags);
631 break;
a282926d
HS		 632 default:
633 dev_err(info->dev, "unsupported pinctrl type\n");
634 return -EINVAL;
d3e51161
HS		 635 }
636
751a99ab 637 return ret;
d3e51161
HS		 638}
639
640/*
641 * Pinmux_ops handling
642 */
643
644static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
645{
646 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
647
648 return info->nfunctions;
649}
650
651static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
652 unsigned selector)
653{
654 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
655
656 return info->functions[selector].name;
657}
658
659static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
660 unsigned selector, const char * const **groups,
661 unsigned * const num_groups)
662{
663 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
664
665 *groups = info->functions[selector].groups;
666 *num_groups = info->functions[selector].ngroups;
667
668 return 0;
669}
670
671static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
672 unsigned group)
673{
674 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
675 const unsigned int *pins = info->groups[group].pins;
676 const struct rockchip_pin_config *data = info->groups[group].data;
677 struct rockchip_pin_bank *bank;
14797189 678 int cnt, ret = 0;
d3e51161
HS		 679
680 dev_dbg(info->dev, "enable function %s group %s\n",
681 info->functions[selector].name, info->groups[group].name);
682
683 /*
684 * for each pin in the pin group selected, program the correspoding pin
685 * pin function number in the config register.
686 */
687 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
688 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 689 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
690 data[cnt].func);
691 if (ret)
692 break;
693 }
694
695 if (ret) {
696 /* revert the already done pin settings */
697 for (cnt--; cnt >= 0; cnt--)
698 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
699
700 return ret;
d3e51161
HS		 701 }
702
703 return 0;
704}
705
d3e51161
HS		 706/*
707 * The calls to gpio_direction_output() and gpio_direction_input()
708 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
709 * function called from the gpiolib interface).
710 */
711static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
712 struct pinctrl_gpio_range *range,
713 unsigned offset, bool input)
714{
715 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
716 struct rockchip_pin_bank *bank;
717 struct gpio_chip *chip;
14797189 718 int pin, ret;
d3e51161
HS		 719 u32 data;
720
721 chip = range->gc;
722 bank = gc_to_pin_bank(chip);
723 pin = offset - chip->base;
724
725 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
726 offset, range->name, pin, input ? "input" : "output");
727
14797189
HS		 728 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
729 if (ret < 0)
730 return ret;
d3e51161
HS		 731
732 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
733 /* set bit to 1 for output, 0 for input */
734 if (!input)
735 data |= BIT(pin);
736 else
737 data &= ~BIT(pin);
738 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
739
740 return 0;
741}
742
743static const struct pinmux_ops rockchip_pmx_ops = {
744 .get_functions_count = rockchip_pmx_get_funcs_count,
745 .get_function_name = rockchip_pmx_get_func_name,
746 .get_function_groups = rockchip_pmx_get_groups,
747 .enable = rockchip_pmx_enable,
d3e51161
HS		 748 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
749};
750
751/*
752 * Pinconf_ops handling
753 */
754
44b6d930
HS		 755static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
756 enum pin_config_param pull)
757{
a282926d
HS		 758 switch (ctrl->type) {
759 case RK2928:
760 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
761 pull == PIN_CONFIG_BIAS_DISABLE);
762 case RK3066B:
44b6d930 763 return pull ? false : true;
a282926d
HS		 764 case RK3188:
765 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 766 }
767
a282926d 768 return false;
44b6d930
HS		 769}
770
a076e2ed
HS		 771static int rockchip_gpio_direction_output(struct gpio_chip *gc,
772 unsigned offset, int value);
773static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
774
d3e51161
HS		 775/* set the pin config settings for a specified pin */
776static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 777 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 778{
779 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
780 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9
SY		 781 enum pin_config_param param;
782 u16 arg;
783 int i;
784 int rc;
785
786 for (i = 0; i < num_configs; i++) {
787 param = pinconf_to_config_param(configs[i]);
788 arg = pinconf_to_config_argument(configs[i]);
789
790 switch (param) {
791 case PIN_CONFIG_BIAS_DISABLE:
792 rc = rockchip_set_pull(bank, pin - bank->pin_base,
793 param);
794 if (rc)
795 return rc;
796 break;
797 case PIN_CONFIG_BIAS_PULL_UP:
798 case PIN_CONFIG_BIAS_PULL_DOWN:
799 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 800 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 801 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
802 return -ENOTSUPP;
803
804 if (!arg)
805 return -EINVAL;
806
807 rc = rockchip_set_pull(bank, pin - bank->pin_base,
808 param);
809 if (rc)
810 return rc;
811 break;
a076e2ed
HS		 812 case PIN_CONFIG_OUTPUT:
813 rc = rockchip_gpio_direction_output(&bank->gpio_chip,
814 pin - bank->pin_base,
815 arg);
816 if (rc)
817 return rc;
818 break;
03b054e9 819 default:
44b6d930 820 return -ENOTSUPP;
03b054e9
SY		 821 break;
822 }
823 } /* for each config */
d3e51161
HS		 824
825 return 0;
826}
827
828/* get the pin config settings for a specified pin */
829static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
830 unsigned long *config)
831{
832 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
833 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
834 enum pin_config_param param = pinconf_to_config_param(*config);
dab3eba7 835 u16 arg;
a076e2ed 836 int rc;
d3e51161
HS		 837
838 switch (param) {
839 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 840 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
841 return -EINVAL;
842
dab3eba7 843 arg = 0;
44b6d930 844 break;
d3e51161
HS		 845 case PIN_CONFIG_BIAS_PULL_UP:
846 case PIN_CONFIG_BIAS_PULL_DOWN:
847 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 848 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 849 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
850 return -ENOTSUPP;
d3e51161 851
44b6d930 852 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 853 return -EINVAL;
854
dab3eba7 855 arg = 1;
d3e51161 856 break;
a076e2ed
HS		 857 case PIN_CONFIG_OUTPUT:
858 rc = rockchip_get_mux(bank, pin - bank->pin_base);
859 if (rc != RK_FUNC_GPIO)
860 return -EINVAL;
861
862 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
863 if (rc < 0)
864 return rc;
865
866 arg = rc ? 1 : 0;
867 break;
d3e51161
HS		 868 default:
869 return -ENOTSUPP;
870 break;
871 }
872
dab3eba7
HS		 873 *config = pinconf_to_config_packed(param, arg);
874
d3e51161
HS		 875 return 0;
876}
877
878static const struct pinconf_ops rockchip_pinconf_ops = {
879 .pin_config_get = rockchip_pinconf_get,
880 .pin_config_set = rockchip_pinconf_set,
881};
882
65fca613
HS		 883static const struct of_device_id rockchip_bank_match[] = {
884 { .compatible = "rockchip,gpio-bank" },
6ca5274d 885 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 886 {},
887};
d3e51161
HS		 888
889static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
890 struct device_node *np)
891{
892 struct device_node *child;
893
894 for_each_child_of_node(np, child) {
65fca613 895 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 896 continue;
897
898 info->nfunctions++;
899 info->ngroups += of_get_child_count(child);
900 }
901}
902
903static int rockchip_pinctrl_parse_groups(struct device_node *np,
904 struct rockchip_pin_group *grp,
905 struct rockchip_pinctrl *info,
906 u32 index)
907{
908 struct rockchip_pin_bank *bank;
909 int size;
910 const __be32 *list;
911 int num;
912 int i, j;
913 int ret;
914
915 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
916
917 /* Initialise group */
918 grp->name = np->name;
919
920 /*
921 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
922 * do sanity check and calculate pins number
923 */
924 list = of_get_property(np, "rockchip,pins", &size);
925 /* we do not check return since it's safe node passed down */
926 size /= sizeof(*list);
927 if (!size || size % 4) {
928 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
929 return -EINVAL;
930 }
931
932 grp->npins = size / 4;
933
934 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
935 GFP_KERNEL);
936 grp->data = devm_kzalloc(info->dev, grp->npins *
937 sizeof(struct rockchip_pin_config),
938 GFP_KERNEL);
939 if (!grp->pins || !grp->data)
940 return -ENOMEM;
941
942 for (i = 0, j = 0; i < size; i += 4, j++) {
943 const __be32 *phandle;
944 struct device_node *np_config;
945
946 num = be32_to_cpu(*list++);
947 bank = bank_num_to_bank(info, num);
948 if (IS_ERR(bank))
949 return PTR_ERR(bank);
950
951 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
952 grp->data[j].func = be32_to_cpu(*list++);
953
954 phandle = list++;
955 if (!phandle)
956 return -EINVAL;
957
958 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
959 ret = pinconf_generic_parse_dt_config(np_config,
960 &grp->data[j].configs, &grp->data[j].nconfigs);
961 if (ret)
962 return ret;
963 }
964
965 return 0;
966}
967
968static int rockchip_pinctrl_parse_functions(struct device_node *np,
969 struct rockchip_pinctrl *info,
970 u32 index)
971{
972 struct device_node *child;
973 struct rockchip_pmx_func *func;
974 struct rockchip_pin_group *grp;
975 int ret;
976 static u32 grp_index;
977 u32 i = 0;
978
979 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
980
981 func = &info->functions[index];
982
983 /* Initialise function */
984 func->name = np->name;
985 func->ngroups = of_get_child_count(np);
986 if (func->ngroups <= 0)
987 return 0;
988
989 func->groups = devm_kzalloc(info->dev,
990 func->ngroups * sizeof(char *), GFP_KERNEL);
991 if (!func->groups)
992 return -ENOMEM;
993
994 for_each_child_of_node(np, child) {
995 func->groups[i] = child->name;
996 grp = &info->groups[grp_index++];
997 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
998 if (ret)
999 return ret;
1000 }
1001
1002 return 0;
1003}
1004
1005static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1006 struct rockchip_pinctrl *info)
1007{
1008 struct device *dev = &pdev->dev;
1009 struct device_node *np = dev->of_node;
1010 struct device_node *child;
1011 int ret;
1012 int i;
1013
1014 rockchip_pinctrl_child_count(info, np);
1015
1016 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1017 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1018
1019 info->functions = devm_kzalloc(dev, info->nfunctions *
1020 sizeof(struct rockchip_pmx_func),
1021 GFP_KERNEL);
1022 if (!info->functions) {
1023 dev_err(dev, "failed to allocate memory for function list\n");
1024 return -EINVAL;
1025 }
1026
1027 info->groups = devm_kzalloc(dev, info->ngroups *
1028 sizeof(struct rockchip_pin_group),
1029 GFP_KERNEL);
1030 if (!info->groups) {
1031 dev_err(dev, "failed allocate memory for ping group list\n");
1032 return -EINVAL;
1033 }
1034
1035 i = 0;
1036
1037 for_each_child_of_node(np, child) {
65fca613 1038 if (of_match_node(rockchip_bank_match, child))
d3e51161 1039 continue;
65fca613 1040
d3e51161
HS		 1041 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1042 if (ret) {
1043 dev_err(&pdev->dev, "failed to parse function\n");
1044 return ret;
1045 }
1046 }
1047
1048 return 0;
1049}
1050
1051static int rockchip_pinctrl_register(struct platform_device *pdev,
1052 struct rockchip_pinctrl *info)
1053{
1054 struct pinctrl_desc *ctrldesc = &info->pctl;
1055 struct pinctrl_pin_desc *pindesc, *pdesc;
1056 struct rockchip_pin_bank *pin_bank;
1057 int pin, bank, ret;
1058 int k;
1059
1060 ctrldesc->name = "rockchip-pinctrl";
1061 ctrldesc->owner = THIS_MODULE;
1062 ctrldesc->pctlops = &rockchip_pctrl_ops;
1063 ctrldesc->pmxops = &rockchip_pmx_ops;
1064 ctrldesc->confops = &rockchip_pinconf_ops;
1065
1066 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1067 info->ctrl->nr_pins, GFP_KERNEL);
1068 if (!pindesc) {
1069 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1070 return -ENOMEM;
1071 }
1072 ctrldesc->pins = pindesc;
1073 ctrldesc->npins = info->ctrl->nr_pins;
1074
1075 pdesc = pindesc;
1076 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1077 pin_bank = &info->ctrl->pin_banks[bank];
1078 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1079 pdesc->number = k;
1080 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1081 pin_bank->name, pin);
1082 pdesc++;
1083 }
1084 }
1085
1086 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1087 if (!info->pctl_dev) {
1088 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1089 return -EINVAL;
1090 }
1091
1092 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1093 pin_bank = &info->ctrl->pin_banks[bank];
1094 pin_bank->grange.name = pin_bank->name;
1095 pin_bank->grange.id = bank;
1096 pin_bank->grange.pin_base = pin_bank->pin_base;
1097 pin_bank->grange.base = pin_bank->gpio_chip.base;
1098 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1099 pin_bank->grange.gc = &pin_bank->gpio_chip;
1100 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1101 }
1102
1103 ret = rockchip_pinctrl_parse_dt(pdev, info);
1104 if (ret) {
1105 pinctrl_unregister(info->pctl_dev);
1106 return ret;
1107 }
1108
1109 return 0;
1110}
1111
1112/*
1113 * GPIO handling
1114 */
1115
0351c287
AL		 1116static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1117{
1118 return pinctrl_request_gpio(chip->base + offset);
1119}
1120
1121static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1122{
1123 pinctrl_free_gpio(chip->base + offset);
1124}
1125
d3e51161
HS		 1126static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1127{
1128 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1129 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1130 unsigned long flags;
1131 u32 data;
1132
1133 spin_lock_irqsave(&bank->slock, flags);
1134
1135 data = readl(reg);
1136 data &= ~BIT(offset);
1137 if (value)
1138 data |= BIT(offset);
1139 writel(data, reg);
1140
1141 spin_unlock_irqrestore(&bank->slock, flags);
1142}
1143
1144/*
1145 * Returns the level of the pin for input direction and setting of the DR
1146 * register for output gpios.
1147 */
1148static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1149{
1150 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1151 u32 data;
1152
1153 data = readl(bank->reg_base + GPIO_EXT_PORT);
1154 data >>= offset;
1155 data &= 1;
1156 return data;
1157}
1158
1159/*
1160 * gpiolib gpio_direction_input callback function. The setting of the pin
1161 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1162 * interface.
1163 */
1164static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1165{
1166 return pinctrl_gpio_direction_input(gc->base + offset);
1167}
1168
1169/*
1170 * gpiolib gpio_direction_output callback function. The setting of the pin
1171 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1172 * interface.
1173 */
1174static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1175 unsigned offset, int value)
1176{
1177 rockchip_gpio_set(gc, offset, value);
1178 return pinctrl_gpio_direction_output(gc->base + offset);
1179}
1180
1181/*
1182 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1183 * and a virtual IRQ, if not already present.
1184 */
1185static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1186{
1187 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1188 unsigned int virq;
1189
1190 if (!bank->domain)
1191 return -ENXIO;
1192
1193 virq = irq_create_mapping(bank->domain, offset);
1194
1195 return (virq) ? : -ENXIO;
1196}
1197
1198static const struct gpio_chip rockchip_gpiolib_chip = {
0351c287
AL		 1199 .request = rockchip_gpio_request,
1200 .free = rockchip_gpio_free,
d3e51161
HS		 1201 .set = rockchip_gpio_set,
1202 .get = rockchip_gpio_get,
1203 .direction_input = rockchip_gpio_direction_input,
1204 .direction_output = rockchip_gpio_direction_output,
1205 .to_irq = rockchip_gpio_to_irq,
1206 .owner = THIS_MODULE,
1207};
1208
1209/*
1210 * Interrupt handling
1211 */
1212
1213static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1214{
1215 struct irq_chip *chip = irq_get_chip(irq);
1216 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
5a927501 1217 u32 polarity = 0, data = 0;
d3e51161 1218 u32 pend;
5a927501 1219 bool edge_changed = false;
d3e51161
HS		 1220
1221 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1222
1223 chained_irq_enter(chip, desc);
1224
1225 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1226
5a927501
HS		 1227 if (bank->toggle_edge_mode) {
1228 polarity = readl_relaxed(bank->reg_base +
1229 GPIO_INT_POLARITY);
1230 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1231 }
1232
d3e51161
HS		 1233 while (pend) {
1234 unsigned int virq;
1235
1236 irq = __ffs(pend);
1237 pend &= ~BIT(irq);
1238 virq = irq_linear_revmap(bank->domain, irq);
1239
1240 if (!virq) {
1241 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1242 continue;
1243 }
1244
1245 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1246
5a927501
HS		 1247 /*
1248 * Triggering IRQ on both rising and falling edge
1249 * needs manual intervention.
1250 */
1251 if (bank->toggle_edge_mode & BIT(irq)) {
1252 if (data & BIT(irq))
1253 polarity &= ~BIT(irq);
1254 else
1255 polarity |= BIT(irq);
1256
1257 edge_changed = true;
1258 }
1259
d3e51161
HS		 1260 generic_handle_irq(virq);
1261 }
1262
5a927501
HS		 1263 if (bank->toggle_edge_mode && edge_changed) {
1264 /* Interrupt params should only be set with ints disabled */
1265 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1266 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1267 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1268 writel(data, bank->reg_base + GPIO_INTEN);
1269 }
1270
d3e51161
HS		 1271 chained_irq_exit(chip, desc);
1272}
1273
1274static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1275{
1276 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1277 struct rockchip_pin_bank *bank = gc->private;
1278 u32 mask = BIT(d->hwirq);
1279 u32 polarity;
1280 u32 level;
1281 u32 data;
14797189 1282 int ret;
d3e51161 1283
5a927501 1284 /* make sure the pin is configured as gpio input */
14797189
HS		 1285 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1286 if (ret < 0)
1287 return ret;
1288
5a927501
HS		 1289 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1290 data &= ~mask;
1291 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1292
d3e51161
HS		 1293 if (type & IRQ_TYPE_EDGE_BOTH)
1294 __irq_set_handler_locked(d->irq, handle_edge_irq);
1295 else
1296 __irq_set_handler_locked(d->irq, handle_level_irq);
1297
1298 irq_gc_lock(gc);
1299
1300 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1301 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1302
1303 switch (type) {
5a927501
HS		 1304 case IRQ_TYPE_EDGE_BOTH:
1305 bank->toggle_edge_mode |= mask;
1306 level |= mask;
1307
1308 /*
1309 * Determine gpio state. If 1 next interrupt should be falling
1310 * otherwise rising.
1311 */
1312 data = readl(bank->reg_base + GPIO_EXT_PORT);
1313 if (data & mask)
1314 polarity &= ~mask;
1315 else
1316 polarity |= mask;
1317 break;
d3e51161 1318 case IRQ_TYPE_EDGE_RISING:
5a927501 1319 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1320 level |= mask;
1321 polarity |= mask;
1322 break;
1323 case IRQ_TYPE_EDGE_FALLING:
5a927501 1324 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1325 level |= mask;
1326 polarity &= ~mask;
1327 break;
1328 case IRQ_TYPE_LEVEL_HIGH:
5a927501 1329 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1330 level &= ~mask;
1331 polarity |= mask;
1332 break;
1333 case IRQ_TYPE_LEVEL_LOW:
5a927501 1334 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1335 level &= ~mask;
1336 polarity &= ~mask;
1337 break;
1338 default:
7cc5f970 1339 irq_gc_unlock(gc);
d3e51161
HS		 1340 return -EINVAL;
1341 }
1342
1343 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1344 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1345
1346 irq_gc_unlock(gc);
1347
d3e51161
HS		 1348 return 0;
1349}
1350
1351static int rockchip_interrupts_register(struct platform_device *pdev,
1352 struct rockchip_pinctrl *info)
1353{
1354 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1355 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1356 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1357 struct irq_chip_generic *gc;
1358 int ret;
1359 int i;
1360
1361 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1362 if (!bank->valid) {
1363 dev_warn(&pdev->dev, "bank %s is not valid\n",
1364 bank->name);
1365 continue;
1366 }
1367
1368 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1369 &irq_generic_chip_ops, NULL);
1370 if (!bank->domain) {
1371 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1372 bank->name);
1373 continue;
1374 }
1375
1376 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1377 "rockchip_gpio_irq", handle_level_irq,
1378 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1379 if (ret) {
1380 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1381 bank->name);
1382 irq_domain_remove(bank->domain);
1383 continue;
1384 }
1385
1386 gc = irq_get_domain_generic_chip(bank->domain, 0);
1387 gc->reg_base = bank->reg_base;
1388 gc->private = bank;
1389 gc->chip_types[0].regs.mask = GPIO_INTEN;
1390 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1391 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1392 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1393 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1394 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1395 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1396
1397 irq_set_handler_data(bank->irq, bank);
1398 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1399 }
1400
1401 return 0;
1402}
1403
1404static int rockchip_gpiolib_register(struct platform_device *pdev,
1405 struct rockchip_pinctrl *info)
1406{
1407 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1408 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1409 struct gpio_chip *gc;
1410 int ret;
1411 int i;
1412
1413 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1414 if (!bank->valid) {
1415 dev_warn(&pdev->dev, "bank %s is not valid\n",
1416 bank->name);
1417 continue;
1418 }
1419
1420 bank->gpio_chip = rockchip_gpiolib_chip;
1421
1422 gc = &bank->gpio_chip;
1423 gc->base = bank->pin_base;
1424 gc->ngpio = bank->nr_pins;
1425 gc->dev = &pdev->dev;
1426 gc->of_node = bank->of_node;
1427 gc->label = bank->name;
1428
1429 ret = gpiochip_add(gc);
1430 if (ret) {
1431 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1432 gc->label, ret);
1433 goto fail;
1434 }
1435 }
1436
1437 rockchip_interrupts_register(pdev, info);
1438
1439 return 0;
1440
1441fail:
1442 for (--i, --bank; i >= 0; --i, --bank) {
1443 if (!bank->valid)
1444 continue;
1445
1446 if (gpiochip_remove(&bank->gpio_chip))
1447 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1448 bank->gpio_chip.label);
1449 }
1450 return ret;
1451}
1452
1453static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1454 struct rockchip_pinctrl *info)
1455{
1456 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1457 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1458 int ret = 0;
1459 int i;
1460
1461 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1462 if (!bank->valid)
1463 continue;
1464
1465 ret = gpiochip_remove(&bank->gpio_chip);
1466 }
1467
1468 if (ret)
1469 dev_err(&pdev->dev, "gpio chip remove failed\n");
1470
1471 return ret;
1472}
1473
1474static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
622f3237 1475 struct rockchip_pinctrl *info)
d3e51161
HS		 1476{
1477 struct resource res;
751a99ab 1478 void __iomem *base;
d3e51161
HS		 1479
1480 if (of_address_to_resource(bank->of_node, 0, &res)) {
622f3237 1481 dev_err(info->dev, "cannot find IO resource for bank\n");
d3e51161
HS		 1482 return -ENOENT;
1483 }
1484
622f3237 1485 bank->reg_base = devm_ioremap_resource(info->dev, &res);
d3e51161
HS		 1486 if (IS_ERR(bank->reg_base))
1487 return PTR_ERR(bank->reg_base);
1488
6ca5274d
HS		 1489 /*
1490 * special case, where parts of the pull setting-registers are
1491 * part of the PMU register space
1492 */
1493 if (of_device_is_compatible(bank->of_node,
1494 "rockchip,rk3188-gpio-bank0")) {
a658efaa 1495 struct device_node *node;
bfc7a42a 1496
a658efaa
HS		 1497 node = of_parse_phandle(bank->of_node->parent,
1498 "rockchip,pmu", 0);
1499 if (!node) {
1500 if (of_address_to_resource(bank->of_node, 1, &res)) {
1501 dev_err(info->dev, "cannot find IO resource for bank\n");
1502 return -ENOENT;
1503 }
1504
1505 base = devm_ioremap_resource(info->dev, &res);
1506 if (IS_ERR(base))
1507 return PTR_ERR(base);
1508 rockchip_regmap_config.max_register =
1509 resource_size(&res) - 4;
1510 rockchip_regmap_config.name =
1511 "rockchip,rk3188-gpio-bank0-pull";
1512 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1513 base,
1514 &rockchip_regmap_config);
6ca5274d 1515 }
6ca5274d 1516 }
65fca613 1517
d3e51161
HS		 1518 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1519
1520 bank->clk = of_clk_get(bank->of_node, 0);
1521 if (IS_ERR(bank->clk))
1522 return PTR_ERR(bank->clk);
1523
1524 return clk_prepare_enable(bank->clk);
1525}
1526
1527static const struct of_device_id rockchip_pinctrl_dt_match[];
1528
1529/* retrieve the soc specific data */
1530static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1531 struct rockchip_pinctrl *d,
1532 struct platform_device *pdev)
1533{
1534 const struct of_device_id *match;
1535 struct device_node *node = pdev->dev.of_node;
1536 struct device_node *np;
1537 struct rockchip_pin_ctrl *ctrl;
1538 struct rockchip_pin_bank *bank;
6bc0d121 1539 int grf_offs, i, j;
d3e51161
HS		 1540
1541 match = of_match_node(rockchip_pinctrl_dt_match, node);
1542 ctrl = (struct rockchip_pin_ctrl *)match->data;
1543
1544 for_each_child_of_node(node, np) {
1545 if (!of_find_property(np, "gpio-controller", NULL))
1546 continue;
1547
1548 bank = ctrl->pin_banks;
1549 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1550 if (!strcmp(bank->name, np->name)) {
1551 bank->of_node = np;
1552
622f3237 1553 if (!rockchip_get_bank_data(bank, d))
d3e51161
HS		 1554 bank->valid = true;
1555
1556 break;
1557 }
1558 }
1559 }
1560
6bc0d121 1561 grf_offs = ctrl->mux_offset;
d3e51161
HS		 1562 bank = ctrl->pin_banks;
1563 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
6bc0d121
HS		 1564 int bank_pins = 0;
1565
d3e51161
HS		 1566 spin_lock_init(&bank->slock);
1567 bank->drvdata = d;
1568 bank->pin_base = ctrl->nr_pins;
1569 ctrl->nr_pins += bank->nr_pins;
6bc0d121
HS		 1570
1571 /* calculate iomux offsets */
1572 for (j = 0; j < 4; j++) {
1573 struct rockchip_iomux *iom = &bank->iomux[j];
03716e1d 1574 int inc;
6bc0d121
HS		 1575
1576 if (bank_pins >= bank->nr_pins)
1577 break;
1578
1579 /* preset offset value, set new start value */
1580 if (iom->offset >= 0) {
1581 grf_offs = iom->offset;
1582 } else { /* set current offset */
1583 iom->offset = grf_offs;
1584 }
1585
1586 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1587 i, j, iom->offset);
1588
1589 /*
1590 * Increase offset according to iomux width.
03716e1d 1591 * 4bit iomux'es are spread over two registers.
6bc0d121 1592 */
03716e1d
HS		 1593 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1594 grf_offs += inc;
6bc0d121
HS		 1595
1596 bank_pins += 8;
1597 }
d3e51161
HS		 1598 }
1599
1600 return ctrl;
1601}
1602
1603static int rockchip_pinctrl_probe(struct platform_device *pdev)
1604{
1605 struct rockchip_pinctrl *info;
1606 struct device *dev = &pdev->dev;
1607 struct rockchip_pin_ctrl *ctrl;
14dee867 1608 struct device_node *np = pdev->dev.of_node, *node;
d3e51161 1609 struct resource *res;
751a99ab 1610 void __iomem *base;
d3e51161
HS		 1611 int ret;
1612
1613 if (!dev->of_node) {
1614 dev_err(dev, "device tree node not found\n");
1615 return -ENODEV;
1616 }
1617
1618 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1619 if (!info)
1620 return -ENOMEM;
1621
622f3237
HS		 1622 info->dev = dev;
1623
d3e51161
HS		 1624 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1625 if (!ctrl) {
1626 dev_err(dev, "driver data not available\n");
1627 return -EINVAL;
1628 }
1629 info->ctrl = ctrl;
d3e51161 1630
1e747e59
HS		 1631 node = of_parse_phandle(np, "rockchip,grf", 0);
1632 if (node) {
1633 info->regmap_base = syscon_node_to_regmap(node);
1634 if (IS_ERR(info->regmap_base))
1635 return PTR_ERR(info->regmap_base);
1636 } else {
1637 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751a99ab
HS		 1638 base = devm_ioremap_resource(&pdev->dev, res);
1639 if (IS_ERR(base))
1640 return PTR_ERR(base);
1641
1642 rockchip_regmap_config.max_register = resource_size(res) - 4;
1e747e59
HS		 1643 rockchip_regmap_config.name = "rockchip,pinctrl";
1644 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1645 &rockchip_regmap_config);
1646
1647 /* to check for the old dt-bindings */
1648 info->reg_size = resource_size(res);
1649
1650 /* Honor the old binding, with pull registers as 2nd resource */
1651 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1652 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1653 base = devm_ioremap_resource(&pdev->dev, res);
1654 if (IS_ERR(base))
1655 return PTR_ERR(base);
1656
1657 rockchip_regmap_config.max_register =
1658 resource_size(res) - 4;
1659 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1660 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
1661 base,
1662 &rockchip_regmap_config);
1663 }
6ca5274d
HS		 1664 }
1665
14dee867
HS		 1666 /* try to find the optional reference to the pmu syscon */
1667 node = of_parse_phandle(np, "rockchip,pmu", 0);
1668 if (node) {
1669 info->regmap_pmu = syscon_node_to_regmap(node);
1670 if (IS_ERR(info->regmap_pmu))
1671 return PTR_ERR(info->regmap_pmu);
1672 }
1673
d3e51161
HS		 1674 ret = rockchip_gpiolib_register(pdev, info);
1675 if (ret)
1676 return ret;
1677
1678 ret = rockchip_pinctrl_register(pdev, info);
1679 if (ret) {
1680 rockchip_gpiolib_unregister(pdev, info);
1681 return ret;
1682 }
1683
1684 platform_set_drvdata(pdev, info);
1685
1686 return 0;
1687}
1688
1689static struct rockchip_pin_bank rk2928_pin_banks[] = {
1690 PIN_BANK(0, 32, "gpio0"),
1691 PIN_BANK(1, 32, "gpio1"),
1692 PIN_BANK(2, 32, "gpio2"),
1693 PIN_BANK(3, 32, "gpio3"),
1694};
1695
1696static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1697 .pin_banks = rk2928_pin_banks,
1698 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1699 .label = "RK2928-GPIO",
a282926d 1700 .type = RK2928,
d3e51161 1701 .mux_offset = 0xa8,
a282926d 1702 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 1703};
1704
1705static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1706 PIN_BANK(0, 32, "gpio0"),
1707 PIN_BANK(1, 32, "gpio1"),
1708 PIN_BANK(2, 32, "gpio2"),
1709 PIN_BANK(3, 32, "gpio3"),
1710 PIN_BANK(4, 32, "gpio4"),
1711 PIN_BANK(6, 16, "gpio6"),
1712};
1713
1714static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1715 .pin_banks = rk3066a_pin_banks,
1716 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1717 .label = "RK3066a-GPIO",
a282926d 1718 .type = RK2928,
d3e51161 1719 .mux_offset = 0xa8,
a282926d 1720 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 1721};
1722
1723static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1724 PIN_BANK(0, 32, "gpio0"),
1725 PIN_BANK(1, 32, "gpio1"),
1726 PIN_BANK(2, 32, "gpio2"),
1727 PIN_BANK(3, 32, "gpio3"),
1728};
1729
1730static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1731 .pin_banks = rk3066b_pin_banks,
1732 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1733 .label = "RK3066b-GPIO",
a282926d 1734 .type = RK3066B,
d3e51161 1735 .mux_offset = 0x60,
d3e51161
HS		 1736};
1737
1738static struct rockchip_pin_bank rk3188_pin_banks[] = {
fc72c923 1739 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
d3e51161
HS		 1740 PIN_BANK(1, 32, "gpio1"),
1741 PIN_BANK(2, 32, "gpio2"),
1742 PIN_BANK(3, 32, "gpio3"),
1743};
1744
1745static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1746 .pin_banks = rk3188_pin_banks,
1747 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1748 .label = "RK3188-GPIO",
a282926d 1749 .type = RK3188,
22c0d7e3 1750 .mux_offset = 0x60,
6ca5274d 1751 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 1752};
1753
1754static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1755 { .compatible = "rockchip,rk2928-pinctrl",
1756 .data = (void *)&rk2928_pin_ctrl },
1757 { .compatible = "rockchip,rk3066a-pinctrl",
1758 .data = (void *)&rk3066a_pin_ctrl },
1759 { .compatible = "rockchip,rk3066b-pinctrl",
1760 .data = (void *)&rk3066b_pin_ctrl },
1761 { .compatible = "rockchip,rk3188-pinctrl",
1762 .data = (void *)&rk3188_pin_ctrl },
1763 {},
1764};
1765MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1766
1767static struct platform_driver rockchip_pinctrl_driver = {
1768 .probe = rockchip_pinctrl_probe,
1769 .driver = {
1770 .name = "rockchip-pinctrl",
1771 .owner = THIS_MODULE,
0be9e70d 1772 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 1773 },
1774};
1775
1776static int __init rockchip_pinctrl_drv_register(void)
1777{
1778 return platform_driver_register(&rockchip_pinctrl_driver);
1779}
1780postcore_initcall(rockchip_pinctrl_drv_register);
1781
1782MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1783MODULE_DESCRIPTION("Rockchip pinctrl driver");
1784MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)