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Merge branch 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
d3e51161
HS		 2/*
3 * Pinctrl driver for Rockchip SoCs
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * http://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
d3e51161
HS		 16 */
17
2f436204 18#include <linux/init.h>
d3e51161
HS		 19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/bitops.h>
1c5fb66a 22#include <linux/gpio/driver.h>
d3e51161
HS		 23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/pinctrl/machine.h>
26#include <linux/pinctrl/pinconf.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf-generic.h>
30#include <linux/irqchip/chained_irq.h>
7e865abb 31#include <linux/clk.h>
751a99ab 32#include <linux/regmap.h>
14dee867 33#include <linux/mfd/syscon.h>
d3e51161
HS		 34#include <dt-bindings/pinctrl/rockchip.h>
35
36#include "core.h"
37#include "pinconf.h"
38
39/* GPIO control registers */
40#define GPIO_SWPORT_DR 0x00
41#define GPIO_SWPORT_DDR 0x04
42#define GPIO_INTEN 0x30
43#define GPIO_INTMASK 0x34
44#define GPIO_INTTYPE_LEVEL 0x38
45#define GPIO_INT_POLARITY 0x3c
46#define GPIO_INT_STATUS 0x40
47#define GPIO_INT_RAWSTATUS 0x44
48#define GPIO_DEBOUNCE 0x48
49#define GPIO_PORTS_EOI 0x4c
50#define GPIO_EXT_PORT 0x50
51#define GPIO_LS_SYNC 0x60
52
a282926d 53enum rockchip_pinctrl_type {
87065ca9 54 PX30,
b9c6dcab 55 RV1108,
a282926d
HS		 56 RK2928,
57 RK3066B,
d23c66df 58 RK3128,
a282926d 59 RK3188,
66d750e1 60 RK3288,
daecdc66 61 RK3368,
b6c23275 62 RK3399,
a282926d
HS		 63};
64
fc72c923
HS		 65/**
66 * Encode variants of iomux registers into a type variable
67 */
68#define IOMUX_GPIO_ONLY BIT(0)
03716e1d 69#define IOMUX_WIDTH_4BIT BIT(1)
95ec8ae4 70#define IOMUX_SOURCE_PMU BIT(2)
62f49226 71#define IOMUX_UNROUTED BIT(3)
8b6c6f93 72#define IOMUX_WIDTH_3BIT BIT(4)
fc72c923
HS		 73
74/**
75 * @type: iomux variant using IOMUX_* constants
6bc0d121
HS		 76 * @offset: if initialized to -1 it will be autocalculated, by specifying
77 * an initial offset value the relevant source offset can be reset
78 * to a new value for autocalculating the following iomux registers.
fc72c923
HS		 79 */
80struct rockchip_iomux {
81 int type;
6bc0d121 82 int offset;
65fca613
HS		 83};
84
b6c23275
DW		 85/**
86 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
87 */
88enum rockchip_pin_drv_type {
89 DRV_TYPE_IO_DEFAULT = 0,
90 DRV_TYPE_IO_1V8_OR_3V0,
91 DRV_TYPE_IO_1V8_ONLY,
92 DRV_TYPE_IO_1V8_3V0_AUTO,
93 DRV_TYPE_IO_3V3_ONLY,
94 DRV_TYPE_MAX
95};
96
3ba6767a
DW		 97/**
98 * enum type index corresponding to rockchip_pull_list arrays index.
99 */
100enum rockchip_pin_pull_type {
101 PULL_TYPE_IO_DEFAULT = 0,
102 PULL_TYPE_IO_1V8_ONLY,
103 PULL_TYPE_MAX
104};
105
b6c23275
DW		 106/**
107 * @drv_type: drive strength variant using rockchip_perpin_drv_type
108 * @offset: if initialized to -1 it will be autocalculated, by specifying
109 * an initial offset value the relevant source offset can be reset
110 * to a new value for autocalculating the following drive strength
111 * registers. if used chips own cal_drv func instead to calculate
112 * registers offset, the variant could be ignored.
113 */
114struct rockchip_drv {
115 enum rockchip_pin_drv_type drv_type;
116 int offset;
117};
118
d3e51161
HS		 119/**
120 * @reg_base: register base of the gpio bank
6ca5274d 121 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 122 * @clk: clock of the gpio bank
123 * @irq: interrupt of the gpio bank
5ae0c7ad 124 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
d3e51161
HS		 125 * @pin_base: first pin number
126 * @nr_pins: number of pins in this bank
127 * @name: name of the bank
128 * @bank_num: number of the bank, to account for holes
fc72c923 129 * @iomux: array describing the 4 iomux sources of the bank
b6c23275 130 * @drv: array describing the 4 drive strength sources of the bank
3ba6767a 131 * @pull_type: array describing the 4 pull type sources of the bank
85dc397a 132 * @valid: is all necessary information present
d3e51161
HS		 133 * @of_node: dt node of this bank
134 * @drvdata: common pinctrl basedata
135 * @domain: irqdomain of the gpio bank
136 * @gpio_chip: gpiolib chip
137 * @grange: gpio range
138 * @slock: spinlock for the gpio bank
bd35b9bf 139 * @route_mask: bits describing the routing pins of per bank
d3e51161
HS		 140 */
141struct rockchip_pin_bank {
142 void __iomem *reg_base;
751a99ab 143 struct regmap *regmap_pull;
d3e51161
HS		 144 struct clk *clk;
145 int irq;
5ae0c7ad 146 u32 saved_masks;
d3e51161
HS		 147 u32 pin_base;
148 u8 nr_pins;
149 char *name;
150 u8 bank_num;
fc72c923 151 struct rockchip_iomux iomux[4];
b6c23275 152 struct rockchip_drv drv[4];
3ba6767a 153 enum rockchip_pin_pull_type pull_type[4];
d3e51161
HS		 154 bool valid;
155 struct device_node *of_node;
156 struct rockchip_pinctrl *drvdata;
157 struct irq_domain *domain;
158 struct gpio_chip gpio_chip;
159 struct pinctrl_gpio_range grange;
70b7aa7a 160 raw_spinlock_t slock;
5a927501 161 u32 toggle_edge_mode;
c04c3fa6 162 u32 recalced_mask;
bd35b9bf 163 u32 route_mask;
d3e51161
HS		 164};
165
166#define PIN_BANK(id, pins, label) \
167 { \
168 .bank_num = id, \
169 .nr_pins = pins, \
170 .name = label, \
6bc0d121
HS		 171 .iomux = { \
172 { .offset = -1 }, \
173 { .offset = -1 }, \
174 { .offset = -1 }, \
175 { .offset = -1 }, \
176 }, \
d3e51161
HS		 177 }
178
fc72c923
HS		 179#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
180 { \
181 .bank_num = id, \
182 .nr_pins = pins, \
183 .name = label, \
184 .iomux = { \
6bc0d121
HS		 185 { .type = iom0, .offset = -1 }, \
186 { .type = iom1, .offset = -1 }, \
187 { .type = iom2, .offset = -1 }, \
188 { .type = iom3, .offset = -1 }, \
fc72c923
HS		 189 }, \
190 }
191
b6c23275
DW		 192#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
193 { \
194 .bank_num = id, \
195 .nr_pins = pins, \
196 .name = label, \
197 .iomux = { \
198 { .offset = -1 }, \
199 { .offset = -1 }, \
200 { .offset = -1 }, \
201 { .offset = -1 }, \
202 }, \
203 .drv = { \
204 { .drv_type = type0, .offset = -1 }, \
205 { .drv_type = type1, .offset = -1 }, \
206 { .drv_type = type2, .offset = -1 }, \
207 { .drv_type = type3, .offset = -1 }, \
208 }, \
209 }
210
3ba6767a
DW		 211#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
212 drv2, drv3, pull0, pull1, \
213 pull2, pull3) \
214 { \
215 .bank_num = id, \
216 .nr_pins = pins, \
217 .name = label, \
218 .iomux = { \
219 { .offset = -1 }, \
220 { .offset = -1 }, \
221 { .offset = -1 }, \
222 { .offset = -1 }, \
223 }, \
224 .drv = { \
225 { .drv_type = drv0, .offset = -1 }, \
226 { .drv_type = drv1, .offset = -1 }, \
227 { .drv_type = drv2, .offset = -1 }, \
228 { .drv_type = drv3, .offset = -1 }, \
229 }, \
230 .pull_type[0] = pull0, \
231 .pull_type[1] = pull1, \
232 .pull_type[2] = pull2, \
233 .pull_type[3] = pull3, \
234 }
235
b6c23275
DW		 236#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
237 iom2, iom3, drv0, drv1, drv2, \
238 drv3, offset0, offset1, \
239 offset2, offset3) \
240 { \
241 .bank_num = id, \
242 .nr_pins = pins, \
243 .name = label, \
244 .iomux = { \
245 { .type = iom0, .offset = -1 }, \
246 { .type = iom1, .offset = -1 }, \
247 { .type = iom2, .offset = -1 }, \
248 { .type = iom3, .offset = -1 }, \
249 }, \
250 .drv = { \
251 { .drv_type = drv0, .offset = offset0 }, \
252 { .drv_type = drv1, .offset = offset1 }, \
253 { .drv_type = drv2, .offset = offset2 }, \
254 { .drv_type = drv3, .offset = offset3 }, \
255 }, \
256 }
257
3ba6767a
DW		 258#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
259 label, iom0, iom1, iom2, \
260 iom3, drv0, drv1, drv2, \
261 drv3, offset0, offset1, \
262 offset2, offset3, pull0, \
263 pull1, pull2, pull3) \
264 { \
265 .bank_num = id, \
266 .nr_pins = pins, \
267 .name = label, \
268 .iomux = { \
269 { .type = iom0, .offset = -1 }, \
270 { .type = iom1, .offset = -1 }, \
271 { .type = iom2, .offset = -1 }, \
272 { .type = iom3, .offset = -1 }, \
273 }, \
274 .drv = { \
275 { .drv_type = drv0, .offset = offset0 }, \
276 { .drv_type = drv1, .offset = offset1 }, \
277 { .drv_type = drv2, .offset = offset2 }, \
278 { .drv_type = drv3, .offset = offset3 }, \
279 }, \
280 .pull_type[0] = pull0, \
281 .pull_type[1] = pull1, \
282 .pull_type[2] = pull2, \
283 .pull_type[3] = pull3, \
284 }
285
c04c3fa6
DW		 286/**
287 * struct rockchip_mux_recalced_data: represent a pin iomux data.
288 * @num: bank number.
289 * @pin: pin number.
290 * @bit: index at register.
291 * @reg: register offset.
292 * @mask: mask bit
293 */
294struct rockchip_mux_recalced_data {
295 u8 num;
296 u8 pin;
12b8f018 297 u32 reg;
c04c3fa6
DW		 298 u8 bit;
299 u8 mask;
300};
301
51ff47aa
HS		 302enum rockchip_mux_route_location {
303 ROCKCHIP_ROUTE_SAME = 0,
304 ROCKCHIP_ROUTE_PMU,
305 ROCKCHIP_ROUTE_GRF,
306};
307
bd35b9bf
DW		 308/**
309 * struct rockchip_mux_recalced_data: represent a pin iomux data.
310 * @bank_num: bank number.
311 * @pin: index at register or used to calc index.
312 * @func: the min pin.
313 * @route_offset: the max pin.
314 * @route_val: the register offset.
315 */
316struct rockchip_mux_route_data {
317 u8 bank_num;
318 u8 pin;
319 u8 func;
51ff47aa 320 enum rockchip_mux_route_location route_location;
bd35b9bf
DW		 321 u32 route_offset;
322 u32 route_val;
323};
324
d3e51161 325/**
d3e51161
HS		 326 */
327struct rockchip_pin_ctrl {
328 struct rockchip_pin_bank *pin_banks;
329 u32 nr_banks;
330 u32 nr_pins;
331 char *label;
a282926d 332 enum rockchip_pinctrl_type type;
95ec8ae4
HS		 333 int grf_mux_offset;
334 int pmu_mux_offset;
b6c23275
DW		 335 int grf_drv_offset;
336 int pmu_drv_offset;
c04c3fa6
DW		 337 struct rockchip_mux_recalced_data *iomux_recalced;
338 u32 niomux_recalced;
bd35b9bf
DW		 339 struct rockchip_mux_route_data *iomux_routes;
340 u32 niomux_routes;
b6c23275 341
751a99ab
HS		 342 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
343 int pin_num, struct regmap **regmap,
344 int *reg, u8 *bit);
ef17f69f
HS		 345 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
346 int pin_num, struct regmap **regmap,
347 int *reg, u8 *bit);
e3b357d7 348 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
349 int pin_num, struct regmap **regmap,
350 int *reg, u8 *bit);
d3e51161
HS		 351};
352
353struct rockchip_pin_config {
354 unsigned int func;
355 unsigned long *configs;
356 unsigned int nconfigs;
357};
358
359/**
360 * struct rockchip_pin_group: represent group of pins of a pinmux function.
361 * @name: name of the pin group, used to lookup the group.
362 * @pins: the pins included in this group.
363 * @npins: number of pins included in this group.
364 * @func: the mux function number to be programmed when selected.
365 * @configs: the config values to be set for each pin
366 * @nconfigs: number of configs for each pin
367 */
368struct rockchip_pin_group {
369 const char *name;
370 unsigned int npins;
371 unsigned int *pins;
372 struct rockchip_pin_config *data;
373};
374
375/**
376 * struct rockchip_pmx_func: represent a pin function.
377 * @name: name of the pin function, used to lookup the function.
378 * @groups: one or more names of pin groups that provide this function.
379 * @num_groups: number of groups included in @groups.
380 */
381struct rockchip_pmx_func {
382 const char *name;
383 const char **groups;
384 u8 ngroups;
385};
386
387struct rockchip_pinctrl {
751a99ab 388 struct regmap *regmap_base;
bfc7a42a 389 int reg_size;
751a99ab 390 struct regmap *regmap_pull;
14dee867 391 struct regmap *regmap_pmu;
d3e51161
HS		 392 struct device *dev;
393 struct rockchip_pin_ctrl *ctrl;
394 struct pinctrl_desc pctl;
395 struct pinctrl_dev *pctl_dev;
396 struct rockchip_pin_group *groups;
397 unsigned int ngroups;
398 struct rockchip_pmx_func *functions;
399 unsigned int nfunctions;
400};
401
751a99ab
HS		 402static struct regmap_config rockchip_regmap_config = {
403 .reg_bits = 32,
404 .val_bits = 32,
405 .reg_stride = 4,
406};
407
56411f3c 408static inline const struct rockchip_pin_group *pinctrl_name_to_group(
d3e51161
HS		 409 const struct rockchip_pinctrl *info,
410 const char *name)
411{
d3e51161
HS		 412 int i;
413
414 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 415 if (!strcmp(info->groups[i].name, name))
416 return &info->groups[i];
d3e51161
HS		 417 }
418
1cb95395 419 return NULL;
d3e51161
HS		 420}
421
422/*
423 * given a pin number that is local to a pin controller, find out the pin bank
424 * and the register base of the pin bank.
425 */
426static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
427 unsigned pin)
428{
429 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
430
51578b9b 431 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 432 b++;
433
434 return b;
435}
436
437static struct rockchip_pin_bank *bank_num_to_bank(
438 struct rockchip_pinctrl *info,
439 unsigned num)
440{
441 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
442 int i;
443
1cb95395 444 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 445 if (b->bank_num == num)
1cb95395 446 return b;
d3e51161
HS		 447 }
448
1cb95395 449 return ERR_PTR(-EINVAL);
d3e51161
HS		 450}
451
452/*
453 * Pinctrl_ops handling
454 */
455
456static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
457{
458 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
459
460 return info->ngroups;
461}
462
463static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
464 unsigned selector)
465{
466 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
467
468 return info->groups[selector].name;
469}
470
471static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
472 unsigned selector, const unsigned **pins,
473 unsigned *npins)
474{
475 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
476
477 if (selector >= info->ngroups)
478 return -EINVAL;
479
480 *pins = info->groups[selector].pins;
481 *npins = info->groups[selector].npins;
482
483 return 0;
484}
485
486static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *np,
488 struct pinctrl_map **map, unsigned *num_maps)
489{
490 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
491 const struct rockchip_pin_group *grp;
492 struct pinctrl_map *new_map;
493 struct device_node *parent;
494 int map_num = 1;
495 int i;
496
497 /*
498 * first find the group of this node and check if we need to create
499 * config maps for pins
500 */
501 grp = pinctrl_name_to_group(info, np->name);
502 if (!grp) {
94f4e54c
RH		 503 dev_err(info->dev, "unable to find group for node %pOFn\n",
504 np);
d3e51161
HS		 505 return -EINVAL;
506 }
507
508 map_num += grp->npins;
a86854d0 509 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
d3e51161
HS		 510 GFP_KERNEL);
511 if (!new_map)
512 return -ENOMEM;
513
514 *map = new_map;
515 *num_maps = map_num;
516
517 /* create mux map */
518 parent = of_get_parent(np);
519 if (!parent) {
520 devm_kfree(pctldev->dev, new_map);
521 return -EINVAL;
522 }
523 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
524 new_map[0].data.mux.function = parent->name;
525 new_map[0].data.mux.group = np->name;
526 of_node_put(parent);
527
528 /* create config map */
529 new_map++;
530 for (i = 0; i < grp->npins; i++) {
531 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
532 new_map[i].data.configs.group_or_pin =
533 pin_get_name(pctldev, grp->pins[i]);
534 new_map[i].data.configs.configs = grp->data[i].configs;
535 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
536 }
537
538 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
539 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
540
541 return 0;
542}
543
544static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
545 struct pinctrl_map *map, unsigned num_maps)
546{
547}
548
549static const struct pinctrl_ops rockchip_pctrl_ops = {
550 .get_groups_count = rockchip_get_groups_count,
551 .get_group_name = rockchip_get_group_name,
552 .get_group_pins = rockchip_get_group_pins,
553 .dt_node_to_map = rockchip_dt_node_to_map,
554 .dt_free_map = rockchip_dt_free_map,
555};
556
557/*
558 * Hardware access
559 */
560
12b8f018
DW		 561static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
562 {
563 .num = 1,
564 .pin = 0,
565 .reg = 0x418,
566 .bit = 0,
567 .mask = 0x3
568 }, {
569 .num = 1,
570 .pin = 1,
571 .reg = 0x418,
572 .bit = 2,
573 .mask = 0x3
574 }, {
575 .num = 1,
576 .pin = 2,
577 .reg = 0x418,
578 .bit = 4,
579 .mask = 0x3
580 }, {
581 .num = 1,
582 .pin = 3,
583 .reg = 0x418,
584 .bit = 6,
585 .mask = 0x3
586 }, {
587 .num = 1,
588 .pin = 4,
589 .reg = 0x418,
590 .bit = 8,
591 .mask = 0x3
592 }, {
593 .num = 1,
594 .pin = 5,
595 .reg = 0x418,
596 .bit = 10,
597 .mask = 0x3
598 }, {
599 .num = 1,
600 .pin = 6,
601 .reg = 0x418,
602 .bit = 12,
603 .mask = 0x3
604 }, {
605 .num = 1,
606 .pin = 7,
607 .reg = 0x418,
608 .bit = 14,
609 .mask = 0x3
610 }, {
611 .num = 1,
612 .pin = 8,
613 .reg = 0x41c,
614 .bit = 0,
615 .mask = 0x3
616 }, {
617 .num = 1,
618 .pin = 9,
619 .reg = 0x41c,
620 .bit = 2,
621 .mask = 0x3
622 },
623};
624
d23c66df
DW		 625static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
626 {
627 .num = 2,
628 .pin = 20,
629 .reg = 0xe8,
630 .bit = 0,
631 .mask = 0x7
632 }, {
633 .num = 2,
634 .pin = 21,
635 .reg = 0xe8,
636 .bit = 4,
637 .mask = 0x7
638 }, {
639 .num = 2,
640 .pin = 22,
641 .reg = 0xe8,
642 .bit = 8,
643 .mask = 0x7
644 }, {
645 .num = 2,
646 .pin = 23,
647 .reg = 0xe8,
648 .bit = 12,
649 .mask = 0x7
650 }, {
651 .num = 2,
652 .pin = 24,
653 .reg = 0xd4,
654 .bit = 12,
655 .mask = 0x7
656 },
657};
658
c04c3fa6 659static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
3818e4a7 660 {
661 .num = 2,
662 .pin = 12,
663 .reg = 0x24,
664 .bit = 8,
665 .mask = 0x3
666 }, {
667 .num = 2,
668 .pin = 15,
669 .reg = 0x28,
670 .bit = 0,
671 .mask = 0x7
672 }, {
673 .num = 2,
674 .pin = 23,
675 .reg = 0x30,
676 .bit = 14,
677 .mask = 0x3
678 },
679};
680
c04c3fa6
DW		 681static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
682 int *reg, u8 *bit, int *mask)
3818e4a7 683{
c04c3fa6
DW		 684 struct rockchip_pinctrl *info = bank->drvdata;
685 struct rockchip_pin_ctrl *ctrl = info->ctrl;
686 struct rockchip_mux_recalced_data *data;
3818e4a7 687 int i;
688
c04c3fa6
DW		 689 for (i = 0; i < ctrl->niomux_recalced; i++) {
690 data = &ctrl->iomux_recalced[i];
691 if (data->num == bank->bank_num &&
692 data->pin == pin)
3818e4a7 693 break;
c04c3fa6 694 }
3818e4a7 695
c04c3fa6 696 if (i >= ctrl->niomux_recalced)
3818e4a7 697 return;
698
699 *reg = data->reg;
700 *mask = data->mask;
701 *bit = data->bit;
702}
703
87065ca9
DW		 704static struct rockchip_mux_route_data px30_mux_route_data[] = {
705 {
706 /* cif-d2m0 */
707 .bank_num = 2,
708 .pin = 0,
709 .func = 1,
710 .route_offset = 0x184,
711 .route_val = BIT(16 + 7),
712 }, {
713 /* cif-d2m1 */
714 .bank_num = 3,
715 .pin = 3,
716 .func = 3,
717 .route_offset = 0x184,
718 .route_val = BIT(16 + 7) | BIT(7),
719 }, {
720 /* pdm-m0 */
721 .bank_num = 3,
722 .pin = 22,
723 .func = 2,
724 .route_offset = 0x184,
725 .route_val = BIT(16 + 8),
726 }, {
727 /* pdm-m1 */
728 .bank_num = 2,
729 .pin = 22,
730 .func = 1,
731 .route_offset = 0x184,
732 .route_val = BIT(16 + 8) | BIT(8),
733 }, {
734 /* uart2-rxm0 */
735 .bank_num = 1,
736 .pin = 27,
737 .func = 2,
738 .route_offset = 0x184,
739 .route_val = BIT(16 + 10),
740 }, {
741 /* uart2-rxm1 */
742 .bank_num = 2,
743 .pin = 14,
744 .func = 2,
745 .route_offset = 0x184,
746 .route_val = BIT(16 + 10) | BIT(10),
747 }, {
748 /* uart3-rxm0 */
749 .bank_num = 0,
750 .pin = 17,
751 .func = 2,
752 .route_offset = 0x184,
753 .route_val = BIT(16 + 9),
754 }, {
755 /* uart3-rxm1 */
756 .bank_num = 1,
757 .pin = 15,
758 .func = 2,
759 .route_offset = 0x184,
760 .route_val = BIT(16 + 9) | BIT(9),
761 },
762};
763
d23c66df
DW		 764static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
765 {
766 /* spi-0 */
767 .bank_num = 1,
768 .pin = 10,
769 .func = 1,
770 .route_offset = 0x144,
771 .route_val = BIT(16 + 3) | BIT(16 + 4),
772 }, {
773 /* spi-1 */
774 .bank_num = 1,
775 .pin = 27,
776 .func = 3,
777 .route_offset = 0x144,
778 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
779 }, {
780 /* spi-2 */
781 .bank_num = 0,
782 .pin = 13,
783 .func = 2,
784 .route_offset = 0x144,
785 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
786 }, {
787 /* i2s-0 */
788 .bank_num = 1,
789 .pin = 5,
790 .func = 1,
791 .route_offset = 0x144,
792 .route_val = BIT(16 + 5),
793 }, {
794 /* i2s-1 */
795 .bank_num = 0,
796 .pin = 14,
797 .func = 1,
798 .route_offset = 0x144,
799 .route_val = BIT(16 + 5) | BIT(5),
800 }, {
801 /* emmc-0 */
802 .bank_num = 1,
803 .pin = 22,
804 .func = 2,
805 .route_offset = 0x144,
806 .route_val = BIT(16 + 6),
807 }, {
808 /* emmc-1 */
809 .bank_num = 2,
810 .pin = 4,
811 .func = 2,
812 .route_offset = 0x144,
813 .route_val = BIT(16 + 6) | BIT(6),
814 },
815};
816
ada62b7c
HS		 817static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
818 {
819 /* non-iomuxed emmc/flash pins on flash-dqs */
820 .bank_num = 0,
821 .pin = 24,
822 .func = 1,
823 .route_location = ROCKCHIP_ROUTE_GRF,
824 .route_offset = 0xa0,
825 .route_val = BIT(16 + 11),
826 }, {
827 /* non-iomuxed emmc/flash pins on emmc-clk */
828 .bank_num = 0,
829 .pin = 24,
830 .func = 2,
831 .route_location = ROCKCHIP_ROUTE_GRF,
832 .route_offset = 0xa0,
833 .route_val = BIT(16 + 11) | BIT(11),
834 },
835};
836
d4970ee0
DW		 837static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
838 {
839 /* pwm0-0 */
840 .bank_num = 0,
841 .pin = 26,
842 .func = 1,
843 .route_offset = 0x50,
844 .route_val = BIT(16),
845 }, {
846 /* pwm0-1 */
847 .bank_num = 3,
848 .pin = 21,
849 .func = 1,
850 .route_offset = 0x50,
851 .route_val = BIT(16) | BIT(0),
852 }, {
853 /* pwm1-0 */
854 .bank_num = 0,
855 .pin = 27,
856 .func = 1,
857 .route_offset = 0x50,
858 .route_val = BIT(16 + 1),
859 }, {
860 /* pwm1-1 */
861 .bank_num = 0,
862 .pin = 30,
863 .func = 2,
864 .route_offset = 0x50,
865 .route_val = BIT(16 + 1) | BIT(1),
866 }, {
867 /* pwm2-0 */
868 .bank_num = 0,
869 .pin = 28,
870 .func = 1,
871 .route_offset = 0x50,
872 .route_val = BIT(16 + 2),
873 }, {
874 /* pwm2-1 */
875 .bank_num = 1,
876 .pin = 12,
877 .func = 2,
878 .route_offset = 0x50,
879 .route_val = BIT(16 + 2) | BIT(2),
880 }, {
881 /* pwm3-0 */
882 .bank_num = 3,
883 .pin = 26,
884 .func = 1,
885 .route_offset = 0x50,
886 .route_val = BIT(16 + 3),
887 }, {
888 /* pwm3-1 */
889 .bank_num = 1,
890 .pin = 11,
891 .func = 2,
892 .route_offset = 0x50,
893 .route_val = BIT(16 + 3) | BIT(3),
894 }, {
895 /* sdio-0_d0 */
896 .bank_num = 1,
897 .pin = 1,
898 .func = 1,
899 .route_offset = 0x50,
900 .route_val = BIT(16 + 4),
901 }, {
902 /* sdio-1_d0 */
903 .bank_num = 3,
904 .pin = 2,
905 .func = 1,
906 .route_offset = 0x50,
907 .route_val = BIT(16 + 4) | BIT(4),
908 }, {
909 /* spi-0_rx */
910 .bank_num = 0,
911 .pin = 13,
912 .func = 2,
913 .route_offset = 0x50,
914 .route_val = BIT(16 + 5),
915 }, {
916 /* spi-1_rx */
917 .bank_num = 2,
918 .pin = 0,
919 .func = 2,
920 .route_offset = 0x50,
921 .route_val = BIT(16 + 5) | BIT(5),
922 }, {
923 /* emmc-0_cmd */
924 .bank_num = 1,
925 .pin = 22,
926 .func = 2,
927 .route_offset = 0x50,
928 .route_val = BIT(16 + 7),
929 }, {
930 /* emmc-1_cmd */
931 .bank_num = 2,
932 .pin = 4,
933 .func = 2,
934 .route_offset = 0x50,
935 .route_val = BIT(16 + 7) | BIT(7),
936 }, {
937 /* uart2-0_rx */
938 .bank_num = 1,
939 .pin = 19,
940 .func = 2,
941 .route_offset = 0x50,
942 .route_val = BIT(16 + 8),
943 }, {
944 /* uart2-1_rx */
945 .bank_num = 1,
946 .pin = 10,
947 .func = 2,
948 .route_offset = 0x50,
949 .route_val = BIT(16 + 8) | BIT(8),
950 }, {
951 /* uart1-0_rx */
952 .bank_num = 1,
953 .pin = 10,
954 .func = 1,
955 .route_offset = 0x50,
956 .route_val = BIT(16 + 11),
957 }, {
958 /* uart1-1_rx */
959 .bank_num = 3,
960 .pin = 13,
961 .func = 1,
962 .route_offset = 0x50,
963 .route_val = BIT(16 + 11) | BIT(11),
964 },
965};
966
4e96fd30
HS		 967static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
968 {
969 /* edphdmi_cecinoutt1 */
970 .bank_num = 7,
971 .pin = 16,
972 .func = 2,
973 .route_offset = 0x264,
974 .route_val = BIT(16 + 12) | BIT(12),
975 }, {
976 /* edphdmi_cecinout */
977 .bank_num = 7,
978 .pin = 23,
979 .func = 4,
980 .route_offset = 0x264,
981 .route_val = BIT(16 + 12),
982 },
983};
984
cedc964a
DW		 985static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
986 {
987 /* uart2dbg_rxm0 */
988 .bank_num = 1,
989 .pin = 1,
990 .func = 2,
991 .route_offset = 0x50,
992 .route_val = BIT(16) | BIT(16 + 1),
993 }, {
994 /* uart2dbg_rxm1 */
995 .bank_num = 2,
996 .pin = 1,
997 .func = 1,
998 .route_offset = 0x50,
999 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1000 }, {
a976d7b1 1001 /* gmac-m1_rxd0 */
cedc964a
DW		 1002 .bank_num = 1,
1003 .pin = 11,
1004 .func = 2,
1005 .route_offset = 0x50,
a976d7b1
DW		 1006 .route_val = BIT(16 + 2) | BIT(2),
1007 }, {
1008 /* gmac-m1-optimized_rxd3 */
1009 .bank_num = 1,
1010 .pin = 14,
1011 .func = 2,
1012 .route_offset = 0x50,
1013 .route_val = BIT(16 + 10) | BIT(10),
cedc964a
DW		 1014 }, {
1015 /* pdm_sdi0m0 */
1016 .bank_num = 2,
1017 .pin = 19,
1018 .func = 2,
1019 .route_offset = 0x50,
1020 .route_val = BIT(16 + 3),
1021 }, {
1022 /* pdm_sdi0m1 */
1023 .bank_num = 1,
1024 .pin = 23,
1025 .func = 3,
1026 .route_offset = 0x50,
1027 .route_val = BIT(16 + 3) | BIT(3),
1028 }, {
1029 /* spi_rxdm2 */
1030 .bank_num = 3,
1031 .pin = 2,
1032 .func = 4,
1033 .route_offset = 0x50,
1034 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1035 }, {
1036 /* i2s2_sdim0 */
1037 .bank_num = 1,
1038 .pin = 24,
1039 .func = 1,
1040 .route_offset = 0x50,
1041 .route_val = BIT(16 + 6),
1042 }, {
1043 /* i2s2_sdim1 */
1044 .bank_num = 3,
1045 .pin = 2,
1046 .func = 6,
1047 .route_offset = 0x50,
1048 .route_val = BIT(16 + 6) | BIT(6),
1049 }, {
1050 /* card_iom1 */
1051 .bank_num = 2,
1052 .pin = 22,
1053 .func = 3,
1054 .route_offset = 0x50,
1055 .route_val = BIT(16 + 7) | BIT(7),
1056 }, {
1057 /* tsp_d5m1 */
1058 .bank_num = 2,
1059 .pin = 16,
1060 .func = 3,
1061 .route_offset = 0x50,
1062 .route_val = BIT(16 + 8) | BIT(8),
1063 }, {
1064 /* cif_data5m1 */
1065 .bank_num = 2,
1066 .pin = 16,
1067 .func = 4,
1068 .route_offset = 0x50,
1069 .route_val = BIT(16 + 9) | BIT(9),
1070 },
1071};
1072
accc1ce7
DW		 1073static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1074 {
1075 /* uart2dbga_rx */
1076 .bank_num = 4,
1077 .pin = 8,
1078 .func = 2,
1079 .route_offset = 0xe21c,
1080 .route_val = BIT(16 + 10) | BIT(16 + 11),
1081 }, {
1082 /* uart2dbgb_rx */
1083 .bank_num = 4,
1084 .pin = 16,
1085 .func = 2,
1086 .route_offset = 0xe21c,
1087 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1088 }, {
1089 /* uart2dbgc_rx */
1090 .bank_num = 4,
1091 .pin = 19,
1092 .func = 1,
1093 .route_offset = 0xe21c,
1094 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1095 }, {
1096 /* pcie_clkreqn */
1097 .bank_num = 2,
1098 .pin = 26,
1099 .func = 2,
1100 .route_offset = 0xe21c,
1101 .route_val = BIT(16 + 14),
1102 }, {
1103 /* pcie_clkreqnb */
1104 .bank_num = 4,
1105 .pin = 24,
1106 .func = 1,
1107 .route_offset = 0xe21c,
1108 .route_val = BIT(16 + 14) | BIT(14),
1109 },
1110};
1111
bd35b9bf 1112static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
51ff47aa 1113 int mux, u32 *loc, u32 *reg, u32 *value)
bd35b9bf
DW		 1114{
1115 struct rockchip_pinctrl *info = bank->drvdata;
1116 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1117 struct rockchip_mux_route_data *data;
1118 int i;
1119
1120 for (i = 0; i < ctrl->niomux_routes; i++) {
1121 data = &ctrl->iomux_routes[i];
1122 if ((data->bank_num == bank->bank_num) &&
1123 (data->pin == pin) && (data->func == mux))
1124 break;
1125 }
1126
1127 if (i >= ctrl->niomux_routes)
1128 return false;
1129
51ff47aa 1130 *loc = data->route_location;
bd35b9bf
DW		 1131 *reg = data->route_offset;
1132 *value = data->route_val;
1133
1134 return true;
1135}
1136
a076e2ed
HS		 1137static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1138{
1139 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 1140 int iomux_num = (pin / 8);
95ec8ae4 1141 struct regmap *regmap;
751a99ab 1142 unsigned int val;
ea262ad6 1143 int reg, ret, mask, mux_type;
a076e2ed
HS		 1144 u8 bit;
1145
fc72c923
HS		 1146 if (iomux_num > 3)
1147 return -EINVAL;
1148
62f49226
HS		 1149 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1150 dev_err(info->dev, "pin %d is unrouted\n", pin);
1151 return -EINVAL;
1152 }
1153
fc72c923 1154 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
a076e2ed
HS		 1155 return RK_FUNC_GPIO;
1156
95ec8ae4
HS		 1157 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1158 ? info->regmap_pmu : info->regmap_base;
1159
a076e2ed 1160 /* get basic quadrupel of mux registers and the correct reg inside */
ea262ad6 1161 mux_type = bank->iomux[iomux_num].type;
6bc0d121 1162 reg = bank->iomux[iomux_num].offset;
ea262ad6 1163 if (mux_type & IOMUX_WIDTH_4BIT) {
03716e1d
HS		 1164 if ((pin % 8) >= 4)
1165 reg += 0x4;
1166 bit = (pin % 4) * 4;
8b6c6f93 1167 mask = 0xf;
ea262ad6 1168 } else if (mux_type & IOMUX_WIDTH_3BIT) {
8b6c6f93 1169 if ((pin % 8) >= 5)
1170 reg += 0x4;
1171 bit = (pin % 8 % 5) * 3;
1172 mask = 0x7;
03716e1d
HS		 1173 } else {
1174 bit = (pin % 8) * 2;
8b6c6f93 1175 mask = 0x3;
03716e1d 1176 }
a076e2ed 1177
c04c3fa6
DW		 1178 if (bank->recalced_mask & BIT(pin))
1179 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
ea262ad6 1180
95ec8ae4 1181 ret = regmap_read(regmap, reg, &val);
751a99ab
HS		 1182 if (ret)
1183 return ret;
1184
03716e1d 1185 return ((val >> bit) & mask);
a076e2ed
HS		 1186}
1187
05709c3e
JK		 1188static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1189 int pin, int mux)
1190{
1191 struct rockchip_pinctrl *info = bank->drvdata;
1192 int iomux_num = (pin / 8);
1193
1194 if (iomux_num > 3)
1195 return -EINVAL;
1196
1197 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1198 dev_err(info->dev, "pin %d is unrouted\n", pin);
1199 return -EINVAL;
1200 }
1201
1202 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1203 if (mux != RK_FUNC_GPIO) {
1204 dev_err(info->dev,
1205 "pin %d only supports a gpio mux\n", pin);
1206 return -ENOTSUPP;
1207 }
1208 }
1209
1210 return 0;
1211}
1212
d3e51161
HS		 1213/*
1214 * Set a new mux function for a pin.
1215 *
1216 * The register is divided into the upper and lower 16 bit. When changing
1217 * a value, the previous register value is not read and changed. Instead
1218 * it seems the changed bits are marked in the upper 16 bit, while the
1219 * changed value gets set in the same offset in the lower 16 bit.
1220 * All pin settings seem to be 2 bit wide in both the upper and lower
1221 * parts.
1222 * @bank: pin bank to change
1223 * @pin: pin to change
1224 * @mux: new mux function to set
1225 */
14797189 1226static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 1227{
1228 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 1229 int iomux_num = (pin / 8);
95ec8ae4 1230 struct regmap *regmap;
ea262ad6 1231 int reg, ret, mask, mux_type;
d3e51161 1232 u8 bit;
51ff47aa 1233 u32 data, rmask, route_location, route_reg, route_val;
d3e51161 1234
05709c3e
JK		 1235 ret = rockchip_verify_mux(bank, pin, mux);
1236 if (ret < 0)
1237 return ret;
62f49226 1238
05709c3e
JK		 1239 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1240 return 0;
c4a532de 1241
d3e51161
HS		 1242 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1243 bank->bank_num, pin, mux);
1244
95ec8ae4
HS		 1245 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1246 ? info->regmap_pmu : info->regmap_base;
1247
d3e51161 1248 /* get basic quadrupel of mux registers and the correct reg inside */
ea262ad6 1249 mux_type = bank->iomux[iomux_num].type;
6bc0d121 1250 reg = bank->iomux[iomux_num].offset;
ea262ad6 1251 if (mux_type & IOMUX_WIDTH_4BIT) {
03716e1d
HS		 1252 if ((pin % 8) >= 4)
1253 reg += 0x4;
1254 bit = (pin % 4) * 4;
8b6c6f93 1255 mask = 0xf;
ea262ad6 1256 } else if (mux_type & IOMUX_WIDTH_3BIT) {
8b6c6f93 1257 if ((pin % 8) >= 5)
1258 reg += 0x4;
1259 bit = (pin % 8 % 5) * 3;
1260 mask = 0x7;
03716e1d
HS		 1261 } else {
1262 bit = (pin % 8) * 2;
8b6c6f93 1263 mask = 0x3;
03716e1d 1264 }
d3e51161 1265
c04c3fa6
DW		 1266 if (bank->recalced_mask & BIT(pin))
1267 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
ea262ad6 1268
bd35b9bf 1269 if (bank->route_mask & BIT(pin)) {
51ff47aa
HS		 1270 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1271 &route_reg, &route_val)) {
1272 struct regmap *route_regmap = regmap;
1273
1274 /* handle special locations */
1275 switch (route_location) {
1276 case ROCKCHIP_ROUTE_PMU:
1277 route_regmap = info->regmap_pmu;
1278 break;
1279 case ROCKCHIP_ROUTE_GRF:
1280 route_regmap = info->regmap_base;
1281 break;
1282 }
1283
1284 ret = regmap_write(route_regmap, route_reg, route_val);
bd35b9bf
DW		 1285 if (ret)
1286 return ret;
1287 }
1288 }
1289
03716e1d 1290 data = (mask << (bit + 16));
99e872d9 1291 rmask = data | (data >> 16);
03716e1d 1292 data |= (mux & mask) << bit;
99e872d9 1293 ret = regmap_update_bits(regmap, reg, rmask, data);
d3e51161 1294
751a99ab 1295 return ret;
d3e51161
HS		 1296}
1297
87065ca9
DW		 1298#define PX30_PULL_PMU_OFFSET 0x10
1299#define PX30_PULL_GRF_OFFSET 0x60
1300#define PX30_PULL_BITS_PER_PIN 2
1301#define PX30_PULL_PINS_PER_REG 8
1302#define PX30_PULL_BANK_STRIDE 16
1303
1304static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1305 int pin_num, struct regmap **regmap,
1306 int *reg, u8 *bit)
1307{
1308 struct rockchip_pinctrl *info = bank->drvdata;
1309
1310 /* The first 32 pins of the first bank are located in PMU */
1311 if (bank->bank_num == 0) {
1312 *regmap = info->regmap_pmu;
1313 *reg = PX30_PULL_PMU_OFFSET;
1314 } else {
1315 *regmap = info->regmap_base;
1316 *reg = PX30_PULL_GRF_OFFSET;
1317
1318 /* correct the offset, as we're starting with the 2nd bank */
1319 *reg -= 0x10;
1320 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1321 }
1322
1323 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1324 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1325 *bit *= PX30_PULL_BITS_PER_PIN;
1326}
1327
1328#define PX30_DRV_PMU_OFFSET 0x20
1329#define PX30_DRV_GRF_OFFSET 0xf0
1330#define PX30_DRV_BITS_PER_PIN 2
1331#define PX30_DRV_PINS_PER_REG 8
1332#define PX30_DRV_BANK_STRIDE 16
1333
1334static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1335 int pin_num, struct regmap **regmap,
1336 int *reg, u8 *bit)
1337{
1338 struct rockchip_pinctrl *info = bank->drvdata;
1339
1340 /* The first 32 pins of the first bank are located in PMU */
1341 if (bank->bank_num == 0) {
1342 *regmap = info->regmap_pmu;
1343 *reg = PX30_DRV_PMU_OFFSET;
1344 } else {
1345 *regmap = info->regmap_base;
1346 *reg = PX30_DRV_GRF_OFFSET;
1347
1348 /* correct the offset, as we're starting with the 2nd bank */
1349 *reg -= 0x10;
1350 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1351 }
1352
1353 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1354 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1355 *bit *= PX30_DRV_BITS_PER_PIN;
1356}
1357
1358#define PX30_SCHMITT_PMU_OFFSET 0x38
1359#define PX30_SCHMITT_GRF_OFFSET 0xc0
1360#define PX30_SCHMITT_PINS_PER_PMU_REG 16
1361#define PX30_SCHMITT_BANK_STRIDE 16
1362#define PX30_SCHMITT_PINS_PER_GRF_REG 8
1363
1364static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1365 int pin_num,
1366 struct regmap **regmap,
1367 int *reg, u8 *bit)
1368{
1369 struct rockchip_pinctrl *info = bank->drvdata;
1370 int pins_per_reg;
1371
1372 if (bank->bank_num == 0) {
1373 *regmap = info->regmap_pmu;
1374 *reg = PX30_SCHMITT_PMU_OFFSET;
1375 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1376 } else {
1377 *regmap = info->regmap_base;
1378 *reg = PX30_SCHMITT_GRF_OFFSET;
1379 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1380 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1381 }
1382
1383 *reg += ((pin_num / pins_per_reg) * 4);
1384 *bit = pin_num % pins_per_reg;
1385
1386 return 0;
1387}
1388
b9c6dcab
AY		 1389#define RV1108_PULL_PMU_OFFSET 0x10
1390#define RV1108_PULL_OFFSET 0x110
1391#define RV1108_PULL_PINS_PER_REG 8
1392#define RV1108_PULL_BITS_PER_PIN 2
1393#define RV1108_PULL_BANK_STRIDE 16
688daf23 1394
b9c6dcab 1395static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
688daf23
AY		 1396 int pin_num, struct regmap **regmap,
1397 int *reg, u8 *bit)
1398{
1399 struct rockchip_pinctrl *info = bank->drvdata;
1400
1401 /* The first 24 pins of the first bank are located in PMU */
1402 if (bank->bank_num == 0) {
1403 *regmap = info->regmap_pmu;
b9c6dcab 1404 *reg = RV1108_PULL_PMU_OFFSET;
688daf23 1405 } else {
b9c6dcab 1406 *reg = RV1108_PULL_OFFSET;
688daf23
AY		 1407 *regmap = info->regmap_base;
1408 /* correct the offset, as we're starting with the 2nd bank */
1409 *reg -= 0x10;
b9c6dcab 1410 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
688daf23
AY		 1411 }
1412
b9c6dcab
AY		 1413 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1414 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1415 *bit *= RV1108_PULL_BITS_PER_PIN;
688daf23
AY		 1416}
1417
b9c6dcab
AY		 1418#define RV1108_DRV_PMU_OFFSET 0x20
1419#define RV1108_DRV_GRF_OFFSET 0x210
1420#define RV1108_DRV_BITS_PER_PIN 2
1421#define RV1108_DRV_PINS_PER_REG 8
1422#define RV1108_DRV_BANK_STRIDE 16
688daf23 1423
b9c6dcab 1424static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
688daf23
AY		 1425 int pin_num, struct regmap **regmap,
1426 int *reg, u8 *bit)
1427{
1428 struct rockchip_pinctrl *info = bank->drvdata;
1429
1430 /* The first 24 pins of the first bank are located in PMU */
1431 if (bank->bank_num == 0) {
1432 *regmap = info->regmap_pmu;
b9c6dcab 1433 *reg = RV1108_DRV_PMU_OFFSET;
688daf23
AY		 1434 } else {
1435 *regmap = info->regmap_base;
b9c6dcab 1436 *reg = RV1108_DRV_GRF_OFFSET;
688daf23
AY		 1437
1438 /* correct the offset, as we're starting with the 2nd bank */
1439 *reg -= 0x10;
b9c6dcab 1440 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
688daf23
AY		 1441 }
1442
b9c6dcab
AY		 1443 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1444 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1445 *bit *= RV1108_DRV_BITS_PER_PIN;
688daf23
AY		 1446}
1447
5caff7ea
AY		 1448#define RV1108_SCHMITT_PMU_OFFSET 0x30
1449#define RV1108_SCHMITT_GRF_OFFSET 0x388
1450#define RV1108_SCHMITT_BANK_STRIDE 8
1451#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1452#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1453
1454static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1455 int pin_num,
1456 struct regmap **regmap,
1457 int *reg, u8 *bit)
1458{
1459 struct rockchip_pinctrl *info = bank->drvdata;
1460 int pins_per_reg;
1461
1462 if (bank->bank_num == 0) {
1463 *regmap = info->regmap_pmu;
1464 *reg = RV1108_SCHMITT_PMU_OFFSET;
1465 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1466 } else {
1467 *regmap = info->regmap_base;
1468 *reg = RV1108_SCHMITT_GRF_OFFSET;
1469 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1470 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1471 }
1472 *reg += ((pin_num / pins_per_reg) * 4);
1473 *bit = pin_num % pins_per_reg;
1474
1475 return 0;
1476}
1477
a282926d
HS		 1478#define RK2928_PULL_OFFSET 0x118
1479#define RK2928_PULL_PINS_PER_REG 16
1480#define RK2928_PULL_BANK_STRIDE 8
1481
1482static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 1483 int pin_num, struct regmap **regmap,
1484 int *reg, u8 *bit)
a282926d
HS		 1485{
1486 struct rockchip_pinctrl *info = bank->drvdata;
1487
751a99ab
HS		 1488 *regmap = info->regmap_base;
1489 *reg = RK2928_PULL_OFFSET;
a282926d
HS		 1490 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1491 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1492
1493 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1494};
1495
d23c66df
DW		 1496#define RK3128_PULL_OFFSET 0x118
1497
1498static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1499 int pin_num, struct regmap **regmap,
1500 int *reg, u8 *bit)
1501{
1502 struct rockchip_pinctrl *info = bank->drvdata;
1503
1504 *regmap = info->regmap_base;
1505 *reg = RK3128_PULL_OFFSET;
1506 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1507 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1508
1509 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1510}
1511
bfc7a42a 1512#define RK3188_PULL_OFFSET 0x164
6ca5274d
HS		 1513#define RK3188_PULL_BITS_PER_PIN 2
1514#define RK3188_PULL_PINS_PER_REG 8
1515#define RK3188_PULL_BANK_STRIDE 16
14dee867 1516#define RK3188_PULL_PMU_OFFSET 0x64
6ca5274d
HS		 1517
1518static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 1519 int pin_num, struct regmap **regmap,
1520 int *reg, u8 *bit)
6ca5274d
HS		 1521{
1522 struct rockchip_pinctrl *info = bank->drvdata;
1523
1524 /* The first 12 pins of the first bank are located elsewhere */
fc72c923 1525 if (bank->bank_num == 0 && pin_num < 12) {
14dee867
HS		 1526 *regmap = info->regmap_pmu ? info->regmap_pmu
1527 : bank->regmap_pull;
1528 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
751a99ab 1529 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
6ca5274d
HS		 1530 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1531 *bit *= RK3188_PULL_BITS_PER_PIN;
1532 } else {
751a99ab
HS		 1533 *regmap = info->regmap_pull ? info->regmap_pull
1534 : info->regmap_base;
1535 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1536
bfc7a42a
HS		 1537 /* correct the offset, as it is the 2nd pull register */
1538 *reg -= 4;
6ca5274d
HS		 1539 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1540 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1541
1542 /*
1543 * The bits in these registers have an inverse ordering
1544 * with the lowest pin being in bits 15:14 and the highest
1545 * pin in bits 1:0
1546 */
1547 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1548 *bit *= RK3188_PULL_BITS_PER_PIN;
1549 }
1550}
1551
304f077d
HS		 1552#define RK3288_PULL_OFFSET 0x140
1553static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1554 int pin_num, struct regmap **regmap,
1555 int *reg, u8 *bit)
1556{
1557 struct rockchip_pinctrl *info = bank->drvdata;
1558
1559 /* The first 24 pins of the first bank are located in PMU */
1560 if (bank->bank_num == 0) {
1561 *regmap = info->regmap_pmu;
1562 *reg = RK3188_PULL_PMU_OFFSET;
1563
1564 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1565 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1566 *bit *= RK3188_PULL_BITS_PER_PIN;
1567 } else {
1568 *regmap = info->regmap_base;
1569 *reg = RK3288_PULL_OFFSET;
1570
1571 /* correct the offset, as we're starting with the 2nd bank */
1572 *reg -= 0x10;
1573 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1574 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1575
1576 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1577 *bit *= RK3188_PULL_BITS_PER_PIN;
1578 }
1579}
1580
b547c800
HS		 1581#define RK3288_DRV_PMU_OFFSET 0x70
1582#define RK3288_DRV_GRF_OFFSET 0x1c0
1583#define RK3288_DRV_BITS_PER_PIN 2
1584#define RK3288_DRV_PINS_PER_REG 8
1585#define RK3288_DRV_BANK_STRIDE 16
b547c800
HS		 1586
1587static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1588 int pin_num, struct regmap **regmap,
1589 int *reg, u8 *bit)
1590{
1591 struct rockchip_pinctrl *info = bank->drvdata;
1592
1593 /* The first 24 pins of the first bank are located in PMU */
1594 if (bank->bank_num == 0) {
1595 *regmap = info->regmap_pmu;
1596 *reg = RK3288_DRV_PMU_OFFSET;
1597
1598 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1599 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1600 *bit *= RK3288_DRV_BITS_PER_PIN;
1601 } else {
1602 *regmap = info->regmap_base;
1603 *reg = RK3288_DRV_GRF_OFFSET;
1604
1605 /* correct the offset, as we're starting with the 2nd bank */
1606 *reg -= 0x10;
1607 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1608 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1609
1610 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1611 *bit *= RK3288_DRV_BITS_PER_PIN;
1612 }
1613}
1614
fea0fe60
JC		 1615#define RK3228_PULL_OFFSET 0x100
1616
1617static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1618 int pin_num, struct regmap **regmap,
1619 int *reg, u8 *bit)
1620{
1621 struct rockchip_pinctrl *info = bank->drvdata;
1622
1623 *regmap = info->regmap_base;
1624 *reg = RK3228_PULL_OFFSET;
1625 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1626 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1627
1628 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1629 *bit *= RK3188_PULL_BITS_PER_PIN;
1630}
1631
1632#define RK3228_DRV_GRF_OFFSET 0x200
1633
1634static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1635 int pin_num, struct regmap **regmap,
1636 int *reg, u8 *bit)
1637{
1638 struct rockchip_pinctrl *info = bank->drvdata;
1639
1640 *regmap = info->regmap_base;
1641 *reg = RK3228_DRV_GRF_OFFSET;
1642 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1643 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1644
1645 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1646 *bit *= RK3288_DRV_BITS_PER_PIN;
1647}
1648
daecdc66
HS		 1649#define RK3368_PULL_GRF_OFFSET 0x100
1650#define RK3368_PULL_PMU_OFFSET 0x10
1651
1652static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1653 int pin_num, struct regmap **regmap,
1654 int *reg, u8 *bit)
1655{
1656 struct rockchip_pinctrl *info = bank->drvdata;
1657
1658 /* The first 32 pins of the first bank are located in PMU */
1659 if (bank->bank_num == 0) {
1660 *regmap = info->regmap_pmu;
1661 *reg = RK3368_PULL_PMU_OFFSET;
1662
1663 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1664 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1665 *bit *= RK3188_PULL_BITS_PER_PIN;
1666 } else {
1667 *regmap = info->regmap_base;
1668 *reg = RK3368_PULL_GRF_OFFSET;
1669
1670 /* correct the offset, as we're starting with the 2nd bank */
1671 *reg -= 0x10;
1672 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1673 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1674
1675 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1676 *bit *= RK3188_PULL_BITS_PER_PIN;
1677 }
1678}
1679
1680#define RK3368_DRV_PMU_OFFSET 0x20
1681#define RK3368_DRV_GRF_OFFSET 0x200
1682
1683static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1684 int pin_num, struct regmap **regmap,
1685 int *reg, u8 *bit)
1686{
1687 struct rockchip_pinctrl *info = bank->drvdata;
1688
1689 /* The first 32 pins of the first bank are located in PMU */
1690 if (bank->bank_num == 0) {
1691 *regmap = info->regmap_pmu;
1692 *reg = RK3368_DRV_PMU_OFFSET;
1693
1694 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1695 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1696 *bit *= RK3288_DRV_BITS_PER_PIN;
1697 } else {
1698 *regmap = info->regmap_base;
1699 *reg = RK3368_DRV_GRF_OFFSET;
1700
1701 /* correct the offset, as we're starting with the 2nd bank */
1702 *reg -= 0x10;
1703 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1704 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1705
1706 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1707 *bit *= RK3288_DRV_BITS_PER_PIN;
1708 }
1709}
1710
b6c23275
DW		 1711#define RK3399_PULL_GRF_OFFSET 0xe040
1712#define RK3399_PULL_PMU_OFFSET 0x40
1713#define RK3399_DRV_3BITS_PER_PIN 3
1714
1715static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1716 int pin_num, struct regmap **regmap,
1717 int *reg, u8 *bit)
1718{
1719 struct rockchip_pinctrl *info = bank->drvdata;
1720
1721 /* The bank0:16 and bank1:32 pins are located in PMU */
1722 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1723 *regmap = info->regmap_pmu;
1724 *reg = RK3399_PULL_PMU_OFFSET;
1725
1726 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1727
1728 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1729 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1730 *bit *= RK3188_PULL_BITS_PER_PIN;
1731 } else {
1732 *regmap = info->regmap_base;
1733 *reg = RK3399_PULL_GRF_OFFSET;
1734
1735 /* correct the offset, as we're starting with the 3rd bank */
1736 *reg -= 0x20;
1737 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1738 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1739
1740 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1741 *bit *= RK3188_PULL_BITS_PER_PIN;
1742 }
1743}
1744
1745static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1746 int pin_num, struct regmap **regmap,
1747 int *reg, u8 *bit)
1748{
1749 struct rockchip_pinctrl *info = bank->drvdata;
1750 int drv_num = (pin_num / 8);
1751
1752 /* The bank0:16 and bank1:32 pins are located in PMU */
1753 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1754 *regmap = info->regmap_pmu;
1755 else
1756 *regmap = info->regmap_base;
1757
1758 *reg = bank->drv[drv_num].offset;
1759 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1760 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1761 *bit = (pin_num % 8) * 3;
1762 else
1763 *bit = (pin_num % 8) * 2;
1764}
1765
1766static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1767 { 2, 4, 8, 12, -1, -1, -1, -1 },
1768 { 3, 6, 9, 12, -1, -1, -1, -1 },
1769 { 5, 10, 15, 20, -1, -1, -1, -1 },
1770 { 4, 6, 8, 10, 12, 14, 16, 18 },
1771 { 4, 7, 10, 13, 16, 19, 22, 26 }
1772};
ef17f69f
HS		 1773
1774static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1775 int pin_num)
b547c800 1776{
ef17f69f
HS		 1777 struct rockchip_pinctrl *info = bank->drvdata;
1778 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 1779 struct regmap *regmap;
1780 int reg, ret;
b6c23275 1781 u32 data, temp, rmask_bits;
b547c800 1782 u8 bit;
b6c23275 1783 int drv_type = bank->drv[pin_num / 8].drv_type;
b547c800 1784
ef17f69f 1785 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800 1786
b6c23275
DW		 1787 switch (drv_type) {
1788 case DRV_TYPE_IO_1V8_3V0_AUTO:
1789 case DRV_TYPE_IO_3V3_ONLY:
1790 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1791 switch (bit) {
1792 case 0 ... 12:
1793 /* regular case, nothing to do */
1794 break;
1795 case 15:
1796 /*
1797 * drive-strength offset is special, as it is
1798 * spread over 2 registers
1799 */
1800 ret = regmap_read(regmap, reg, &data);
1801 if (ret)
1802 return ret;
1803
1804 ret = regmap_read(regmap, reg + 0x4, &temp);
1805 if (ret)
1806 return ret;
1807
1808 /*
1809 * the bit data[15] contains bit 0 of the value
1810 * while temp[1:0] contains bits 2 and 1
1811 */
1812 data >>= 15;
1813 temp &= 0x3;
1814 temp <<= 1;
1815 data |= temp;
1816
1817 return rockchip_perpin_drv_list[drv_type][data];
1818 case 18 ... 21:
1819 /* setting fully enclosed in the second register */
1820 reg += 4;
1821 bit -= 16;
1822 break;
1823 default:
1824 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1825 bit, drv_type);
1826 return -EINVAL;
1827 }
1828
1829 break;
1830 case DRV_TYPE_IO_DEFAULT:
1831 case DRV_TYPE_IO_1V8_OR_3V0:
1832 case DRV_TYPE_IO_1V8_ONLY:
1833 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1834 break;
1835 default:
1836 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1837 drv_type);
1838 return -EINVAL;
1839 }
1840
b547c800
HS		 1841 ret = regmap_read(regmap, reg, &data);
1842 if (ret)
1843 return ret;
1844
1845 data >>= bit;
b6c23275 1846 data &= (1 << rmask_bits) - 1;
b547c800 1847
b6c23275 1848 return rockchip_perpin_drv_list[drv_type][data];
b547c800
HS		 1849}
1850
ef17f69f
HS		 1851static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1852 int pin_num, int strength)
b547c800
HS		 1853{
1854 struct rockchip_pinctrl *info = bank->drvdata;
ef17f69f 1855 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800 1856 struct regmap *regmap;
b547c800 1857 int reg, ret, i;
b6c23275 1858 u32 data, rmask, rmask_bits, temp;
b547c800 1859 u8 bit;
b6c23275
DW		 1860 int drv_type = bank->drv[pin_num / 8].drv_type;
1861
1862 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1863 bank->bank_num, pin_num, strength);
b547c800 1864
ef17f69f 1865 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800
HS		 1866
1867 ret = -EINVAL;
b6c23275
DW		 1868 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1869 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
b547c800
HS		 1870 ret = i;
1871 break;
b6c23275
DW		 1872 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1873 ret = rockchip_perpin_drv_list[drv_type][i];
1874 break;
b547c800
HS		 1875 }
1876 }
1877
1878 if (ret < 0) {
1879 dev_err(info->dev, "unsupported driver strength %d\n",
1880 strength);
1881 return ret;
1882 }
1883
b6c23275
DW		 1884 switch (drv_type) {
1885 case DRV_TYPE_IO_1V8_3V0_AUTO:
1886 case DRV_TYPE_IO_3V3_ONLY:
1887 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1888 switch (bit) {
1889 case 0 ... 12:
1890 /* regular case, nothing to do */
1891 break;
1892 case 15:
1893 /*
1894 * drive-strength offset is special, as it is spread
1895 * over 2 registers, the bit data[15] contains bit 0
1896 * of the value while temp[1:0] contains bits 2 and 1
1897 */
1898 data = (ret & 0x1) << 15;
1899 temp = (ret >> 0x1) & 0x3;
1900
1901 rmask = BIT(15) | BIT(31);
1902 data |= BIT(31);
1903 ret = regmap_update_bits(regmap, reg, rmask, data);
f07bedc3 1904 if (ret)
b6c23275 1905 return ret;
b6c23275
DW		 1906
1907 rmask = 0x3 | (0x3 << 16);
1908 temp |= (0x3 << 16);
1909 reg += 0x4;
1910 ret = regmap_update_bits(regmap, reg, rmask, temp);
1911
b6c23275
DW		 1912 return ret;
1913 case 18 ... 21:
1914 /* setting fully enclosed in the second register */
1915 reg += 4;
1916 bit -= 16;
1917 break;
1918 default:
b6c23275
DW		 1919 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1920 bit, drv_type);
1921 return -EINVAL;
1922 }
1923 break;
1924 case DRV_TYPE_IO_DEFAULT:
1925 case DRV_TYPE_IO_1V8_OR_3V0:
1926 case DRV_TYPE_IO_1V8_ONLY:
1927 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1928 break;
1929 default:
b6c23275
DW		 1930 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1931 drv_type);
1932 return -EINVAL;
1933 }
1934
b547c800 1935 /* enable the write to the equivalent lower bits */
b6c23275 1936 data = ((1 << rmask_bits) - 1) << (bit + 16);
99e872d9 1937 rmask = data | (data >> 16);
b547c800
HS		 1938 data |= (ret << bit);
1939
99e872d9 1940 ret = regmap_update_bits(regmap, reg, rmask, data);
b547c800
HS		 1941
1942 return ret;
1943}
1944
3ba6767a
DW		 1945static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1946 {
1947 PIN_CONFIG_BIAS_DISABLE,
1948 PIN_CONFIG_BIAS_PULL_UP,
1949 PIN_CONFIG_BIAS_PULL_DOWN,
1950 PIN_CONFIG_BIAS_BUS_HOLD
1951 },
1952 {
1953 PIN_CONFIG_BIAS_DISABLE,
1954 PIN_CONFIG_BIAS_PULL_DOWN,
1955 PIN_CONFIG_BIAS_DISABLE,
1956 PIN_CONFIG_BIAS_PULL_UP
1957 },
1958};
1959
d3e51161
HS		 1960static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1961{
1962 struct rockchip_pinctrl *info = bank->drvdata;
1963 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 1964 struct regmap *regmap;
3ba6767a 1965 int reg, ret, pull_type;
d3e51161 1966 u8 bit;
6ca5274d 1967 u32 data;
d3e51161
HS		 1968
1969 /* rk3066b does support any pulls */
a282926d 1970 if (ctrl->type == RK3066B)
d3e51161
HS		 1971 return PIN_CONFIG_BIAS_DISABLE;
1972
751a99ab
HS		 1973 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1974
1975 ret = regmap_read(regmap, reg, &data);
1976 if (ret)
1977 return ret;
6ca5274d 1978
a282926d
HS		 1979 switch (ctrl->type) {
1980 case RK2928:
d23c66df 1981 case RK3128:
751a99ab 1982 return !(data & BIT(bit))
d3e51161
HS		 1983 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1984 : PIN_CONFIG_BIAS_DISABLE;
87065ca9 1985 case PX30:
b9c6dcab 1986 case RV1108:
a282926d 1987 case RK3188:
66d750e1 1988 case RK3288:
daecdc66 1989 case RK3368:
b6c23275 1990 case RK3399:
3ba6767a 1991 pull_type = bank->pull_type[pin_num / 8];
751a99ab 1992 data >>= bit;
6ca5274d
HS		 1993 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1994
3ba6767a 1995 return rockchip_pull_list[pull_type][data];
a282926d
HS		 1996 default:
1997 dev_err(info->dev, "unsupported pinctrl type\n");
1998 return -EINVAL;
1999 };
d3e51161
HS		 2000}
2001
2002static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2003 int pin_num, int pull)
2004{
2005 struct rockchip_pinctrl *info = bank->drvdata;
2006 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 2007 struct regmap *regmap;
3ba6767a 2008 int reg, ret, i, pull_type;
d3e51161 2009 u8 bit;
99e872d9 2010 u32 data, rmask;
d3e51161
HS		 2011
2012 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2013 bank->bank_num, pin_num, pull);
2014
2015 /* rk3066b does support any pulls */
a282926d 2016 if (ctrl->type == RK3066B)
d3e51161
HS		 2017 return pull ? -EINVAL : 0;
2018
751a99ab 2019 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
6ca5274d 2020
a282926d
HS		 2021 switch (ctrl->type) {
2022 case RK2928:
d23c66df 2023 case RK3128:
d3e51161
HS		 2024 data = BIT(bit + 16);
2025 if (pull == PIN_CONFIG_BIAS_DISABLE)
2026 data |= BIT(bit);
751a99ab 2027 ret = regmap_write(regmap, reg, data);
a282926d 2028 break;
87065ca9 2029 case PX30:
b9c6dcab 2030 case RV1108:
a282926d 2031 case RK3188:
66d750e1 2032 case RK3288:
daecdc66 2033 case RK3368:
b6c23275 2034 case RK3399:
3ba6767a
DW		 2035 pull_type = bank->pull_type[pin_num / 8];
2036 ret = -EINVAL;
2037 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2038 i++) {
2039 if (rockchip_pull_list[pull_type][i] == pull) {
2040 ret = i;
2041 break;
2042 }
2043 }
2044
2045 if (ret < 0) {
2046 dev_err(info->dev, "unsupported pull setting %d\n",
2047 pull);
2048 return ret;
2049 }
2050
6ca5274d
HS		 2051 /* enable the write to the equivalent lower bits */
2052 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
99e872d9 2053 rmask = data | (data >> 16);
3ba6767a 2054 data |= (ret << bit);
6ca5274d 2055
99e872d9 2056 ret = regmap_update_bits(regmap, reg, rmask, data);
6ca5274d 2057 break;
a282926d
HS		 2058 default:
2059 dev_err(info->dev, "unsupported pinctrl type\n");
2060 return -EINVAL;
d3e51161
HS		 2061 }
2062
751a99ab 2063 return ret;
d3e51161
HS		 2064}
2065
728d3f5a 2066#define RK3328_SCHMITT_BITS_PER_PIN 1
2067#define RK3328_SCHMITT_PINS_PER_REG 16
2068#define RK3328_SCHMITT_BANK_STRIDE 8
2069#define RK3328_SCHMITT_GRF_OFFSET 0x380
2070
2071static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2072 int pin_num,
2073 struct regmap **regmap,
2074 int *reg, u8 *bit)
2075{
2076 struct rockchip_pinctrl *info = bank->drvdata;
2077
2078 *regmap = info->regmap_base;
2079 *reg = RK3328_SCHMITT_GRF_OFFSET;
2080
2081 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2082 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2083 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2084
2085 return 0;
2086}
2087
e3b357d7 2088static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2089{
2090 struct rockchip_pinctrl *info = bank->drvdata;
2091 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2092 struct regmap *regmap;
2093 int reg, ret;
2094 u8 bit;
2095 u32 data;
2096
2097 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2098 if (ret)
2099 return ret;
2100
2101 ret = regmap_read(regmap, reg, &data);
2102 if (ret)
2103 return ret;
2104
2105 data >>= bit;
2106 return data & 0x1;
2107}
2108
2109static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2110 int pin_num, int enable)
2111{
2112 struct rockchip_pinctrl *info = bank->drvdata;
2113 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2114 struct regmap *regmap;
2115 int reg, ret;
e3b357d7 2116 u8 bit;
2117 u32 data, rmask;
2118
2119 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2120 bank->bank_num, pin_num, enable);
2121
2122 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2123 if (ret)
2124 return ret;
2125
e3b357d7 2126 /* enable the write to the equivalent lower bits */
2127 data = BIT(bit + 16) | (enable << bit);
2128 rmask = BIT(bit + 16) | BIT(bit);
2129
f07bedc3 2130 return regmap_update_bits(regmap, reg, rmask, data);
e3b357d7 2131}
2132
d3e51161
HS		 2133/*
2134 * Pinmux_ops handling
2135 */
2136
2137static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2138{
2139 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2140
2141 return info->nfunctions;
2142}
2143
2144static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2145 unsigned selector)
2146{
2147 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2148
2149 return info->functions[selector].name;
2150}
2151
2152static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2153 unsigned selector, const char * const **groups,
2154 unsigned * const num_groups)
2155{
2156 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2157
2158 *groups = info->functions[selector].groups;
2159 *num_groups = info->functions[selector].ngroups;
2160
2161 return 0;
2162}
2163
03e9f0ca
LW		 2164static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2165 unsigned group)
d3e51161
HS		 2166{
2167 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2168 const unsigned int *pins = info->groups[group].pins;
2169 const struct rockchip_pin_config *data = info->groups[group].data;
2170 struct rockchip_pin_bank *bank;
14797189 2171 int cnt, ret = 0;
d3e51161
HS		 2172
2173 dev_dbg(info->dev, "enable function %s group %s\n",
2174 info->functions[selector].name, info->groups[group].name);
2175
2176 /*
85dc397a 2177 * for each pin in the pin group selected, program the corresponding
d3e51161
HS		 2178 * pin function number in the config register.
2179 */
2180 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2181 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 2182 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2183 data[cnt].func);
2184 if (ret)
2185 break;
2186 }
2187
2188 if (ret) {
2189 /* revert the already done pin settings */
2190 for (cnt--; cnt >= 0; cnt--)
2191 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2192
2193 return ret;
d3e51161
HS		 2194 }
2195
2196 return 0;
2197}
2198
6ba20a00
CW		 2199static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2200{
2201 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2202 u32 data;
5c9d8c4f 2203 int ret;
6ba20a00 2204
5c9d8c4f
BN		 2205 ret = clk_enable(bank->clk);
2206 if (ret < 0) {
2207 dev_err(bank->drvdata->dev,
2208 "failed to enable clock for bank %s\n", bank->name);
2209 return ret;
2210 }
6ba20a00 2211 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
5c9d8c4f 2212 clk_disable(bank->clk);
6ba20a00
CW		 2213
2214 return !(data & BIT(offset));
2215}
2216
d3e51161
HS		 2217/*
2218 * The calls to gpio_direction_output() and gpio_direction_input()
2219 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2220 * function called from the gpiolib interface).
2221 */
e5c2c9db
DA		 2222static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2223 int pin, bool input)
d3e51161 2224{
d3e51161 2225 struct rockchip_pin_bank *bank;
e5c2c9db 2226 int ret;
fab262f5 2227 unsigned long flags;
d3e51161
HS		 2228 u32 data;
2229
03bf81f1 2230 bank = gpiochip_get_data(chip);
d3e51161 2231
14797189
HS		 2232 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2233 if (ret < 0)
2234 return ret;
d3e51161 2235
07a06ae9 2236 clk_enable(bank->clk);
70b7aa7a 2237 raw_spin_lock_irqsave(&bank->slock, flags);
fab262f5 2238
d3e51161
HS		 2239 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2240 /* set bit to 1 for output, 0 for input */
2241 if (!input)
2242 data |= BIT(pin);
2243 else
2244 data &= ~BIT(pin);
2245 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2246
70b7aa7a 2247 raw_spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 2248 clk_disable(bank->clk);
fab262f5 2249
d3e51161
HS		 2250 return 0;
2251}
2252
e5c2c9db
DA		 2253static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2254 struct pinctrl_gpio_range *range,
2255 unsigned offset, bool input)
2256{
2257 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2258 struct gpio_chip *chip;
2259 int pin;
2260
2261 chip = range->gc;
2262 pin = offset - chip->base;
2263 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2264 offset, range->name, pin, input ? "input" : "output");
2265
2266 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2267 input);
2268}
2269
d3e51161
HS		 2270static const struct pinmux_ops rockchip_pmx_ops = {
2271 .get_functions_count = rockchip_pmx_get_funcs_count,
2272 .get_function_name = rockchip_pmx_get_func_name,
2273 .get_function_groups = rockchip_pmx_get_groups,
03e9f0ca 2274 .set_mux = rockchip_pmx_set,
d3e51161
HS		 2275 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2276};
2277
2278/*
2279 * Pinconf_ops handling
2280 */
2281
44b6d930
HS		 2282static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2283 enum pin_config_param pull)
2284{
a282926d
HS		 2285 switch (ctrl->type) {
2286 case RK2928:
d23c66df 2287 case RK3128:
a282926d
HS		 2288 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2289 pull == PIN_CONFIG_BIAS_DISABLE);
2290 case RK3066B:
44b6d930 2291 return pull ? false : true;
87065ca9 2292 case PX30:
b9c6dcab 2293 case RV1108:
a282926d 2294 case RK3188:
66d750e1 2295 case RK3288:
daecdc66 2296 case RK3368:
b6c23275 2297 case RK3399:
a282926d 2298 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 2299 }
2300
a282926d 2301 return false;
44b6d930
HS		 2302}
2303
e5c2c9db 2304static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
a076e2ed
HS		 2305static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2306
d3e51161
HS		 2307/* set the pin config settings for a specified pin */
2308static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 2309 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 2310{
2311 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2312 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9 2313 enum pin_config_param param;
58957d2e 2314 u32 arg;
03b054e9
SY		 2315 int i;
2316 int rc;
2317
2318 for (i = 0; i < num_configs; i++) {
2319 param = pinconf_to_config_param(configs[i]);
2320 arg = pinconf_to_config_argument(configs[i]);
2321
2322 switch (param) {
2323 case PIN_CONFIG_BIAS_DISABLE:
2324 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2325 param);
2326 if (rc)
2327 return rc;
2328 break;
2329 case PIN_CONFIG_BIAS_PULL_UP:
2330 case PIN_CONFIG_BIAS_PULL_DOWN:
2331 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 2332 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 2333 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2334 return -ENOTSUPP;
2335
2336 if (!arg)
2337 return -EINVAL;
2338
2339 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2340 param);
2341 if (rc)
2342 return rc;
2343 break;
a076e2ed 2344 case PIN_CONFIG_OUTPUT:
e5c2c9db
DA		 2345 rockchip_gpio_set(&bank->gpio_chip,
2346 pin - bank->pin_base, arg);
2347 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2348 pin - bank->pin_base, false);
a076e2ed
HS		 2349 if (rc)
2350 return rc;
2351 break;
b547c800
HS		 2352 case PIN_CONFIG_DRIVE_STRENGTH:
2353 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 2354 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 2355 return -ENOTSUPP;
2356
ef17f69f
HS		 2357 rc = rockchip_set_drive_perpin(bank,
2358 pin - bank->pin_base, arg);
b547c800
HS		 2359 if (rc < 0)
2360 return rc;
2361 break;
e3b357d7 2362 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2363 if (!info->ctrl->schmitt_calc_reg)
2364 return -ENOTSUPP;
2365
2366 rc = rockchip_set_schmitt(bank,
2367 pin - bank->pin_base, arg);
2368 if (rc < 0)
2369 return rc;
2370 break;
03b054e9 2371 default:
44b6d930 2372 return -ENOTSUPP;
03b054e9
SY		 2373 break;
2374 }
2375 } /* for each config */
d3e51161
HS		 2376
2377 return 0;
2378}
2379
2380/* get the pin config settings for a specified pin */
2381static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2382 unsigned long *config)
2383{
2384 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2385 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2386 enum pin_config_param param = pinconf_to_config_param(*config);
dab3eba7 2387 u16 arg;
a076e2ed 2388 int rc;
d3e51161
HS		 2389
2390 switch (param) {
2391 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 2392 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2393 return -EINVAL;
2394
dab3eba7 2395 arg = 0;
44b6d930 2396 break;
d3e51161
HS		 2397 case PIN_CONFIG_BIAS_PULL_UP:
2398 case PIN_CONFIG_BIAS_PULL_DOWN:
2399 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 2400 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 2401 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2402 return -ENOTSUPP;
d3e51161 2403
44b6d930 2404 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 2405 return -EINVAL;
2406
dab3eba7 2407 arg = 1;
d3e51161 2408 break;
a076e2ed
HS		 2409 case PIN_CONFIG_OUTPUT:
2410 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2411 if (rc != RK_FUNC_GPIO)
2412 return -EINVAL;
2413
2414 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2415 if (rc < 0)
2416 return rc;
2417
2418 arg = rc ? 1 : 0;
2419 break;
b547c800
HS		 2420 case PIN_CONFIG_DRIVE_STRENGTH:
2421 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 2422 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 2423 return -ENOTSUPP;
2424
ef17f69f 2425 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
b547c800
HS		 2426 if (rc < 0)
2427 return rc;
2428
e3b357d7 2429 arg = rc;
2430 break;
2431 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2432 if (!info->ctrl->schmitt_calc_reg)
2433 return -ENOTSUPP;
2434
2435 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2436 if (rc < 0)
2437 return rc;
2438
b547c800
HS		 2439 arg = rc;
2440 break;
d3e51161
HS		 2441 default:
2442 return -ENOTSUPP;
2443 break;
2444 }
2445
dab3eba7
HS		 2446 *config = pinconf_to_config_packed(param, arg);
2447
d3e51161
HS		 2448 return 0;
2449}
2450
2451static const struct pinconf_ops rockchip_pinconf_ops = {
2452 .pin_config_get = rockchip_pinconf_get,
2453 .pin_config_set = rockchip_pinconf_set,
ed62f2f2 2454 .is_generic = true,
d3e51161
HS		 2455};
2456
65fca613
HS		 2457static const struct of_device_id rockchip_bank_match[] = {
2458 { .compatible = "rockchip,gpio-bank" },
6ca5274d 2459 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 2460 {},
2461};
d3e51161
HS		 2462
2463static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2464 struct device_node *np)
2465{
2466 struct device_node *child;
2467
2468 for_each_child_of_node(np, child) {
65fca613 2469 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 2470 continue;
2471
2472 info->nfunctions++;
2473 info->ngroups += of_get_child_count(child);
2474 }
2475}
2476
2477static int rockchip_pinctrl_parse_groups(struct device_node *np,
2478 struct rockchip_pin_group *grp,
2479 struct rockchip_pinctrl *info,
2480 u32 index)
2481{
2482 struct rockchip_pin_bank *bank;
2483 int size;
2484 const __be32 *list;
2485 int num;
2486 int i, j;
2487 int ret;
2488
94f4e54c 2489 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
d3e51161
HS		 2490
2491 /* Initialise group */
2492 grp->name = np->name;
2493
2494 /*
2495 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2496 * do sanity check and calculate pins number
2497 */
2498 list = of_get_property(np, "rockchip,pins", &size);
2499 /* we do not check return since it's safe node passed down */
2500 size /= sizeof(*list);
2501 if (!size || size % 4) {
2502 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2503 return -EINVAL;
2504 }
2505
2506 grp->npins = size / 4;
2507
a86854d0 2508 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
d3e51161 2509 GFP_KERNEL);
a86854d0
KC		 2510 grp->data = devm_kcalloc(info->dev,
2511 grp->npins,
2512 sizeof(struct rockchip_pin_config),
d3e51161
HS		 2513 GFP_KERNEL);
2514 if (!grp->pins || !grp->data)
2515 return -ENOMEM;
2516
2517 for (i = 0, j = 0; i < size; i += 4, j++) {
2518 const __be32 *phandle;
2519 struct device_node *np_config;
2520
2521 num = be32_to_cpu(*list++);
2522 bank = bank_num_to_bank(info, num);
2523 if (IS_ERR(bank))
2524 return PTR_ERR(bank);
2525
2526 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2527 grp->data[j].func = be32_to_cpu(*list++);
2528
2529 phandle = list++;
2530 if (!phandle)
2531 return -EINVAL;
2532
2533 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
dd4d01f7 2534 ret = pinconf_generic_parse_dt_config(np_config, NULL,
d3e51161
HS		 2535 &grp->data[j].configs, &grp->data[j].nconfigs);
2536 if (ret)
2537 return ret;
2538 }
2539
2540 return 0;
2541}
2542
2543static int rockchip_pinctrl_parse_functions(struct device_node *np,
2544 struct rockchip_pinctrl *info,
2545 u32 index)
2546{
2547 struct device_node *child;
2548 struct rockchip_pmx_func *func;
2549 struct rockchip_pin_group *grp;
2550 int ret;
2551 static u32 grp_index;
2552 u32 i = 0;
2553
94f4e54c 2554 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
d3e51161
HS		 2555
2556 func = &info->functions[index];
2557
2558 /* Initialise function */
2559 func->name = np->name;
2560 func->ngroups = of_get_child_count(np);
2561 if (func->ngroups <= 0)
2562 return 0;
2563
a86854d0
KC		 2564 func->groups = devm_kcalloc(info->dev,
2565 func->ngroups, sizeof(char *), GFP_KERNEL);
d3e51161
HS		 2566 if (!func->groups)
2567 return -ENOMEM;
2568
2569 for_each_child_of_node(np, child) {
2570 func->groups[i] = child->name;
2571 grp = &info->groups[grp_index++];
2572 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
f7a81b7f
JL		 2573 if (ret) {
2574 of_node_put(child);
d3e51161 2575 return ret;
f7a81b7f 2576 }
d3e51161
HS		 2577 }
2578
2579 return 0;
2580}
2581
2582static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2583 struct rockchip_pinctrl *info)
2584{
2585 struct device *dev = &pdev->dev;
2586 struct device_node *np = dev->of_node;
2587 struct device_node *child;
2588 int ret;
2589 int i;
2590
2591 rockchip_pinctrl_child_count(info, np);
2592
2593 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2594 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2595
a86854d0
KC		 2596 info->functions = devm_kcalloc(dev,
2597 info->nfunctions,
d3e51161
HS		 2598 sizeof(struct rockchip_pmx_func),
2599 GFP_KERNEL);
98c8ee73 2600 if (!info->functions)
d3e51161 2601 return -EINVAL;
d3e51161 2602
a86854d0
KC		 2603 info->groups = devm_kcalloc(dev,
2604 info->ngroups,
d3e51161
HS		 2605 sizeof(struct rockchip_pin_group),
2606 GFP_KERNEL);
98c8ee73 2607 if (!info->groups)
d3e51161 2608 return -EINVAL;
d3e51161
HS		 2609
2610 i = 0;
2611
2612 for_each_child_of_node(np, child) {
65fca613 2613 if (of_match_node(rockchip_bank_match, child))
d3e51161 2614 continue;
65fca613 2615
d3e51161
HS		 2616 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2617 if (ret) {
2618 dev_err(&pdev->dev, "failed to parse function\n");
f7a81b7f 2619 of_node_put(child);
d3e51161
HS		 2620 return ret;
2621 }
2622 }
2623
2624 return 0;
2625}
2626
2627static int rockchip_pinctrl_register(struct platform_device *pdev,
2628 struct rockchip_pinctrl *info)
2629{
2630 struct pinctrl_desc *ctrldesc = &info->pctl;
2631 struct pinctrl_pin_desc *pindesc, *pdesc;
2632 struct rockchip_pin_bank *pin_bank;
2633 int pin, bank, ret;
2634 int k;
2635
2636 ctrldesc->name = "rockchip-pinctrl";
2637 ctrldesc->owner = THIS_MODULE;
2638 ctrldesc->pctlops = &rockchip_pctrl_ops;
2639 ctrldesc->pmxops = &rockchip_pmx_ops;
2640 ctrldesc->confops = &rockchip_pinconf_ops;
2641
a86854d0
KC		 2642 pindesc = devm_kcalloc(&pdev->dev,
2643 info->ctrl->nr_pins, sizeof(*pindesc),
2644 GFP_KERNEL);
98c8ee73 2645 if (!pindesc)
d3e51161 2646 return -ENOMEM;
98c8ee73 2647
d3e51161
HS		 2648 ctrldesc->pins = pindesc;
2649 ctrldesc->npins = info->ctrl->nr_pins;
2650
2651 pdesc = pindesc;
2652 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2653 pin_bank = &info->ctrl->pin_banks[bank];
2654 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2655 pdesc->number = k;
2656 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2657 pin_bank->name, pin);
2658 pdesc++;
2659 }
2660 }
2661
0fb7dcb1
DA		 2662 ret = rockchip_pinctrl_parse_dt(pdev, info);
2663 if (ret)
2664 return ret;
2665
0085a2b4 2666 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
323de9ef 2667 if (IS_ERR(info->pctl_dev)) {
d3e51161 2668 dev_err(&pdev->dev, "could not register pinctrl driver\n");
323de9ef 2669 return PTR_ERR(info->pctl_dev);
d3e51161
HS		 2670 }
2671
2672 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2673 pin_bank = &info->ctrl->pin_banks[bank];
2674 pin_bank->grange.name = pin_bank->name;
2675 pin_bank->grange.id = bank;
2676 pin_bank->grange.pin_base = pin_bank->pin_base;
2677 pin_bank->grange.base = pin_bank->gpio_chip.base;
2678 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2679 pin_bank->grange.gc = &pin_bank->gpio_chip;
2680 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2681 }
2682
d3e51161
HS		 2683 return 0;
2684}
2685
2686/*
2687 * GPIO handling
2688 */
2689
2690static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2691{
03bf81f1 2692 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2693 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2694 unsigned long flags;
2695 u32 data;
2696
07a06ae9 2697 clk_enable(bank->clk);
70b7aa7a 2698 raw_spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 2699
2700 data = readl(reg);
2701 data &= ~BIT(offset);
2702 if (value)
2703 data |= BIT(offset);
2704 writel(data, reg);
2705
70b7aa7a 2706 raw_spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 2707 clk_disable(bank->clk);
d3e51161
HS		 2708}
2709
2710/*
2711 * Returns the level of the pin for input direction and setting of the DR
2712 * register for output gpios.
2713 */
2714static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2715{
03bf81f1 2716 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2717 u32 data;
2718
07a06ae9 2719 clk_enable(bank->clk);
d3e51161 2720 data = readl(bank->reg_base + GPIO_EXT_PORT);
07a06ae9 2721 clk_disable(bank->clk);
d3e51161
HS		 2722 data >>= offset;
2723 data &= 1;
2724 return data;
2725}
2726
2727/*
2728 * gpiolib gpio_direction_input callback function. The setting of the pin
85dc397a 2729 * mux function as 'gpio input' will be handled by the pinctrl subsystem
d3e51161
HS		 2730 * interface.
2731 */
2732static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2733{
2734 return pinctrl_gpio_direction_input(gc->base + offset);
2735}
2736
2737/*
2738 * gpiolib gpio_direction_output callback function. The setting of the pin
85dc397a 2739 * mux function as 'gpio output' will be handled by the pinctrl subsystem
d3e51161
HS		 2740 * interface.
2741 */
2742static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2743 unsigned offset, int value)
2744{
2745 rockchip_gpio_set(gc, offset, value);
2746 return pinctrl_gpio_direction_output(gc->base + offset);
2747}
2748
b97038af
SL		 2749static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2750 unsigned int offset, bool enable)
2751{
2752 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2753 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2754 unsigned long flags;
2755 u32 data;
2756
2757 clk_enable(bank->clk);
2758 raw_spin_lock_irqsave(&bank->slock, flags);
2759
2760 data = readl(reg);
2761 if (enable)
2762 data |= BIT(offset);
2763 else
2764 data &= ~BIT(offset);
2765 writel(data, reg);
2766
2767 raw_spin_unlock_irqrestore(&bank->slock, flags);
2768 clk_disable(bank->clk);
2769}
2770
2771/*
2772 * gpiolib set_config callback function. The setting of the pin
2773 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2774 * interface.
2775 */
2776static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2777 unsigned long config)
2778{
2779 enum pin_config_param param = pinconf_to_config_param(config);
2780
2781 switch (param) {
2782 case PIN_CONFIG_INPUT_DEBOUNCE:
2783 rockchip_gpio_set_debounce(gc, offset, true);
2784 /*
2785 * Rockchip's gpio could only support up to one period
2786 * of the debounce clock(pclk), which is far away from
2787 * satisftying the requirement, as pclk is usually near
2788 * 100MHz shared by all peripherals. So the fact is it
2789 * has crippled debounce capability could only be useful
2790 * to prevent any spurious glitches from waking up the system
2791 * if the gpio is conguired as wakeup interrupt source. Let's
2792 * still return -ENOTSUPP as before, to make sure the caller
2793 * of gpiod_set_debounce won't change its behaviour.
2794 */
2795 default:
2796 return -ENOTSUPP;
2797 }
2798}
2799
d3e51161
HS		 2800/*
2801 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2802 * and a virtual IRQ, if not already present.
2803 */
2804static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2805{
03bf81f1 2806 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2807 unsigned int virq;
2808
2809 if (!bank->domain)
2810 return -ENXIO;
2811
2812 virq = irq_create_mapping(bank->domain, offset);
2813
2814 return (virq) ? : -ENXIO;
2815}
2816
2817static const struct gpio_chip rockchip_gpiolib_chip = {
98c85d58
JG		 2818 .request = gpiochip_generic_request,
2819 .free = gpiochip_generic_free,
d3e51161
HS		 2820 .set = rockchip_gpio_set,
2821 .get = rockchip_gpio_get,
6ba20a00 2822 .get_direction = rockchip_gpio_get_direction,
d3e51161
HS		 2823 .direction_input = rockchip_gpio_direction_input,
2824 .direction_output = rockchip_gpio_direction_output,
b97038af 2825 .set_config = rockchip_gpio_set_config,
d3e51161
HS		 2826 .to_irq = rockchip_gpio_to_irq,
2827 .owner = THIS_MODULE,
2828};
2829
2830/*
2831 * Interrupt handling
2832 */
2833
bd0b9ac4 2834static void rockchip_irq_demux(struct irq_desc *desc)
d3e51161 2835{
5663bb27
JL		 2836 struct irq_chip *chip = irq_desc_get_chip(desc);
2837 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
d3e51161
HS		 2838 u32 pend;
2839
2840 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2841
2842 chained_irq_enter(chip, desc);
2843
2844 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2845
2846 while (pend) {
415f748c 2847 unsigned int irq, virq;
d3e51161
HS		 2848
2849 irq = __ffs(pend);
2850 pend &= ~BIT(irq);
2851 virq = irq_linear_revmap(bank->domain, irq);
2852
2853 if (!virq) {
2854 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2855 continue;
2856 }
2857
2858 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2859
5a927501
HS		 2860 /*
2861 * Triggering IRQ on both rising and falling edge
2862 * needs manual intervention.
2863 */
2864 if (bank->toggle_edge_mode & BIT(irq)) {
53b1bfc7
DA		 2865 u32 data, data_old, polarity;
2866 unsigned long flags;
2867
2868 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2869 do {
70b7aa7a 2870 raw_spin_lock_irqsave(&bank->slock, flags);
53b1bfc7
DA		 2871
2872 polarity = readl_relaxed(bank->reg_base +
2873 GPIO_INT_POLARITY);
2874 if (data & BIT(irq))
2875 polarity &= ~BIT(irq);
2876 else
2877 polarity |= BIT(irq);
2878 writel(polarity,
2879 bank->reg_base + GPIO_INT_POLARITY);
2880
70b7aa7a 2881 raw_spin_unlock_irqrestore(&bank->slock, flags);
53b1bfc7
DA		 2882
2883 data_old = data;
2884 data = readl_relaxed(bank->reg_base +
2885 GPIO_EXT_PORT);
2886 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
5a927501
HS		 2887 }
2888
d3e51161
HS		 2889 generic_handle_irq(virq);
2890 }
2891
2892 chained_irq_exit(chip, desc);
2893}
2894
2895static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2896{
2897 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2898 struct rockchip_pin_bank *bank = gc->private;
2899 u32 mask = BIT(d->hwirq);
2900 u32 polarity;
2901 u32 level;
2902 u32 data;
fab262f5 2903 unsigned long flags;
14797189 2904 int ret;
d3e51161 2905
5a927501 2906 /* make sure the pin is configured as gpio input */
1d80df93 2907 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
14797189
HS		 2908 if (ret < 0)
2909 return ret;
2910
1d80df93 2911 clk_enable(bank->clk);
70b7aa7a 2912 raw_spin_lock_irqsave(&bank->slock, flags);
fab262f5 2913
5a927501
HS		 2914 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2915 data &= ~mask;
2916 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2917
70b7aa7a 2918 raw_spin_unlock_irqrestore(&bank->slock, flags);
fab262f5 2919
d3e51161 2920 if (type & IRQ_TYPE_EDGE_BOTH)
2dbf1bc5 2921 irq_set_handler_locked(d, handle_edge_irq);
d3e51161 2922 else
2dbf1bc5 2923 irq_set_handler_locked(d, handle_level_irq);
d3e51161 2924
70b7aa7a 2925 raw_spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 2926 irq_gc_lock(gc);
2927
2928 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2929 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2930
2931 switch (type) {
5a927501
HS		 2932 case IRQ_TYPE_EDGE_BOTH:
2933 bank->toggle_edge_mode |= mask;
2934 level |= mask;
2935
2936 /*
2937 * Determine gpio state. If 1 next interrupt should be falling
2938 * otherwise rising.
2939 */
2940 data = readl(bank->reg_base + GPIO_EXT_PORT);
2941 if (data & mask)
2942 polarity &= ~mask;
2943 else
2944 polarity |= mask;
2945 break;
d3e51161 2946 case IRQ_TYPE_EDGE_RISING:
5a927501 2947 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2948 level |= mask;
2949 polarity |= mask;
2950 break;
2951 case IRQ_TYPE_EDGE_FALLING:
5a927501 2952 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2953 level |= mask;
2954 polarity &= ~mask;
2955 break;
2956 case IRQ_TYPE_LEVEL_HIGH:
5a927501 2957 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2958 level &= ~mask;
2959 polarity |= mask;
2960 break;
2961 case IRQ_TYPE_LEVEL_LOW:
5a927501 2962 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2963 level &= ~mask;
2964 polarity &= ~mask;
2965 break;
2966 default:
7cc5f970 2967 irq_gc_unlock(gc);
70b7aa7a 2968 raw_spin_unlock_irqrestore(&bank->slock, flags);
1d80df93 2969 clk_disable(bank->clk);
d3e51161
HS		 2970 return -EINVAL;
2971 }
2972
2973 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2974 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2975
2976 irq_gc_unlock(gc);
70b7aa7a 2977 raw_spin_unlock_irqrestore(&bank->slock, flags);
1d80df93 2978 clk_disable(bank->clk);
d3e51161 2979
d3e51161
HS		 2980 return 0;
2981}
2982
68bda47c
DA		 2983static void rockchip_irq_suspend(struct irq_data *d)
2984{
2985 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2986 struct rockchip_pin_bank *bank = gc->private;
2987
07a06ae9 2988 clk_enable(bank->clk);
5ae0c7ad
DA		 2989 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2990 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
07a06ae9 2991 clk_disable(bank->clk);
68bda47c
DA		 2992}
2993
2994static void rockchip_irq_resume(struct irq_data *d)
2995{
2996 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2997 struct rockchip_pin_bank *bank = gc->private;
2998
07a06ae9 2999 clk_enable(bank->clk);
5ae0c7ad 3000 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
07a06ae9
LH		 3001 clk_disable(bank->clk);
3002}
3003
d468289a 3004static void rockchip_irq_enable(struct irq_data *d)
07a06ae9
LH		 3005{
3006 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3007 struct rockchip_pin_bank *bank = gc->private;
3008
3009 clk_enable(bank->clk);
3010 irq_gc_mask_clr_bit(d);
3011}
3012
d468289a 3013static void rockchip_irq_disable(struct irq_data *d)
07a06ae9
LH		 3014{
3015 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3016 struct rockchip_pin_bank *bank = gc->private;
3017
3018 irq_gc_mask_set_bit(d);
3019 clk_disable(bank->clk);
f2dd028c
DA		 3020}
3021
d3e51161
HS		 3022static int rockchip_interrupts_register(struct platform_device *pdev,
3023 struct rockchip_pinctrl *info)
3024{
3025 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3026 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3027 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3028 struct irq_chip_generic *gc;
3029 int ret;
07a06ae9 3030 int i, j;
d3e51161
HS		 3031
3032 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3033 if (!bank->valid) {
3034 dev_warn(&pdev->dev, "bank %s is not valid\n",
3035 bank->name);
3036 continue;
3037 }
3038
07a06ae9
LH		 3039 ret = clk_enable(bank->clk);
3040 if (ret) {
3041 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3042 bank->name);
3043 continue;
3044 }
3045
d3e51161
HS		 3046 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3047 &irq_generic_chip_ops, NULL);
3048 if (!bank->domain) {
3049 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3050 bank->name);
07a06ae9 3051 clk_disable(bank->clk);
d3e51161
HS		 3052 continue;
3053 }
3054
3055 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3056 "rockchip_gpio_irq", handle_level_irq,
3057 clr, 0, IRQ_GC_INIT_MASK_CACHE);
3058 if (ret) {
3059 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3060 bank->name);
3061 irq_domain_remove(bank->domain);
07a06ae9 3062 clk_disable(bank->clk);
d3e51161
HS		 3063 continue;
3064 }
3065
5ae0c7ad
DA		 3066 /*
3067 * Linux assumes that all interrupts start out disabled/masked.
3068 * Our driver only uses the concept of masked and always keeps
3069 * things enabled, so for us that's all masked and all enabled.
3070 */
3071 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3072 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3073
d3e51161
HS		 3074 gc = irq_get_domain_generic_chip(bank->domain, 0);
3075 gc->reg_base = bank->reg_base;
3076 gc->private = bank;
f2dd028c 3077 gc->chip_types[0].regs.mask = GPIO_INTMASK;
d3e51161
HS		 3078 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3079 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
d468289a
JC		 3080 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3081 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3082 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3083 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
d3e51161 3084 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
68bda47c
DA		 3085 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3086 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
d3e51161 3087 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
876d716b 3088 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
d3e51161 3089
03051bc2
TG		 3090 irq_set_chained_handler_and_data(bank->irq,
3091 rockchip_irq_demux, bank);
07a06ae9
LH		 3092
3093 /* map the gpio irqs here, when the clock is still running */
3094 for (j = 0 ; j < 32 ; j++)
3095 irq_create_mapping(bank->domain, j);
3096
3097 clk_disable(bank->clk);
d3e51161
HS		 3098 }
3099
3100 return 0;
3101}
3102
3103static int rockchip_gpiolib_register(struct platform_device *pdev,
3104 struct rockchip_pinctrl *info)
3105{
3106 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3107 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3108 struct gpio_chip *gc;
3109 int ret;
3110 int i;
3111
3112 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3113 if (!bank->valid) {
3114 dev_warn(&pdev->dev, "bank %s is not valid\n",
3115 bank->name);
3116 continue;
3117 }
3118
3119 bank->gpio_chip = rockchip_gpiolib_chip;
3120
3121 gc = &bank->gpio_chip;
3122 gc->base = bank->pin_base;
3123 gc->ngpio = bank->nr_pins;
58383c78 3124 gc->parent = &pdev->dev;
d3e51161
HS		 3125 gc->of_node = bank->of_node;
3126 gc->label = bank->name;
3127
03bf81f1 3128 ret = gpiochip_add_data(gc, bank);
d3e51161
HS		 3129 if (ret) {
3130 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3131 gc->label, ret);
3132 goto fail;
3133 }
3134 }
3135
3136 rockchip_interrupts_register(pdev, info);
3137
3138 return 0;
3139
3140fail:
3141 for (--i, --bank; i >= 0; --i, --bank) {
3142 if (!bank->valid)
3143 continue;
b4e7c55d 3144 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 3145 }
3146 return ret;
3147}
3148
3149static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3150 struct rockchip_pinctrl *info)
3151{
3152 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3153 struct rockchip_pin_bank *bank = ctrl->pin_banks;
d3e51161
HS		 3154 int i;
3155
b4e7c55d 3156 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
d3e51161
HS		 3157 if (!bank->valid)
3158 continue;
b4e7c55d 3159 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 3160 }
3161
b4e7c55d 3162 return 0;
d3e51161
HS		 3163}
3164
3165static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
622f3237 3166 struct rockchip_pinctrl *info)
d3e51161
HS		 3167{
3168 struct resource res;
751a99ab 3169 void __iomem *base;
d3e51161
HS		 3170
3171 if (of_address_to_resource(bank->of_node, 0, &res)) {
622f3237 3172 dev_err(info->dev, "cannot find IO resource for bank\n");
d3e51161
HS		 3173 return -ENOENT;
3174 }
3175
622f3237 3176 bank->reg_base = devm_ioremap_resource(info->dev, &res);
d3e51161
HS		 3177 if (IS_ERR(bank->reg_base))
3178 return PTR_ERR(bank->reg_base);
3179
6ca5274d
HS		 3180 /*
3181 * special case, where parts of the pull setting-registers are
3182 * part of the PMU register space
3183 */
3184 if (of_device_is_compatible(bank->of_node,
3185 "rockchip,rk3188-gpio-bank0")) {
a658efaa 3186 struct device_node *node;
bfc7a42a 3187
a658efaa
HS		 3188 node = of_parse_phandle(bank->of_node->parent,
3189 "rockchip,pmu", 0);
3190 if (!node) {
3191 if (of_address_to_resource(bank->of_node, 1, &res)) {
3192 dev_err(info->dev, "cannot find IO resource for bank\n");
3193 return -ENOENT;
3194 }
3195
3196 base = devm_ioremap_resource(info->dev, &res);
3197 if (IS_ERR(base))
3198 return PTR_ERR(base);
3199 rockchip_regmap_config.max_register =
3200 resource_size(&res) - 4;
3201 rockchip_regmap_config.name =
3202 "rockchip,rk3188-gpio-bank0-pull";
3203 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3204 base,
3205 &rockchip_regmap_config);
6ca5274d 3206 }
6ca5274d 3207 }
65fca613 3208
d3e51161
HS		 3209 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3210
3211 bank->clk = of_clk_get(bank->of_node, 0);
3212 if (IS_ERR(bank->clk))
3213 return PTR_ERR(bank->clk);
3214
07a06ae9 3215 return clk_prepare(bank->clk);
d3e51161
HS		 3216}
3217
3218static const struct of_device_id rockchip_pinctrl_dt_match[];
3219
3220/* retrieve the soc specific data */
3221static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3222 struct rockchip_pinctrl *d,
3223 struct platform_device *pdev)
3224{
3225 const struct of_device_id *match;
3226 struct device_node *node = pdev->dev.of_node;
3227 struct device_node *np;
3228 struct rockchip_pin_ctrl *ctrl;
3229 struct rockchip_pin_bank *bank;
b6c23275 3230 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
d3e51161
HS		 3231
3232 match = of_match_node(rockchip_pinctrl_dt_match, node);
3233 ctrl = (struct rockchip_pin_ctrl *)match->data;
3234
3235 for_each_child_of_node(node, np) {
3236 if (!of_find_property(np, "gpio-controller", NULL))
3237 continue;
3238
3239 bank = ctrl->pin_banks;
3240 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3241 if (!strcmp(bank->name, np->name)) {
3242 bank->of_node = np;
3243
622f3237 3244 if (!rockchip_get_bank_data(bank, d))
d3e51161
HS		 3245 bank->valid = true;
3246
3247 break;
3248 }
3249 }
3250 }
3251
95ec8ae4
HS		 3252 grf_offs = ctrl->grf_mux_offset;
3253 pmu_offs = ctrl->pmu_mux_offset;
b6c23275
DW		 3254 drv_pmu_offs = ctrl->pmu_drv_offset;
3255 drv_grf_offs = ctrl->grf_drv_offset;
d3e51161
HS		 3256 bank = ctrl->pin_banks;
3257 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
6bc0d121
HS		 3258 int bank_pins = 0;
3259
70b7aa7a 3260 raw_spin_lock_init(&bank->slock);
d3e51161
HS		 3261 bank->drvdata = d;
3262 bank->pin_base = ctrl->nr_pins;
3263 ctrl->nr_pins += bank->nr_pins;
6bc0d121 3264
b6c23275 3265 /* calculate iomux and drv offsets */
6bc0d121
HS		 3266 for (j = 0; j < 4; j++) {
3267 struct rockchip_iomux *iom = &bank->iomux[j];
b6c23275 3268 struct rockchip_drv *drv = &bank->drv[j];
03716e1d 3269 int inc;
6bc0d121
HS		 3270
3271 if (bank_pins >= bank->nr_pins)
3272 break;
3273
b6c23275 3274 /* preset iomux offset value, set new start value */
6bc0d121 3275 if (iom->offset >= 0) {
95ec8ae4
HS		 3276 if (iom->type & IOMUX_SOURCE_PMU)
3277 pmu_offs = iom->offset;
3278 else
3279 grf_offs = iom->offset;
b6c23275 3280 } else { /* set current iomux offset */
95ec8ae4
HS		 3281 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3282 pmu_offs : grf_offs;
6bc0d121
HS		 3283 }
3284
b6c23275
DW		 3285 /* preset drv offset value, set new start value */
3286 if (drv->offset >= 0) {
3287 if (iom->type & IOMUX_SOURCE_PMU)
3288 drv_pmu_offs = drv->offset;
3289 else
3290 drv_grf_offs = drv->offset;
3291 } else { /* set current drv offset */
3292 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3293 drv_pmu_offs : drv_grf_offs;
3294 }
3295
3296 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3297 i, j, iom->offset, drv->offset);
6bc0d121
HS		 3298
3299 /*
3300 * Increase offset according to iomux width.
03716e1d 3301 * 4bit iomux'es are spread over two registers.
6bc0d121 3302 */
8b6c6f93 3303 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3304 IOMUX_WIDTH_3BIT)) ? 8 : 4;
95ec8ae4
HS		 3305 if (iom->type & IOMUX_SOURCE_PMU)
3306 pmu_offs += inc;
3307 else
3308 grf_offs += inc;
6bc0d121 3309
b6c23275
DW		 3310 /*
3311 * Increase offset according to drv width.
3312 * 3bit drive-strenth'es are spread over two registers.
3313 */
3314 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3315 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3316 inc = 8;
3317 else
3318 inc = 4;
3319
3320 if (iom->type & IOMUX_SOURCE_PMU)
3321 drv_pmu_offs += inc;
3322 else
3323 drv_grf_offs += inc;
3324
6bc0d121
HS		 3325 bank_pins += 8;
3326 }
bd35b9bf 3327
c04c3fa6
DW		 3328 /* calculate the per-bank recalced_mask */
3329 for (j = 0; j < ctrl->niomux_recalced; j++) {
3330 int pin = 0;
3331
3332 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3333 pin = ctrl->iomux_recalced[j].pin;
3334 bank->recalced_mask |= BIT(pin);
3335 }
3336 }
3337
bd35b9bf
DW		 3338 /* calculate the per-bank route_mask */
3339 for (j = 0; j < ctrl->niomux_routes; j++) {
3340 int pin = 0;
3341
3342 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3343 pin = ctrl->iomux_routes[j].pin;
3344 bank->route_mask |= BIT(pin);
3345 }
3346 }
d3e51161
HS		 3347 }
3348
3349 return ctrl;
3350}
3351
8dca9331
CZ		 3352#define RK3288_GRF_GPIO6C_IOMUX 0x64
3353#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3354
3355static u32 rk3288_grf_gpio6c_iomux;
3356
9198f509
CZ		 3357static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3358{
3359 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 3360 int ret = pinctrl_force_sleep(info->pctl_dev);
3361
3362 if (ret)
3363 return ret;
3364
3365 /*
3366 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3367 * the setting here, and restore it at resume.
3368 */
3369 if (info->ctrl->type == RK3288) {
3370 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3371 &rk3288_grf_gpio6c_iomux);
3372 if (ret) {
3373 pinctrl_force_default(info->pctl_dev);
3374 return ret;
3375 }
3376 }
9198f509 3377
8dca9331 3378 return 0;
9198f509
CZ		 3379}
3380
3381static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3382{
3383 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 3384 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3385 rk3288_grf_gpio6c_iomux |
3386 GPIO6C6_SEL_WRITE_ENABLE);
3387
3388 if (ret)
3389 return ret;
9198f509
CZ		 3390
3391 return pinctrl_force_default(info->pctl_dev);
3392}
3393
3394static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3395 rockchip_pinctrl_resume);
3396
d3e51161
HS		 3397static int rockchip_pinctrl_probe(struct platform_device *pdev)
3398{
3399 struct rockchip_pinctrl *info;
3400 struct device *dev = &pdev->dev;
3401 struct rockchip_pin_ctrl *ctrl;
14dee867 3402 struct device_node *np = pdev->dev.of_node, *node;
d3e51161 3403 struct resource *res;
751a99ab 3404 void __iomem *base;
d3e51161
HS		 3405 int ret;
3406
3407 if (!dev->of_node) {
3408 dev_err(dev, "device tree node not found\n");
3409 return -ENODEV;
3410 }
3411
283b7ac9 3412 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
d3e51161
HS		 3413 if (!info)
3414 return -ENOMEM;
3415
622f3237
HS		 3416 info->dev = dev;
3417
d3e51161
HS		 3418 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3419 if (!ctrl) {
3420 dev_err(dev, "driver data not available\n");
3421 return -EINVAL;
3422 }
3423 info->ctrl = ctrl;
d3e51161 3424
1e747e59
HS		 3425 node = of_parse_phandle(np, "rockchip,grf", 0);
3426 if (node) {
3427 info->regmap_base = syscon_node_to_regmap(node);
3428 if (IS_ERR(info->regmap_base))
3429 return PTR_ERR(info->regmap_base);
3430 } else {
3431 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751a99ab
HS		 3432 base = devm_ioremap_resource(&pdev->dev, res);
3433 if (IS_ERR(base))
3434 return PTR_ERR(base);
3435
3436 rockchip_regmap_config.max_register = resource_size(res) - 4;
1e747e59
HS		 3437 rockchip_regmap_config.name = "rockchip,pinctrl";
3438 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3439 &rockchip_regmap_config);
3440
3441 /* to check for the old dt-bindings */
3442 info->reg_size = resource_size(res);
3443
3444 /* Honor the old binding, with pull registers as 2nd resource */
3445 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3446 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3447 base = devm_ioremap_resource(&pdev->dev, res);
3448 if (IS_ERR(base))
3449 return PTR_ERR(base);
3450
3451 rockchip_regmap_config.max_register =
3452 resource_size(res) - 4;
3453 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3454 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3455 base,
3456 &rockchip_regmap_config);
3457 }
6ca5274d
HS		 3458 }
3459
14dee867
HS		 3460 /* try to find the optional reference to the pmu syscon */
3461 node = of_parse_phandle(np, "rockchip,pmu", 0);
3462 if (node) {
3463 info->regmap_pmu = syscon_node_to_regmap(node);
3464 if (IS_ERR(info->regmap_pmu))
3465 return PTR_ERR(info->regmap_pmu);
3466 }
3467
d3e51161
HS		 3468 ret = rockchip_gpiolib_register(pdev, info);
3469 if (ret)
3470 return ret;
3471
3472 ret = rockchip_pinctrl_register(pdev, info);
3473 if (ret) {
3474 rockchip_gpiolib_unregister(pdev, info);
3475 return ret;
3476 }
3477
3478 platform_set_drvdata(pdev, info);
3479
3480 return 0;
3481}
3482
87065ca9
DW		 3483static struct rockchip_pin_bank px30_pin_banks[] = {
3484 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3485 IOMUX_SOURCE_PMU,
3486 IOMUX_SOURCE_PMU,
3487 IOMUX_SOURCE_PMU
3488 ),
3489 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3490 IOMUX_WIDTH_4BIT,
3491 IOMUX_WIDTH_4BIT,
3492 IOMUX_WIDTH_4BIT
3493 ),
3494 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3495 IOMUX_WIDTH_4BIT,
3496 IOMUX_WIDTH_4BIT,
3497 IOMUX_WIDTH_4BIT
3498 ),
3499 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3500 IOMUX_WIDTH_4BIT,
3501 IOMUX_WIDTH_4BIT,
3502 IOMUX_WIDTH_4BIT
3503 ),
3504};
3505
3506static struct rockchip_pin_ctrl px30_pin_ctrl = {
3507 .pin_banks = px30_pin_banks,
3508 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3509 .label = "PX30-GPIO",
3510 .type = PX30,
3511 .grf_mux_offset = 0x0,
3512 .pmu_mux_offset = 0x0,
3513 .iomux_routes = px30_mux_route_data,
3514 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3515 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3516 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3517 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3518};
3519
b9c6dcab 3520static struct rockchip_pin_bank rv1108_pin_banks[] = {
688daf23
AY		 3521 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3522 IOMUX_SOURCE_PMU,
3523 IOMUX_SOURCE_PMU,
3524 IOMUX_SOURCE_PMU),
3525 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3526 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3527 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3528};
3529
b9c6dcab
AY		 3530static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3531 .pin_banks = rv1108_pin_banks,
3532 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3533 .label = "RV1108-GPIO",
3534 .type = RV1108,
688daf23
AY		 3535 .grf_mux_offset = 0x10,
3536 .pmu_mux_offset = 0x0,
12b8f018
DW		 3537 .iomux_recalced = rv1108_mux_recalced_data,
3538 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
b9c6dcab
AY		 3539 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3540 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
5caff7ea 3541 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
688daf23
AY		 3542};
3543
d3e51161
HS		 3544static struct rockchip_pin_bank rk2928_pin_banks[] = {
3545 PIN_BANK(0, 32, "gpio0"),
3546 PIN_BANK(1, 32, "gpio1"),
3547 PIN_BANK(2, 32, "gpio2"),
3548 PIN_BANK(3, 32, "gpio3"),
3549};
3550
3551static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3552 .pin_banks = rk2928_pin_banks,
3553 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3554 .label = "RK2928-GPIO",
a282926d 3555 .type = RK2928,
95ec8ae4 3556 .grf_mux_offset = 0xa8,
a282926d 3557 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 3558};
3559
c5ce7670
XZ		 3560static struct rockchip_pin_bank rk3036_pin_banks[] = {
3561 PIN_BANK(0, 32, "gpio0"),
3562 PIN_BANK(1, 32, "gpio1"),
3563 PIN_BANK(2, 32, "gpio2"),
3564};
3565
3566static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3567 .pin_banks = rk3036_pin_banks,
3568 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3569 .label = "RK3036-GPIO",
3570 .type = RK2928,
3571 .grf_mux_offset = 0xa8,
3572 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3573};
3574
d3e51161
HS		 3575static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3576 PIN_BANK(0, 32, "gpio0"),
3577 PIN_BANK(1, 32, "gpio1"),
3578 PIN_BANK(2, 32, "gpio2"),
3579 PIN_BANK(3, 32, "gpio3"),
3580 PIN_BANK(4, 32, "gpio4"),
3581 PIN_BANK(6, 16, "gpio6"),
3582};
3583
3584static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3585 .pin_banks = rk3066a_pin_banks,
3586 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3587 .label = "RK3066a-GPIO",
a282926d 3588 .type = RK2928,
95ec8ae4 3589 .grf_mux_offset = 0xa8,
a282926d 3590 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 3591};
3592
3593static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3594 PIN_BANK(0, 32, "gpio0"),
3595 PIN_BANK(1, 32, "gpio1"),
3596 PIN_BANK(2, 32, "gpio2"),
3597 PIN_BANK(3, 32, "gpio3"),
3598};
3599
3600static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3601 .pin_banks = rk3066b_pin_banks,
3602 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3603 .label = "RK3066b-GPIO",
a282926d 3604 .type = RK3066B,
95ec8ae4 3605 .grf_mux_offset = 0x60,
d3e51161
HS		 3606};
3607
d23c66df
DW		 3608static struct rockchip_pin_bank rk3128_pin_banks[] = {
3609 PIN_BANK(0, 32, "gpio0"),
3610 PIN_BANK(1, 32, "gpio1"),
3611 PIN_BANK(2, 32, "gpio2"),
3612 PIN_BANK(3, 32, "gpio3"),
3613};
3614
3615static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3616 .pin_banks = rk3128_pin_banks,
3617 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3618 .label = "RK3128-GPIO",
3619 .type = RK3128,
3620 .grf_mux_offset = 0xa8,
3621 .iomux_recalced = rk3128_mux_recalced_data,
3622 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3623 .iomux_routes = rk3128_mux_route_data,
3624 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3625 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3626};
3627
d3e51161 3628static struct rockchip_pin_bank rk3188_pin_banks[] = {
fc72c923 3629 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
d3e51161
HS		 3630 PIN_BANK(1, 32, "gpio1"),
3631 PIN_BANK(2, 32, "gpio2"),
3632 PIN_BANK(3, 32, "gpio3"),
3633};
3634
3635static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3636 .pin_banks = rk3188_pin_banks,
3637 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3638 .label = "RK3188-GPIO",
a282926d 3639 .type = RK3188,
95ec8ae4 3640 .grf_mux_offset = 0x60,
ada62b7c
HS		 3641 .iomux_routes = rk3188_mux_route_data,
3642 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
6ca5274d 3643 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 3644};
3645
fea0fe60
JC		 3646static struct rockchip_pin_bank rk3228_pin_banks[] = {
3647 PIN_BANK(0, 32, "gpio0"),
3648 PIN_BANK(1, 32, "gpio1"),
3649 PIN_BANK(2, 32, "gpio2"),
3650 PIN_BANK(3, 32, "gpio3"),
3651};
3652
3653static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3654 .pin_banks = rk3228_pin_banks,
3655 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3656 .label = "RK3228-GPIO",
3657 .type = RK3288,
3658 .grf_mux_offset = 0x0,
d4970ee0
DW		 3659 .iomux_routes = rk3228_mux_route_data,
3660 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
fea0fe60
JC		 3661 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3662 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3663};
3664
304f077d
HS		 3665static struct rockchip_pin_bank rk3288_pin_banks[] = {
3666 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3667 IOMUX_SOURCE_PMU,
3668 IOMUX_SOURCE_PMU,
3669 IOMUX_UNROUTED
3670 ),
3671 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3672 IOMUX_UNROUTED,
3673 IOMUX_UNROUTED,
3674 0
3675 ),
3676 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3677 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3678 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3679 IOMUX_WIDTH_4BIT,
3680 0,
3681 0
3682 ),
3683 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3684 0,
3685 0,
3686 IOMUX_UNROUTED
3687 ),
3688 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3689 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3690 0,
3691 IOMUX_WIDTH_4BIT,
3692 IOMUX_UNROUTED
3693 ),
3694 PIN_BANK(8, 16, "gpio8"),
3695};
3696
3697static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3698 .pin_banks = rk3288_pin_banks,
3699 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3700 .label = "RK3288-GPIO",
66d750e1 3701 .type = RK3288,
304f077d
HS		 3702 .grf_mux_offset = 0x0,
3703 .pmu_mux_offset = 0x84,
4e96fd30
HS		 3704 .iomux_routes = rk3288_mux_route_data,
3705 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
304f077d 3706 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
ef17f69f 3707 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
304f077d
HS		 3708};
3709
3818e4a7 3710static struct rockchip_pin_bank rk3328_pin_banks[] = {
3711 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3712 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3713 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
c04c3fa6
DW		 3714 IOMUX_WIDTH_3BIT,
3715 IOMUX_WIDTH_3BIT,
3818e4a7 3716 0),
3717 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3718 IOMUX_WIDTH_3BIT,
c04c3fa6 3719 IOMUX_WIDTH_3BIT,
3818e4a7 3720 0,
3721 0),
3722};
3723
3724static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3725 .pin_banks = rk3328_pin_banks,
3726 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3727 .label = "RK3328-GPIO",
3728 .type = RK3288,
3729 .grf_mux_offset = 0x0,
c04c3fa6
DW		 3730 .iomux_recalced = rk3328_mux_recalced_data,
3731 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
cedc964a
DW		 3732 .iomux_routes = rk3328_mux_route_data,
3733 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3818e4a7 3734 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3735 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
728d3f5a 3736 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3818e4a7 3737};
3738
daecdc66
HS		 3739static struct rockchip_pin_bank rk3368_pin_banks[] = {
3740 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3741 IOMUX_SOURCE_PMU,
3742 IOMUX_SOURCE_PMU,
3743 IOMUX_SOURCE_PMU
3744 ),
3745 PIN_BANK(1, 32, "gpio1"),
3746 PIN_BANK(2, 32, "gpio2"),
3747 PIN_BANK(3, 32, "gpio3"),
3748};
3749
3750static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3751 .pin_banks = rk3368_pin_banks,
3752 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3753 .label = "RK3368-GPIO",
3754 .type = RK3368,
3755 .grf_mux_offset = 0x0,
3756 .pmu_mux_offset = 0x0,
3757 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3758 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3759};
3760
b6c23275 3761static struct rockchip_pin_bank rk3399_pin_banks[] = {
3ba6767a
DW		 3762 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3763 IOMUX_SOURCE_PMU,
3764 IOMUX_SOURCE_PMU,
3765 IOMUX_SOURCE_PMU,
3766 IOMUX_SOURCE_PMU,
3767 DRV_TYPE_IO_1V8_ONLY,
3768 DRV_TYPE_IO_1V8_ONLY,
3769 DRV_TYPE_IO_DEFAULT,
3770 DRV_TYPE_IO_DEFAULT,
c437f65c
DW		 3771 0x80,
3772 0x88,
3ba6767a
DW		 3773 -1,
3774 -1,
3775 PULL_TYPE_IO_1V8_ONLY,
3776 PULL_TYPE_IO_1V8_ONLY,
3777 PULL_TYPE_IO_DEFAULT,
3778 PULL_TYPE_IO_DEFAULT
3779 ),
b6c23275
DW		 3780 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3781 IOMUX_SOURCE_PMU,
3782 IOMUX_SOURCE_PMU,
3783 IOMUX_SOURCE_PMU,
3784 DRV_TYPE_IO_1V8_OR_3V0,
3785 DRV_TYPE_IO_1V8_OR_3V0,
3786 DRV_TYPE_IO_1V8_OR_3V0,
3787 DRV_TYPE_IO_1V8_OR_3V0,
c437f65c
DW		 3788 0xa0,
3789 0xa8,
3790 0xb0,
3791 0xb8
b6c23275 3792 ),
3ba6767a
DW		 3793 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3794 DRV_TYPE_IO_1V8_OR_3V0,
3795 DRV_TYPE_IO_1V8_ONLY,
3796 DRV_TYPE_IO_1V8_ONLY,
3797 PULL_TYPE_IO_DEFAULT,
3798 PULL_TYPE_IO_DEFAULT,
3799 PULL_TYPE_IO_1V8_ONLY,
3800 PULL_TYPE_IO_1V8_ONLY
3801 ),
b6c23275
DW		 3802 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3803 DRV_TYPE_IO_3V3_ONLY,
3804 DRV_TYPE_IO_3V3_ONLY,
3805 DRV_TYPE_IO_1V8_OR_3V0
3806 ),
3807 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3808 DRV_TYPE_IO_1V8_3V0_AUTO,
3809 DRV_TYPE_IO_1V8_OR_3V0,
3810 DRV_TYPE_IO_1V8_OR_3V0
3811 ),
3812};
3813
3814static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3815 .pin_banks = rk3399_pin_banks,
3816 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3817 .label = "RK3399-GPIO",
3818 .type = RK3399,
3819 .grf_mux_offset = 0xe000,
3820 .pmu_mux_offset = 0x0,
3821 .grf_drv_offset = 0xe100,
3822 .pmu_drv_offset = 0x80,
accc1ce7
DW		 3823 .iomux_routes = rk3399_mux_route_data,
3824 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
b6c23275
DW		 3825 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3826 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3827};
daecdc66 3828
d3e51161 3829static const struct of_device_id rockchip_pinctrl_dt_match[] = {
87065ca9
DW		 3830 { .compatible = "rockchip,px30-pinctrl",
3831 .data = &px30_pin_ctrl },
b9c6dcab 3832 { .compatible = "rockchip,rv1108-pinctrl",
cdbbd26f 3833 .data = &rv1108_pin_ctrl },
d3e51161 3834 { .compatible = "rockchip,rk2928-pinctrl",
cdbbd26f 3835 .data = &rk2928_pin_ctrl },
c5ce7670 3836 { .compatible = "rockchip,rk3036-pinctrl",
cdbbd26f 3837 .data = &rk3036_pin_ctrl },
d3e51161 3838 { .compatible = "rockchip,rk3066a-pinctrl",
cdbbd26f 3839 .data = &rk3066a_pin_ctrl },
d3e51161 3840 { .compatible = "rockchip,rk3066b-pinctrl",
cdbbd26f 3841 .data = &rk3066b_pin_ctrl },
d23c66df
DW		 3842 { .compatible = "rockchip,rk3128-pinctrl",
3843 .data = (void *)&rk3128_pin_ctrl },
d3e51161 3844 { .compatible = "rockchip,rk3188-pinctrl",
cdbbd26f 3845 .data = &rk3188_pin_ctrl },
fea0fe60 3846 { .compatible = "rockchip,rk3228-pinctrl",
cdbbd26f 3847 .data = &rk3228_pin_ctrl },
304f077d 3848 { .compatible = "rockchip,rk3288-pinctrl",
cdbbd26f 3849 .data = &rk3288_pin_ctrl },
3818e4a7 3850 { .compatible = "rockchip,rk3328-pinctrl",
cdbbd26f 3851 .data = &rk3328_pin_ctrl },
daecdc66 3852 { .compatible = "rockchip,rk3368-pinctrl",
cdbbd26f 3853 .data = &rk3368_pin_ctrl },
b6c23275 3854 { .compatible = "rockchip,rk3399-pinctrl",
cdbbd26f 3855 .data = &rk3399_pin_ctrl },
d3e51161
HS		 3856 {},
3857};
d3e51161
HS		 3858
3859static struct platform_driver rockchip_pinctrl_driver = {
3860 .probe = rockchip_pinctrl_probe,
3861 .driver = {
3862 .name = "rockchip-pinctrl",
9198f509 3863 .pm = &rockchip_pinctrl_dev_pm_ops,
0be9e70d 3864 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 3865 },
3866};
3867
3868static int __init rockchip_pinctrl_drv_register(void)
3869{
3870 return platform_driver_register(&rockchip_pinctrl_driver);
3871}
3872postcore_initcall(rockchip_pinctrl_drv_register);
Linux 6.x block layer and io_uring tree(s)