Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
a60b57ed | 25 | #include <linux/irqdomain.h> |
de88cbb7 | 26 | #include <linux/irqchip/chained_irq.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
855f80cd | 28 | #include <linux/of_device.h> |
32e67eee | 29 | #include <linux/of_address.h> |
e32af889 | 30 | #include <linux/pinctrl/machine.h> |
e98ea774 | 31 | #include <linux/pinctrl/pinctrl.h> |
dbfe8ca2 | 32 | #include <linux/pinctrl/pinmux.h> |
d41af627 | 33 | #include <linux/pinctrl/pinconf.h> |
dbfe8ca2 LW |
34 | /* Since we request GPIOs from ourself */ |
35 | #include <linux/pinctrl/consumer.h> | |
bb16bd9b | 36 | #include <linux/platform_data/pinctrl-nomadik.h> |
e98ea774 | 37 | #include "pinctrl-nomadik.h" |
8d99b32d | 38 | #include "core.h" |
e98ea774 | 39 | |
2ec1d359 AR |
40 | /* |
41 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
42 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 43 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
44 | * |
45 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
46 | */ | |
47 | ||
2ec1d359 AR |
48 | struct nmk_gpio_chip { |
49 | struct gpio_chip chip; | |
a60b57ed | 50 | struct irq_domain *domain; |
2ec1d359 | 51 | void __iomem *addr; |
af7dc228 | 52 | struct clk *clk; |
33b744b3 | 53 | unsigned int bank; |
2ec1d359 | 54 | unsigned int parent_irq; |
2c8bb0eb | 55 | int secondary_parent_irq; |
33b744b3 | 56 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 57 | void (*set_ioforce)(bool enable); |
c0fcb8db | 58 | spinlock_t lock; |
33d78647 | 59 | bool sleepmode; |
2ec1d359 AR |
60 | /* Keep track of configured edges */ |
61 | u32 edge_rising; | |
62 | u32 edge_falling; | |
b9df468d RV |
63 | u32 real_wake; |
64 | u32 rwimsc; | |
65 | u32 fwimsc; | |
6c12fe88 RV |
66 | u32 rimsc; |
67 | u32 fimsc; | |
bc6f5cf6 | 68 | u32 pull_up; |
ebc6178d | 69 | u32 lowemi; |
2ec1d359 AR |
70 | }; |
71 | ||
f1671bf5 JA |
72 | /** |
73 | * struct nmk_pinctrl - state container for the Nomadik pin controller | |
74 | * @dev: containing device pointer | |
75 | * @pctl: corresponding pin controller device | |
76 | * @soc: SoC data for this specific chip | |
77 | * @prcm_base: PRCM register range virtual base | |
78 | */ | |
e98ea774 LW |
79 | struct nmk_pinctrl { |
80 | struct device *dev; | |
81 | struct pinctrl_dev *pctl; | |
82 | const struct nmk_pinctrl_soc_data *soc; | |
f1671bf5 | 83 | void __iomem *prcm_base; |
e98ea774 LW |
84 | }; |
85 | ||
01727e61 RV |
86 | static struct nmk_gpio_chip * |
87 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
88 | ||
89 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
90 | ||
91 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
92 | ||
6f9a974c RV |
93 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
94 | unsigned offset, int gpio_mode) | |
95 | { | |
96 | u32 bit = 1 << offset; | |
97 | u32 afunc, bfunc; | |
98 | ||
99 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
100 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
101 | if (gpio_mode & NMK_GPIO_ALT_A) | |
102 | afunc |= bit; | |
103 | if (gpio_mode & NMK_GPIO_ALT_B) | |
104 | bfunc |= bit; | |
105 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
106 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
107 | } | |
108 | ||
81a3c298 RV |
109 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
110 | unsigned offset, enum nmk_gpio_slpm mode) | |
111 | { | |
112 | u32 bit = 1 << offset; | |
113 | u32 slpm; | |
114 | ||
115 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
116 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
117 | slpm |= bit; | |
118 | else | |
119 | slpm &= ~bit; | |
120 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
121 | } | |
122 | ||
5b327edf RV |
123 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
124 | unsigned offset, enum nmk_gpio_pull pull) | |
125 | { | |
126 | u32 bit = 1 << offset; | |
127 | u32 pdis; | |
128 | ||
129 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 130 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 131 | pdis |= bit; |
bc6f5cf6 RA |
132 | nmk_chip->pull_up &= ~bit; |
133 | } else { | |
5b327edf | 134 | pdis &= ~bit; |
bc6f5cf6 RA |
135 | } |
136 | ||
5b327edf RV |
137 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
138 | ||
bc6f5cf6 RA |
139 | if (pull == NMK_GPIO_PULL_UP) { |
140 | nmk_chip->pull_up |= bit; | |
5b327edf | 141 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
142 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
143 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 144 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 145 | } |
5b327edf RV |
146 | } |
147 | ||
ebc6178d RV |
148 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
149 | unsigned offset, bool lowemi) | |
150 | { | |
151 | u32 bit = BIT(offset); | |
152 | bool enabled = nmk_chip->lowemi & bit; | |
153 | ||
154 | if (lowemi == enabled) | |
155 | return; | |
156 | ||
157 | if (lowemi) | |
158 | nmk_chip->lowemi |= bit; | |
159 | else | |
160 | nmk_chip->lowemi &= ~bit; | |
161 | ||
162 | writel_relaxed(nmk_chip->lowemi, | |
163 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
164 | } | |
165 | ||
378be066 RV |
166 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
167 | unsigned offset) | |
168 | { | |
169 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
170 | } | |
171 | ||
6720db7c RV |
172 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
173 | unsigned offset, int val) | |
174 | { | |
175 | if (val) | |
176 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
177 | else | |
178 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
179 | } | |
180 | ||
181 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
182 | unsigned offset, int val) | |
183 | { | |
184 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
185 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
186 | } | |
187 | ||
01727e61 RV |
188 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
189 | unsigned offset, int gpio_mode, | |
190 | bool glitch) | |
191 | { | |
6c12fe88 RV |
192 | u32 rwimsc = nmk_chip->rwimsc; |
193 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
194 | |
195 | if (glitch && nmk_chip->set_ioforce) { | |
196 | u32 bit = BIT(offset); | |
197 | ||
01727e61 RV |
198 | /* Prevent spurious wakeups */ |
199 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
200 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
201 | ||
202 | nmk_chip->set_ioforce(true); | |
203 | } | |
204 | ||
205 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
206 | ||
207 | if (glitch && nmk_chip->set_ioforce) { | |
208 | nmk_chip->set_ioforce(false); | |
209 | ||
210 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
211 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
212 | } | |
213 | } | |
214 | ||
6c42ad1c RV |
215 | static void |
216 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
217 | { | |
218 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
219 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
220 | int gpio = nmk_chip->chip.base + offset; | |
aa6e379a | 221 | int irq = irq_find_mapping(nmk_chip->domain, offset); |
6c42ad1c RV |
222 | struct irq_data *d = irq_get_irq_data(irq); |
223 | ||
224 | if (!rising && !falling) | |
225 | return; | |
226 | ||
227 | if (!d || !irqd_irq_disabled(d)) | |
228 | return; | |
229 | ||
230 | if (rising) { | |
231 | nmk_chip->rimsc &= ~BIT(offset); | |
232 | writel_relaxed(nmk_chip->rimsc, | |
233 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
234 | } | |
235 | ||
236 | if (falling) { | |
237 | nmk_chip->fimsc &= ~BIT(offset); | |
238 | writel_relaxed(nmk_chip->fimsc, | |
239 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
240 | } | |
241 | ||
242 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | |
243 | } | |
244 | ||
f1671bf5 JA |
245 | static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) |
246 | { | |
247 | u32 val; | |
248 | ||
249 | val = readl(reg); | |
250 | val = ((val & ~mask) | (value & mask)); | |
251 | writel(val, reg); | |
252 | } | |
253 | ||
c22df08c JNG |
254 | static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, |
255 | unsigned offset, unsigned alt_num) | |
256 | { | |
257 | int i; | |
258 | u16 reg; | |
259 | u8 bit; | |
260 | u8 alt_index; | |
261 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
262 | const u16 *gpiocr_regs; | |
263 | ||
4ca075de FB |
264 | if (!npct->prcm_base) |
265 | return; | |
266 | ||
c22df08c JNG |
267 | if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { |
268 | dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", | |
269 | alt_num); | |
270 | return; | |
271 | } | |
272 | ||
273 | for (i = 0 ; i < npct->soc->npins_altcx ; i++) { | |
274 | if (npct->soc->altcx_pins[i].pin == offset) | |
275 | break; | |
276 | } | |
277 | if (i == npct->soc->npins_altcx) { | |
278 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", | |
279 | offset); | |
280 | return; | |
281 | } | |
282 | ||
283 | pin_desc = npct->soc->altcx_pins + i; | |
284 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
285 | ||
286 | /* | |
287 | * If alt_num is NULL, just clear current ALTCx selection | |
288 | * to make sure we come back to a pure ALTC selection | |
289 | */ | |
290 | if (!alt_num) { | |
291 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
292 | if (pin_desc->altcx[i].used == true) { | |
293 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
294 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
295 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
296 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
297 | dev_dbg(npct->dev, |
298 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
299 | offset, i+1); | |
300 | } | |
301 | } | |
302 | } | |
303 | return; | |
304 | } | |
305 | ||
306 | alt_index = alt_num - 1; | |
307 | if (pin_desc->altcx[alt_index].used == false) { | |
308 | dev_warn(npct->dev, | |
309 | "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", | |
310 | offset, alt_num); | |
311 | return; | |
312 | } | |
313 | ||
314 | /* | |
315 | * Check if any other ALTCx functions are activated on this pin | |
316 | * and disable it first. | |
317 | */ | |
318 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
319 | if (i == alt_index) | |
320 | continue; | |
321 | if (pin_desc->altcx[i].used == true) { | |
322 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
323 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
324 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
325 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
326 | dev_dbg(npct->dev, |
327 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
328 | offset, i+1); | |
329 | } | |
330 | } | |
331 | } | |
332 | ||
333 | reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; | |
334 | bit = pin_desc->altcx[alt_index].control_bit; | |
335 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", | |
336 | offset, alt_index+1); | |
f1671bf5 | 337 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); |
c22df08c JNG |
338 | } |
339 | ||
01727e61 RV |
340 | /* |
341 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
342 | * - Save SLPM registers | |
343 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
344 | * - Configure the GPIO registers for the IOs that are being switched | |
345 | * - Set IOFORCE=1 | |
346 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
347 | * - Set IOFORCE=0 | |
348 | * - Restore SLPM registers | |
349 | * - Any spurious wake up event during switch sequence to be ignored and | |
350 | * cleared | |
351 | */ | |
352 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
353 | { | |
354 | int i; | |
355 | ||
356 | for (i = 0; i < NUM_BANKS; i++) { | |
357 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
358 | unsigned int temp = slpm[i]; | |
359 | ||
360 | if (!chip) | |
361 | break; | |
362 | ||
3c0227d2 RV |
363 | clk_enable(chip->clk); |
364 | ||
01727e61 RV |
365 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
366 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
367 | } | |
368 | } | |
369 | ||
370 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
371 | { | |
372 | int i; | |
373 | ||
374 | for (i = 0; i < NUM_BANKS; i++) { | |
375 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
376 | ||
377 | if (!chip) | |
378 | break; | |
379 | ||
380 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
381 | |
382 | clk_disable(chip->clk); | |
01727e61 RV |
383 | } |
384 | } | |
385 | ||
0fafd50e | 386 | static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) |
2249b19f JNG |
387 | { |
388 | int i; | |
389 | u16 reg; | |
390 | u8 bit; | |
391 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
392 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
393 | const u16 *gpiocr_regs; | |
394 | ||
4ca075de FB |
395 | if (!npct->prcm_base) |
396 | return NMK_GPIO_ALT_C; | |
397 | ||
2249b19f JNG |
398 | for (i = 0; i < npct->soc->npins_altcx; i++) { |
399 | if (npct->soc->altcx_pins[i].pin == gpio) | |
400 | break; | |
401 | } | |
402 | if (i == npct->soc->npins_altcx) | |
403 | return NMK_GPIO_ALT_C; | |
404 | ||
405 | pin_desc = npct->soc->altcx_pins + i; | |
406 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
407 | for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { | |
408 | if (pin_desc->altcx[i].used == true) { | |
409 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
410 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 | 411 | if (readl(npct->prcm_base + reg) & BIT(bit)) |
2249b19f JNG |
412 | return NMK_GPIO_ALT_C+i+1; |
413 | } | |
414 | } | |
415 | return NMK_GPIO_ALT_C; | |
416 | } | |
417 | ||
2ec1d359 AR |
418 | int nmk_gpio_get_mode(int gpio) |
419 | { | |
420 | struct nmk_gpio_chip *nmk_chip; | |
421 | u32 afunc, bfunc, bit; | |
422 | ||
a60b57ed | 423 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
424 | if (!nmk_chip) |
425 | return -EINVAL; | |
426 | ||
a60b57ed | 427 | bit = 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 | 428 | |
3c0227d2 RV |
429 | clk_enable(nmk_chip->clk); |
430 | ||
2ec1d359 AR |
431 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
432 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
433 | ||
3c0227d2 RV |
434 | clk_disable(nmk_chip->clk); |
435 | ||
2ec1d359 AR |
436 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
437 | } | |
438 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
439 | ||
440 | ||
441 | /* IRQ functions */ | |
442 | static inline int nmk_gpio_get_bitmask(int gpio) | |
443 | { | |
a60b57ed | 444 | return 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 AR |
445 | } |
446 | ||
f272c00e | 447 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 448 | { |
2ec1d359 AR |
449 | struct nmk_gpio_chip *nmk_chip; |
450 | ||
f272c00e | 451 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 AR |
452 | if (!nmk_chip) |
453 | return; | |
3c0227d2 RV |
454 | |
455 | clk_enable(nmk_chip->clk); | |
a60b57ed | 456 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 457 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
458 | } |
459 | ||
4d4e20f7 RV |
460 | enum nmk_gpio_irq_type { |
461 | NORMAL, | |
462 | WAKE, | |
463 | }; | |
464 | ||
040e5ecd | 465 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
466 | int gpio, enum nmk_gpio_irq_type which, |
467 | bool enable) | |
2ec1d359 | 468 | { |
040e5ecd | 469 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
470 | u32 *rimscval; |
471 | u32 *fimscval; | |
472 | u32 rimscreg; | |
473 | u32 fimscreg; | |
474 | ||
475 | if (which == NORMAL) { | |
476 | rimscreg = NMK_GPIO_RIMSC; | |
477 | fimscreg = NMK_GPIO_FIMSC; | |
478 | rimscval = &nmk_chip->rimsc; | |
479 | fimscval = &nmk_chip->fimsc; | |
480 | } else { | |
481 | rimscreg = NMK_GPIO_RWIMSC; | |
482 | fimscreg = NMK_GPIO_FWIMSC; | |
483 | rimscval = &nmk_chip->rwimsc; | |
484 | fimscval = &nmk_chip->fwimsc; | |
485 | } | |
2ec1d359 | 486 | |
040e5ecd | 487 | /* we must individually set/clear the two edges */ |
2ec1d359 | 488 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 489 | if (enable) |
6c12fe88 | 490 | *rimscval |= bitmask; |
040e5ecd | 491 | else |
6c12fe88 RV |
492 | *rimscval &= ~bitmask; |
493 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
494 | } |
495 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 496 | if (enable) |
6c12fe88 | 497 | *fimscval |= bitmask; |
040e5ecd | 498 | else |
6c12fe88 RV |
499 | *fimscval &= ~bitmask; |
500 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 501 | } |
040e5ecd | 502 | } |
2ec1d359 | 503 | |
b9df468d RV |
504 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
505 | int gpio, bool on) | |
506 | { | |
b982ff0e RV |
507 | /* |
508 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
509 | * disabled, since setting SLPM to 1 increases power consumption, and | |
510 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
511 | */ | |
512 | if (nmk_chip->sleepmode && on) { | |
e85bbc19 | 513 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, |
b982ff0e | 514 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
515 | } |
516 | ||
b9df468d RV |
517 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
518 | } | |
519 | ||
520 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 521 | { |
2ec1d359 AR |
522 | struct nmk_gpio_chip *nmk_chip; |
523 | unsigned long flags; | |
040e5ecd | 524 | u32 bitmask; |
2ec1d359 | 525 | |
f272c00e | 526 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 527 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 | 528 | if (!nmk_chip) |
4d4e20f7 | 529 | return -EINVAL; |
2ec1d359 | 530 | |
3c0227d2 | 531 | clk_enable(nmk_chip->clk); |
b9df468d RV |
532 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
533 | spin_lock(&nmk_chip->lock); | |
534 | ||
a60b57ed | 535 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d RV |
536 | |
537 | if (!(nmk_chip->real_wake & bitmask)) | |
a60b57ed | 538 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
539 | |
540 | spin_unlock(&nmk_chip->lock); | |
541 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 542 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
543 | |
544 | return 0; | |
2ec1d359 AR |
545 | } |
546 | ||
f272c00e | 547 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 548 | { |
b9df468d | 549 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 550 | } |
040e5ecd | 551 | |
f272c00e | 552 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 553 | { |
b9df468d | 554 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
555 | } |
556 | ||
f272c00e | 557 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 558 | { |
7e3f7e59 RV |
559 | struct nmk_gpio_chip *nmk_chip; |
560 | unsigned long flags; | |
b9df468d | 561 | u32 bitmask; |
7e3f7e59 | 562 | |
f272c00e | 563 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
564 | if (!nmk_chip) |
565 | return -EINVAL; | |
a60b57ed | 566 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
7e3f7e59 | 567 | |
3c0227d2 | 568 | clk_enable(nmk_chip->clk); |
01727e61 RV |
569 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
570 | spin_lock(&nmk_chip->lock); | |
571 | ||
479a0c7e | 572 | if (irqd_irq_disabled(d)) |
a60b57ed | 573 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
574 | |
575 | if (on) | |
576 | nmk_chip->real_wake |= bitmask; | |
577 | else | |
578 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
579 | |
580 | spin_unlock(&nmk_chip->lock); | |
581 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 582 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
583 | |
584 | return 0; | |
040e5ecd RV |
585 | } |
586 | ||
f272c00e | 587 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 588 | { |
479a0c7e | 589 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 590 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
591 | struct nmk_gpio_chip *nmk_chip; |
592 | unsigned long flags; | |
593 | u32 bitmask; | |
594 | ||
f272c00e | 595 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 596 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 AR |
597 | if (!nmk_chip) |
598 | return -EINVAL; | |
2ec1d359 AR |
599 | if (type & IRQ_TYPE_LEVEL_HIGH) |
600 | return -EINVAL; | |
601 | if (type & IRQ_TYPE_LEVEL_LOW) | |
602 | return -EINVAL; | |
603 | ||
3c0227d2 | 604 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
605 | spin_lock_irqsave(&nmk_chip->lock, flags); |
606 | ||
7a852d80 | 607 | if (enabled) |
a60b57ed | 608 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 609 | |
b9df468d | 610 | if (enabled || wake) |
a60b57ed | 611 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 612 | |
2ec1d359 AR |
613 | nmk_chip->edge_rising &= ~bitmask; |
614 | if (type & IRQ_TYPE_EDGE_RISING) | |
615 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
616 | |
617 | nmk_chip->edge_falling &= ~bitmask; | |
618 | if (type & IRQ_TYPE_EDGE_FALLING) | |
619 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 620 | |
7a852d80 | 621 | if (enabled) |
a60b57ed | 622 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 623 | |
b9df468d | 624 | if (enabled || wake) |
a60b57ed | 625 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 626 | |
7a852d80 | 627 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 628 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
629 | |
630 | return 0; | |
631 | } | |
632 | ||
3c0227d2 RV |
633 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
634 | { | |
635 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 636 | |
494336f3 LW |
637 | if (gpio_lock_as_irq(&nmk_chip->chip, d->hwirq)) |
638 | dev_err(nmk_chip->chip.dev, | |
639 | "unable to lock HW IRQ %lu for IRQ\n", | |
640 | d->hwirq); | |
3c0227d2 RV |
641 | clk_enable(nmk_chip->clk); |
642 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
643 | return 0; |
644 | } | |
645 | ||
3c0227d2 RV |
646 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
647 | { | |
648 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
649 | ||
650 | nmk_gpio_irq_mask(d); | |
651 | clk_disable(nmk_chip->clk); | |
494336f3 | 652 | gpio_unlock_as_irq(&nmk_chip->chip, d->hwirq); |
3c0227d2 RV |
653 | } |
654 | ||
2ec1d359 AR |
655 | static struct irq_chip nmk_gpio_irq_chip = { |
656 | .name = "Nomadik-GPIO", | |
f272c00e LB |
657 | .irq_ack = nmk_gpio_irq_ack, |
658 | .irq_mask = nmk_gpio_irq_mask, | |
659 | .irq_unmask = nmk_gpio_irq_unmask, | |
660 | .irq_set_type = nmk_gpio_irq_set_type, | |
661 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
662 | .irq_startup = nmk_gpio_irq_startup, |
663 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
4921e745 | 664 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
2ec1d359 AR |
665 | }; |
666 | ||
33b744b3 RV |
667 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
668 | u32 status) | |
2ec1d359 AR |
669 | { |
670 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 671 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 | 672 | |
adfed159 | 673 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 674 | |
6845664a | 675 | nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
676 | while (status) { |
677 | int bit = __ffs(status); | |
678 | ||
95f0bc9b | 679 | generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit)); |
33b744b3 | 680 | status &= ~BIT(bit); |
2ec1d359 | 681 | } |
aaedaa2b | 682 | |
adfed159 | 683 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
684 | } |
685 | ||
33b744b3 RV |
686 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
687 | { | |
6845664a | 688 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
689 | u32 status; |
690 | ||
691 | clk_enable(nmk_chip->clk); | |
692 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
693 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
694 | |
695 | __nmk_gpio_irq_handler(irq, desc, status); | |
696 | } | |
697 | ||
698 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
699 | struct irq_desc *desc) | |
700 | { | |
6845664a | 701 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
702 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
703 | ||
704 | __nmk_gpio_irq_handler(irq, desc, status); | |
705 | } | |
706 | ||
2ec1d359 AR |
707 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
708 | { | |
6845664a TG |
709 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
710 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
711 | |
712 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 713 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 714 | nmk_gpio_secondary_irq_handler); |
6845664a | 715 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
716 | } |
717 | ||
2ec1d359 AR |
718 | return 0; |
719 | } | |
720 | ||
721 | /* I/O Functions */ | |
dbfe8ca2 LW |
722 | |
723 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) | |
724 | { | |
725 | /* | |
726 | * Map back to global GPIO space and request muxing, the direction | |
727 | * parameter does not matter for this controller. | |
728 | */ | |
729 | int gpio = chip->base + offset; | |
730 | ||
731 | return pinctrl_request_gpio(gpio); | |
732 | } | |
733 | ||
734 | static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) | |
735 | { | |
736 | int gpio = chip->base + offset; | |
737 | ||
738 | pinctrl_free_gpio(gpio); | |
739 | } | |
740 | ||
2ec1d359 AR |
741 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
742 | { | |
743 | struct nmk_gpio_chip *nmk_chip = | |
744 | container_of(chip, struct nmk_gpio_chip, chip); | |
745 | ||
3c0227d2 RV |
746 | clk_enable(nmk_chip->clk); |
747 | ||
2ec1d359 | 748 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
749 | |
750 | clk_disable(nmk_chip->clk); | |
751 | ||
2ec1d359 AR |
752 | return 0; |
753 | } | |
754 | ||
2ec1d359 AR |
755 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
756 | { | |
757 | struct nmk_gpio_chip *nmk_chip = | |
758 | container_of(chip, struct nmk_gpio_chip, chip); | |
759 | u32 bit = 1 << offset; | |
3c0227d2 RV |
760 | int value; |
761 | ||
762 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 763 | |
3c0227d2 | 764 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 765 | |
3c0227d2 RV |
766 | clk_disable(nmk_chip->clk); |
767 | ||
768 | return value; | |
2ec1d359 AR |
769 | } |
770 | ||
771 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
772 | int val) | |
773 | { | |
774 | struct nmk_gpio_chip *nmk_chip = | |
775 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 776 | |
3c0227d2 RV |
777 | clk_enable(nmk_chip->clk); |
778 | ||
6720db7c | 779 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
780 | |
781 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
782 | } |
783 | ||
6647c6c0 RV |
784 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
785 | int val) | |
786 | { | |
787 | struct nmk_gpio_chip *nmk_chip = | |
788 | container_of(chip, struct nmk_gpio_chip, chip); | |
789 | ||
3c0227d2 RV |
790 | clk_enable(nmk_chip->clk); |
791 | ||
6720db7c | 792 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 793 | |
3c0227d2 RV |
794 | clk_disable(nmk_chip->clk); |
795 | ||
6647c6c0 RV |
796 | return 0; |
797 | } | |
798 | ||
0d2aec9c RV |
799 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
800 | { | |
801 | struct nmk_gpio_chip *nmk_chip = | |
802 | container_of(chip, struct nmk_gpio_chip, chip); | |
803 | ||
268300be | 804 | return irq_create_mapping(nmk_chip->domain, offset); |
0d2aec9c RV |
805 | } |
806 | ||
d0b543c7 RV |
807 | #ifdef CONFIG_DEBUG_FS |
808 | ||
809 | #include <linux/seq_file.h> | |
810 | ||
2249b19f JNG |
811 | static void nmk_gpio_dbg_show_one(struct seq_file *s, |
812 | struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
813 | unsigned offset, unsigned gpio) | |
d0b543c7 | 814 | { |
6f4350a6 | 815 | const char *label = gpiochip_is_requested(chip, offset); |
d0b543c7 RV |
816 | struct nmk_gpio_chip *nmk_chip = |
817 | container_of(chip, struct nmk_gpio_chip, chip); | |
6f4350a6 LW |
818 | int mode; |
819 | bool is_out; | |
820 | bool pull; | |
821 | u32 bit = 1 << offset; | |
d0b543c7 RV |
822 | const char *modes[] = { |
823 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
824 | [NMK_GPIO_ALT_A] = "altA", | |
825 | [NMK_GPIO_ALT_B] = "altB", | |
826 | [NMK_GPIO_ALT_C] = "altC", | |
2249b19f JNG |
827 | [NMK_GPIO_ALT_C+1] = "altC1", |
828 | [NMK_GPIO_ALT_C+2] = "altC2", | |
829 | [NMK_GPIO_ALT_C+3] = "altC3", | |
830 | [NMK_GPIO_ALT_C+4] = "altC4", | |
d0b543c7 RV |
831 | }; |
832 | ||
3c0227d2 | 833 | clk_enable(nmk_chip->clk); |
6f4350a6 LW |
834 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); |
835 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
836 | mode = nmk_gpio_get_mode(gpio); | |
2249b19f JNG |
837 | if ((mode == NMK_GPIO_ALT_C) && pctldev) |
838 | mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); | |
6f4350a6 LW |
839 | |
840 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
841 | gpio, label ?: "(none)", | |
842 | is_out ? "out" : "in ", | |
843 | chip->get | |
844 | ? (chip->get(chip, offset) ? "hi" : "lo") | |
845 | : "? ", | |
846 | (mode < 0) ? "unknown" : modes[mode], | |
847 | pull ? "pull" : "none"); | |
848 | ||
849 | if (label && !is_out) { | |
850 | int irq = gpio_to_irq(gpio); | |
851 | struct irq_desc *desc = irq_to_desc(irq); | |
852 | ||
853 | /* This races with request_irq(), set_irq_type(), | |
854 | * and set_irq_wake() ... but those are "rare". | |
855 | */ | |
856 | if (irq >= 0 && desc->action) { | |
857 | char *trigger; | |
858 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
859 | ||
860 | if (nmk_chip->edge_rising & bitmask) | |
861 | trigger = "edge-rising"; | |
862 | else if (nmk_chip->edge_falling & bitmask) | |
863 | trigger = "edge-falling"; | |
864 | else | |
865 | trigger = "edge-undefined"; | |
866 | ||
867 | seq_printf(s, " irq-%d %s%s", | |
868 | irq, trigger, | |
869 | irqd_is_wakeup_set(&desc->irq_data) | |
870 | ? " wakeup" : ""); | |
8ea72a30 | 871 | } |
6f4350a6 LW |
872 | } |
873 | clk_disable(nmk_chip->clk); | |
874 | } | |
875 | ||
876 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
877 | { | |
878 | unsigned i; | |
879 | unsigned gpio = chip->base; | |
8ea72a30 | 880 | |
6f4350a6 | 881 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
2249b19f | 882 | nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
d0b543c7 RV |
883 | seq_printf(s, "\n"); |
884 | } | |
885 | } | |
886 | ||
887 | #else | |
6f4350a6 | 888 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, |
2249b19f | 889 | struct pinctrl_dev *pctldev, |
6f4350a6 LW |
890 | struct gpio_chip *chip, |
891 | unsigned offset, unsigned gpio) | |
892 | { | |
893 | } | |
d0b543c7 RV |
894 | #define nmk_gpio_dbg_show NULL |
895 | #endif | |
896 | ||
2ec1d359 AR |
897 | /* This structure is replicated for each GPIO block allocated at probe time */ |
898 | static struct gpio_chip nmk_gpio_template = { | |
dbfe8ca2 LW |
899 | .request = nmk_gpio_request, |
900 | .free = nmk_gpio_free, | |
2ec1d359 AR |
901 | .direction_input = nmk_gpio_make_input, |
902 | .get = nmk_gpio_get_input, | |
903 | .direction_output = nmk_gpio_make_output, | |
904 | .set = nmk_gpio_set_output, | |
0d2aec9c | 905 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 906 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
907 | .can_sleep = 0, |
908 | }; | |
909 | ||
3c0227d2 RV |
910 | void nmk_gpio_clocks_enable(void) |
911 | { | |
912 | int i; | |
913 | ||
914 | for (i = 0; i < NUM_BANKS; i++) { | |
915 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
916 | ||
917 | if (!chip) | |
918 | continue; | |
919 | ||
920 | clk_enable(chip->clk); | |
921 | } | |
922 | } | |
923 | ||
924 | void nmk_gpio_clocks_disable(void) | |
925 | { | |
926 | int i; | |
927 | ||
928 | for (i = 0; i < NUM_BANKS; i++) { | |
929 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
930 | ||
931 | if (!chip) | |
932 | continue; | |
933 | ||
934 | clk_disable(chip->clk); | |
935 | } | |
936 | } | |
937 | ||
b9df468d RV |
938 | /* |
939 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
940 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
941 | * and not the rest of the interrupts which we needed to have as wakeups for | |
942 | * cpuidle. | |
943 | * | |
944 | * PM ops are not used since this needs to be done at the end, after all the | |
945 | * other drivers are done with their suspend callbacks. | |
946 | */ | |
947 | void nmk_gpio_wakeups_suspend(void) | |
948 | { | |
949 | int i; | |
950 | ||
951 | for (i = 0; i < NUM_BANKS; i++) { | |
952 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
953 | ||
954 | if (!chip) | |
955 | break; | |
956 | ||
3c0227d2 RV |
957 | clk_enable(chip->clk); |
958 | ||
b9df468d RV |
959 | writel(chip->rwimsc & chip->real_wake, |
960 | chip->addr + NMK_GPIO_RWIMSC); | |
961 | writel(chip->fwimsc & chip->real_wake, | |
962 | chip->addr + NMK_GPIO_FWIMSC); | |
963 | ||
3c0227d2 | 964 | clk_disable(chip->clk); |
b9df468d RV |
965 | } |
966 | } | |
967 | ||
968 | void nmk_gpio_wakeups_resume(void) | |
969 | { | |
970 | int i; | |
971 | ||
972 | for (i = 0; i < NUM_BANKS; i++) { | |
973 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
974 | ||
975 | if (!chip) | |
976 | break; | |
977 | ||
3c0227d2 RV |
978 | clk_enable(chip->clk); |
979 | ||
b9df468d RV |
980 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
981 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
982 | ||
3c0227d2 | 983 | clk_disable(chip->clk); |
b9df468d RV |
984 | } |
985 | } | |
986 | ||
bc6f5cf6 RA |
987 | /* |
988 | * Read the pull up/pull down status. | |
989 | * A bit set in 'pull_up' means that pull up | |
990 | * is selected if pull is enabled in PDIS register. | |
991 | * Note: only pull up/down set via this driver can | |
992 | * be detected due to HW limitations. | |
993 | */ | |
994 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
995 | { | |
996 | if (gpio_bank < NUM_BANKS) { | |
997 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
998 | ||
999 | if (!chip) | |
1000 | return; | |
1001 | ||
1002 | *pull_up = chip->pull_up; | |
1003 | } | |
1004 | } | |
1005 | ||
5212d096 AL |
1006 | static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
1007 | irq_hw_number_t hwirq) | |
a60b57ed LJ |
1008 | { |
1009 | struct nmk_gpio_chip *nmk_chip = d->host_data; | |
1010 | ||
1011 | if (!nmk_chip) | |
1012 | return -EINVAL; | |
1013 | ||
1014 | irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); | |
1015 | set_irq_flags(irq, IRQF_VALID); | |
1016 | irq_set_chip_data(irq, nmk_chip); | |
1017 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); | |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
2230a36e | 1022 | static const struct irq_domain_ops nmk_gpio_irq_simple_ops = { |
a60b57ed LJ |
1023 | .map = nmk_gpio_irq_map, |
1024 | .xlate = irq_domain_xlate_twocell, | |
1025 | }; | |
1026 | ||
150632b0 | 1027 | static int nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1028 | { |
3e3c62ca | 1029 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
513c27f8 | 1030 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1031 | struct nmk_gpio_chip *nmk_chip; |
1032 | struct gpio_chip *chip; | |
3e3c62ca | 1033 | struct resource *res; |
af7dc228 | 1034 | struct clk *clk; |
33b744b3 | 1035 | int secondary_irq; |
8d91771c | 1036 | void __iomem *base; |
832b6cdf | 1037 | int irq_start = 0; |
3e3c62ca | 1038 | int irq; |
2ec1d359 AR |
1039 | int ret; |
1040 | ||
513c27f8 LJ |
1041 | if (!pdata && !np) { |
1042 | dev_err(&dev->dev, "No platform data or device tree found\n"); | |
3e3c62ca | 1043 | return -ENODEV; |
513c27f8 LJ |
1044 | } |
1045 | ||
1046 | if (np) { | |
5e754f33 | 1047 | pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); |
513c27f8 LJ |
1048 | if (!pdata) |
1049 | return -ENOMEM; | |
1050 | ||
612e1d5f | 1051 | if (of_get_property(np, "st,supports-sleepmode", NULL)) |
513c27f8 LJ |
1052 | pdata->supports_sleepmode = true; |
1053 | ||
1054 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | |
1055 | dev_err(&dev->dev, "gpio-bank property not found\n"); | |
50f690d8 | 1056 | return -EINVAL; |
513c27f8 LJ |
1057 | } |
1058 | ||
1059 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | |
1060 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | |
1061 | } | |
3e3c62ca | 1062 | |
3e3c62ca | 1063 | irq = platform_get_irq(dev, 0); |
50f690d8 LW |
1064 | if (irq < 0) |
1065 | return irq; | |
3e3c62ca | 1066 | |
33b744b3 | 1067 | secondary_irq = platform_get_irq(dev, 1); |
50f690d8 LW |
1068 | if (secondary_irq >= 0 && !pdata->get_secondary_status) |
1069 | return -EINVAL; | |
33b744b3 | 1070 | |
690ebabb | 1071 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
9e0c1fb2 | 1072 | base = devm_ioremap_resource(&dev->dev, res); |
06991c28 LT |
1073 | if (IS_ERR(base)) |
1074 | return PTR_ERR(base); | |
8d91771c | 1075 | |
5e754f33 | 1076 | clk = devm_clk_get(&dev->dev, NULL); |
50f690d8 LW |
1077 | if (IS_ERR(clk)) |
1078 | return PTR_ERR(clk); | |
efec381c | 1079 | clk_prepare(clk); |
af7dc228 | 1080 | |
5e754f33 | 1081 | nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); |
50f690d8 LW |
1082 | if (!nmk_chip) |
1083 | return -ENOMEM; | |
513c27f8 | 1084 | |
2ec1d359 AR |
1085 | /* |
1086 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1087 | * so we can simply convert the resource address, without remapping | |
1088 | */ | |
33b744b3 | 1089 | nmk_chip->bank = dev->id; |
af7dc228 | 1090 | nmk_chip->clk = clk; |
8d91771c | 1091 | nmk_chip->addr = base; |
2ec1d359 | 1092 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1093 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1094 | nmk_chip->secondary_parent_irq = secondary_irq; |
1095 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1096 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1097 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1098 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1099 | |
1100 | chip = &nmk_chip->chip; | |
1101 | chip->base = pdata->first_gpio; | |
e493e06f | 1102 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1103 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1104 | chip->dev = &dev->dev; |
1105 | chip->owner = THIS_MODULE; | |
1106 | ||
ebc6178d RV |
1107 | clk_enable(nmk_chip->clk); |
1108 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1109 | clk_disable(nmk_chip->clk); | |
1110 | ||
072e82a1 | 1111 | #ifdef CONFIG_OF_GPIO |
513c27f8 | 1112 | chip->of_node = np; |
072e82a1 | 1113 | #endif |
513c27f8 | 1114 | |
2ec1d359 AR |
1115 | ret = gpiochip_add(&nmk_chip->chip); |
1116 | if (ret) | |
50f690d8 | 1117 | return ret; |
2ec1d359 | 1118 | |
01727e61 RV |
1119 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1120 | ||
1121 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
513c27f8 | 1122 | |
3e3c62ca | 1123 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1124 | |
51f58c68 | 1125 | if (!np) |
aa6e379a | 1126 | irq_start = pdata->first_irq; |
38843e29 | 1127 | nmk_chip->domain = irq_domain_add_simple(np, |
6054b9ca LW |
1128 | NMK_GPIO_PER_CHIP, irq_start, |
1129 | &nmk_gpio_irq_simple_ops, nmk_chip); | |
a60b57ed | 1130 | if (!nmk_chip->domain) { |
2ee38d4d | 1131 | dev_err(&dev->dev, "failed to create irqdomain\n"); |
50f690d8 LW |
1132 | /* Just do this, no matter if it fails */ |
1133 | ret = gpiochip_remove(&nmk_chip->chip); | |
1134 | return -ENOSYS; | |
a60b57ed LJ |
1135 | } |
1136 | ||
2ec1d359 AR |
1137 | nmk_gpio_init_irq(nmk_chip); |
1138 | ||
513c27f8 LJ |
1139 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1140 | ||
2ec1d359 | 1141 | return 0; |
2ec1d359 AR |
1142 | } |
1143 | ||
e98ea774 LW |
1144 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) |
1145 | { | |
1146 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1147 | ||
1148 | return npct->soc->ngroups; | |
1149 | } | |
1150 | ||
1151 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | |
1152 | unsigned selector) | |
1153 | { | |
1154 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1155 | ||
1156 | return npct->soc->groups[selector].name; | |
1157 | } | |
1158 | ||
1159 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
1160 | const unsigned **pins, | |
1161 | unsigned *num_pins) | |
1162 | { | |
1163 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1164 | ||
1165 | *pins = npct->soc->groups[selector].pins; | |
1166 | *num_pins = npct->soc->groups[selector].npins; | |
1167 | return 0; | |
1168 | } | |
1169 | ||
24cbdd75 LW |
1170 | static struct pinctrl_gpio_range * |
1171 | nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) | |
1172 | { | |
1173 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1174 | int i; | |
1175 | ||
1176 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1177 | struct pinctrl_gpio_range *range; | |
1178 | ||
1179 | range = &npct->soc->gpio_ranges[i]; | |
1180 | if (offset >= range->pin_base && | |
1181 | offset <= (range->pin_base + range->npins - 1)) | |
1182 | return range; | |
1183 | } | |
1184 | return NULL; | |
1185 | } | |
1186 | ||
e98ea774 LW |
1187 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1188 | unsigned offset) | |
1189 | { | |
24cbdd75 LW |
1190 | struct pinctrl_gpio_range *range; |
1191 | struct gpio_chip *chip; | |
1192 | ||
1193 | range = nmk_match_gpio_range(pctldev, offset); | |
1194 | if (!range || !range->gc) { | |
1195 | seq_printf(s, "invalid pin offset"); | |
1196 | return; | |
1197 | } | |
1198 | chip = range->gc; | |
2249b19f | 1199 | nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); |
e98ea774 LW |
1200 | } |
1201 | ||
e32af889 GF |
1202 | static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, |
1203 | struct pinctrl_map *map, unsigned num_maps) | |
1204 | { | |
1205 | int i; | |
1206 | ||
1207 | for (i = 0; i < num_maps; i++) | |
1208 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) | |
1209 | kfree(map[i].data.configs.configs); | |
1210 | kfree(map); | |
1211 | } | |
1212 | ||
1213 | static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, | |
1214 | unsigned *num_maps, unsigned reserve) | |
1215 | { | |
1216 | unsigned old_num = *reserved_maps; | |
1217 | unsigned new_num = *num_maps + reserve; | |
1218 | struct pinctrl_map *new_map; | |
1219 | ||
1220 | if (old_num >= new_num) | |
1221 | return 0; | |
1222 | ||
1223 | new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); | |
1224 | if (!new_map) | |
1225 | return -ENOMEM; | |
1226 | ||
1227 | memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); | |
1228 | ||
1229 | *map = new_map; | |
1230 | *reserved_maps = new_num; | |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, | |
1236 | unsigned *num_maps, const char *group, | |
1237 | const char *function) | |
1238 | { | |
1239 | if (*num_maps == *reserved_maps) | |
1240 | return -ENOSPC; | |
1241 | ||
1242 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
1243 | (*map)[*num_maps].data.mux.group = group; | |
1244 | (*map)[*num_maps].data.mux.function = function; | |
1245 | (*num_maps)++; | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | static int nmk_dt_add_map_configs(struct pinctrl_map **map, | |
1251 | unsigned *reserved_maps, | |
1252 | unsigned *num_maps, const char *group, | |
1253 | unsigned long *configs, unsigned num_configs) | |
1254 | { | |
1255 | unsigned long *dup_configs; | |
1256 | ||
1257 | if (*num_maps == *reserved_maps) | |
1258 | return -ENOSPC; | |
1259 | ||
1260 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
1261 | GFP_KERNEL); | |
1262 | if (!dup_configs) | |
1263 | return -ENOMEM; | |
1264 | ||
1265 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
1266 | ||
1267 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
1268 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
1269 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
1270 | (*num_maps)++; | |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
87ff934a SK |
1275 | #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } |
1276 | #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ | |
e32af889 GF |
1277 | .size = ARRAY_SIZE(y), } |
1278 | ||
1279 | static const unsigned long nmk_pin_input_modes[] = { | |
1280 | PIN_INPUT_NOPULL, | |
1281 | PIN_INPUT_PULLUP, | |
1282 | PIN_INPUT_PULLDOWN, | |
1283 | }; | |
1284 | ||
1285 | static const unsigned long nmk_pin_output_modes[] = { | |
1286 | PIN_OUTPUT_LOW, | |
1287 | PIN_OUTPUT_HIGH, | |
1288 | PIN_DIR_OUTPUT, | |
1289 | }; | |
1290 | ||
1291 | static const unsigned long nmk_pin_sleep_modes[] = { | |
1292 | PIN_SLEEPMODE_DISABLED, | |
1293 | PIN_SLEEPMODE_ENABLED, | |
1294 | }; | |
1295 | ||
1296 | static const unsigned long nmk_pin_sleep_input_modes[] = { | |
1297 | PIN_SLPM_INPUT_NOPULL, | |
1298 | PIN_SLPM_INPUT_PULLUP, | |
1299 | PIN_SLPM_INPUT_PULLDOWN, | |
1300 | PIN_SLPM_DIR_INPUT, | |
1301 | }; | |
1302 | ||
1303 | static const unsigned long nmk_pin_sleep_output_modes[] = { | |
1304 | PIN_SLPM_OUTPUT_LOW, | |
1305 | PIN_SLPM_OUTPUT_HIGH, | |
1306 | PIN_SLPM_DIR_OUTPUT, | |
1307 | }; | |
1308 | ||
1309 | static const unsigned long nmk_pin_sleep_wakeup_modes[] = { | |
1310 | PIN_SLPM_WAKEUP_DISABLE, | |
1311 | PIN_SLPM_WAKEUP_ENABLE, | |
1312 | }; | |
1313 | ||
1314 | static const unsigned long nmk_pin_gpio_modes[] = { | |
1315 | PIN_GPIOMODE_DISABLED, | |
1316 | PIN_GPIOMODE_ENABLED, | |
1317 | }; | |
1318 | ||
1319 | static const unsigned long nmk_pin_sleep_pdis_modes[] = { | |
1320 | PIN_SLPM_PDIS_DISABLED, | |
1321 | PIN_SLPM_PDIS_ENABLED, | |
1322 | }; | |
1323 | ||
1324 | struct nmk_cfg_param { | |
1325 | const char *property; | |
1326 | unsigned long config; | |
1327 | const unsigned long *choice; | |
1328 | int size; | |
1329 | }; | |
1330 | ||
1331 | static const struct nmk_cfg_param nmk_cfg_params[] = { | |
1332 | NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), | |
1333 | NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), | |
1334 | NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), | |
1335 | NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), | |
1336 | NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), | |
1337 | NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), | |
1338 | NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), | |
1339 | NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), | |
1340 | }; | |
1341 | ||
1342 | static int nmk_dt_pin_config(int index, int val, unsigned long *config) | |
1343 | { | |
1344 | int ret = 0; | |
1345 | ||
1346 | if (nmk_cfg_params[index].choice == NULL) | |
1347 | *config = nmk_cfg_params[index].config; | |
1348 | else { | |
1349 | /* test if out of range */ | |
1350 | if (val < nmk_cfg_params[index].size) { | |
1351 | *config = nmk_cfg_params[index].config | | |
1352 | nmk_cfg_params[index].choice[val]; | |
1353 | } | |
1354 | } | |
1355 | return ret; | |
1356 | } | |
1357 | ||
1358 | static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) | |
1359 | { | |
1360 | int i, pin_number; | |
1361 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1362 | ||
1363 | if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) | |
1364 | for (i = 0; i < npct->soc->npins; i++) | |
1365 | if (npct->soc->pins[i].number == pin_number) | |
1366 | return npct->soc->pins[i].name; | |
1367 | return NULL; | |
1368 | } | |
1369 | ||
1370 | static bool nmk_pinctrl_dt_get_config(struct device_node *np, | |
1371 | unsigned long *configs) | |
1372 | { | |
1373 | bool has_config = 0; | |
1374 | unsigned long cfg = 0; | |
1375 | int i, val, ret; | |
1376 | ||
1377 | for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { | |
1378 | ret = of_property_read_u32(np, | |
1379 | nmk_cfg_params[i].property, &val); | |
1380 | if (ret != -EINVAL) { | |
1381 | if (nmk_dt_pin_config(i, val, &cfg) == 0) { | |
1382 | *configs |= cfg; | |
1383 | has_config = 1; | |
1384 | } | |
1385 | } | |
1386 | } | |
1387 | ||
1388 | return has_config; | |
1389 | } | |
1390 | ||
2230a36e | 1391 | static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
e32af889 GF |
1392 | struct device_node *np, |
1393 | struct pinctrl_map **map, | |
1394 | unsigned *reserved_maps, | |
1395 | unsigned *num_maps) | |
1396 | { | |
1397 | int ret; | |
1398 | const char *function = NULL; | |
1399 | unsigned long configs = 0; | |
1400 | bool has_config = 0; | |
1401 | unsigned reserve = 0; | |
1402 | struct property *prop; | |
1403 | const char *group, *gpio_name; | |
1404 | struct device_node *np_config; | |
1405 | ||
1406 | ret = of_property_read_string(np, "ste,function", &function); | |
1407 | if (ret >= 0) | |
1408 | reserve = 1; | |
1409 | ||
1410 | has_config = nmk_pinctrl_dt_get_config(np, &configs); | |
1411 | ||
1412 | np_config = of_parse_phandle(np, "ste,config", 0); | |
1413 | if (np_config) | |
1414 | has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); | |
1415 | ||
1416 | ret = of_property_count_strings(np, "ste,pins"); | |
1417 | if (ret < 0) | |
1418 | goto exit; | |
1419 | ||
1420 | if (has_config) | |
1421 | reserve++; | |
1422 | ||
1423 | reserve *= ret; | |
1424 | ||
1425 | ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve); | |
1426 | if (ret < 0) | |
1427 | goto exit; | |
1428 | ||
1429 | of_property_for_each_string(np, "ste,pins", prop, group) { | |
1430 | if (function) { | |
1431 | ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, | |
1432 | group, function); | |
1433 | if (ret < 0) | |
1434 | goto exit; | |
1435 | } | |
1436 | if (has_config) { | |
1437 | gpio_name = nmk_find_pin_name(pctldev, group); | |
1438 | ||
1439 | ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps, | |
1440 | gpio_name, &configs, 1); | |
1441 | if (ret < 0) | |
1442 | goto exit; | |
1443 | } | |
1444 | ||
1445 | } | |
1446 | exit: | |
1447 | return ret; | |
1448 | } | |
1449 | ||
2230a36e | 1450 | static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
e32af889 GF |
1451 | struct device_node *np_config, |
1452 | struct pinctrl_map **map, unsigned *num_maps) | |
1453 | { | |
1454 | unsigned reserved_maps; | |
1455 | struct device_node *np; | |
1456 | int ret; | |
1457 | ||
1458 | reserved_maps = 0; | |
1459 | *map = NULL; | |
1460 | *num_maps = 0; | |
1461 | ||
1462 | for_each_child_of_node(np_config, np) { | |
1463 | ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, | |
1464 | &reserved_maps, num_maps); | |
1465 | if (ret < 0) { | |
1466 | nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps); | |
1467 | return ret; | |
1468 | } | |
1469 | } | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
022ab148 | 1474 | static const struct pinctrl_ops nmk_pinctrl_ops = { |
e98ea774 LW |
1475 | .get_groups_count = nmk_get_groups_cnt, |
1476 | .get_group_name = nmk_get_group_name, | |
1477 | .get_group_pins = nmk_get_group_pins, | |
1478 | .pin_dbg_show = nmk_pin_dbg_show, | |
e32af889 GF |
1479 | .dt_node_to_map = nmk_pinctrl_dt_node_to_map, |
1480 | .dt_free_map = nmk_pinctrl_dt_free_map, | |
e98ea774 LW |
1481 | }; |
1482 | ||
dbfe8ca2 LW |
1483 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
1484 | { | |
1485 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1486 | ||
1487 | return npct->soc->nfunctions; | |
1488 | } | |
1489 | ||
1490 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1491 | unsigned function) | |
1492 | { | |
1493 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1494 | ||
1495 | return npct->soc->functions[function].name; | |
1496 | } | |
1497 | ||
1498 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1499 | unsigned function, | |
1500 | const char * const **groups, | |
1501 | unsigned * const num_groups) | |
1502 | { | |
1503 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1504 | ||
1505 | *groups = npct->soc->functions[function].groups; | |
1506 | *num_groups = npct->soc->functions[function].ngroups; | |
1507 | ||
1508 | return 0; | |
1509 | } | |
1510 | ||
1511 | static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, | |
1512 | unsigned group) | |
1513 | { | |
1514 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1515 | const struct nmk_pingroup *g; | |
1516 | static unsigned int slpm[NUM_BANKS]; | |
f84b4171 | 1517 | unsigned long flags = 0; |
dbfe8ca2 LW |
1518 | bool glitch; |
1519 | int ret = -EINVAL; | |
1520 | int i; | |
1521 | ||
1522 | g = &npct->soc->groups[group]; | |
1523 | ||
1524 | if (g->altsetting < 0) | |
1525 | return -EINVAL; | |
1526 | ||
1527 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
1528 | ||
daf73174 LW |
1529 | /* |
1530 | * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, | |
1531 | * we may pass through an undesired state. In this case we take | |
1532 | * some extra care. | |
1533 | * | |
1534 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
1535 | * - Save SLPM registers (since we have a shadow register in the | |
1536 | * nmk_chip we're using that as backup) | |
1537 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
1538 | * - Configure the GPIO registers for the IOs that are being switched | |
1539 | * - Set IOFORCE=1 | |
1540 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
1541 | * - Set IOFORCE=0 | |
1542 | * - Restore SLPM registers | |
1543 | * - Any spurious wake up event during switch sequence to be ignored | |
1544 | * and cleared | |
1545 | * | |
1546 | * We REALLY need to save ALL slpm registers, because the external | |
1547 | * IOFORCE will switch *all* ports to their sleepmode setting to as | |
1548 | * to avoid glitches. (Not just one port!) | |
1549 | */ | |
c22df08c | 1550 | glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); |
dbfe8ca2 LW |
1551 | |
1552 | if (glitch) { | |
1553 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
1554 | ||
1555 | /* Initially don't put any pins to sleep when switching */ | |
1556 | memset(slpm, 0xff, sizeof(slpm)); | |
1557 | ||
1558 | /* | |
1559 | * Then mask the pins that need to be sleeping now when we're | |
1560 | * switching to the ALT C function. | |
1561 | */ | |
1562 | for (i = 0; i < g->npins; i++) | |
1563 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | |
1564 | nmk_gpio_glitch_slpm_init(slpm); | |
1565 | } | |
1566 | ||
1567 | for (i = 0; i < g->npins; i++) { | |
1568 | struct pinctrl_gpio_range *range; | |
1569 | struct nmk_gpio_chip *nmk_chip; | |
1570 | struct gpio_chip *chip; | |
1571 | unsigned bit; | |
1572 | ||
1573 | range = nmk_match_gpio_range(pctldev, g->pins[i]); | |
1574 | if (!range) { | |
1575 | dev_err(npct->dev, | |
1576 | "invalid pin offset %d in group %s at index %d\n", | |
1577 | g->pins[i], g->name, i); | |
1578 | goto out_glitch; | |
1579 | } | |
1580 | if (!range->gc) { | |
1581 | dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", | |
1582 | g->pins[i], g->name, i); | |
1583 | goto out_glitch; | |
1584 | } | |
1585 | chip = range->gc; | |
1586 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1587 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); | |
1588 | ||
1589 | clk_enable(nmk_chip->clk); | |
1590 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | |
1591 | /* | |
1592 | * If the pin is switching to altfunc, and there was an | |
1593 | * interrupt installed on it which has been lazy disabled, | |
1594 | * actually mask the interrupt to prevent spurious interrupts | |
1595 | * that would occur while the pin is under control of the | |
1596 | * peripheral. Only SKE does this. | |
1597 | */ | |
1598 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | |
1599 | ||
c22df08c JNG |
1600 | __nmk_gpio_set_mode_safe(nmk_chip, bit, |
1601 | (g->altsetting & NMK_GPIO_ALT_C), glitch); | |
dbfe8ca2 | 1602 | clk_disable(nmk_chip->clk); |
c22df08c JNG |
1603 | |
1604 | /* | |
1605 | * Call PRCM GPIOCR config function in case ALTC | |
1606 | * has been selected: | |
1607 | * - If selection is a ALTCx, some bits in PRCM GPIOCR registers | |
1608 | * must be set. | |
1609 | * - If selection is pure ALTC and previous selection was ALTCx, | |
1610 | * then some bits in PRCM GPIOCR registers must be cleared. | |
1611 | */ | |
1612 | if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) | |
1613 | nmk_prcm_altcx_set_mode(npct, g->pins[i], | |
1614 | g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); | |
dbfe8ca2 LW |
1615 | } |
1616 | ||
1617 | /* When all pins are successfully reconfigured we get here */ | |
1618 | ret = 0; | |
1619 | ||
1620 | out_glitch: | |
1621 | if (glitch) { | |
1622 | nmk_gpio_glitch_slpm_restore(slpm); | |
1623 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
1624 | } | |
1625 | ||
1626 | return ret; | |
1627 | } | |
1628 | ||
1629 | static void nmk_pmx_disable(struct pinctrl_dev *pctldev, | |
1630 | unsigned function, unsigned group) | |
1631 | { | |
1632 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1633 | const struct nmk_pingroup *g; | |
1634 | ||
1635 | g = &npct->soc->groups[group]; | |
1636 | ||
1637 | if (g->altsetting < 0) | |
1638 | return; | |
1639 | ||
1640 | /* Poke out the mux, set the pin to some default state? */ | |
1641 | dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
1642 | } | |
1643 | ||
5212d096 AL |
1644 | static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, |
1645 | struct pinctrl_gpio_range *range, | |
1646 | unsigned offset) | |
dbfe8ca2 LW |
1647 | { |
1648 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1649 | struct nmk_gpio_chip *nmk_chip; | |
1650 | struct gpio_chip *chip; | |
1651 | unsigned bit; | |
1652 | ||
1653 | if (!range) { | |
1654 | dev_err(npct->dev, "invalid range\n"); | |
1655 | return -EINVAL; | |
1656 | } | |
1657 | if (!range->gc) { | |
1658 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
1659 | return -EINVAL; | |
1660 | } | |
1661 | chip = range->gc; | |
1662 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1663 | ||
1664 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
1665 | ||
1666 | clk_enable(nmk_chip->clk); | |
1667 | bit = offset % NMK_GPIO_PER_CHIP; | |
1668 | /* There is no glitch when converting any pin to GPIO */ | |
1669 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1670 | clk_disable(nmk_chip->clk); | |
1671 | ||
1672 | return 0; | |
1673 | } | |
1674 | ||
5212d096 AL |
1675 | static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, |
1676 | struct pinctrl_gpio_range *range, | |
1677 | unsigned offset) | |
dbfe8ca2 LW |
1678 | { |
1679 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1680 | ||
1681 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
1682 | /* Set the pin to some default state, GPIO is usually default */ | |
1683 | } | |
1684 | ||
022ab148 | 1685 | static const struct pinmux_ops nmk_pinmux_ops = { |
dbfe8ca2 LW |
1686 | .get_functions_count = nmk_pmx_get_funcs_cnt, |
1687 | .get_function_name = nmk_pmx_get_func_name, | |
1688 | .get_function_groups = nmk_pmx_get_func_groups, | |
1689 | .enable = nmk_pmx_enable, | |
1690 | .disable = nmk_pmx_disable, | |
1691 | .gpio_request_enable = nmk_gpio_request_enable, | |
1692 | .gpio_disable_free = nmk_gpio_disable_free, | |
1693 | }; | |
1694 | ||
5212d096 AL |
1695 | static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, |
1696 | unsigned long *config) | |
d41af627 LW |
1697 | { |
1698 | /* Not implemented */ | |
1699 | return -EINVAL; | |
1700 | } | |
1701 | ||
5212d096 | 1702 | static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
03b054e9 | 1703 | unsigned long *configs, unsigned num_configs) |
d41af627 LW |
1704 | { |
1705 | static const char *pullnames[] = { | |
1706 | [NMK_GPIO_PULL_NONE] = "none", | |
1707 | [NMK_GPIO_PULL_UP] = "up", | |
1708 | [NMK_GPIO_PULL_DOWN] = "down", | |
1709 | [3] /* illegal */ = "??" | |
1710 | }; | |
1711 | static const char *slpmnames[] = { | |
1712 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | |
1713 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
1714 | }; | |
1715 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1716 | struct nmk_gpio_chip *nmk_chip; | |
1717 | struct pinctrl_gpio_range *range; | |
1718 | struct gpio_chip *chip; | |
1719 | unsigned bit; | |
03b054e9 SY |
1720 | pin_cfg_t cfg; |
1721 | int pull, slpm, output, val, i; | |
1722 | bool lowemi, gpiomode, sleep; | |
d41af627 LW |
1723 | |
1724 | range = nmk_match_gpio_range(pctldev, pin); | |
1725 | if (!range) { | |
1726 | dev_err(npct->dev, "invalid pin offset %d\n", pin); | |
1727 | return -EINVAL; | |
1728 | } | |
1729 | if (!range->gc) { | |
1730 | dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", | |
1731 | pin); | |
1732 | return -EINVAL; | |
1733 | } | |
1734 | chip = range->gc; | |
1735 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1736 | ||
03b054e9 | 1737 | for (i = 0; i < num_configs; i++) { |
d41af627 | 1738 | /* |
03b054e9 SY |
1739 | * The pin config contains pin number and altfunction fields, |
1740 | * here we just ignore that part. It's being handled by the | |
1741 | * framework and pinmux callback respectively. | |
d41af627 | 1742 | */ |
03b054e9 SY |
1743 | cfg = (pin_cfg_t) configs[i]; |
1744 | pull = PIN_PULL(cfg); | |
1745 | slpm = PIN_SLPM(cfg); | |
1746 | output = PIN_DIR(cfg); | |
1747 | val = PIN_VAL(cfg); | |
1748 | lowemi = PIN_LOWEMI(cfg); | |
1749 | gpiomode = PIN_GPIOMODE(cfg); | |
1750 | sleep = PIN_SLEEPMODE(cfg); | |
1751 | ||
1752 | if (sleep) { | |
1753 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
1754 | int slpm_output = PIN_SLPM_DIR(cfg); | |
1755 | int slpm_val = PIN_SLPM_VAL(cfg); | |
1756 | ||
1757 | /* All pins go into GPIO mode at sleep */ | |
1758 | gpiomode = true; | |
1759 | ||
1760 | /* | |
1761 | * The SLPM_* values are normal values + 1 to allow zero | |
1762 | * to mean "same as normal". | |
1763 | */ | |
1764 | if (slpm_pull) | |
1765 | pull = slpm_pull - 1; | |
1766 | if (slpm_output) | |
1767 | output = slpm_output - 1; | |
1768 | if (slpm_val) | |
1769 | val = slpm_val - 1; | |
1770 | ||
1771 | dev_dbg(nmk_chip->chip.dev, | |
1772 | "pin %d: sleep pull %s, dir %s, val %s\n", | |
1773 | pin, | |
1774 | slpm_pull ? pullnames[pull] : "same", | |
1775 | slpm_output ? (output ? "output" : "input") | |
1776 | : "same", | |
1777 | slpm_val ? (val ? "high" : "low") : "same"); | |
1778 | } | |
d41af627 | 1779 | |
03b054e9 SY |
1780 | dev_dbg(nmk_chip->chip.dev, |
1781 | "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", | |
1782 | pin, cfg, pullnames[pull], slpmnames[slpm], | |
1783 | output ? "output " : "input", | |
1784 | output ? (val ? "high" : "low") : "", | |
1785 | lowemi ? "on" : "off"); | |
d41af627 | 1786 | |
03b054e9 SY |
1787 | clk_enable(nmk_chip->clk); |
1788 | bit = pin % NMK_GPIO_PER_CHIP; | |
1789 | if (gpiomode) | |
1790 | /* No glitch when going to GPIO mode */ | |
1791 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1792 | if (output) | |
1793 | __nmk_gpio_make_output(nmk_chip, bit, val); | |
1794 | else { | |
1795 | __nmk_gpio_make_input(nmk_chip, bit); | |
1796 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | |
1797 | } | |
1798 | /* TODO: isn't this only applicable on output pins? */ | |
1799 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | |
1800 | ||
1801 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | |
1802 | clk_disable(nmk_chip->clk); | |
1803 | } /* for each config */ | |
d41af627 | 1804 | |
d41af627 LW |
1805 | return 0; |
1806 | } | |
1807 | ||
022ab148 | 1808 | static const struct pinconf_ops nmk_pinconf_ops = { |
d41af627 LW |
1809 | .pin_config_get = nmk_pin_config_get, |
1810 | .pin_config_set = nmk_pin_config_set, | |
1811 | }; | |
1812 | ||
e98ea774 LW |
1813 | static struct pinctrl_desc nmk_pinctrl_desc = { |
1814 | .name = "pinctrl-nomadik", | |
1815 | .pctlops = &nmk_pinctrl_ops, | |
dbfe8ca2 | 1816 | .pmxops = &nmk_pinmux_ops, |
d41af627 | 1817 | .confops = &nmk_pinconf_ops, |
e98ea774 LW |
1818 | .owner = THIS_MODULE, |
1819 | }; | |
1820 | ||
855f80cd | 1821 | static const struct of_device_id nmk_pinctrl_match[] = { |
6010d403 | 1822 | { |
3fd765a9 | 1823 | .compatible = "stericsson,stn8815-pinctrl", |
6010d403 LW |
1824 | .data = (void *)PINCTRL_NMK_STN8815, |
1825 | }, | |
855f80cd | 1826 | { |
6b09a834 | 1827 | .compatible = "stericsson,db8500-pinctrl", |
855f80cd LJ |
1828 | .data = (void *)PINCTRL_NMK_DB8500, |
1829 | }, | |
356d3e45 | 1830 | { |
6b09a834 | 1831 | .compatible = "stericsson,db8540-pinctrl", |
356d3e45 GF |
1832 | .data = (void *)PINCTRL_NMK_DB8540, |
1833 | }, | |
855f80cd LJ |
1834 | {}, |
1835 | }; | |
1836 | ||
8d99b32d JD |
1837 | static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) |
1838 | { | |
1839 | struct nmk_pinctrl *npct; | |
1840 | ||
1841 | npct = platform_get_drvdata(pdev); | |
1842 | if (!npct) | |
1843 | return -EINVAL; | |
1844 | ||
1845 | return pinctrl_force_sleep(npct->pctl); | |
1846 | } | |
1847 | ||
1848 | static int nmk_pinctrl_resume(struct platform_device *pdev) | |
1849 | { | |
1850 | struct nmk_pinctrl *npct; | |
1851 | ||
1852 | npct = platform_get_drvdata(pdev); | |
1853 | if (!npct) | |
1854 | return -EINVAL; | |
1855 | ||
1856 | return pinctrl_force_default(npct->pctl); | |
1857 | } | |
1858 | ||
150632b0 | 1859 | static int nmk_pinctrl_probe(struct platform_device *pdev) |
e98ea774 LW |
1860 | { |
1861 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
855f80cd | 1862 | struct device_node *np = pdev->dev.of_node; |
32e67eee | 1863 | struct device_node *prcm_np; |
e98ea774 | 1864 | struct nmk_pinctrl *npct; |
f1671bf5 | 1865 | struct resource *res; |
855f80cd | 1866 | unsigned int version = 0; |
e98ea774 LW |
1867 | int i; |
1868 | ||
1869 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | |
1870 | if (!npct) | |
1871 | return -ENOMEM; | |
1872 | ||
855f80cd LJ |
1873 | if (platid) |
1874 | version = platid->driver_data; | |
953e9e93 AL |
1875 | else if (np) { |
1876 | const struct of_device_id *match; | |
1877 | ||
1878 | match = of_match_device(nmk_pinctrl_match, &pdev->dev); | |
1879 | if (!match) | |
1880 | return -ENODEV; | |
1881 | version = (unsigned int) match->data; | |
1882 | } | |
855f80cd | 1883 | |
e98ea774 | 1884 | /* Poke in other ASIC variants here */ |
f79c5ed9 LW |
1885 | if (version == PINCTRL_NMK_STN8815) |
1886 | nmk_pinctrl_stn8815_init(&npct->soc); | |
855f80cd | 1887 | if (version == PINCTRL_NMK_DB8500) |
e98ea774 | 1888 | nmk_pinctrl_db8500_init(&npct->soc); |
45a1b531 PC |
1889 | if (version == PINCTRL_NMK_DB8540) |
1890 | nmk_pinctrl_db8540_init(&npct->soc); | |
e98ea774 | 1891 | |
32e67eee LJ |
1892 | if (np) { |
1893 | prcm_np = of_parse_phandle(np, "prcm", 0); | |
1894 | if (prcm_np) | |
1895 | npct->prcm_base = of_iomap(prcm_np, 0); | |
1896 | } | |
1897 | ||
1898 | /* Allow platform passed information to over-write DT. */ | |
f1671bf5 | 1899 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
32e67eee | 1900 | if (res) |
f1671bf5 JA |
1901 | npct->prcm_base = devm_ioremap(&pdev->dev, res->start, |
1902 | resource_size(res)); | |
32e67eee LJ |
1903 | if (!npct->prcm_base) { |
1904 | if (version == PINCTRL_NMK_STN8815) { | |
1905 | dev_info(&pdev->dev, | |
1906 | "No PRCM base, " | |
1907 | "assuming no ALT-Cx control is available\n"); | |
1908 | } else { | |
1909 | dev_err(&pdev->dev, "missing PRCM base address\n"); | |
1910 | return -EINVAL; | |
f1671bf5 | 1911 | } |
f1671bf5 JA |
1912 | } |
1913 | ||
e98ea774 LW |
1914 | /* |
1915 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
1916 | * to obtain references to the struct gpio_chip * for them, and we | |
1917 | * need this to proceed. | |
1918 | */ | |
1919 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1d853ca5 | 1920 | if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { |
e98ea774 | 1921 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); |
e98ea774 LW |
1922 | return -EPROBE_DEFER; |
1923 | } | |
1d853ca5 | 1924 | npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; |
e98ea774 LW |
1925 | } |
1926 | ||
1927 | nmk_pinctrl_desc.pins = npct->soc->pins; | |
1928 | nmk_pinctrl_desc.npins = npct->soc->npins; | |
1929 | npct->dev = &pdev->dev; | |
f1671bf5 | 1930 | |
e98ea774 LW |
1931 | npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); |
1932 | if (!npct->pctl) { | |
1933 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); | |
1934 | return -EINVAL; | |
1935 | } | |
1936 | ||
1937 | /* We will handle a range of GPIO pins */ | |
1938 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) | |
1939 | pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); | |
1940 | ||
1941 | platform_set_drvdata(pdev, npct); | |
1942 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | |
1943 | ||
1944 | return 0; | |
1945 | } | |
1946 | ||
513c27f8 LJ |
1947 | static const struct of_device_id nmk_gpio_match[] = { |
1948 | { .compatible = "st,nomadik-gpio", }, | |
1949 | {} | |
1950 | }; | |
1951 | ||
3e3c62ca RV |
1952 | static struct platform_driver nmk_gpio_driver = { |
1953 | .driver = { | |
2ec1d359 AR |
1954 | .owner = THIS_MODULE, |
1955 | .name = "gpio", | |
513c27f8 | 1956 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 1957 | }, |
2ec1d359 | 1958 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1959 | }; |
1960 | ||
e98ea774 LW |
1961 | static const struct platform_device_id nmk_pinctrl_id[] = { |
1962 | { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, | |
1963 | { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, | |
45a1b531 | 1964 | { "pinctrl-db8540", PINCTRL_NMK_DB8540 }, |
8c995d6d | 1965 | { } |
e98ea774 LW |
1966 | }; |
1967 | ||
1968 | static struct platform_driver nmk_pinctrl_driver = { | |
1969 | .driver = { | |
1970 | .owner = THIS_MODULE, | |
1971 | .name = "pinctrl-nomadik", | |
855f80cd | 1972 | .of_match_table = nmk_pinctrl_match, |
e98ea774 LW |
1973 | }, |
1974 | .probe = nmk_pinctrl_probe, | |
1975 | .id_table = nmk_pinctrl_id, | |
8d99b32d JD |
1976 | #ifdef CONFIG_PM |
1977 | .suspend = nmk_pinctrl_suspend, | |
1978 | .resume = nmk_pinctrl_resume, | |
1979 | #endif | |
e98ea774 LW |
1980 | }; |
1981 | ||
2ec1d359 AR |
1982 | static int __init nmk_gpio_init(void) |
1983 | { | |
e98ea774 LW |
1984 | int ret; |
1985 | ||
1986 | ret = platform_driver_register(&nmk_gpio_driver); | |
1987 | if (ret) | |
1988 | return ret; | |
1989 | return platform_driver_register(&nmk_pinctrl_driver); | |
2ec1d359 AR |
1990 | } |
1991 | ||
33f45ea9 | 1992 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1993 | |
1994 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1995 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1996 | MODULE_LICENSE("GPL"); |