Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
a60b57ed | 25 | #include <linux/irqdomain.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
2ec1d359 | 27 | |
adfed159 WD |
28 | #include <asm/mach/irq.h> |
29 | ||
378be066 | 30 | #include <plat/pincfg.h> |
0f332861 | 31 | #include <plat/gpio-nomadik.h> |
2ec1d359 AR |
32 | |
33 | /* | |
34 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
35 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 36 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
37 | * |
38 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
39 | */ | |
40 | ||
01727e61 RV |
41 | #define NMK_GPIO_PER_CHIP 32 |
42 | ||
2ec1d359 AR |
43 | struct nmk_gpio_chip { |
44 | struct gpio_chip chip; | |
a60b57ed | 45 | struct irq_domain *domain; |
2ec1d359 | 46 | void __iomem *addr; |
af7dc228 | 47 | struct clk *clk; |
33b744b3 | 48 | unsigned int bank; |
2ec1d359 | 49 | unsigned int parent_irq; |
2c8bb0eb | 50 | int secondary_parent_irq; |
33b744b3 | 51 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 52 | void (*set_ioforce)(bool enable); |
c0fcb8db | 53 | spinlock_t lock; |
33d78647 | 54 | bool sleepmode; |
2ec1d359 AR |
55 | /* Keep track of configured edges */ |
56 | u32 edge_rising; | |
57 | u32 edge_falling; | |
b9df468d RV |
58 | u32 real_wake; |
59 | u32 rwimsc; | |
60 | u32 fwimsc; | |
6c12fe88 RV |
61 | u32 rimsc; |
62 | u32 fimsc; | |
bc6f5cf6 | 63 | u32 pull_up; |
ebc6178d | 64 | u32 lowemi; |
2ec1d359 AR |
65 | }; |
66 | ||
01727e61 RV |
67 | static struct nmk_gpio_chip * |
68 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
69 | ||
70 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
71 | ||
72 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
73 | ||
6f9a974c RV |
74 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
75 | unsigned offset, int gpio_mode) | |
76 | { | |
77 | u32 bit = 1 << offset; | |
78 | u32 afunc, bfunc; | |
79 | ||
80 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
81 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
82 | if (gpio_mode & NMK_GPIO_ALT_A) | |
83 | afunc |= bit; | |
84 | if (gpio_mode & NMK_GPIO_ALT_B) | |
85 | bfunc |= bit; | |
86 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
87 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
88 | } | |
89 | ||
81a3c298 RV |
90 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
91 | unsigned offset, enum nmk_gpio_slpm mode) | |
92 | { | |
93 | u32 bit = 1 << offset; | |
94 | u32 slpm; | |
95 | ||
96 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
97 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
98 | slpm |= bit; | |
99 | else | |
100 | slpm &= ~bit; | |
101 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
102 | } | |
103 | ||
5b327edf RV |
104 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
105 | unsigned offset, enum nmk_gpio_pull pull) | |
106 | { | |
107 | u32 bit = 1 << offset; | |
108 | u32 pdis; | |
109 | ||
110 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 111 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 112 | pdis |= bit; |
bc6f5cf6 RA |
113 | nmk_chip->pull_up &= ~bit; |
114 | } else { | |
5b327edf | 115 | pdis &= ~bit; |
bc6f5cf6 RA |
116 | } |
117 | ||
5b327edf RV |
118 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
119 | ||
bc6f5cf6 RA |
120 | if (pull == NMK_GPIO_PULL_UP) { |
121 | nmk_chip->pull_up |= bit; | |
5b327edf | 122 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
123 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
124 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 125 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 126 | } |
5b327edf RV |
127 | } |
128 | ||
ebc6178d RV |
129 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
130 | unsigned offset, bool lowemi) | |
131 | { | |
132 | u32 bit = BIT(offset); | |
133 | bool enabled = nmk_chip->lowemi & bit; | |
134 | ||
135 | if (lowemi == enabled) | |
136 | return; | |
137 | ||
138 | if (lowemi) | |
139 | nmk_chip->lowemi |= bit; | |
140 | else | |
141 | nmk_chip->lowemi &= ~bit; | |
142 | ||
143 | writel_relaxed(nmk_chip->lowemi, | |
144 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
145 | } | |
146 | ||
378be066 RV |
147 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
148 | unsigned offset) | |
149 | { | |
150 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
151 | } | |
152 | ||
6720db7c RV |
153 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
154 | unsigned offset, int val) | |
155 | { | |
156 | if (val) | |
157 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
158 | else | |
159 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
160 | } | |
161 | ||
162 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
163 | unsigned offset, int val) | |
164 | { | |
165 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
166 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
167 | } | |
168 | ||
01727e61 RV |
169 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
170 | unsigned offset, int gpio_mode, | |
171 | bool glitch) | |
172 | { | |
6c12fe88 RV |
173 | u32 rwimsc = nmk_chip->rwimsc; |
174 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
175 | |
176 | if (glitch && nmk_chip->set_ioforce) { | |
177 | u32 bit = BIT(offset); | |
178 | ||
01727e61 RV |
179 | /* Prevent spurious wakeups */ |
180 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
181 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
182 | ||
183 | nmk_chip->set_ioforce(true); | |
184 | } | |
185 | ||
186 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
187 | ||
188 | if (glitch && nmk_chip->set_ioforce) { | |
189 | nmk_chip->set_ioforce(false); | |
190 | ||
191 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
192 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
193 | } | |
194 | } | |
195 | ||
6c42ad1c RV |
196 | static void |
197 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
198 | { | |
199 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
200 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
201 | int gpio = nmk_chip->chip.base + offset; | |
202 | int irq = NOMADIK_GPIO_TO_IRQ(gpio); | |
203 | struct irq_data *d = irq_get_irq_data(irq); | |
204 | ||
205 | if (!rising && !falling) | |
206 | return; | |
207 | ||
208 | if (!d || !irqd_irq_disabled(d)) | |
209 | return; | |
210 | ||
211 | if (rising) { | |
212 | nmk_chip->rimsc &= ~BIT(offset); | |
213 | writel_relaxed(nmk_chip->rimsc, | |
214 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
215 | } | |
216 | ||
217 | if (falling) { | |
218 | nmk_chip->fimsc &= ~BIT(offset); | |
219 | writel_relaxed(nmk_chip->fimsc, | |
220 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
221 | } | |
222 | ||
223 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | |
224 | } | |
225 | ||
378be066 | 226 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 227 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
228 | { |
229 | static const char *afnames[] = { | |
230 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
231 | [NMK_GPIO_ALT_A] = "A", | |
232 | [NMK_GPIO_ALT_B] = "B", | |
233 | [NMK_GPIO_ALT_C] = "C" | |
234 | }; | |
235 | static const char *pullnames[] = { | |
236 | [NMK_GPIO_PULL_NONE] = "none", | |
237 | [NMK_GPIO_PULL_UP] = "up", | |
238 | [NMK_GPIO_PULL_DOWN] = "down", | |
239 | [3] /* illegal */ = "??" | |
240 | }; | |
241 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
242 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
243 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
244 | }; |
245 | ||
246 | int pin = PIN_NUM(cfg); | |
247 | int pull = PIN_PULL(cfg); | |
248 | int af = PIN_ALT(cfg); | |
249 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
250 | int output = PIN_DIR(cfg); |
251 | int val = PIN_VAL(cfg); | |
01727e61 | 252 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 253 | |
dacdc96c RV |
254 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
255 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
256 | output ? "output " : "input", |
257 | output ? (val ? "high" : "low") : ""); | |
258 | ||
dacdc96c RV |
259 | if (sleep) { |
260 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
261 | int slpm_output = PIN_SLPM_DIR(cfg); | |
262 | int slpm_val = PIN_SLPM_VAL(cfg); | |
263 | ||
3546d15c RV |
264 | af = NMK_GPIO_ALT_GPIO; |
265 | ||
dacdc96c RV |
266 | /* |
267 | * The SLPM_* values are normal values + 1 to allow zero to | |
268 | * mean "same as normal". | |
269 | */ | |
270 | if (slpm_pull) | |
271 | pull = slpm_pull - 1; | |
272 | if (slpm_output) | |
273 | output = slpm_output - 1; | |
274 | if (slpm_val) | |
275 | val = slpm_val - 1; | |
276 | ||
277 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
278 | pin, | |
279 | slpm_pull ? pullnames[pull] : "same", | |
280 | slpm_output ? (output ? "output" : "input") : "same", | |
281 | slpm_val ? (val ? "high" : "low") : "same"); | |
282 | } | |
283 | ||
6720db7c RV |
284 | if (output) |
285 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
286 | else { | |
287 | __nmk_gpio_make_input(nmk_chip, offset); | |
288 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
289 | } | |
378be066 | 290 | |
ebc6178d RV |
291 | __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); |
292 | ||
6c42ad1c RV |
293 | /* |
294 | * If the pin is switching to altfunc, and there was an interrupt | |
295 | * installed on it which has been lazy disabled, actually mask the | |
296 | * interrupt to prevent spurious interrupts that would occur while the | |
297 | * pin is under control of the peripheral. Only SKE does this. | |
298 | */ | |
299 | if (af != NMK_GPIO_ALT_GPIO) | |
300 | nmk_gpio_disable_lazy_irq(nmk_chip, offset); | |
301 | ||
01727e61 RV |
302 | /* |
303 | * If we've backed up the SLPM registers (glitch workaround), modify | |
304 | * the backups since they will be restored. | |
305 | */ | |
306 | if (slpmregs) { | |
307 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
308 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
309 | else | |
310 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
311 | } else | |
312 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
313 | ||
314 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
315 | } | |
316 | ||
317 | /* | |
318 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
319 | * - Save SLPM registers | |
320 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
321 | * - Configure the GPIO registers for the IOs that are being switched | |
322 | * - Set IOFORCE=1 | |
323 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
324 | * - Set IOFORCE=0 | |
325 | * - Restore SLPM registers | |
326 | * - Any spurious wake up event during switch sequence to be ignored and | |
327 | * cleared | |
328 | */ | |
329 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
330 | { | |
331 | int i; | |
332 | ||
333 | for (i = 0; i < NUM_BANKS; i++) { | |
334 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
335 | unsigned int temp = slpm[i]; | |
336 | ||
337 | if (!chip) | |
338 | break; | |
339 | ||
3c0227d2 RV |
340 | clk_enable(chip->clk); |
341 | ||
01727e61 RV |
342 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
343 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
344 | } | |
345 | } | |
346 | ||
347 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
348 | { | |
349 | int i; | |
350 | ||
351 | for (i = 0; i < NUM_BANKS; i++) { | |
352 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
353 | ||
354 | if (!chip) | |
355 | break; | |
356 | ||
357 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
358 | |
359 | clk_disable(chip->clk); | |
01727e61 RV |
360 | } |
361 | } | |
362 | ||
363 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
364 | { | |
365 | static unsigned int slpm[NUM_BANKS]; | |
366 | unsigned long flags; | |
367 | bool glitch = false; | |
368 | int ret = 0; | |
369 | int i; | |
370 | ||
371 | for (i = 0; i < num; i++) { | |
372 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
373 | glitch = true; | |
374 | break; | |
375 | } | |
376 | } | |
377 | ||
378 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
379 | ||
380 | if (glitch) { | |
381 | memset(slpm, 0xff, sizeof(slpm)); | |
382 | ||
383 | for (i = 0; i < num; i++) { | |
384 | int pin = PIN_NUM(cfgs[i]); | |
385 | int offset = pin % NMK_GPIO_PER_CHIP; | |
386 | ||
387 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
388 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
389 | } | |
390 | ||
391 | nmk_gpio_glitch_slpm_init(slpm); | |
392 | } | |
393 | ||
394 | for (i = 0; i < num; i++) { | |
395 | struct nmk_gpio_chip *nmk_chip; | |
396 | int pin = PIN_NUM(cfgs[i]); | |
397 | ||
a60b57ed | 398 | nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; |
01727e61 RV |
399 | if (!nmk_chip) { |
400 | ret = -EINVAL; | |
401 | break; | |
402 | } | |
403 | ||
3c0227d2 | 404 | clk_enable(nmk_chip->clk); |
01727e61 | 405 | spin_lock(&nmk_chip->lock); |
a60b57ed | 406 | __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, |
01727e61 RV |
407 | cfgs[i], sleep, glitch ? slpm : NULL); |
408 | spin_unlock(&nmk_chip->lock); | |
3c0227d2 | 409 | clk_disable(nmk_chip->clk); |
01727e61 RV |
410 | } |
411 | ||
412 | if (glitch) | |
413 | nmk_gpio_glitch_slpm_restore(slpm); | |
414 | ||
415 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
416 | ||
417 | return ret; | |
378be066 RV |
418 | } |
419 | ||
420 | /** | |
421 | * nmk_config_pin - configure a pin's mux attributes | |
422 | * @cfg: pin confguration | |
423 | * | |
424 | * Configures a pin's mode (alternate function or GPIO), its pull up status, | |
425 | * and its sleep mode based on the specified configuration. The @cfg is | |
426 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
427 | * are constructed using, and can be further enhanced with, the macros in | |
428 | * plat/pincfg.h. | |
429 | * | |
430 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
431 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
432 | * calls. | |
433 | */ | |
dacdc96c | 434 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 435 | { |
01727e61 | 436 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
437 | } |
438 | EXPORT_SYMBOL(nmk_config_pin); | |
439 | ||
440 | /** | |
441 | * nmk_config_pins - configure several pins at once | |
442 | * @cfgs: array of pin configurations | |
443 | * @num: number of elments in the array | |
444 | * | |
445 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
446 | * further information. | |
447 | */ | |
448 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
449 | { | |
01727e61 | 450 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
451 | } |
452 | EXPORT_SYMBOL(nmk_config_pins); | |
453 | ||
dacdc96c RV |
454 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
455 | { | |
01727e61 | 456 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
457 | } |
458 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
459 | ||
81a3c298 RV |
460 | /** |
461 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
462 | * @gpio: pin number | |
463 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
464 | * | |
33d78647 LW |
465 | * This register is actually in the pinmux layer, not the GPIO block itself. |
466 | * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP | |
467 | * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). | |
468 | * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is | |
469 | * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. | |
470 | * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), | |
471 | * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. | |
7e3f7e59 | 472 | * |
33d78647 LW |
473 | * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO |
474 | * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is | |
475 | * entered) regardless of the altfunction selected. Also wake-up detection is | |
476 | * ENABLED. | |
477 | * | |
478 | * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains | |
479 | * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS | |
480 | * (for altfunction GPIO) or respective on-chip peripherals (for other | |
481 | * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. | |
482 | * | |
483 | * Note that enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
484 | */ |
485 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
486 | { | |
487 | struct nmk_gpio_chip *nmk_chip; | |
488 | unsigned long flags; | |
489 | ||
a60b57ed | 490 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
81a3c298 RV |
491 | if (!nmk_chip) |
492 | return -EINVAL; | |
493 | ||
3c0227d2 | 494 | clk_enable(nmk_chip->clk); |
01727e61 RV |
495 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
496 | spin_lock(&nmk_chip->lock); | |
497 | ||
a60b57ed | 498 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); |
01727e61 RV |
499 | |
500 | spin_unlock(&nmk_chip->lock); | |
501 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 502 | clk_disable(nmk_chip->clk); |
81a3c298 RV |
503 | |
504 | return 0; | |
505 | } | |
506 | ||
5b327edf RV |
507 | /** |
508 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
509 | * @gpio: pin number | |
510 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
511 | * | |
512 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
513 | * the pin is configured as an input (either explicitly or by the alternate | |
514 | * function). | |
515 | * | |
516 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
517 | * configured as an input. Otherwise, due to the way the controller registers | |
518 | * work, this function will change the value output on the pin. | |
519 | */ | |
520 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
521 | { | |
522 | struct nmk_gpio_chip *nmk_chip; | |
523 | unsigned long flags; | |
524 | ||
a60b57ed | 525 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
5b327edf RV |
526 | if (!nmk_chip) |
527 | return -EINVAL; | |
528 | ||
3c0227d2 | 529 | clk_enable(nmk_chip->clk); |
5b327edf | 530 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 531 | __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); |
5b327edf | 532 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 533 | clk_disable(nmk_chip->clk); |
5b327edf RV |
534 | |
535 | return 0; | |
536 | } | |
537 | ||
2ec1d359 | 538 | /* Mode functions */ |
9c66ee6f JA |
539 | /** |
540 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
541 | * @gpio: pin number | |
542 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
543 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
544 | * | |
545 | * Sets the mode of the specified pin to one of the alternate functions or | |
546 | * plain GPIO. | |
547 | */ | |
2ec1d359 AR |
548 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
549 | { | |
550 | struct nmk_gpio_chip *nmk_chip; | |
551 | unsigned long flags; | |
2ec1d359 | 552 | |
a60b57ed | 553 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
554 | if (!nmk_chip) |
555 | return -EINVAL; | |
556 | ||
3c0227d2 | 557 | clk_enable(nmk_chip->clk); |
2ec1d359 | 558 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 559 | __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); |
2ec1d359 | 560 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 561 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
562 | |
563 | return 0; | |
564 | } | |
565 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
566 | ||
567 | int nmk_gpio_get_mode(int gpio) | |
568 | { | |
569 | struct nmk_gpio_chip *nmk_chip; | |
570 | u32 afunc, bfunc, bit; | |
571 | ||
a60b57ed | 572 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
573 | if (!nmk_chip) |
574 | return -EINVAL; | |
575 | ||
a60b57ed | 576 | bit = 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 | 577 | |
3c0227d2 RV |
578 | clk_enable(nmk_chip->clk); |
579 | ||
2ec1d359 AR |
580 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
581 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
582 | ||
3c0227d2 RV |
583 | clk_disable(nmk_chip->clk); |
584 | ||
2ec1d359 AR |
585 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
586 | } | |
587 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
588 | ||
589 | ||
590 | /* IRQ functions */ | |
591 | static inline int nmk_gpio_get_bitmask(int gpio) | |
592 | { | |
a60b57ed | 593 | return 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 AR |
594 | } |
595 | ||
f272c00e | 596 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 597 | { |
2ec1d359 AR |
598 | struct nmk_gpio_chip *nmk_chip; |
599 | ||
f272c00e | 600 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 AR |
601 | if (!nmk_chip) |
602 | return; | |
3c0227d2 RV |
603 | |
604 | clk_enable(nmk_chip->clk); | |
a60b57ed | 605 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 606 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
607 | } |
608 | ||
4d4e20f7 RV |
609 | enum nmk_gpio_irq_type { |
610 | NORMAL, | |
611 | WAKE, | |
612 | }; | |
613 | ||
040e5ecd | 614 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
615 | int gpio, enum nmk_gpio_irq_type which, |
616 | bool enable) | |
2ec1d359 | 617 | { |
040e5ecd | 618 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
619 | u32 *rimscval; |
620 | u32 *fimscval; | |
621 | u32 rimscreg; | |
622 | u32 fimscreg; | |
623 | ||
624 | if (which == NORMAL) { | |
625 | rimscreg = NMK_GPIO_RIMSC; | |
626 | fimscreg = NMK_GPIO_FIMSC; | |
627 | rimscval = &nmk_chip->rimsc; | |
628 | fimscval = &nmk_chip->fimsc; | |
629 | } else { | |
630 | rimscreg = NMK_GPIO_RWIMSC; | |
631 | fimscreg = NMK_GPIO_FWIMSC; | |
632 | rimscval = &nmk_chip->rwimsc; | |
633 | fimscval = &nmk_chip->fwimsc; | |
634 | } | |
2ec1d359 | 635 | |
040e5ecd | 636 | /* we must individually set/clear the two edges */ |
2ec1d359 | 637 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 638 | if (enable) |
6c12fe88 | 639 | *rimscval |= bitmask; |
040e5ecd | 640 | else |
6c12fe88 RV |
641 | *rimscval &= ~bitmask; |
642 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
643 | } |
644 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 645 | if (enable) |
6c12fe88 | 646 | *fimscval |= bitmask; |
040e5ecd | 647 | else |
6c12fe88 RV |
648 | *fimscval &= ~bitmask; |
649 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 650 | } |
040e5ecd | 651 | } |
2ec1d359 | 652 | |
b9df468d RV |
653 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
654 | int gpio, bool on) | |
655 | { | |
b982ff0e RV |
656 | /* |
657 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
658 | * disabled, since setting SLPM to 1 increases power consumption, and | |
659 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
660 | */ | |
661 | if (nmk_chip->sleepmode && on) { | |
a60b57ed | 662 | __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base, |
b982ff0e | 663 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
664 | } |
665 | ||
b9df468d RV |
666 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
667 | } | |
668 | ||
669 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 670 | { |
2ec1d359 AR |
671 | struct nmk_gpio_chip *nmk_chip; |
672 | unsigned long flags; | |
040e5ecd | 673 | u32 bitmask; |
2ec1d359 | 674 | |
f272c00e | 675 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 676 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 | 677 | if (!nmk_chip) |
4d4e20f7 | 678 | return -EINVAL; |
2ec1d359 | 679 | |
3c0227d2 | 680 | clk_enable(nmk_chip->clk); |
b9df468d RV |
681 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
682 | spin_lock(&nmk_chip->lock); | |
683 | ||
a60b57ed | 684 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d RV |
685 | |
686 | if (!(nmk_chip->real_wake & bitmask)) | |
a60b57ed | 687 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
688 | |
689 | spin_unlock(&nmk_chip->lock); | |
690 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 691 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
692 | |
693 | return 0; | |
2ec1d359 AR |
694 | } |
695 | ||
f272c00e | 696 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 697 | { |
b9df468d | 698 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 699 | } |
040e5ecd | 700 | |
f272c00e | 701 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 702 | { |
b9df468d | 703 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
704 | } |
705 | ||
f272c00e | 706 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 707 | { |
7e3f7e59 RV |
708 | struct nmk_gpio_chip *nmk_chip; |
709 | unsigned long flags; | |
b9df468d | 710 | u32 bitmask; |
7e3f7e59 | 711 | |
f272c00e | 712 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
713 | if (!nmk_chip) |
714 | return -EINVAL; | |
a60b57ed | 715 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
7e3f7e59 | 716 | |
3c0227d2 | 717 | clk_enable(nmk_chip->clk); |
01727e61 RV |
718 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
719 | spin_lock(&nmk_chip->lock); | |
720 | ||
479a0c7e | 721 | if (irqd_irq_disabled(d)) |
a60b57ed | 722 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
723 | |
724 | if (on) | |
725 | nmk_chip->real_wake |= bitmask; | |
726 | else | |
727 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
728 | |
729 | spin_unlock(&nmk_chip->lock); | |
730 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 731 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
732 | |
733 | return 0; | |
040e5ecd RV |
734 | } |
735 | ||
f272c00e | 736 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 737 | { |
479a0c7e | 738 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 739 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
740 | struct nmk_gpio_chip *nmk_chip; |
741 | unsigned long flags; | |
742 | u32 bitmask; | |
743 | ||
f272c00e | 744 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 745 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 AR |
746 | if (!nmk_chip) |
747 | return -EINVAL; | |
2ec1d359 AR |
748 | if (type & IRQ_TYPE_LEVEL_HIGH) |
749 | return -EINVAL; | |
750 | if (type & IRQ_TYPE_LEVEL_LOW) | |
751 | return -EINVAL; | |
752 | ||
3c0227d2 | 753 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
754 | spin_lock_irqsave(&nmk_chip->lock, flags); |
755 | ||
7a852d80 | 756 | if (enabled) |
a60b57ed | 757 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 758 | |
b9df468d | 759 | if (enabled || wake) |
a60b57ed | 760 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 761 | |
2ec1d359 AR |
762 | nmk_chip->edge_rising &= ~bitmask; |
763 | if (type & IRQ_TYPE_EDGE_RISING) | |
764 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
765 | |
766 | nmk_chip->edge_falling &= ~bitmask; | |
767 | if (type & IRQ_TYPE_EDGE_FALLING) | |
768 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 769 | |
7a852d80 | 770 | if (enabled) |
a60b57ed | 771 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 772 | |
b9df468d | 773 | if (enabled || wake) |
a60b57ed | 774 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 775 | |
7a852d80 | 776 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 777 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
778 | |
779 | return 0; | |
780 | } | |
781 | ||
3c0227d2 RV |
782 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
783 | { | |
784 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 785 | |
3c0227d2 RV |
786 | clk_enable(nmk_chip->clk); |
787 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
788 | return 0; |
789 | } | |
790 | ||
3c0227d2 RV |
791 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
792 | { | |
793 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
794 | ||
795 | nmk_gpio_irq_mask(d); | |
796 | clk_disable(nmk_chip->clk); | |
797 | } | |
798 | ||
2ec1d359 AR |
799 | static struct irq_chip nmk_gpio_irq_chip = { |
800 | .name = "Nomadik-GPIO", | |
f272c00e LB |
801 | .irq_ack = nmk_gpio_irq_ack, |
802 | .irq_mask = nmk_gpio_irq_mask, | |
803 | .irq_unmask = nmk_gpio_irq_unmask, | |
804 | .irq_set_type = nmk_gpio_irq_set_type, | |
805 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
806 | .irq_startup = nmk_gpio_irq_startup, |
807 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
2ec1d359 AR |
808 | }; |
809 | ||
33b744b3 RV |
810 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
811 | u32 status) | |
2ec1d359 AR |
812 | { |
813 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 814 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 AR |
815 | unsigned int first_irq; |
816 | ||
adfed159 | 817 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 818 | |
6845664a | 819 | nmk_chip = irq_get_handler_data(irq); |
a60b57ed | 820 | first_irq = nmk_chip->domain->revmap_data.legacy.first_irq; |
33b744b3 RV |
821 | while (status) { |
822 | int bit = __ffs(status); | |
823 | ||
824 | generic_handle_irq(first_irq + bit); | |
825 | status &= ~BIT(bit); | |
2ec1d359 | 826 | } |
aaedaa2b | 827 | |
adfed159 | 828 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
829 | } |
830 | ||
33b744b3 RV |
831 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
832 | { | |
6845664a | 833 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
834 | u32 status; |
835 | ||
836 | clk_enable(nmk_chip->clk); | |
837 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
838 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
839 | |
840 | __nmk_gpio_irq_handler(irq, desc, status); | |
841 | } | |
842 | ||
843 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
844 | struct irq_desc *desc) | |
845 | { | |
6845664a | 846 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
847 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
848 | ||
849 | __nmk_gpio_irq_handler(irq, desc, status); | |
850 | } | |
851 | ||
2ec1d359 AR |
852 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
853 | { | |
6845664a TG |
854 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
855 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
856 | |
857 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 858 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 859 | nmk_gpio_secondary_irq_handler); |
6845664a | 860 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
861 | } |
862 | ||
2ec1d359 AR |
863 | return 0; |
864 | } | |
865 | ||
866 | /* I/O Functions */ | |
867 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) | |
868 | { | |
869 | struct nmk_gpio_chip *nmk_chip = | |
870 | container_of(chip, struct nmk_gpio_chip, chip); | |
871 | ||
3c0227d2 RV |
872 | clk_enable(nmk_chip->clk); |
873 | ||
2ec1d359 | 874 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
875 | |
876 | clk_disable(nmk_chip->clk); | |
877 | ||
2ec1d359 AR |
878 | return 0; |
879 | } | |
880 | ||
2ec1d359 AR |
881 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
882 | { | |
883 | struct nmk_gpio_chip *nmk_chip = | |
884 | container_of(chip, struct nmk_gpio_chip, chip); | |
885 | u32 bit = 1 << offset; | |
3c0227d2 RV |
886 | int value; |
887 | ||
888 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 889 | |
3c0227d2 | 890 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 891 | |
3c0227d2 RV |
892 | clk_disable(nmk_chip->clk); |
893 | ||
894 | return value; | |
2ec1d359 AR |
895 | } |
896 | ||
897 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
898 | int val) | |
899 | { | |
900 | struct nmk_gpio_chip *nmk_chip = | |
901 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 902 | |
3c0227d2 RV |
903 | clk_enable(nmk_chip->clk); |
904 | ||
6720db7c | 905 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
906 | |
907 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
908 | } |
909 | ||
6647c6c0 RV |
910 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
911 | int val) | |
912 | { | |
913 | struct nmk_gpio_chip *nmk_chip = | |
914 | container_of(chip, struct nmk_gpio_chip, chip); | |
915 | ||
3c0227d2 RV |
916 | clk_enable(nmk_chip->clk); |
917 | ||
6720db7c | 918 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 919 | |
3c0227d2 RV |
920 | clk_disable(nmk_chip->clk); |
921 | ||
6647c6c0 RV |
922 | return 0; |
923 | } | |
924 | ||
0d2aec9c RV |
925 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
926 | { | |
927 | struct nmk_gpio_chip *nmk_chip = | |
928 | container_of(chip, struct nmk_gpio_chip, chip); | |
929 | ||
a60b57ed | 930 | return irq_find_mapping(nmk_chip->domain, offset); |
0d2aec9c RV |
931 | } |
932 | ||
d0b543c7 RV |
933 | #ifdef CONFIG_DEBUG_FS |
934 | ||
935 | #include <linux/seq_file.h> | |
936 | ||
937 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
938 | { | |
939 | int mode; | |
940 | unsigned i; | |
941 | unsigned gpio = chip->base; | |
942 | int is_out; | |
943 | struct nmk_gpio_chip *nmk_chip = | |
944 | container_of(chip, struct nmk_gpio_chip, chip); | |
945 | const char *modes[] = { | |
946 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
947 | [NMK_GPIO_ALT_A] = "altA", | |
948 | [NMK_GPIO_ALT_B] = "altB", | |
949 | [NMK_GPIO_ALT_C] = "altC", | |
950 | }; | |
951 | ||
3c0227d2 RV |
952 | clk_enable(nmk_chip->clk); |
953 | ||
d0b543c7 RV |
954 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
955 | const char *label = gpiochip_is_requested(chip, i); | |
956 | bool pull; | |
957 | u32 bit = 1 << i; | |
958 | ||
d0b543c7 RV |
959 | is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; |
960 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
961 | mode = nmk_gpio_get_mode(gpio); | |
962 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
8ea72a30 | 963 | gpio, label ?: "(none)", |
d0b543c7 RV |
964 | is_out ? "out" : "in ", |
965 | chip->get | |
966 | ? (chip->get(chip, i) ? "hi" : "lo") | |
967 | : "? ", | |
968 | (mode < 0) ? "unknown" : modes[mode], | |
969 | pull ? "pull" : "none"); | |
8ea72a30 RV |
970 | |
971 | if (label && !is_out) { | |
972 | int irq = gpio_to_irq(gpio); | |
973 | struct irq_desc *desc = irq_to_desc(irq); | |
974 | ||
975 | /* This races with request_irq(), set_irq_type(), | |
976 | * and set_irq_wake() ... but those are "rare". | |
977 | */ | |
978 | if (irq >= 0 && desc->action) { | |
979 | char *trigger; | |
980 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
981 | ||
982 | if (nmk_chip->edge_rising & bitmask) | |
983 | trigger = "edge-rising"; | |
984 | else if (nmk_chip->edge_falling & bitmask) | |
985 | trigger = "edge-falling"; | |
986 | else | |
987 | trigger = "edge-undefined"; | |
988 | ||
989 | seq_printf(s, " irq-%d %s%s", | |
990 | irq, trigger, | |
991 | irqd_is_wakeup_set(&desc->irq_data) | |
992 | ? " wakeup" : ""); | |
993 | } | |
994 | } | |
995 | ||
d0b543c7 RV |
996 | seq_printf(s, "\n"); |
997 | } | |
3c0227d2 RV |
998 | |
999 | clk_disable(nmk_chip->clk); | |
d0b543c7 RV |
1000 | } |
1001 | ||
1002 | #else | |
1003 | #define nmk_gpio_dbg_show NULL | |
1004 | #endif | |
1005 | ||
2ec1d359 AR |
1006 | /* This structure is replicated for each GPIO block allocated at probe time */ |
1007 | static struct gpio_chip nmk_gpio_template = { | |
1008 | .direction_input = nmk_gpio_make_input, | |
1009 | .get = nmk_gpio_get_input, | |
1010 | .direction_output = nmk_gpio_make_output, | |
1011 | .set = nmk_gpio_set_output, | |
0d2aec9c | 1012 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 1013 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
1014 | .can_sleep = 0, |
1015 | }; | |
1016 | ||
3c0227d2 RV |
1017 | void nmk_gpio_clocks_enable(void) |
1018 | { | |
1019 | int i; | |
1020 | ||
1021 | for (i = 0; i < NUM_BANKS; i++) { | |
1022 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1023 | ||
1024 | if (!chip) | |
1025 | continue; | |
1026 | ||
1027 | clk_enable(chip->clk); | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | void nmk_gpio_clocks_disable(void) | |
1032 | { | |
1033 | int i; | |
1034 | ||
1035 | for (i = 0; i < NUM_BANKS; i++) { | |
1036 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1037 | ||
1038 | if (!chip) | |
1039 | continue; | |
1040 | ||
1041 | clk_disable(chip->clk); | |
1042 | } | |
1043 | } | |
1044 | ||
b9df468d RV |
1045 | /* |
1046 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1047 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1048 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1049 | * cpuidle. | |
1050 | * | |
1051 | * PM ops are not used since this needs to be done at the end, after all the | |
1052 | * other drivers are done with their suspend callbacks. | |
1053 | */ | |
1054 | void nmk_gpio_wakeups_suspend(void) | |
1055 | { | |
1056 | int i; | |
1057 | ||
1058 | for (i = 0; i < NUM_BANKS; i++) { | |
1059 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1060 | ||
1061 | if (!chip) | |
1062 | break; | |
1063 | ||
3c0227d2 RV |
1064 | clk_enable(chip->clk); |
1065 | ||
b9df468d RV |
1066 | writel(chip->rwimsc & chip->real_wake, |
1067 | chip->addr + NMK_GPIO_RWIMSC); | |
1068 | writel(chip->fwimsc & chip->real_wake, | |
1069 | chip->addr + NMK_GPIO_FWIMSC); | |
1070 | ||
3c0227d2 | 1071 | clk_disable(chip->clk); |
b9df468d RV |
1072 | } |
1073 | } | |
1074 | ||
1075 | void nmk_gpio_wakeups_resume(void) | |
1076 | { | |
1077 | int i; | |
1078 | ||
1079 | for (i = 0; i < NUM_BANKS; i++) { | |
1080 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1081 | ||
1082 | if (!chip) | |
1083 | break; | |
1084 | ||
3c0227d2 RV |
1085 | clk_enable(chip->clk); |
1086 | ||
b9df468d RV |
1087 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1088 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1089 | ||
3c0227d2 | 1090 | clk_disable(chip->clk); |
b9df468d RV |
1091 | } |
1092 | } | |
1093 | ||
bc6f5cf6 RA |
1094 | /* |
1095 | * Read the pull up/pull down status. | |
1096 | * A bit set in 'pull_up' means that pull up | |
1097 | * is selected if pull is enabled in PDIS register. | |
1098 | * Note: only pull up/down set via this driver can | |
1099 | * be detected due to HW limitations. | |
1100 | */ | |
1101 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1102 | { | |
1103 | if (gpio_bank < NUM_BANKS) { | |
1104 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1105 | ||
1106 | if (!chip) | |
1107 | return; | |
1108 | ||
1109 | *pull_up = chip->pull_up; | |
1110 | } | |
1111 | } | |
1112 | ||
a60b57ed LJ |
1113 | int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
1114 | irq_hw_number_t hwirq) | |
1115 | { | |
1116 | struct nmk_gpio_chip *nmk_chip = d->host_data; | |
1117 | ||
1118 | if (!nmk_chip) | |
1119 | return -EINVAL; | |
1120 | ||
1121 | irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); | |
1122 | set_irq_flags(irq, IRQF_VALID); | |
1123 | irq_set_chip_data(irq, nmk_chip); | |
1124 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | const struct irq_domain_ops nmk_gpio_irq_simple_ops = { | |
1130 | .map = nmk_gpio_irq_map, | |
1131 | .xlate = irq_domain_xlate_twocell, | |
1132 | }; | |
1133 | ||
fd0d67d6 | 1134 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1135 | { |
3e3c62ca | 1136 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
513c27f8 | 1137 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1138 | struct nmk_gpio_chip *nmk_chip; |
1139 | struct gpio_chip *chip; | |
3e3c62ca | 1140 | struct resource *res; |
af7dc228 | 1141 | struct clk *clk; |
33b744b3 | 1142 | int secondary_irq; |
8d91771c | 1143 | void __iomem *base; |
3e3c62ca | 1144 | int irq; |
2ec1d359 AR |
1145 | int ret; |
1146 | ||
513c27f8 LJ |
1147 | if (!pdata && !np) { |
1148 | dev_err(&dev->dev, "No platform data or device tree found\n"); | |
3e3c62ca | 1149 | return -ENODEV; |
513c27f8 LJ |
1150 | } |
1151 | ||
1152 | if (np) { | |
1153 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
1154 | if (!pdata) | |
1155 | return -ENOMEM; | |
1156 | ||
1157 | if (of_get_property(np, "supports-sleepmode", NULL)) | |
1158 | pdata->supports_sleepmode = true; | |
1159 | ||
1160 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | |
1161 | dev_err(&dev->dev, "gpio-bank property not found\n"); | |
1162 | ret = -EINVAL; | |
a60b57ed | 1163 | goto out; |
513c27f8 LJ |
1164 | } |
1165 | ||
1166 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | |
1167 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | |
1168 | } | |
3e3c62ca RV |
1169 | |
1170 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1171 | if (!res) { | |
1172 | ret = -ENOENT; | |
1173 | goto out; | |
1174 | } | |
1175 | ||
1176 | irq = platform_get_irq(dev, 0); | |
1177 | if (irq < 0) { | |
1178 | ret = irq; | |
1179 | goto out; | |
1180 | } | |
1181 | ||
33b744b3 RV |
1182 | secondary_irq = platform_get_irq(dev, 1); |
1183 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
1184 | ret = -EINVAL; | |
1185 | goto out; | |
1186 | } | |
1187 | ||
3e3c62ca RV |
1188 | if (request_mem_region(res->start, resource_size(res), |
1189 | dev_name(&dev->dev)) == NULL) { | |
1190 | ret = -EBUSY; | |
1191 | goto out; | |
1192 | } | |
2ec1d359 | 1193 | |
8d91771c LW |
1194 | base = ioremap(res->start, resource_size(res)); |
1195 | if (!base) { | |
1196 | ret = -ENOMEM; | |
1197 | goto out_release; | |
1198 | } | |
1199 | ||
af7dc228 RV |
1200 | clk = clk_get(&dev->dev, NULL); |
1201 | if (IS_ERR(clk)) { | |
1202 | ret = PTR_ERR(clk); | |
8d91771c | 1203 | goto out_unmap; |
af7dc228 RV |
1204 | } |
1205 | ||
2ec1d359 AR |
1206 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
1207 | if (!nmk_chip) { | |
1208 | ret = -ENOMEM; | |
af7dc228 | 1209 | goto out_clk; |
2ec1d359 | 1210 | } |
513c27f8 | 1211 | |
2ec1d359 AR |
1212 | /* |
1213 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1214 | * so we can simply convert the resource address, without remapping | |
1215 | */ | |
33b744b3 | 1216 | nmk_chip->bank = dev->id; |
af7dc228 | 1217 | nmk_chip->clk = clk; |
8d91771c | 1218 | nmk_chip->addr = base; |
2ec1d359 | 1219 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1220 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1221 | nmk_chip->secondary_parent_irq = secondary_irq; |
1222 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1223 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1224 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1225 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1226 | |
1227 | chip = &nmk_chip->chip; | |
1228 | chip->base = pdata->first_gpio; | |
e493e06f | 1229 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1230 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1231 | chip->dev = &dev->dev; |
1232 | chip->owner = THIS_MODULE; | |
1233 | ||
ebc6178d RV |
1234 | clk_enable(nmk_chip->clk); |
1235 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1236 | clk_disable(nmk_chip->clk); | |
1237 | ||
072e82a1 | 1238 | #ifdef CONFIG_OF_GPIO |
513c27f8 | 1239 | chip->of_node = np; |
072e82a1 | 1240 | #endif |
513c27f8 | 1241 | |
2ec1d359 AR |
1242 | ret = gpiochip_add(&nmk_chip->chip); |
1243 | if (ret) | |
1244 | goto out_free; | |
1245 | ||
01727e61 RV |
1246 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1247 | ||
1248 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
513c27f8 | 1249 | |
3e3c62ca | 1250 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1251 | |
a60b57ed LJ |
1252 | nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP, |
1253 | NOMADIK_GPIO_TO_IRQ(pdata->first_gpio), | |
1254 | 0, &nmk_gpio_irq_simple_ops, nmk_chip); | |
1255 | if (!nmk_chip->domain) { | |
1256 | pr_err("%s: Failed to create irqdomain\n", np->full_name); | |
1257 | ret = -ENOSYS; | |
1258 | goto out_free; | |
1259 | } | |
1260 | ||
2ec1d359 AR |
1261 | nmk_gpio_init_irq(nmk_chip); |
1262 | ||
513c27f8 LJ |
1263 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1264 | ||
2ec1d359 AR |
1265 | return 0; |
1266 | ||
3e3c62ca | 1267 | out_free: |
2ec1d359 | 1268 | kfree(nmk_chip); |
af7dc228 RV |
1269 | out_clk: |
1270 | clk_disable(clk); | |
1271 | clk_put(clk); | |
8d91771c LW |
1272 | out_unmap: |
1273 | iounmap(base); | |
3e3c62ca RV |
1274 | out_release: |
1275 | release_mem_region(res->start, resource_size(res)); | |
1276 | out: | |
2ec1d359 AR |
1277 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1278 | pdata->first_gpio, pdata->first_gpio+31); | |
513c27f8 LJ |
1279 | if (np) |
1280 | kfree(pdata); | |
1281 | ||
2ec1d359 AR |
1282 | return ret; |
1283 | } | |
1284 | ||
513c27f8 LJ |
1285 | static const struct of_device_id nmk_gpio_match[] = { |
1286 | { .compatible = "st,nomadik-gpio", }, | |
1287 | {} | |
1288 | }; | |
1289 | ||
3e3c62ca RV |
1290 | static struct platform_driver nmk_gpio_driver = { |
1291 | .driver = { | |
2ec1d359 AR |
1292 | .owner = THIS_MODULE, |
1293 | .name = "gpio", | |
513c27f8 | 1294 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 1295 | }, |
2ec1d359 | 1296 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1297 | }; |
1298 | ||
1299 | static int __init nmk_gpio_init(void) | |
1300 | { | |
3e3c62ca | 1301 | return platform_driver_register(&nmk_gpio_driver); |
2ec1d359 AR |
1302 | } |
1303 | ||
33f45ea9 | 1304 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1305 | |
1306 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1307 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1308 | MODULE_LICENSE("GPL"); |