Commit | Line | Data |
---|---|---|
e58b9e27 | 1 | /* |
4e47f91b LP |
2 | * MCP23S08 SPI/I2C GPIO gpio expander driver |
3 | * | |
4 | * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are | |
5 | * supported. | |
6 | * For the I2C versions of the chips (mcp23008 and mcp23017) generation of | |
7 | * interrupts is also supported. | |
8 | * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is | |
9 | * also capable of generating interrupts, but the linux driver does not | |
10 | * support that yet. | |
e58b9e27 DB |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/device.h> | |
e58b9e27 | 15 | #include <linux/mutex.h> |
bb207ef1 | 16 | #include <linux/module.h> |
d120c17f | 17 | #include <linux/gpio.h> |
752ad5e8 | 18 | #include <linux/i2c.h> |
e58b9e27 DB |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/mcp23s08.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
0b7bb77f | 22 | #include <asm/byteorder.h> |
4e47f91b | 23 | #include <linux/interrupt.h> |
97ddb1c8 | 24 | #include <linux/of_device.h> |
3d84fdb3 | 25 | #include <linux/regmap.h> |
82039d24 SR |
26 | #include <linux/pinctrl/pinctrl.h> |
27 | #include <linux/pinctrl/pinconf.h> | |
28 | #include <linux/pinctrl/pinconf-generic.h> | |
e58b9e27 | 29 | |
0b7bb77f PK |
30 | /** |
31 | * MCP types supported by driver | |
32 | */ | |
33 | #define MCP_TYPE_S08 0 | |
34 | #define MCP_TYPE_S17 1 | |
752ad5e8 PK |
35 | #define MCP_TYPE_008 2 |
36 | #define MCP_TYPE_017 3 | |
28c5a41e | 37 | #define MCP_TYPE_S18 4 |
e58b9e27 | 38 | |
ce9bd0a0 SR |
39 | #define MCP_MAX_DEV_PER_CS 8 |
40 | ||
e58b9e27 DB |
41 | /* Registers are all 8 bits wide. |
42 | * | |
43 | * The mcp23s17 has twice as many bits, and can be configured to work | |
44 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
45 | */ |
46 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
47 | #define MCP_IPOL 0x01 | |
48 | #define MCP_GPINTEN 0x02 | |
49 | #define MCP_DEFVAL 0x03 | |
50 | #define MCP_INTCON 0x04 | |
51 | #define MCP_IOCON 0x05 | |
4e47f91b | 52 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
53 | # define IOCON_SEQOP (1 << 5) |
54 | # define IOCON_HAEN (1 << 3) | |
55 | # define IOCON_ODR (1 << 2) | |
56 | # define IOCON_INTPOL (1 << 1) | |
3539699c | 57 | # define IOCON_INTCC (1) |
e58b9e27 DB |
58 | #define MCP_GPPU 0x06 |
59 | #define MCP_INTF 0x07 | |
60 | #define MCP_INTCAP 0x08 | |
61 | #define MCP_GPIO 0x09 | |
62 | #define MCP_OLAT 0x0a | |
63 | ||
0b7bb77f PK |
64 | struct mcp23s08; |
65 | ||
e58b9e27 | 66 | struct mcp23s08 { |
e58b9e27 | 67 | u8 addr; |
a4e63554 | 68 | bool irq_active_high; |
3d84fdb3 | 69 | bool reg_shift; |
e58b9e27 | 70 | |
4e47f91b LP |
71 | u16 irq_rise; |
72 | u16 irq_fall; | |
73 | int irq; | |
74 | bool irq_controller; | |
8f38910b SR |
75 | int cached_gpio; |
76 | /* lock protects regmap access with bypass/cache flags */ | |
e58b9e27 | 77 | struct mutex lock; |
e58b9e27 DB |
78 | |
79 | struct gpio_chip chip; | |
80 | ||
3d84fdb3 SR |
81 | struct regmap *regmap; |
82 | struct device *dev; | |
82039d24 SR |
83 | |
84 | struct pinctrl_dev *pctldev; | |
85 | struct pinctrl_desc pinctrl_desc; | |
8f1cc3b1 DB |
86 | }; |
87 | ||
8f38910b SR |
88 | static const struct reg_default mcp23x08_defaults[] = { |
89 | {.reg = MCP_IODIR, .def = 0xff}, | |
90 | {.reg = MCP_IPOL, .def = 0x00}, | |
91 | {.reg = MCP_GPINTEN, .def = 0x00}, | |
92 | {.reg = MCP_DEFVAL, .def = 0x00}, | |
93 | {.reg = MCP_INTCON, .def = 0x00}, | |
94 | {.reg = MCP_IOCON, .def = 0x00}, | |
95 | {.reg = MCP_GPPU, .def = 0x00}, | |
96 | {.reg = MCP_OLAT, .def = 0x00}, | |
97 | }; | |
98 | ||
99 | static const struct regmap_range mcp23x08_volatile_range = { | |
100 | .range_min = MCP_INTF, | |
101 | .range_max = MCP_GPIO, | |
102 | }; | |
103 | ||
104 | static const struct regmap_access_table mcp23x08_volatile_table = { | |
105 | .yes_ranges = &mcp23x08_volatile_range, | |
106 | .n_yes_ranges = 1, | |
107 | }; | |
108 | ||
109 | static const struct regmap_range mcp23x08_precious_range = { | |
110 | .range_min = MCP_GPIO, | |
111 | .range_max = MCP_GPIO, | |
112 | }; | |
113 | ||
114 | static const struct regmap_access_table mcp23x08_precious_table = { | |
115 | .yes_ranges = &mcp23x08_precious_range, | |
116 | .n_yes_ranges = 1, | |
117 | }; | |
118 | ||
3d84fdb3 SR |
119 | static const struct regmap_config mcp23x08_regmap = { |
120 | .reg_bits = 8, | |
121 | .val_bits = 8, | |
752ad5e8 | 122 | |
3d84fdb3 | 123 | .reg_stride = 1, |
8f38910b SR |
124 | .volatile_table = &mcp23x08_volatile_table, |
125 | .precious_table = &mcp23x08_precious_table, | |
126 | .reg_defaults = mcp23x08_defaults, | |
127 | .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), | |
128 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 | 129 | .max_register = MCP_OLAT, |
752ad5e8 PK |
130 | }; |
131 | ||
8f38910b SR |
132 | static const struct reg_default mcp23x16_defaults[] = { |
133 | {.reg = MCP_IODIR << 1, .def = 0xffff}, | |
134 | {.reg = MCP_IPOL << 1, .def = 0x0000}, | |
135 | {.reg = MCP_GPINTEN << 1, .def = 0x0000}, | |
136 | {.reg = MCP_DEFVAL << 1, .def = 0x0000}, | |
137 | {.reg = MCP_INTCON << 1, .def = 0x0000}, | |
138 | {.reg = MCP_IOCON << 1, .def = 0x0000}, | |
139 | {.reg = MCP_GPPU << 1, .def = 0x0000}, | |
140 | {.reg = MCP_OLAT << 1, .def = 0x0000}, | |
141 | }; | |
142 | ||
143 | static const struct regmap_range mcp23x16_volatile_range = { | |
144 | .range_min = MCP_INTF << 1, | |
145 | .range_max = MCP_GPIO << 1, | |
146 | }; | |
147 | ||
148 | static const struct regmap_access_table mcp23x16_volatile_table = { | |
149 | .yes_ranges = &mcp23x16_volatile_range, | |
150 | .n_yes_ranges = 1, | |
151 | }; | |
152 | ||
153 | static const struct regmap_range mcp23x16_precious_range = { | |
154 | .range_min = MCP_GPIO << 1, | |
155 | .range_max = MCP_GPIO << 1, | |
156 | }; | |
157 | ||
158 | static const struct regmap_access_table mcp23x16_precious_table = { | |
159 | .yes_ranges = &mcp23x16_precious_range, | |
160 | .n_yes_ranges = 1, | |
161 | }; | |
162 | ||
3d84fdb3 SR |
163 | static const struct regmap_config mcp23x17_regmap = { |
164 | .reg_bits = 8, | |
165 | .val_bits = 16, | |
752ad5e8 | 166 | |
3d84fdb3 SR |
167 | .reg_stride = 2, |
168 | .max_register = MCP_OLAT << 1, | |
8f38910b SR |
169 | .volatile_table = &mcp23x16_volatile_table, |
170 | .precious_table = &mcp23x16_precious_table, | |
171 | .reg_defaults = mcp23x16_defaults, | |
172 | .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), | |
173 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 SR |
174 | .val_format_endian = REGMAP_ENDIAN_LITTLE, |
175 | }; | |
752ad5e8 | 176 | |
82039d24 SR |
177 | static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) |
178 | { | |
179 | return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); | |
180 | } | |
181 | ||
182 | static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) | |
183 | { | |
184 | return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); | |
185 | } | |
186 | ||
8f38910b SR |
187 | static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, |
188 | unsigned int mask, bool enabled) | |
82039d24 SR |
189 | { |
190 | u16 val = enabled ? 0xffff : 0x0000; | |
82039d24 SR |
191 | return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, |
192 | mask, val); | |
193 | } | |
194 | ||
8f38910b SR |
195 | static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, |
196 | unsigned int pin, bool enabled) | |
82039d24 | 197 | { |
8f38910b SR |
198 | u16 mask = BIT(pin); |
199 | return mcp_set_mask(mcp, reg, mask, enabled); | |
82039d24 SR |
200 | } |
201 | ||
202 | static const struct pinctrl_pin_desc mcp23x08_pins[] = { | |
203 | PINCTRL_PIN(0, "gpio0"), | |
204 | PINCTRL_PIN(1, "gpio1"), | |
205 | PINCTRL_PIN(2, "gpio2"), | |
206 | PINCTRL_PIN(3, "gpio3"), | |
207 | PINCTRL_PIN(4, "gpio4"), | |
208 | PINCTRL_PIN(5, "gpio5"), | |
209 | PINCTRL_PIN(6, "gpio6"), | |
210 | PINCTRL_PIN(7, "gpio7"), | |
211 | }; | |
212 | ||
213 | static const struct pinctrl_pin_desc mcp23x17_pins[] = { | |
214 | PINCTRL_PIN(0, "gpio0"), | |
215 | PINCTRL_PIN(1, "gpio1"), | |
216 | PINCTRL_PIN(2, "gpio2"), | |
217 | PINCTRL_PIN(3, "gpio3"), | |
218 | PINCTRL_PIN(4, "gpio4"), | |
219 | PINCTRL_PIN(5, "gpio5"), | |
220 | PINCTRL_PIN(6, "gpio6"), | |
221 | PINCTRL_PIN(7, "gpio7"), | |
222 | PINCTRL_PIN(8, "gpio8"), | |
223 | PINCTRL_PIN(9, "gpio9"), | |
224 | PINCTRL_PIN(10, "gpio10"), | |
225 | PINCTRL_PIN(11, "gpio11"), | |
226 | PINCTRL_PIN(12, "gpio12"), | |
227 | PINCTRL_PIN(13, "gpio13"), | |
228 | PINCTRL_PIN(14, "gpio14"), | |
229 | PINCTRL_PIN(15, "gpio15"), | |
230 | }; | |
231 | ||
232 | static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
233 | { | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
238 | unsigned int group) | |
239 | { | |
240 | return NULL; | |
241 | } | |
242 | ||
243 | static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
244 | unsigned int group, | |
245 | const unsigned int **pins, | |
246 | unsigned int *num_pins) | |
247 | { | |
248 | return -ENOTSUPP; | |
249 | } | |
250 | ||
251 | static const struct pinctrl_ops mcp_pinctrl_ops = { | |
252 | .get_groups_count = mcp_pinctrl_get_groups_count, | |
253 | .get_group_name = mcp_pinctrl_get_group_name, | |
254 | .get_group_pins = mcp_pinctrl_get_group_pins, | |
255 | #ifdef CONFIG_OF | |
256 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
257 | .dt_free_map = pinconf_generic_dt_free_map, | |
258 | #endif | |
259 | }; | |
260 | ||
261 | static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
262 | unsigned long *config) | |
263 | { | |
264 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
265 | enum pin_config_param param = pinconf_to_config_param(*config); | |
266 | unsigned int data, status; | |
267 | int ret; | |
268 | ||
269 | switch (param) { | |
270 | case PIN_CONFIG_BIAS_PULL_UP: | |
271 | ret = mcp_read(mcp, MCP_GPPU, &data); | |
272 | if (ret < 0) | |
273 | return ret; | |
274 | status = (data & BIT(pin)) ? 1 : 0; | |
275 | break; | |
276 | default: | |
277 | dev_err(mcp->dev, "Invalid config param %04x\n", param); | |
278 | return -ENOTSUPP; | |
279 | } | |
280 | ||
281 | *config = 0; | |
282 | ||
283 | return status ? 0 : -EINVAL; | |
284 | } | |
285 | ||
286 | static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
287 | unsigned long *configs, unsigned int num_configs) | |
288 | { | |
289 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
290 | enum pin_config_param param; | |
291 | u32 arg, mask; | |
292 | u16 val; | |
293 | int ret = 0; | |
294 | int i; | |
295 | ||
296 | for (i = 0; i < num_configs; i++) { | |
297 | param = pinconf_to_config_param(configs[i]); | |
298 | arg = pinconf_to_config_argument(configs[i]); | |
299 | ||
300 | switch (param) { | |
301 | case PIN_CONFIG_BIAS_PULL_UP: | |
302 | val = arg ? 0xFFFF : 0x0000; | |
303 | mask = BIT(pin); | |
304 | ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); | |
305 | break; | |
306 | default: | |
307 | dev_err(mcp->dev, "Invalid config param %04x\n", param); | |
308 | return -ENOTSUPP; | |
309 | } | |
310 | } | |
311 | ||
312 | return ret; | |
313 | } | |
314 | ||
315 | static const struct pinconf_ops mcp_pinconf_ops = { | |
316 | .pin_config_get = mcp_pinconf_get, | |
317 | .pin_config_set = mcp_pinconf_set, | |
318 | .is_generic = true, | |
319 | }; | |
320 | ||
752ad5e8 PK |
321 | /*----------------------------------------------------------------------*/ |
322 | ||
d62b98f3 PK |
323 | #ifdef CONFIG_SPI_MASTER |
324 | ||
3d84fdb3 | 325 | static int mcp23sxx_spi_write(void *context, const void *data, size_t count) |
e58b9e27 | 326 | { |
3d84fdb3 SR |
327 | struct mcp23s08 *mcp = context; |
328 | struct spi_device *spi = to_spi_device(mcp->dev); | |
329 | struct spi_message m; | |
330 | struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
331 | { .tx_buf = data, .len = count, }, }; | |
e58b9e27 | 332 | |
3d84fdb3 SR |
333 | spi_message_init(&m); |
334 | spi_message_add_tail(&t[0], &m); | |
335 | spi_message_add_tail(&t[1], &m); | |
336 | ||
337 | return spi_sync(spi, &m); | |
e58b9e27 DB |
338 | } |
339 | ||
3d84fdb3 SR |
340 | static int mcp23sxx_spi_gather_write(void *context, |
341 | const void *reg, size_t reg_size, | |
342 | const void *val, size_t val_size) | |
e58b9e27 | 343 | { |
3d84fdb3 SR |
344 | struct mcp23s08 *mcp = context; |
345 | struct spi_device *spi = to_spi_device(mcp->dev); | |
346 | struct spi_message m; | |
347 | struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
348 | { .tx_buf = reg, .len = reg_size, }, | |
349 | { .tx_buf = val, .len = val_size, }, }; | |
350 | ||
351 | spi_message_init(&m); | |
352 | spi_message_add_tail(&t[0], &m); | |
353 | spi_message_add_tail(&t[1], &m); | |
354 | spi_message_add_tail(&t[2], &m); | |
355 | ||
356 | return spi_sync(spi, &m); | |
e58b9e27 DB |
357 | } |
358 | ||
3d84fdb3 SR |
359 | static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, |
360 | void *val, size_t val_size) | |
e58b9e27 | 361 | { |
3d84fdb3 SR |
362 | struct mcp23s08 *mcp = context; |
363 | struct spi_device *spi = to_spi_device(mcp->dev); | |
364 | u8 tx[2]; | |
e58b9e27 | 365 | |
3d84fdb3 | 366 | if (reg_size != 1) |
e58b9e27 | 367 | return -EINVAL; |
3d84fdb3 | 368 | |
e58b9e27 | 369 | tx[0] = mcp->addr | 0x01; |
3d84fdb3 | 370 | tx[1] = *((u8 *) reg); |
0b7bb77f | 371 | |
3d84fdb3 | 372 | return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); |
0b7bb77f PK |
373 | } |
374 | ||
3d84fdb3 SR |
375 | static const struct regmap_bus mcp23sxx_spi_regmap = { |
376 | .write = mcp23sxx_spi_write, | |
377 | .gather_write = mcp23sxx_spi_gather_write, | |
378 | .read = mcp23sxx_spi_read, | |
379 | }; | |
0b7bb77f | 380 | |
3d84fdb3 | 381 | #endif /* CONFIG_SPI_MASTER */ |
0b7bb77f | 382 | |
3d84fdb3 | 383 | /*----------------------------------------------------------------------*/ |
0b7bb77f | 384 | |
3d84fdb3 SR |
385 | /* A given spi_device can represent up to eight mcp23sxx chips |
386 | * sharing the same chipselect but using different addresses | |
387 | * (e.g. chips #0 and #3 might be populated, but not #1 or $2). | |
388 | * Driver data holds all the per-chip data. | |
389 | */ | |
390 | struct mcp23s08_driver_data { | |
391 | unsigned ngpio; | |
392 | struct mcp23s08 *mcp[8]; | |
393 | struct mcp23s08 chip[]; | |
0b7bb77f PK |
394 | }; |
395 | ||
e58b9e27 DB |
396 | |
397 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) | |
398 | { | |
9e03cf0b | 399 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
400 | int status; |
401 | ||
402 | mutex_lock(&mcp->lock); | |
8f38910b | 403 | status = mcp_set_bit(mcp, MCP_IODIR, offset, true); |
e58b9e27 | 404 | mutex_unlock(&mcp->lock); |
8f38910b | 405 | |
e58b9e27 DB |
406 | return status; |
407 | } | |
408 | ||
409 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
410 | { | |
9e03cf0b | 411 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
3d84fdb3 | 412 | int status, ret; |
e58b9e27 DB |
413 | |
414 | mutex_lock(&mcp->lock); | |
415 | ||
416 | /* REVISIT reading this clears any IRQ ... */ | |
3d84fdb3 SR |
417 | ret = mcp_read(mcp, MCP_GPIO, &status); |
418 | if (ret < 0) | |
e58b9e27 | 419 | status = 0; |
8f38910b | 420 | else |
e58b9e27 | 421 | status = !!(status & (1 << offset)); |
8f38910b SR |
422 | |
423 | mcp->cached_gpio = status; | |
424 | ||
e58b9e27 DB |
425 | mutex_unlock(&mcp->lock); |
426 | return status; | |
427 | } | |
428 | ||
8f38910b | 429 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) |
e58b9e27 | 430 | { |
8f38910b | 431 | return mcp_set_mask(mcp, MCP_OLAT, mask, value); |
e58b9e27 DB |
432 | } |
433 | ||
434 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
435 | { | |
9e03cf0b | 436 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 437 | unsigned mask = BIT(offset); |
e58b9e27 DB |
438 | |
439 | mutex_lock(&mcp->lock); | |
8f38910b | 440 | __mcp23s08_set(mcp, mask, !!value); |
e58b9e27 DB |
441 | mutex_unlock(&mcp->lock); |
442 | } | |
443 | ||
444 | static int | |
445 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
446 | { | |
9e03cf0b | 447 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 448 | unsigned mask = BIT(offset); |
e58b9e27 DB |
449 | int status; |
450 | ||
451 | mutex_lock(&mcp->lock); | |
452 | status = __mcp23s08_set(mcp, mask, value); | |
453 | if (status == 0) { | |
8f38910b | 454 | status = mcp_set_mask(mcp, MCP_IODIR, mask, false); |
e58b9e27 DB |
455 | } |
456 | mutex_unlock(&mcp->lock); | |
457 | return status; | |
458 | } | |
459 | ||
4e47f91b LP |
460 | /*----------------------------------------------------------------------*/ |
461 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
462 | { | |
463 | struct mcp23s08 *mcp = data; | |
8f38910b | 464 | int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; |
4e47f91b | 465 | unsigned int child_irq; |
2cd29f23 RM |
466 | bool intf_set, intcap_changed, gpio_bit_changed, |
467 | defval_changed, gpio_set; | |
4e47f91b LP |
468 | |
469 | mutex_lock(&mcp->lock); | |
3d84fdb3 | 470 | if (mcp_read(mcp, MCP_INTF, &intf) < 0) { |
4e47f91b LP |
471 | mutex_unlock(&mcp->lock); |
472 | return IRQ_HANDLED; | |
473 | } | |
474 | ||
3d84fdb3 | 475 | if (mcp_read(mcp, MCP_INTCAP, &intcap) < 0) { |
4e47f91b LP |
476 | mutex_unlock(&mcp->lock); |
477 | return IRQ_HANDLED; | |
478 | } | |
479 | ||
8f38910b SR |
480 | if (mcp_read(mcp, MCP_INTCON, &intcon) < 0) { |
481 | mutex_unlock(&mcp->lock); | |
482 | return IRQ_HANDLED; | |
483 | } | |
484 | ||
485 | if (mcp_read(mcp, MCP_DEFVAL, &defval) < 0) { | |
486 | mutex_unlock(&mcp->lock); | |
487 | return IRQ_HANDLED; | |
488 | } | |
2cd29f23 RM |
489 | |
490 | /* This clears the interrupt(configurable on S18) */ | |
491 | if (mcp_read(mcp, MCP_GPIO, &gpio) < 0) { | |
492 | mutex_unlock(&mcp->lock); | |
493 | return IRQ_HANDLED; | |
494 | } | |
8f38910b SR |
495 | gpio_orig = mcp->cached_gpio; |
496 | mcp->cached_gpio = gpio; | |
4e47f91b LP |
497 | mutex_unlock(&mcp->lock); |
498 | ||
8f38910b | 499 | if (intf == 0) { |
2cd29f23 RM |
500 | /* There is no interrupt pending */ |
501 | return IRQ_HANDLED; | |
502 | } | |
503 | ||
504 | dev_dbg(mcp->chip.parent, | |
505 | "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", | |
506 | intcap, intf, gpio_orig, gpio); | |
4e47f91b LP |
507 | |
508 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
2cd29f23 RM |
509 | /* We must check all of the inputs on the chip, |
510 | * otherwise we may not notice a change on >=2 pins. | |
511 | * | |
512 | * On at least the mcp23s17, INTCAP is only updated | |
513 | * one byte at a time(INTCAPA and INTCAPB are | |
514 | * not written to at the same time - only on a per-bank | |
515 | * basis). | |
516 | * | |
517 | * INTF only contains the single bit that caused the | |
518 | * interrupt per-bank. On the mcp23s17, there is | |
519 | * INTFA and INTFB. If two pins are changed on the A | |
520 | * side at the same time, INTF will only have one bit | |
521 | * set. If one pin on the A side and one pin on the B | |
522 | * side are changed at the same time, INTF will have | |
523 | * two bits set. Thus, INTF can't be the only check | |
524 | * to see if the input has changed. | |
525 | */ | |
526 | ||
8f38910b | 527 | intf_set = intf & BIT(i); |
2cd29f23 RM |
528 | if (i < 8 && intf_set) |
529 | intcap_mask = 0x00FF; | |
530 | else if (i >= 8 && intf_set) | |
531 | intcap_mask = 0xFF00; | |
532 | else | |
533 | intcap_mask = 0x00; | |
534 | ||
535 | intcap_changed = (intcap_mask & | |
8f38910b | 536 | (intcap & BIT(i))) != |
2cd29f23 | 537 | (intcap_mask & (BIT(i) & gpio_orig)); |
8f38910b | 538 | gpio_set = BIT(i) & gpio; |
2cd29f23 | 539 | gpio_bit_changed = (BIT(i) & gpio_orig) != |
8f38910b SR |
540 | (BIT(i) & gpio); |
541 | defval_changed = (BIT(i) & intcon) && | |
542 | ((BIT(i) & gpio) != | |
543 | (BIT(i) & defval)); | |
2cd29f23 RM |
544 | |
545 | if (((gpio_bit_changed || intcap_changed) && | |
546 | (BIT(i) & mcp->irq_rise) && gpio_set) || | |
547 | ((gpio_bit_changed || intcap_changed) && | |
548 | (BIT(i) & mcp->irq_fall) && !gpio_set) || | |
549 | defval_changed) { | |
dad3d272 | 550 | child_irq = irq_find_mapping(mcp->chip.irqdomain, i); |
4e47f91b LP |
551 | handle_nested_irq(child_irq); |
552 | } | |
553 | } | |
554 | ||
555 | return IRQ_HANDLED; | |
556 | } | |
557 | ||
4e47f91b LP |
558 | static void mcp23s08_irq_mask(struct irq_data *data) |
559 | { | |
dad3d272 PR |
560 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
561 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
562 | unsigned int pos = data->hwirq; |
563 | ||
8f38910b | 564 | mcp_set_bit(mcp, MCP_GPINTEN, pos, false); |
4e47f91b LP |
565 | } |
566 | ||
567 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
568 | { | |
dad3d272 PR |
569 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
570 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
571 | unsigned int pos = data->hwirq; |
572 | ||
8f38910b | 573 | mcp_set_bit(mcp, MCP_GPINTEN, pos, true); |
4e47f91b LP |
574 | } |
575 | ||
576 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
577 | { | |
dad3d272 PR |
578 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
579 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
580 | unsigned int pos = data->hwirq; |
581 | int status = 0; | |
582 | ||
583 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
8f38910b | 584 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
585 | mcp->irq_rise |= BIT(pos); |
586 | mcp->irq_fall |= BIT(pos); | |
587 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
8f38910b | 588 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
589 | mcp->irq_rise |= BIT(pos); |
590 | mcp->irq_fall &= ~BIT(pos); | |
591 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
8f38910b | 592 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
593 | mcp->irq_rise &= ~BIT(pos); |
594 | mcp->irq_fall |= BIT(pos); | |
16fe1ad2 | 595 | } else if (type & IRQ_TYPE_LEVEL_HIGH) { |
8f38910b SR |
596 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
597 | mcp_set_bit(mcp, MCP_DEFVAL, pos, false); | |
16fe1ad2 | 598 | } else if (type & IRQ_TYPE_LEVEL_LOW) { |
8f38910b SR |
599 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
600 | mcp_set_bit(mcp, MCP_DEFVAL, pos, true); | |
4e47f91b LP |
601 | } else |
602 | return -EINVAL; | |
603 | ||
604 | return status; | |
605 | } | |
606 | ||
607 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
608 | { | |
dad3d272 PR |
609 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
610 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 611 | |
8f38910b SR |
612 | mutex_lock(&mcp->lock); |
613 | regcache_cache_only(mcp->regmap, true); | |
4e47f91b LP |
614 | } |
615 | ||
616 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
617 | { | |
dad3d272 PR |
618 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
619 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 620 | |
8f38910b SR |
621 | regcache_cache_only(mcp->regmap, false); |
622 | regcache_sync(mcp->regmap); | |
623 | ||
4e47f91b | 624 | mutex_unlock(&mcp->lock); |
4e47f91b LP |
625 | } |
626 | ||
4e47f91b LP |
627 | static struct irq_chip mcp23s08_irq_chip = { |
628 | .name = "gpio-mcp23xxx", | |
629 | .irq_mask = mcp23s08_irq_mask, | |
630 | .irq_unmask = mcp23s08_irq_unmask, | |
631 | .irq_set_type = mcp23s08_irq_set_type, | |
632 | .irq_bus_lock = mcp23s08_irq_bus_lock, | |
633 | .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock, | |
4e47f91b LP |
634 | }; |
635 | ||
636 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) | |
637 | { | |
638 | struct gpio_chip *chip = &mcp->chip; | |
dad3d272 | 639 | int err; |
a4e63554 | 640 | unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; |
4e47f91b | 641 | |
a4e63554 AS |
642 | if (mcp->irq_active_high) |
643 | irqflags |= IRQF_TRIGGER_HIGH; | |
644 | else | |
645 | irqflags |= IRQF_TRIGGER_LOW; | |
646 | ||
58383c78 LW |
647 | err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, |
648 | mcp23s08_irq, | |
649 | irqflags, dev_name(chip->parent), mcp); | |
4e47f91b | 650 | if (err != 0) { |
58383c78 | 651 | dev_err(chip->parent, "unable to request IRQ#%d: %d\n", |
4e47f91b LP |
652 | mcp->irq, err); |
653 | return err; | |
654 | } | |
655 | ||
d245b3f9 LW |
656 | err = gpiochip_irqchip_add_nested(chip, |
657 | &mcp23s08_irq_chip, | |
658 | 0, | |
659 | handle_simple_irq, | |
660 | IRQ_TYPE_NONE); | |
dad3d272 PR |
661 | if (err) { |
662 | dev_err(chip->parent, | |
663 | "could not connect irqchip to gpiochip: %d\n", err); | |
664 | return err; | |
4e47f91b | 665 | } |
4e47f91b | 666 | |
d245b3f9 LW |
667 | gpiochip_set_nested_irqchip(chip, |
668 | &mcp23s08_irq_chip, | |
669 | mcp->irq); | |
4e47f91b | 670 | |
dad3d272 | 671 | return 0; |
4e47f91b LP |
672 | } |
673 | ||
e58b9e27 DB |
674 | /*----------------------------------------------------------------------*/ |
675 | ||
676 | #ifdef CONFIG_DEBUG_FS | |
677 | ||
678 | #include <linux/seq_file.h> | |
679 | ||
8f38910b SR |
680 | /* |
681 | * This compares the chip's registers with the register | |
682 | * cache and corrects any incorrectly set register. This | |
683 | * can be used to fix state for MCP23xxx, that temporary | |
684 | * lost its power supply. | |
685 | */ | |
686 | #define MCP23S08_CONFIG_REGS 8 | |
687 | static int __check_mcp23s08_reg_cache(struct mcp23s08 *mcp) | |
688 | { | |
689 | int cached[MCP23S08_CONFIG_REGS]; | |
690 | int err = 0, i; | |
691 | ||
692 | /* read cached config registers */ | |
693 | for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { | |
694 | err = mcp_read(mcp, i, &cached[i]); | |
695 | if (err) | |
696 | goto out; | |
697 | } | |
698 | ||
699 | regcache_cache_bypass(mcp->regmap, true); | |
700 | ||
701 | for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { | |
702 | int uncached; | |
703 | err = mcp_read(mcp, i, &uncached); | |
704 | if (err) | |
705 | goto out; | |
706 | ||
707 | if (uncached != cached[i]) { | |
708 | dev_err(mcp->dev, "restoring reg 0x%02x from 0x%04x to 0x%04x (power-loss?)\n", | |
709 | i, uncached, cached[i]); | |
710 | mcp_write(mcp, i, cached[i]); | |
711 | } | |
712 | } | |
713 | ||
714 | out: | |
715 | if (err) | |
716 | dev_err(mcp->dev, "read error: reg=%02x, err=%d", i, err); | |
717 | regcache_cache_bypass(mcp->regmap, false); | |
718 | return err; | |
719 | } | |
720 | ||
e58b9e27 DB |
721 | /* |
722 | * This shows more info than the generic gpio dump code: | |
723 | * pullups, deglitching, open drain drive. | |
724 | */ | |
725 | static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
726 | { | |
727 | struct mcp23s08 *mcp; | |
728 | char bank; | |
1d1c1d9b | 729 | int t; |
e58b9e27 | 730 | unsigned mask; |
8f38910b | 731 | int iodir, gpio, gppu; |
e58b9e27 | 732 | |
9e03cf0b | 733 | mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
734 | |
735 | /* NOTE: we only handle one bank for now ... */ | |
0b7bb77f | 736 | bank = '0' + ((mcp->addr >> 1) & 0x7); |
e58b9e27 DB |
737 | |
738 | mutex_lock(&mcp->lock); | |
8f38910b SR |
739 | |
740 | t = __check_mcp23s08_reg_cache(mcp); | |
741 | if (t) { | |
742 | seq_printf(s, " I/O Error\n"); | |
743 | goto done; | |
744 | } | |
745 | t = mcp_read(mcp, MCP_IODIR, &iodir); | |
746 | if (t) { | |
747 | seq_printf(s, " I/O Error\n"); | |
748 | goto done; | |
749 | } | |
750 | t = mcp_read(mcp, MCP_GPIO, &gpio); | |
751 | if (t) { | |
752 | seq_printf(s, " I/O Error\n"); | |
753 | goto done; | |
754 | } | |
755 | t = mcp_read(mcp, MCP_GPPU, &gppu); | |
756 | if (t) { | |
757 | seq_printf(s, " I/O Error\n"); | |
e58b9e27 DB |
758 | goto done; |
759 | } | |
760 | ||
8f38910b SR |
761 | for (t = 0, mask = BIT(0); t < chip->ngpio; t++, mask <<= 1) { |
762 | const char *label; | |
e58b9e27 DB |
763 | |
764 | label = gpiochip_is_requested(chip, t); | |
765 | if (!label) | |
766 | continue; | |
767 | ||
768 | seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", | |
769 | chip->base + t, bank, t, label, | |
8f38910b SR |
770 | (iodir & mask) ? "in " : "out", |
771 | (gpio & mask) ? "hi" : "lo", | |
772 | (gppu & mask) ? "up" : " "); | |
e58b9e27 | 773 | /* NOTE: ignoring the irq-related registers */ |
33bc8411 | 774 | seq_puts(s, "\n"); |
e58b9e27 DB |
775 | } |
776 | done: | |
777 | mutex_unlock(&mcp->lock); | |
778 | } | |
779 | ||
780 | #else | |
781 | #define mcp23s08_dbg_show NULL | |
782 | #endif | |
783 | ||
784 | /*----------------------------------------------------------------------*/ | |
785 | ||
d62b98f3 | 786 | static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
4e47f91b | 787 | void *data, unsigned addr, unsigned type, |
5b1a7e80 | 788 | unsigned int base, int cs) |
e58b9e27 | 789 | { |
3d84fdb3 | 790 | int status, ret; |
4e47f91b | 791 | bool mirror = false; |
e58b9e27 | 792 | |
e58b9e27 DB |
793 | mutex_init(&mcp->lock); |
794 | ||
3d84fdb3 | 795 | mcp->dev = dev; |
d62b98f3 | 796 | mcp->addr = addr; |
a4e63554 | 797 | mcp->irq_active_high = false; |
e58b9e27 | 798 | |
e58b9e27 DB |
799 | mcp->chip.direction_input = mcp23s08_direction_input; |
800 | mcp->chip.get = mcp23s08_get; | |
801 | mcp->chip.direction_output = mcp23s08_direction_output; | |
802 | mcp->chip.set = mcp23s08_set; | |
803 | mcp->chip.dbg_show = mcp23s08_dbg_show; | |
60f749f8 | 804 | #ifdef CONFIG_OF_GPIO |
97ddb1c8 LP |
805 | mcp->chip.of_gpio_n_cells = 2; |
806 | mcp->chip.of_node = dev->of_node; | |
807 | #endif | |
e58b9e27 | 808 | |
d62b98f3 PK |
809 | switch (type) { |
810 | #ifdef CONFIG_SPI_MASTER | |
811 | case MCP_TYPE_S08: | |
3d84fdb3 SR |
812 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
813 | &mcp23x08_regmap); | |
814 | mcp->reg_shift = 0; | |
0b7bb77f PK |
815 | mcp->chip.ngpio = 8; |
816 | mcp->chip.label = "mcp23s08"; | |
d62b98f3 PK |
817 | break; |
818 | ||
819 | case MCP_TYPE_S17: | |
3d84fdb3 SR |
820 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
821 | &mcp23x17_regmap); | |
822 | mcp->reg_shift = 1; | |
d62b98f3 PK |
823 | mcp->chip.ngpio = 16; |
824 | mcp->chip.label = "mcp23s17"; | |
825 | break; | |
28c5a41e PR |
826 | |
827 | case MCP_TYPE_S18: | |
3d84fdb3 SR |
828 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
829 | &mcp23x17_regmap); | |
830 | mcp->reg_shift = 1; | |
28c5a41e PR |
831 | mcp->chip.ngpio = 16; |
832 | mcp->chip.label = "mcp23s18"; | |
833 | break; | |
d62b98f3 PK |
834 | #endif /* CONFIG_SPI_MASTER */ |
835 | ||
cbf24fad | 836 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 837 | case MCP_TYPE_008: |
3d84fdb3 SR |
838 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); |
839 | mcp->reg_shift = 0; | |
752ad5e8 PK |
840 | mcp->chip.ngpio = 8; |
841 | mcp->chip.label = "mcp23008"; | |
842 | break; | |
843 | ||
844 | case MCP_TYPE_017: | |
3d84fdb3 SR |
845 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); |
846 | mcp->reg_shift = 1; | |
752ad5e8 PK |
847 | mcp->chip.ngpio = 16; |
848 | mcp->chip.label = "mcp23017"; | |
849 | break; | |
850 | #endif /* CONFIG_I2C */ | |
851 | ||
d62b98f3 PK |
852 | default: |
853 | dev_err(dev, "invalid device type (%d)\n", type); | |
854 | return -EINVAL; | |
0b7bb77f | 855 | } |
d62b98f3 | 856 | |
3d84fdb3 SR |
857 | if (IS_ERR(mcp->regmap)) |
858 | return PTR_ERR(mcp->regmap); | |
859 | ||
5b1a7e80 | 860 | mcp->chip.base = base; |
9fb1f39e | 861 | mcp->chip.can_sleep = true; |
58383c78 | 862 | mcp->chip.parent = dev; |
d72cbed0 | 863 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 864 | |
8f1cc3b1 DB |
865 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
866 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
867 | */ | |
4e47f91b | 868 | |
3d84fdb3 SR |
869 | ret = mcp_read(mcp, MCP_IOCON, &status); |
870 | if (ret < 0) | |
e58b9e27 | 871 | goto fail; |
4e47f91b | 872 | |
5b1a7e80 SR |
873 | mcp->irq_controller = |
874 | device_property_read_bool(dev, "interrupt-controller"); | |
a4e63554 | 875 | if (mcp->irq && mcp->irq_controller) { |
170680ab | 876 | mcp->irq_active_high = |
5b1a7e80 | 877 | device_property_read_bool(dev, |
170680ab | 878 | "microchip,irq-active-high"); |
4e47f91b | 879 | |
5b1a7e80 | 880 | mirror = device_property_read_bool(dev, "microchip,irq-mirror"); |
a4e63554 AS |
881 | } |
882 | ||
883 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || | |
884 | mcp->irq_active_high) { | |
0b7bb77f PK |
885 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
886 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
887 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
a4e63554 AS |
888 | if (mcp->irq_active_high) |
889 | status |= IOCON_INTPOL | (IOCON_INTPOL << 8); | |
890 | else | |
891 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); | |
892 | ||
4e47f91b LP |
893 | if (mirror) |
894 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
895 | ||
3539699c PR |
896 | if (type == MCP_TYPE_S18) |
897 | status |= IOCON_INTCC | (IOCON_INTCC << 8); | |
898 | ||
3d84fdb3 SR |
899 | ret = mcp_write(mcp, MCP_IOCON, status); |
900 | if (ret < 0) | |
e58b9e27 DB |
901 | goto fail; |
902 | } | |
903 | ||
d0e49dab | 904 | ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); |
3d84fdb3 | 905 | if (ret < 0) |
4e47f91b LP |
906 | goto fail; |
907 | ||
908 | if (mcp->irq && mcp->irq_controller) { | |
3d84fdb3 SR |
909 | ret = mcp23s08_irq_setup(mcp); |
910 | if (ret) | |
4e47f91b | 911 | goto fail; |
4e47f91b | 912 | } |
82039d24 SR |
913 | |
914 | mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; | |
915 | mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; | |
916 | mcp->pinctrl_desc.confops = &mcp_pinconf_ops; | |
917 | mcp->pinctrl_desc.npins = mcp->chip.ngpio; | |
918 | if (mcp->pinctrl_desc.npins == 8) | |
919 | mcp->pinctrl_desc.pins = mcp23x08_pins; | |
920 | else if (mcp->pinctrl_desc.npins == 16) | |
921 | mcp->pinctrl_desc.pins = mcp23x17_pins; | |
922 | mcp->pinctrl_desc.owner = THIS_MODULE; | |
923 | ||
924 | mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); | |
925 | if (IS_ERR(mcp->pctldev)) { | |
926 | ret = PTR_ERR(mcp->pctldev); | |
927 | goto fail; | |
928 | } | |
929 | ||
8f1cc3b1 | 930 | fail: |
3d84fdb3 SR |
931 | if (ret < 0) |
932 | dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); | |
933 | return ret; | |
8f1cc3b1 DB |
934 | } |
935 | ||
752ad5e8 PK |
936 | /*----------------------------------------------------------------------*/ |
937 | ||
97ddb1c8 LP |
938 | #ifdef CONFIG_OF |
939 | #ifdef CONFIG_SPI_MASTER | |
ac791804 | 940 | static const struct of_device_id mcp23s08_spi_of_match[] = { |
97ddb1c8 | 941 | { |
45971686 LP |
942 | .compatible = "microchip,mcp23s08", |
943 | .data = (void *) MCP_TYPE_S08, | |
97ddb1c8 LP |
944 | }, |
945 | { | |
45971686 LP |
946 | .compatible = "microchip,mcp23s17", |
947 | .data = (void *) MCP_TYPE_S17, | |
948 | }, | |
28c5a41e PR |
949 | { |
950 | .compatible = "microchip,mcp23s18", | |
951 | .data = (void *) MCP_TYPE_S18, | |
952 | }, | |
45971686 LP |
953 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ |
954 | { | |
955 | .compatible = "mcp,mcp23s08", | |
956 | .data = (void *) MCP_TYPE_S08, | |
957 | }, | |
958 | { | |
959 | .compatible = "mcp,mcp23s17", | |
960 | .data = (void *) MCP_TYPE_S17, | |
97ddb1c8 LP |
961 | }, |
962 | { }, | |
963 | }; | |
964 | MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); | |
965 | #endif | |
966 | ||
967 | #if IS_ENABLED(CONFIG_I2C) | |
ac791804 | 968 | static const struct of_device_id mcp23s08_i2c_of_match[] = { |
97ddb1c8 | 969 | { |
45971686 LP |
970 | .compatible = "microchip,mcp23008", |
971 | .data = (void *) MCP_TYPE_008, | |
97ddb1c8 LP |
972 | }, |
973 | { | |
45971686 LP |
974 | .compatible = "microchip,mcp23017", |
975 | .data = (void *) MCP_TYPE_017, | |
976 | }, | |
977 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
978 | { | |
979 | .compatible = "mcp,mcp23008", | |
980 | .data = (void *) MCP_TYPE_008, | |
981 | }, | |
982 | { | |
983 | .compatible = "mcp,mcp23017", | |
984 | .data = (void *) MCP_TYPE_017, | |
97ddb1c8 LP |
985 | }, |
986 | { }, | |
987 | }; | |
988 | MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); | |
989 | #endif | |
990 | #endif /* CONFIG_OF */ | |
991 | ||
992 | ||
cbf24fad | 993 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 994 | |
3836309d | 995 | static int mcp230xx_probe(struct i2c_client *client, |
752ad5e8 PK |
996 | const struct i2c_device_id *id) |
997 | { | |
3af0dbd5 | 998 | struct mcp23s08_platform_data *pdata, local_pdata; |
752ad5e8 | 999 | struct mcp23s08 *mcp; |
3af0dbd5 | 1000 | int status; |
97ddb1c8 | 1001 | |
5f853acf SR |
1002 | pdata = dev_get_platdata(&client->dev); |
1003 | if (!pdata) { | |
3af0dbd5 SZ |
1004 | pdata = &local_pdata; |
1005 | pdata->base = -1; | |
752ad5e8 PK |
1006 | } |
1007 | ||
2f98e78b | 1008 | mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); |
752ad5e8 PK |
1009 | if (!mcp) |
1010 | return -ENOMEM; | |
1011 | ||
4e47f91b | 1012 | mcp->irq = client->irq; |
752ad5e8 | 1013 | status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, |
5b1a7e80 | 1014 | id->driver_data, pdata->base, 0); |
752ad5e8 | 1015 | if (status) |
2f98e78b | 1016 | return status; |
752ad5e8 PK |
1017 | |
1018 | i2c_set_clientdata(client, mcp); | |
1019 | ||
1020 | return 0; | |
752ad5e8 PK |
1021 | } |
1022 | ||
752ad5e8 PK |
1023 | static const struct i2c_device_id mcp230xx_id[] = { |
1024 | { "mcp23008", MCP_TYPE_008 }, | |
1025 | { "mcp23017", MCP_TYPE_017 }, | |
1026 | { }, | |
1027 | }; | |
1028 | MODULE_DEVICE_TABLE(i2c, mcp230xx_id); | |
1029 | ||
1030 | static struct i2c_driver mcp230xx_driver = { | |
1031 | .driver = { | |
1032 | .name = "mcp230xx", | |
97ddb1c8 | 1033 | .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), |
752ad5e8 PK |
1034 | }, |
1035 | .probe = mcp230xx_probe, | |
752ad5e8 PK |
1036 | .id_table = mcp230xx_id, |
1037 | }; | |
1038 | ||
1039 | static int __init mcp23s08_i2c_init(void) | |
1040 | { | |
1041 | return i2c_add_driver(&mcp230xx_driver); | |
1042 | } | |
1043 | ||
1044 | static void mcp23s08_i2c_exit(void) | |
1045 | { | |
1046 | i2c_del_driver(&mcp230xx_driver); | |
1047 | } | |
1048 | ||
1049 | #else | |
1050 | ||
1051 | static int __init mcp23s08_i2c_init(void) { return 0; } | |
1052 | static void mcp23s08_i2c_exit(void) { } | |
1053 | ||
1054 | #endif /* CONFIG_I2C */ | |
1055 | ||
1056 | /*----------------------------------------------------------------------*/ | |
1057 | ||
d62b98f3 PK |
1058 | #ifdef CONFIG_SPI_MASTER |
1059 | ||
8f1cc3b1 DB |
1060 | static int mcp23s08_probe(struct spi_device *spi) |
1061 | { | |
3af0dbd5 | 1062 | struct mcp23s08_platform_data *pdata, local_pdata; |
8f1cc3b1 | 1063 | unsigned addr; |
596a1c5f | 1064 | int chips = 0; |
8f1cc3b1 | 1065 | struct mcp23s08_driver_data *data; |
0b7bb77f | 1066 | int status, type; |
3af0dbd5 | 1067 | unsigned ngpio = 0; |
97ddb1c8 | 1068 | const struct of_device_id *match; |
97ddb1c8 LP |
1069 | |
1070 | match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); | |
0d7fcd50 | 1071 | if (match) |
de755c33 | 1072 | type = (int)(uintptr_t)match->data; |
0d7fcd50 SR |
1073 | else |
1074 | type = spi_get_device_id(spi)->driver_data; | |
1075 | ||
1076 | pdata = dev_get_platdata(&spi->dev); | |
1077 | if (!pdata) { | |
1078 | pdata = &local_pdata; | |
1079 | pdata->base = -1; | |
1080 | ||
0d7fcd50 | 1081 | status = device_property_read_u32(&spi->dev, |
ce9bd0a0 | 1082 | "microchip,spi-present-mask", &pdata->spi_present_mask); |
97ddb1c8 | 1083 | if (status) { |
0d7fcd50 | 1084 | status = device_property_read_u32(&spi->dev, |
ce9bd0a0 SR |
1085 | "mcp,spi-present-mask", |
1086 | &pdata->spi_present_mask); | |
0d7fcd50 | 1087 | |
45971686 | 1088 | if (status) { |
0d7fcd50 | 1089 | dev_err(&spi->dev, "missing spi-present-mask"); |
45971686 LP |
1090 | return -ENODEV; |
1091 | } | |
97ddb1c8 | 1092 | } |
8f1cc3b1 | 1093 | } |
8f1cc3b1 | 1094 | |
ce9bd0a0 | 1095 | if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { |
0d7fcd50 SR |
1096 | dev_err(&spi->dev, "invalid spi-present-mask"); |
1097 | return -ENODEV; | |
1098 | } | |
1099 | ||
ce9bd0a0 SR |
1100 | for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { |
1101 | if (pdata->spi_present_mask & BIT(addr)) | |
0d7fcd50 SR |
1102 | chips++; |
1103 | } | |
1104 | ||
99e4b98d MW |
1105 | if (!chips) |
1106 | return -ENODEV; | |
1107 | ||
7898b31e VB |
1108 | data = devm_kzalloc(&spi->dev, |
1109 | sizeof(*data) + chips * sizeof(struct mcp23s08), | |
1110 | GFP_KERNEL); | |
8f1cc3b1 DB |
1111 | if (!data) |
1112 | return -ENOMEM; | |
7898b31e | 1113 | |
8f1cc3b1 DB |
1114 | spi_set_drvdata(spi, data); |
1115 | ||
ce9bd0a0 SR |
1116 | for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { |
1117 | if (!(pdata->spi_present_mask & BIT(addr))) | |
8f1cc3b1 DB |
1118 | continue; |
1119 | chips--; | |
1120 | data->mcp[addr] = &data->chip[chips]; | |
a231b88c | 1121 | data->mcp[addr]->irq = spi->irq; |
d62b98f3 | 1122 | status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, |
5b1a7e80 SR |
1123 | 0x40 | (addr << 1), type, |
1124 | pdata->base, addr); | |
8f1cc3b1 | 1125 | if (status < 0) |
d0e49dab | 1126 | return status; |
0b7bb77f | 1127 | |
3af0dbd5 | 1128 | if (pdata->base != -1) |
28c5a41e PR |
1129 | pdata->base += data->mcp[addr]->chip.ngpio; |
1130 | ngpio += data->mcp[addr]->chip.ngpio; | |
8f1cc3b1 | 1131 | } |
97ddb1c8 | 1132 | data->ngpio = ngpio; |
e58b9e27 DB |
1133 | |
1134 | /* NOTE: these chips have a relatively sane IRQ framework, with | |
1135 | * per-signal masking and level/edge triggering. It's not yet | |
1136 | * handled here... | |
1137 | */ | |
1138 | ||
e58b9e27 | 1139 | return 0; |
e58b9e27 DB |
1140 | } |
1141 | ||
0b7bb77f PK |
1142 | static const struct spi_device_id mcp23s08_ids[] = { |
1143 | { "mcp23s08", MCP_TYPE_S08 }, | |
1144 | { "mcp23s17", MCP_TYPE_S17 }, | |
28c5a41e | 1145 | { "mcp23s18", MCP_TYPE_S18 }, |
0b7bb77f PK |
1146 | { }, |
1147 | }; | |
1148 | MODULE_DEVICE_TABLE(spi, mcp23s08_ids); | |
1149 | ||
e58b9e27 DB |
1150 | static struct spi_driver mcp23s08_driver = { |
1151 | .probe = mcp23s08_probe, | |
0b7bb77f | 1152 | .id_table = mcp23s08_ids, |
e58b9e27 DB |
1153 | .driver = { |
1154 | .name = "mcp23s08", | |
97ddb1c8 | 1155 | .of_match_table = of_match_ptr(mcp23s08_spi_of_match), |
e58b9e27 DB |
1156 | }, |
1157 | }; | |
1158 | ||
d62b98f3 PK |
1159 | static int __init mcp23s08_spi_init(void) |
1160 | { | |
1161 | return spi_register_driver(&mcp23s08_driver); | |
1162 | } | |
1163 | ||
1164 | static void mcp23s08_spi_exit(void) | |
1165 | { | |
1166 | spi_unregister_driver(&mcp23s08_driver); | |
1167 | } | |
1168 | ||
1169 | #else | |
1170 | ||
1171 | static int __init mcp23s08_spi_init(void) { return 0; } | |
1172 | static void mcp23s08_spi_exit(void) { } | |
1173 | ||
1174 | #endif /* CONFIG_SPI_MASTER */ | |
1175 | ||
e58b9e27 DB |
1176 | /*----------------------------------------------------------------------*/ |
1177 | ||
1178 | static int __init mcp23s08_init(void) | |
1179 | { | |
752ad5e8 PK |
1180 | int ret; |
1181 | ||
1182 | ret = mcp23s08_spi_init(); | |
1183 | if (ret) | |
1184 | goto spi_fail; | |
1185 | ||
1186 | ret = mcp23s08_i2c_init(); | |
1187 | if (ret) | |
1188 | goto i2c_fail; | |
1189 | ||
1190 | return 0; | |
1191 | ||
1192 | i2c_fail: | |
1193 | mcp23s08_spi_exit(); | |
1194 | spi_fail: | |
1195 | return ret; | |
e58b9e27 | 1196 | } |
752ad5e8 | 1197 | /* register after spi/i2c postcore initcall and before |
673c0c00 DB |
1198 | * subsys initcalls that may rely on these GPIOs |
1199 | */ | |
1200 | subsys_initcall(mcp23s08_init); | |
e58b9e27 DB |
1201 | |
1202 | static void __exit mcp23s08_exit(void) | |
1203 | { | |
d62b98f3 | 1204 | mcp23s08_spi_exit(); |
752ad5e8 | 1205 | mcp23s08_i2c_exit(); |
e58b9e27 DB |
1206 | } |
1207 | module_exit(mcp23s08_exit); | |
1208 | ||
1209 | MODULE_LICENSE("GPL"); |