Commit | Line | Data |
---|---|---|
e58b9e27 | 1 | /* |
4e47f91b LP |
2 | * MCP23S08 SPI/I2C GPIO gpio expander driver |
3 | * | |
4 | * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are | |
5 | * supported. | |
6 | * For the I2C versions of the chips (mcp23008 and mcp23017) generation of | |
7 | * interrupts is also supported. | |
8 | * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is | |
9 | * also capable of generating interrupts, but the linux driver does not | |
10 | * support that yet. | |
e58b9e27 DB |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/device.h> | |
e58b9e27 | 15 | #include <linux/mutex.h> |
bb207ef1 | 16 | #include <linux/module.h> |
d120c17f | 17 | #include <linux/gpio.h> |
752ad5e8 | 18 | #include <linux/i2c.h> |
e58b9e27 DB |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/mcp23s08.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
0b7bb77f | 22 | #include <asm/byteorder.h> |
4e47f91b LP |
23 | #include <linux/interrupt.h> |
24 | #include <linux/of_irq.h> | |
97ddb1c8 | 25 | #include <linux/of_device.h> |
3d84fdb3 | 26 | #include <linux/regmap.h> |
e58b9e27 | 27 | |
0b7bb77f PK |
28 | /** |
29 | * MCP types supported by driver | |
30 | */ | |
31 | #define MCP_TYPE_S08 0 | |
32 | #define MCP_TYPE_S17 1 | |
752ad5e8 PK |
33 | #define MCP_TYPE_008 2 |
34 | #define MCP_TYPE_017 3 | |
28c5a41e | 35 | #define MCP_TYPE_S18 4 |
e58b9e27 DB |
36 | |
37 | /* Registers are all 8 bits wide. | |
38 | * | |
39 | * The mcp23s17 has twice as many bits, and can be configured to work | |
40 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
41 | */ |
42 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
43 | #define MCP_IPOL 0x01 | |
44 | #define MCP_GPINTEN 0x02 | |
45 | #define MCP_DEFVAL 0x03 | |
46 | #define MCP_INTCON 0x04 | |
47 | #define MCP_IOCON 0x05 | |
4e47f91b | 48 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
49 | # define IOCON_SEQOP (1 << 5) |
50 | # define IOCON_HAEN (1 << 3) | |
51 | # define IOCON_ODR (1 << 2) | |
52 | # define IOCON_INTPOL (1 << 1) | |
3539699c | 53 | # define IOCON_INTCC (1) |
e58b9e27 DB |
54 | #define MCP_GPPU 0x06 |
55 | #define MCP_INTF 0x07 | |
56 | #define MCP_INTCAP 0x08 | |
57 | #define MCP_GPIO 0x09 | |
58 | #define MCP_OLAT 0x0a | |
59 | ||
0b7bb77f PK |
60 | struct mcp23s08; |
61 | ||
e58b9e27 | 62 | struct mcp23s08 { |
e58b9e27 | 63 | u8 addr; |
a4e63554 | 64 | bool irq_active_high; |
3d84fdb3 | 65 | bool reg_shift; |
e58b9e27 | 66 | |
0b7bb77f | 67 | u16 cache[11]; |
4e47f91b LP |
68 | u16 irq_rise; |
69 | u16 irq_fall; | |
70 | int irq; | |
71 | bool irq_controller; | |
e58b9e27 DB |
72 | /* lock protects the cached values */ |
73 | struct mutex lock; | |
4e47f91b | 74 | struct mutex irq_lock; |
e58b9e27 DB |
75 | |
76 | struct gpio_chip chip; | |
77 | ||
3d84fdb3 SR |
78 | struct regmap *regmap; |
79 | struct device *dev; | |
8f1cc3b1 DB |
80 | }; |
81 | ||
3d84fdb3 SR |
82 | static const struct regmap_config mcp23x08_regmap = { |
83 | .reg_bits = 8, | |
84 | .val_bits = 8, | |
752ad5e8 | 85 | |
3d84fdb3 SR |
86 | .reg_stride = 1, |
87 | .max_register = MCP_OLAT, | |
752ad5e8 PK |
88 | }; |
89 | ||
3d84fdb3 SR |
90 | static const struct regmap_config mcp23x17_regmap = { |
91 | .reg_bits = 8, | |
92 | .val_bits = 16, | |
752ad5e8 | 93 | |
3d84fdb3 SR |
94 | .reg_stride = 2, |
95 | .max_register = MCP_OLAT << 1, | |
96 | .val_format_endian = REGMAP_ENDIAN_LITTLE, | |
97 | }; | |
752ad5e8 PK |
98 | |
99 | /*----------------------------------------------------------------------*/ | |
100 | ||
d62b98f3 PK |
101 | #ifdef CONFIG_SPI_MASTER |
102 | ||
3d84fdb3 | 103 | static int mcp23sxx_spi_write(void *context, const void *data, size_t count) |
e58b9e27 | 104 | { |
3d84fdb3 SR |
105 | struct mcp23s08 *mcp = context; |
106 | struct spi_device *spi = to_spi_device(mcp->dev); | |
107 | struct spi_message m; | |
108 | struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
109 | { .tx_buf = data, .len = count, }, }; | |
e58b9e27 | 110 | |
3d84fdb3 SR |
111 | spi_message_init(&m); |
112 | spi_message_add_tail(&t[0], &m); | |
113 | spi_message_add_tail(&t[1], &m); | |
114 | ||
115 | return spi_sync(spi, &m); | |
e58b9e27 DB |
116 | } |
117 | ||
3d84fdb3 SR |
118 | static int mcp23sxx_spi_gather_write(void *context, |
119 | const void *reg, size_t reg_size, | |
120 | const void *val, size_t val_size) | |
e58b9e27 | 121 | { |
3d84fdb3 SR |
122 | struct mcp23s08 *mcp = context; |
123 | struct spi_device *spi = to_spi_device(mcp->dev); | |
124 | struct spi_message m; | |
125 | struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
126 | { .tx_buf = reg, .len = reg_size, }, | |
127 | { .tx_buf = val, .len = val_size, }, }; | |
128 | ||
129 | spi_message_init(&m); | |
130 | spi_message_add_tail(&t[0], &m); | |
131 | spi_message_add_tail(&t[1], &m); | |
132 | spi_message_add_tail(&t[2], &m); | |
133 | ||
134 | return spi_sync(spi, &m); | |
e58b9e27 DB |
135 | } |
136 | ||
3d84fdb3 SR |
137 | static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, |
138 | void *val, size_t val_size) | |
e58b9e27 | 139 | { |
3d84fdb3 SR |
140 | struct mcp23s08 *mcp = context; |
141 | struct spi_device *spi = to_spi_device(mcp->dev); | |
142 | u8 tx[2]; | |
e58b9e27 | 143 | |
3d84fdb3 | 144 | if (reg_size != 1) |
e58b9e27 | 145 | return -EINVAL; |
3d84fdb3 | 146 | |
e58b9e27 | 147 | tx[0] = mcp->addr | 0x01; |
3d84fdb3 | 148 | tx[1] = *((u8 *) reg); |
0b7bb77f | 149 | |
3d84fdb3 | 150 | return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); |
0b7bb77f PK |
151 | } |
152 | ||
3d84fdb3 SR |
153 | static const struct regmap_bus mcp23sxx_spi_regmap = { |
154 | .write = mcp23sxx_spi_write, | |
155 | .gather_write = mcp23sxx_spi_gather_write, | |
156 | .read = mcp23sxx_spi_read, | |
157 | }; | |
0b7bb77f | 158 | |
3d84fdb3 | 159 | #endif /* CONFIG_SPI_MASTER */ |
0b7bb77f | 160 | |
3d84fdb3 | 161 | static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) |
0b7bb77f | 162 | { |
3d84fdb3 | 163 | return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); |
0b7bb77f PK |
164 | } |
165 | ||
3d84fdb3 | 166 | static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) |
0b7bb77f | 167 | { |
3d84fdb3 SR |
168 | return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); |
169 | } | |
0b7bb77f | 170 | |
3d84fdb3 SR |
171 | static int mcp_update_cache(struct mcp23s08 *mcp) |
172 | { | |
173 | int ret, reg, i; | |
0b7bb77f | 174 | |
3d84fdb3 SR |
175 | for (i = 0; i < ARRAY_SIZE(mcp->cache); i++) { |
176 | ret = mcp_read(mcp, i, ®); | |
177 | if (ret < 0) | |
178 | return ret; | |
179 | mcp->cache[i] = reg; | |
0b7bb77f PK |
180 | } |
181 | ||
3d84fdb3 | 182 | return 0; |
e58b9e27 DB |
183 | } |
184 | ||
3d84fdb3 | 185 | /*----------------------------------------------------------------------*/ |
0b7bb77f | 186 | |
3d84fdb3 SR |
187 | /* A given spi_device can represent up to eight mcp23sxx chips |
188 | * sharing the same chipselect but using different addresses | |
189 | * (e.g. chips #0 and #3 might be populated, but not #1 or $2). | |
190 | * Driver data holds all the per-chip data. | |
191 | */ | |
192 | struct mcp23s08_driver_data { | |
193 | unsigned ngpio; | |
194 | struct mcp23s08 *mcp[8]; | |
195 | struct mcp23s08 chip[]; | |
0b7bb77f PK |
196 | }; |
197 | ||
e58b9e27 DB |
198 | |
199 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) | |
200 | { | |
9e03cf0b | 201 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
202 | int status; |
203 | ||
204 | mutex_lock(&mcp->lock); | |
205 | mcp->cache[MCP_IODIR] |= (1 << offset); | |
3d84fdb3 | 206 | status = mcp_write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); |
e58b9e27 DB |
207 | mutex_unlock(&mcp->lock); |
208 | return status; | |
209 | } | |
210 | ||
211 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
212 | { | |
9e03cf0b | 213 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
3d84fdb3 | 214 | int status, ret; |
e58b9e27 DB |
215 | |
216 | mutex_lock(&mcp->lock); | |
217 | ||
218 | /* REVISIT reading this clears any IRQ ... */ | |
3d84fdb3 SR |
219 | ret = mcp_read(mcp, MCP_GPIO, &status); |
220 | if (ret < 0) | |
e58b9e27 DB |
221 | status = 0; |
222 | else { | |
223 | mcp->cache[MCP_GPIO] = status; | |
224 | status = !!(status & (1 << offset)); | |
225 | } | |
226 | mutex_unlock(&mcp->lock); | |
227 | return status; | |
228 | } | |
229 | ||
230 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value) | |
231 | { | |
0b7bb77f | 232 | unsigned olat = mcp->cache[MCP_OLAT]; |
e58b9e27 DB |
233 | |
234 | if (value) | |
235 | olat |= mask; | |
236 | else | |
237 | olat &= ~mask; | |
238 | mcp->cache[MCP_OLAT] = olat; | |
3d84fdb3 | 239 | return mcp_write(mcp, MCP_OLAT, olat); |
e58b9e27 DB |
240 | } |
241 | ||
242 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
243 | { | |
9e03cf0b | 244 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
0b7bb77f | 245 | unsigned mask = 1 << offset; |
e58b9e27 DB |
246 | |
247 | mutex_lock(&mcp->lock); | |
248 | __mcp23s08_set(mcp, mask, value); | |
249 | mutex_unlock(&mcp->lock); | |
250 | } | |
251 | ||
252 | static int | |
253 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
254 | { | |
9e03cf0b | 255 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
0b7bb77f | 256 | unsigned mask = 1 << offset; |
e58b9e27 DB |
257 | int status; |
258 | ||
259 | mutex_lock(&mcp->lock); | |
260 | status = __mcp23s08_set(mcp, mask, value); | |
261 | if (status == 0) { | |
262 | mcp->cache[MCP_IODIR] &= ~mask; | |
3d84fdb3 | 263 | status = mcp_write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); |
e58b9e27 DB |
264 | } |
265 | mutex_unlock(&mcp->lock); | |
266 | return status; | |
267 | } | |
268 | ||
4e47f91b LP |
269 | /*----------------------------------------------------------------------*/ |
270 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
271 | { | |
272 | struct mcp23s08 *mcp = data; | |
2cd29f23 | 273 | int intcap, intf, i, gpio, gpio_orig, intcap_mask; |
4e47f91b | 274 | unsigned int child_irq; |
2cd29f23 RM |
275 | bool intf_set, intcap_changed, gpio_bit_changed, |
276 | defval_changed, gpio_set; | |
4e47f91b LP |
277 | |
278 | mutex_lock(&mcp->lock); | |
3d84fdb3 | 279 | if (mcp_read(mcp, MCP_INTF, &intf) < 0) { |
4e47f91b LP |
280 | mutex_unlock(&mcp->lock); |
281 | return IRQ_HANDLED; | |
282 | } | |
283 | ||
284 | mcp->cache[MCP_INTF] = intf; | |
285 | ||
3d84fdb3 | 286 | if (mcp_read(mcp, MCP_INTCAP, &intcap) < 0) { |
4e47f91b LP |
287 | mutex_unlock(&mcp->lock); |
288 | return IRQ_HANDLED; | |
289 | } | |
290 | ||
291 | mcp->cache[MCP_INTCAP] = intcap; | |
2cd29f23 RM |
292 | |
293 | /* This clears the interrupt(configurable on S18) */ | |
294 | if (mcp_read(mcp, MCP_GPIO, &gpio) < 0) { | |
295 | mutex_unlock(&mcp->lock); | |
296 | return IRQ_HANDLED; | |
297 | } | |
298 | gpio_orig = mcp->cache[MCP_GPIO]; | |
299 | mcp->cache[MCP_GPIO] = gpio; | |
4e47f91b LP |
300 | mutex_unlock(&mcp->lock); |
301 | ||
2cd29f23 RM |
302 | if (mcp->cache[MCP_INTF] == 0) { |
303 | /* There is no interrupt pending */ | |
304 | return IRQ_HANDLED; | |
305 | } | |
306 | ||
307 | dev_dbg(mcp->chip.parent, | |
308 | "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", | |
309 | intcap, intf, gpio_orig, gpio); | |
4e47f91b LP |
310 | |
311 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
2cd29f23 RM |
312 | /* We must check all of the inputs on the chip, |
313 | * otherwise we may not notice a change on >=2 pins. | |
314 | * | |
315 | * On at least the mcp23s17, INTCAP is only updated | |
316 | * one byte at a time(INTCAPA and INTCAPB are | |
317 | * not written to at the same time - only on a per-bank | |
318 | * basis). | |
319 | * | |
320 | * INTF only contains the single bit that caused the | |
321 | * interrupt per-bank. On the mcp23s17, there is | |
322 | * INTFA and INTFB. If two pins are changed on the A | |
323 | * side at the same time, INTF will only have one bit | |
324 | * set. If one pin on the A side and one pin on the B | |
325 | * side are changed at the same time, INTF will have | |
326 | * two bits set. Thus, INTF can't be the only check | |
327 | * to see if the input has changed. | |
328 | */ | |
329 | ||
330 | intf_set = BIT(i) & mcp->cache[MCP_INTF]; | |
331 | if (i < 8 && intf_set) | |
332 | intcap_mask = 0x00FF; | |
333 | else if (i >= 8 && intf_set) | |
334 | intcap_mask = 0xFF00; | |
335 | else | |
336 | intcap_mask = 0x00; | |
337 | ||
338 | intcap_changed = (intcap_mask & | |
339 | (BIT(i) & mcp->cache[MCP_INTCAP])) != | |
340 | (intcap_mask & (BIT(i) & gpio_orig)); | |
341 | gpio_set = BIT(i) & mcp->cache[MCP_GPIO]; | |
342 | gpio_bit_changed = (BIT(i) & gpio_orig) != | |
343 | (BIT(i) & mcp->cache[MCP_GPIO]); | |
344 | defval_changed = (BIT(i) & mcp->cache[MCP_INTCON]) && | |
345 | ((BIT(i) & mcp->cache[MCP_GPIO]) != | |
346 | (BIT(i) & mcp->cache[MCP_DEFVAL])); | |
347 | ||
348 | if (((gpio_bit_changed || intcap_changed) && | |
349 | (BIT(i) & mcp->irq_rise) && gpio_set) || | |
350 | ((gpio_bit_changed || intcap_changed) && | |
351 | (BIT(i) & mcp->irq_fall) && !gpio_set) || | |
352 | defval_changed) { | |
dad3d272 | 353 | child_irq = irq_find_mapping(mcp->chip.irqdomain, i); |
4e47f91b LP |
354 | handle_nested_irq(child_irq); |
355 | } | |
356 | } | |
357 | ||
358 | return IRQ_HANDLED; | |
359 | } | |
360 | ||
4e47f91b LP |
361 | static void mcp23s08_irq_mask(struct irq_data *data) |
362 | { | |
dad3d272 PR |
363 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
364 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
365 | unsigned int pos = data->hwirq; |
366 | ||
367 | mcp->cache[MCP_GPINTEN] &= ~BIT(pos); | |
368 | } | |
369 | ||
370 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
371 | { | |
dad3d272 PR |
372 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
373 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
374 | unsigned int pos = data->hwirq; |
375 | ||
376 | mcp->cache[MCP_GPINTEN] |= BIT(pos); | |
377 | } | |
378 | ||
379 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
380 | { | |
dad3d272 PR |
381 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
382 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
383 | unsigned int pos = data->hwirq; |
384 | int status = 0; | |
385 | ||
386 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
387 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
388 | mcp->irq_rise |= BIT(pos); | |
389 | mcp->irq_fall |= BIT(pos); | |
390 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
391 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
392 | mcp->irq_rise |= BIT(pos); | |
393 | mcp->irq_fall &= ~BIT(pos); | |
394 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
395 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
396 | mcp->irq_rise &= ~BIT(pos); | |
397 | mcp->irq_fall |= BIT(pos); | |
16fe1ad2 AS |
398 | } else if (type & IRQ_TYPE_LEVEL_HIGH) { |
399 | mcp->cache[MCP_INTCON] |= BIT(pos); | |
400 | mcp->cache[MCP_DEFVAL] &= ~BIT(pos); | |
401 | } else if (type & IRQ_TYPE_LEVEL_LOW) { | |
402 | mcp->cache[MCP_INTCON] |= BIT(pos); | |
403 | mcp->cache[MCP_DEFVAL] |= BIT(pos); | |
4e47f91b LP |
404 | } else |
405 | return -EINVAL; | |
406 | ||
407 | return status; | |
408 | } | |
409 | ||
410 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
411 | { | |
dad3d272 PR |
412 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
413 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
414 | |
415 | mutex_lock(&mcp->irq_lock); | |
416 | } | |
417 | ||
418 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
419 | { | |
dad3d272 PR |
420 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
421 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
422 | |
423 | mutex_lock(&mcp->lock); | |
3d84fdb3 SR |
424 | mcp_write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]); |
425 | mcp_write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]); | |
426 | mcp_write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]); | |
4e47f91b LP |
427 | mutex_unlock(&mcp->lock); |
428 | mutex_unlock(&mcp->irq_lock); | |
429 | } | |
430 | ||
4e47f91b LP |
431 | static struct irq_chip mcp23s08_irq_chip = { |
432 | .name = "gpio-mcp23xxx", | |
433 | .irq_mask = mcp23s08_irq_mask, | |
434 | .irq_unmask = mcp23s08_irq_unmask, | |
435 | .irq_set_type = mcp23s08_irq_set_type, | |
436 | .irq_bus_lock = mcp23s08_irq_bus_lock, | |
437 | .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock, | |
4e47f91b LP |
438 | }; |
439 | ||
440 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) | |
441 | { | |
442 | struct gpio_chip *chip = &mcp->chip; | |
dad3d272 | 443 | int err; |
a4e63554 | 444 | unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; |
4e47f91b LP |
445 | |
446 | mutex_init(&mcp->irq_lock); | |
447 | ||
a4e63554 AS |
448 | if (mcp->irq_active_high) |
449 | irqflags |= IRQF_TRIGGER_HIGH; | |
450 | else | |
451 | irqflags |= IRQF_TRIGGER_LOW; | |
452 | ||
58383c78 LW |
453 | err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, |
454 | mcp23s08_irq, | |
455 | irqflags, dev_name(chip->parent), mcp); | |
4e47f91b | 456 | if (err != 0) { |
58383c78 | 457 | dev_err(chip->parent, "unable to request IRQ#%d: %d\n", |
4e47f91b LP |
458 | mcp->irq, err); |
459 | return err; | |
460 | } | |
461 | ||
d245b3f9 LW |
462 | err = gpiochip_irqchip_add_nested(chip, |
463 | &mcp23s08_irq_chip, | |
464 | 0, | |
465 | handle_simple_irq, | |
466 | IRQ_TYPE_NONE); | |
dad3d272 PR |
467 | if (err) { |
468 | dev_err(chip->parent, | |
469 | "could not connect irqchip to gpiochip: %d\n", err); | |
470 | return err; | |
4e47f91b | 471 | } |
4e47f91b | 472 | |
d245b3f9 LW |
473 | gpiochip_set_nested_irqchip(chip, |
474 | &mcp23s08_irq_chip, | |
475 | mcp->irq); | |
4e47f91b | 476 | |
dad3d272 | 477 | return 0; |
4e47f91b LP |
478 | } |
479 | ||
e58b9e27 DB |
480 | /*----------------------------------------------------------------------*/ |
481 | ||
482 | #ifdef CONFIG_DEBUG_FS | |
483 | ||
484 | #include <linux/seq_file.h> | |
485 | ||
486 | /* | |
487 | * This shows more info than the generic gpio dump code: | |
488 | * pullups, deglitching, open drain drive. | |
489 | */ | |
490 | static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
491 | { | |
492 | struct mcp23s08 *mcp; | |
493 | char bank; | |
1d1c1d9b | 494 | int t; |
e58b9e27 DB |
495 | unsigned mask; |
496 | ||
9e03cf0b | 497 | mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
498 | |
499 | /* NOTE: we only handle one bank for now ... */ | |
0b7bb77f | 500 | bank = '0' + ((mcp->addr >> 1) & 0x7); |
e58b9e27 DB |
501 | |
502 | mutex_lock(&mcp->lock); | |
3d84fdb3 | 503 | t = mcp_update_cache(mcp); |
e58b9e27 DB |
504 | if (t < 0) { |
505 | seq_printf(s, " I/O ERROR %d\n", t); | |
506 | goto done; | |
507 | } | |
508 | ||
0b7bb77f | 509 | for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) { |
e58b9e27 DB |
510 | const char *label; |
511 | ||
512 | label = gpiochip_is_requested(chip, t); | |
513 | if (!label) | |
514 | continue; | |
515 | ||
516 | seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", | |
517 | chip->base + t, bank, t, label, | |
518 | (mcp->cache[MCP_IODIR] & mask) ? "in " : "out", | |
519 | (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo", | |
eb1567f7 | 520 | (mcp->cache[MCP_GPPU] & mask) ? "up" : " "); |
e58b9e27 | 521 | /* NOTE: ignoring the irq-related registers */ |
33bc8411 | 522 | seq_puts(s, "\n"); |
e58b9e27 DB |
523 | } |
524 | done: | |
525 | mutex_unlock(&mcp->lock); | |
526 | } | |
527 | ||
528 | #else | |
529 | #define mcp23s08_dbg_show NULL | |
530 | #endif | |
531 | ||
532 | /*----------------------------------------------------------------------*/ | |
533 | ||
d62b98f3 | 534 | static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
4e47f91b | 535 | void *data, unsigned addr, unsigned type, |
3af0dbd5 | 536 | struct mcp23s08_platform_data *pdata, int cs) |
e58b9e27 | 537 | { |
3d84fdb3 | 538 | int status, ret; |
4e47f91b | 539 | bool mirror = false; |
e58b9e27 | 540 | |
e58b9e27 DB |
541 | mutex_init(&mcp->lock); |
542 | ||
3d84fdb3 | 543 | mcp->dev = dev; |
d62b98f3 | 544 | mcp->addr = addr; |
a4e63554 | 545 | mcp->irq_active_high = false; |
e58b9e27 | 546 | |
e58b9e27 DB |
547 | mcp->chip.direction_input = mcp23s08_direction_input; |
548 | mcp->chip.get = mcp23s08_get; | |
549 | mcp->chip.direction_output = mcp23s08_direction_output; | |
550 | mcp->chip.set = mcp23s08_set; | |
551 | mcp->chip.dbg_show = mcp23s08_dbg_show; | |
60f749f8 | 552 | #ifdef CONFIG_OF_GPIO |
97ddb1c8 LP |
553 | mcp->chip.of_gpio_n_cells = 2; |
554 | mcp->chip.of_node = dev->of_node; | |
555 | #endif | |
e58b9e27 | 556 | |
d62b98f3 PK |
557 | switch (type) { |
558 | #ifdef CONFIG_SPI_MASTER | |
559 | case MCP_TYPE_S08: | |
3d84fdb3 SR |
560 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
561 | &mcp23x08_regmap); | |
562 | mcp->reg_shift = 0; | |
0b7bb77f PK |
563 | mcp->chip.ngpio = 8; |
564 | mcp->chip.label = "mcp23s08"; | |
d62b98f3 PK |
565 | break; |
566 | ||
567 | case MCP_TYPE_S17: | |
3d84fdb3 SR |
568 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
569 | &mcp23x17_regmap); | |
570 | mcp->reg_shift = 1; | |
d62b98f3 PK |
571 | mcp->chip.ngpio = 16; |
572 | mcp->chip.label = "mcp23s17"; | |
573 | break; | |
28c5a41e PR |
574 | |
575 | case MCP_TYPE_S18: | |
3d84fdb3 SR |
576 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
577 | &mcp23x17_regmap); | |
578 | mcp->reg_shift = 1; | |
28c5a41e PR |
579 | mcp->chip.ngpio = 16; |
580 | mcp->chip.label = "mcp23s18"; | |
581 | break; | |
d62b98f3 PK |
582 | #endif /* CONFIG_SPI_MASTER */ |
583 | ||
cbf24fad | 584 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 585 | case MCP_TYPE_008: |
3d84fdb3 SR |
586 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); |
587 | mcp->reg_shift = 0; | |
752ad5e8 PK |
588 | mcp->chip.ngpio = 8; |
589 | mcp->chip.label = "mcp23008"; | |
590 | break; | |
591 | ||
592 | case MCP_TYPE_017: | |
3d84fdb3 SR |
593 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); |
594 | mcp->reg_shift = 1; | |
752ad5e8 PK |
595 | mcp->chip.ngpio = 16; |
596 | mcp->chip.label = "mcp23017"; | |
597 | break; | |
598 | #endif /* CONFIG_I2C */ | |
599 | ||
d62b98f3 PK |
600 | default: |
601 | dev_err(dev, "invalid device type (%d)\n", type); | |
602 | return -EINVAL; | |
0b7bb77f | 603 | } |
d62b98f3 | 604 | |
3d84fdb3 SR |
605 | if (IS_ERR(mcp->regmap)) |
606 | return PTR_ERR(mcp->regmap); | |
607 | ||
3af0dbd5 | 608 | mcp->chip.base = pdata->base; |
9fb1f39e | 609 | mcp->chip.can_sleep = true; |
58383c78 | 610 | mcp->chip.parent = dev; |
d72cbed0 | 611 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 612 | |
8f1cc3b1 DB |
613 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
614 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
615 | */ | |
4e47f91b | 616 | |
3d84fdb3 SR |
617 | ret = mcp_read(mcp, MCP_IOCON, &status); |
618 | if (ret < 0) | |
e58b9e27 | 619 | goto fail; |
4e47f91b | 620 | |
3af0dbd5 | 621 | mcp->irq_controller = pdata->irq_controller; |
a4e63554 | 622 | if (mcp->irq && mcp->irq_controller) { |
170680ab | 623 | mcp->irq_active_high = |
58383c78 | 624 | of_property_read_bool(mcp->chip.parent->of_node, |
170680ab | 625 | "microchip,irq-active-high"); |
4e47f91b | 626 | |
28c5a41e | 627 | mirror = pdata->mirror; |
a4e63554 AS |
628 | } |
629 | ||
630 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || | |
631 | mcp->irq_active_high) { | |
0b7bb77f PK |
632 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
633 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
634 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
a4e63554 AS |
635 | if (mcp->irq_active_high) |
636 | status |= IOCON_INTPOL | (IOCON_INTPOL << 8); | |
637 | else | |
638 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); | |
639 | ||
4e47f91b LP |
640 | if (mirror) |
641 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
642 | ||
3539699c PR |
643 | if (type == MCP_TYPE_S18) |
644 | status |= IOCON_INTCC | (IOCON_INTCC << 8); | |
645 | ||
3d84fdb3 SR |
646 | ret = mcp_write(mcp, MCP_IOCON, status); |
647 | if (ret < 0) | |
e58b9e27 DB |
648 | goto fail; |
649 | } | |
650 | ||
651 | /* configure ~100K pullups */ | |
3d84fdb3 SR |
652 | ret = mcp_write(mcp, MCP_GPPU, pdata->chip[cs].pullups); |
653 | if (ret < 0) | |
e58b9e27 DB |
654 | goto fail; |
655 | ||
3d84fdb3 SR |
656 | ret = mcp_update_cache(mcp); |
657 | if (ret < 0) | |
e58b9e27 DB |
658 | goto fail; |
659 | ||
660 | /* disable inverter on input */ | |
661 | if (mcp->cache[MCP_IPOL] != 0) { | |
662 | mcp->cache[MCP_IPOL] = 0; | |
3d84fdb3 SR |
663 | ret = mcp_write(mcp, MCP_IPOL, 0); |
664 | if (ret < 0) | |
0b7bb77f | 665 | goto fail; |
e58b9e27 DB |
666 | } |
667 | ||
668 | /* disable irqs */ | |
669 | if (mcp->cache[MCP_GPINTEN] != 0) { | |
670 | mcp->cache[MCP_GPINTEN] = 0; | |
3d84fdb3 SR |
671 | ret = mcp_write(mcp, MCP_GPINTEN, 0); |
672 | if (ret < 0) | |
8f1cc3b1 | 673 | goto fail; |
e58b9e27 DB |
674 | } |
675 | ||
3d84fdb3 SR |
676 | ret = gpiochip_add_data(&mcp->chip, mcp); |
677 | if (ret < 0) | |
4e47f91b LP |
678 | goto fail; |
679 | ||
680 | if (mcp->irq && mcp->irq_controller) { | |
3d84fdb3 SR |
681 | ret = mcp23s08_irq_setup(mcp); |
682 | if (ret) | |
4e47f91b | 683 | goto fail; |
4e47f91b | 684 | } |
8f1cc3b1 | 685 | fail: |
3d84fdb3 SR |
686 | if (ret < 0) |
687 | dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); | |
688 | return ret; | |
8f1cc3b1 DB |
689 | } |
690 | ||
752ad5e8 PK |
691 | /*----------------------------------------------------------------------*/ |
692 | ||
97ddb1c8 LP |
693 | #ifdef CONFIG_OF |
694 | #ifdef CONFIG_SPI_MASTER | |
ac791804 | 695 | static const struct of_device_id mcp23s08_spi_of_match[] = { |
97ddb1c8 | 696 | { |
45971686 LP |
697 | .compatible = "microchip,mcp23s08", |
698 | .data = (void *) MCP_TYPE_S08, | |
97ddb1c8 LP |
699 | }, |
700 | { | |
45971686 LP |
701 | .compatible = "microchip,mcp23s17", |
702 | .data = (void *) MCP_TYPE_S17, | |
703 | }, | |
28c5a41e PR |
704 | { |
705 | .compatible = "microchip,mcp23s18", | |
706 | .data = (void *) MCP_TYPE_S18, | |
707 | }, | |
45971686 LP |
708 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ |
709 | { | |
710 | .compatible = "mcp,mcp23s08", | |
711 | .data = (void *) MCP_TYPE_S08, | |
712 | }, | |
713 | { | |
714 | .compatible = "mcp,mcp23s17", | |
715 | .data = (void *) MCP_TYPE_S17, | |
97ddb1c8 LP |
716 | }, |
717 | { }, | |
718 | }; | |
719 | MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); | |
720 | #endif | |
721 | ||
722 | #if IS_ENABLED(CONFIG_I2C) | |
ac791804 | 723 | static const struct of_device_id mcp23s08_i2c_of_match[] = { |
97ddb1c8 | 724 | { |
45971686 LP |
725 | .compatible = "microchip,mcp23008", |
726 | .data = (void *) MCP_TYPE_008, | |
97ddb1c8 LP |
727 | }, |
728 | { | |
45971686 LP |
729 | .compatible = "microchip,mcp23017", |
730 | .data = (void *) MCP_TYPE_017, | |
731 | }, | |
732 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
733 | { | |
734 | .compatible = "mcp,mcp23008", | |
735 | .data = (void *) MCP_TYPE_008, | |
736 | }, | |
737 | { | |
738 | .compatible = "mcp,mcp23017", | |
739 | .data = (void *) MCP_TYPE_017, | |
97ddb1c8 LP |
740 | }, |
741 | { }, | |
742 | }; | |
743 | MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); | |
744 | #endif | |
745 | #endif /* CONFIG_OF */ | |
746 | ||
747 | ||
cbf24fad | 748 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 749 | |
3836309d | 750 | static int mcp230xx_probe(struct i2c_client *client, |
752ad5e8 PK |
751 | const struct i2c_device_id *id) |
752 | { | |
3af0dbd5 | 753 | struct mcp23s08_platform_data *pdata, local_pdata; |
752ad5e8 | 754 | struct mcp23s08 *mcp; |
3af0dbd5 | 755 | int status; |
97ddb1c8 LP |
756 | const struct of_device_id *match; |
757 | ||
758 | match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match), | |
759 | &client->dev); | |
3af0dbd5 SZ |
760 | if (match) { |
761 | pdata = &local_pdata; | |
762 | pdata->base = -1; | |
763 | pdata->chip[0].pullups = 0; | |
764 | pdata->irq_controller = of_property_read_bool( | |
765 | client->dev.of_node, | |
766 | "interrupt-controller"); | |
767 | pdata->mirror = of_property_read_bool(client->dev.of_node, | |
768 | "microchip,irq-mirror"); | |
4e47f91b | 769 | client->irq = irq_of_parse_and_map(client->dev.of_node, 0); |
97ddb1c8 | 770 | } else { |
3af0dbd5 | 771 | pdata = dev_get_platdata(&client->dev); |
b184c388 SZ |
772 | if (!pdata) { |
773 | pdata = devm_kzalloc(&client->dev, | |
774 | sizeof(struct mcp23s08_platform_data), | |
775 | GFP_KERNEL); | |
aaf2b3af IY |
776 | if (!pdata) |
777 | return -ENOMEM; | |
b184c388 | 778 | pdata->base = -1; |
97ddb1c8 | 779 | } |
752ad5e8 PK |
780 | } |
781 | ||
33bc8411 | 782 | mcp = kzalloc(sizeof(*mcp), GFP_KERNEL); |
752ad5e8 PK |
783 | if (!mcp) |
784 | return -ENOMEM; | |
785 | ||
4e47f91b | 786 | mcp->irq = client->irq; |
752ad5e8 | 787 | status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, |
3af0dbd5 | 788 | id->driver_data, pdata, 0); |
752ad5e8 PK |
789 | if (status) |
790 | goto fail; | |
791 | ||
792 | i2c_set_clientdata(client, mcp); | |
793 | ||
794 | return 0; | |
795 | ||
796 | fail: | |
797 | kfree(mcp); | |
798 | ||
799 | return status; | |
800 | } | |
801 | ||
206210ce | 802 | static int mcp230xx_remove(struct i2c_client *client) |
752ad5e8 PK |
803 | { |
804 | struct mcp23s08 *mcp = i2c_get_clientdata(client); | |
752ad5e8 | 805 | |
9f5132ae | 806 | gpiochip_remove(&mcp->chip); |
807 | kfree(mcp); | |
752ad5e8 | 808 | |
9f5132ae | 809 | return 0; |
752ad5e8 PK |
810 | } |
811 | ||
812 | static const struct i2c_device_id mcp230xx_id[] = { | |
813 | { "mcp23008", MCP_TYPE_008 }, | |
814 | { "mcp23017", MCP_TYPE_017 }, | |
815 | { }, | |
816 | }; | |
817 | MODULE_DEVICE_TABLE(i2c, mcp230xx_id); | |
818 | ||
819 | static struct i2c_driver mcp230xx_driver = { | |
820 | .driver = { | |
821 | .name = "mcp230xx", | |
97ddb1c8 | 822 | .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), |
752ad5e8 PK |
823 | }, |
824 | .probe = mcp230xx_probe, | |
8283c4ff | 825 | .remove = mcp230xx_remove, |
752ad5e8 PK |
826 | .id_table = mcp230xx_id, |
827 | }; | |
828 | ||
829 | static int __init mcp23s08_i2c_init(void) | |
830 | { | |
831 | return i2c_add_driver(&mcp230xx_driver); | |
832 | } | |
833 | ||
834 | static void mcp23s08_i2c_exit(void) | |
835 | { | |
836 | i2c_del_driver(&mcp230xx_driver); | |
837 | } | |
838 | ||
839 | #else | |
840 | ||
841 | static int __init mcp23s08_i2c_init(void) { return 0; } | |
842 | static void mcp23s08_i2c_exit(void) { } | |
843 | ||
844 | #endif /* CONFIG_I2C */ | |
845 | ||
846 | /*----------------------------------------------------------------------*/ | |
847 | ||
d62b98f3 PK |
848 | #ifdef CONFIG_SPI_MASTER |
849 | ||
8f1cc3b1 DB |
850 | static int mcp23s08_probe(struct spi_device *spi) |
851 | { | |
3af0dbd5 | 852 | struct mcp23s08_platform_data *pdata, local_pdata; |
8f1cc3b1 | 853 | unsigned addr; |
596a1c5f | 854 | int chips = 0; |
8f1cc3b1 | 855 | struct mcp23s08_driver_data *data; |
0b7bb77f | 856 | int status, type; |
3af0dbd5 | 857 | unsigned ngpio = 0; |
97ddb1c8 LP |
858 | const struct of_device_id *match; |
859 | u32 spi_present_mask = 0; | |
860 | ||
861 | match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); | |
862 | if (match) { | |
de755c33 | 863 | type = (int)(uintptr_t)match->data; |
97ddb1c8 | 864 | status = of_property_read_u32(spi->dev.of_node, |
45971686 | 865 | "microchip,spi-present-mask", &spi_present_mask); |
97ddb1c8 | 866 | if (status) { |
45971686 LP |
867 | status = of_property_read_u32(spi->dev.of_node, |
868 | "mcp,spi-present-mask", &spi_present_mask); | |
869 | if (status) { | |
870 | dev_err(&spi->dev, | |
871 | "DT has no spi-present-mask\n"); | |
872 | return -ENODEV; | |
873 | } | |
97ddb1c8 LP |
874 | } |
875 | if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) { | |
876 | dev_err(&spi->dev, "invalid spi-present-mask\n"); | |
877 | return -ENODEV; | |
878 | } | |
8f1cc3b1 | 879 | |
3af0dbd5 SZ |
880 | pdata = &local_pdata; |
881 | pdata->base = -1; | |
99e4b98d | 882 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
3af0dbd5 | 883 | pdata->chip[addr].pullups = 0; |
3e3bed91 MS |
884 | if (spi_present_mask & (1 << addr)) |
885 | chips++; | |
99e4b98d | 886 | } |
3af0dbd5 SZ |
887 | pdata->irq_controller = of_property_read_bool( |
888 | spi->dev.of_node, | |
889 | "interrupt-controller"); | |
890 | pdata->mirror = of_property_read_bool(spi->dev.of_node, | |
891 | "microchip,irq-mirror"); | |
97ddb1c8 LP |
892 | } else { |
893 | type = spi_get_device_id(spi)->driver_data; | |
e56aee18 | 894 | pdata = dev_get_platdata(&spi->dev); |
b184c388 SZ |
895 | if (!pdata) { |
896 | pdata = devm_kzalloc(&spi->dev, | |
897 | sizeof(struct mcp23s08_platform_data), | |
898 | GFP_KERNEL); | |
899 | pdata->base = -1; | |
0b7bb77f | 900 | } |
97ddb1c8 LP |
901 | |
902 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { | |
903 | if (!pdata->chip[addr].is_present) | |
904 | continue; | |
905 | chips++; | |
906 | if ((type == MCP_TYPE_S08) && (addr > 3)) { | |
907 | dev_err(&spi->dev, | |
908 | "mcp23s08 only supports address 0..3\n"); | |
909 | return -EINVAL; | |
910 | } | |
911 | spi_present_mask |= 1 << addr; | |
97ddb1c8 | 912 | } |
8f1cc3b1 | 913 | } |
8f1cc3b1 | 914 | |
99e4b98d MW |
915 | if (!chips) |
916 | return -ENODEV; | |
917 | ||
7898b31e VB |
918 | data = devm_kzalloc(&spi->dev, |
919 | sizeof(*data) + chips * sizeof(struct mcp23s08), | |
920 | GFP_KERNEL); | |
8f1cc3b1 DB |
921 | if (!data) |
922 | return -ENOMEM; | |
7898b31e | 923 | |
8f1cc3b1 DB |
924 | spi_set_drvdata(spi, data); |
925 | ||
a231b88c AS |
926 | spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0); |
927 | ||
0b7bb77f | 928 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
97ddb1c8 | 929 | if (!(spi_present_mask & (1 << addr))) |
8f1cc3b1 DB |
930 | continue; |
931 | chips--; | |
932 | data->mcp[addr] = &data->chip[chips]; | |
a231b88c | 933 | data->mcp[addr]->irq = spi->irq; |
d62b98f3 | 934 | status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, |
3af0dbd5 SZ |
935 | 0x40 | (addr << 1), type, pdata, |
936 | addr); | |
8f1cc3b1 DB |
937 | if (status < 0) |
938 | goto fail; | |
0b7bb77f | 939 | |
3af0dbd5 | 940 | if (pdata->base != -1) |
28c5a41e PR |
941 | pdata->base += data->mcp[addr]->chip.ngpio; |
942 | ngpio += data->mcp[addr]->chip.ngpio; | |
8f1cc3b1 | 943 | } |
97ddb1c8 | 944 | data->ngpio = ngpio; |
e58b9e27 DB |
945 | |
946 | /* NOTE: these chips have a relatively sane IRQ framework, with | |
947 | * per-signal masking and level/edge triggering. It's not yet | |
948 | * handled here... | |
949 | */ | |
950 | ||
e58b9e27 DB |
951 | return 0; |
952 | ||
953 | fail: | |
0b7bb77f | 954 | for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { |
8f1cc3b1 DB |
955 | |
956 | if (!data->mcp[addr]) | |
957 | continue; | |
9f5132ae | 958 | gpiochip_remove(&data->mcp[addr]->chip); |
8f1cc3b1 | 959 | } |
e58b9e27 DB |
960 | return status; |
961 | } | |
962 | ||
963 | static int mcp23s08_remove(struct spi_device *spi) | |
964 | { | |
8f1cc3b1 | 965 | struct mcp23s08_driver_data *data = spi_get_drvdata(spi); |
8f1cc3b1 | 966 | unsigned addr; |
e58b9e27 | 967 | |
0b7bb77f | 968 | for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { |
8f1cc3b1 DB |
969 | |
970 | if (!data->mcp[addr]) | |
971 | continue; | |
972 | ||
9f5132ae | 973 | gpiochip_remove(&data->mcp[addr]->chip); |
8f1cc3b1 | 974 | } |
c4941e07 | 975 | |
9f5132ae | 976 | return 0; |
e58b9e27 DB |
977 | } |
978 | ||
0b7bb77f PK |
979 | static const struct spi_device_id mcp23s08_ids[] = { |
980 | { "mcp23s08", MCP_TYPE_S08 }, | |
981 | { "mcp23s17", MCP_TYPE_S17 }, | |
28c5a41e | 982 | { "mcp23s18", MCP_TYPE_S18 }, |
0b7bb77f PK |
983 | { }, |
984 | }; | |
985 | MODULE_DEVICE_TABLE(spi, mcp23s08_ids); | |
986 | ||
e58b9e27 DB |
987 | static struct spi_driver mcp23s08_driver = { |
988 | .probe = mcp23s08_probe, | |
989 | .remove = mcp23s08_remove, | |
0b7bb77f | 990 | .id_table = mcp23s08_ids, |
e58b9e27 DB |
991 | .driver = { |
992 | .name = "mcp23s08", | |
97ddb1c8 | 993 | .of_match_table = of_match_ptr(mcp23s08_spi_of_match), |
e58b9e27 DB |
994 | }, |
995 | }; | |
996 | ||
d62b98f3 PK |
997 | static int __init mcp23s08_spi_init(void) |
998 | { | |
999 | return spi_register_driver(&mcp23s08_driver); | |
1000 | } | |
1001 | ||
1002 | static void mcp23s08_spi_exit(void) | |
1003 | { | |
1004 | spi_unregister_driver(&mcp23s08_driver); | |
1005 | } | |
1006 | ||
1007 | #else | |
1008 | ||
1009 | static int __init mcp23s08_spi_init(void) { return 0; } | |
1010 | static void mcp23s08_spi_exit(void) { } | |
1011 | ||
1012 | #endif /* CONFIG_SPI_MASTER */ | |
1013 | ||
e58b9e27 DB |
1014 | /*----------------------------------------------------------------------*/ |
1015 | ||
1016 | static int __init mcp23s08_init(void) | |
1017 | { | |
752ad5e8 PK |
1018 | int ret; |
1019 | ||
1020 | ret = mcp23s08_spi_init(); | |
1021 | if (ret) | |
1022 | goto spi_fail; | |
1023 | ||
1024 | ret = mcp23s08_i2c_init(); | |
1025 | if (ret) | |
1026 | goto i2c_fail; | |
1027 | ||
1028 | return 0; | |
1029 | ||
1030 | i2c_fail: | |
1031 | mcp23s08_spi_exit(); | |
1032 | spi_fail: | |
1033 | return ret; | |
e58b9e27 | 1034 | } |
752ad5e8 | 1035 | /* register after spi/i2c postcore initcall and before |
673c0c00 DB |
1036 | * subsys initcalls that may rely on these GPIOs |
1037 | */ | |
1038 | subsys_initcall(mcp23s08_init); | |
e58b9e27 DB |
1039 | |
1040 | static void __exit mcp23s08_exit(void) | |
1041 | { | |
d62b98f3 | 1042 | mcp23s08_spi_exit(); |
752ad5e8 | 1043 | mcp23s08_i2c_exit(); |
e58b9e27 DB |
1044 | } |
1045 | module_exit(mcp23s08_exit); | |
1046 | ||
1047 | MODULE_LICENSE("GPL"); |