Commit | Line | Data |
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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d8f4494e | 2 | /* MCP23S08 SPI/I2C GPIO driver */ |
e58b9e27 DB |
3 | |
4 | #include <linux/kernel.h> | |
5 | #include <linux/device.h> | |
e58b9e27 | 6 | #include <linux/mutex.h> |
1ac30db2 | 7 | #include <linux/mod_devicetable.h> |
bb207ef1 | 8 | #include <linux/module.h> |
1c5fb66a | 9 | #include <linux/gpio/driver.h> |
752ad5e8 | 10 | #include <linux/i2c.h> |
e58b9e27 | 11 | #include <linux/spi/spi.h> |
5a0e3ad6 | 12 | #include <linux/slab.h> |
0b7bb77f | 13 | #include <asm/byteorder.h> |
4e47f91b | 14 | #include <linux/interrupt.h> |
3d84fdb3 | 15 | #include <linux/regmap.h> |
82039d24 SR |
16 | #include <linux/pinctrl/pinctrl.h> |
17 | #include <linux/pinctrl/pinconf.h> | |
18 | #include <linux/pinctrl/pinconf-generic.h> | |
e58b9e27 | 19 | |
d8f4494e | 20 | /* |
0b7bb77f PK |
21 | * MCP types supported by driver |
22 | */ | |
1ac30db2 AS |
23 | #define MCP_TYPE_S08 1 |
24 | #define MCP_TYPE_S17 2 | |
25 | #define MCP_TYPE_008 3 | |
26 | #define MCP_TYPE_017 4 | |
27 | #define MCP_TYPE_S18 5 | |
28 | #define MCP_TYPE_018 6 | |
e58b9e27 DB |
29 | |
30 | /* Registers are all 8 bits wide. | |
31 | * | |
32 | * The mcp23s17 has twice as many bits, and can be configured to work | |
33 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
34 | */ |
35 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
36 | #define MCP_IPOL 0x01 | |
37 | #define MCP_GPINTEN 0x02 | |
38 | #define MCP_DEFVAL 0x03 | |
39 | #define MCP_INTCON 0x04 | |
40 | #define MCP_IOCON 0x05 | |
4e47f91b | 41 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
42 | # define IOCON_SEQOP (1 << 5) |
43 | # define IOCON_HAEN (1 << 3) | |
44 | # define IOCON_ODR (1 << 2) | |
45 | # define IOCON_INTPOL (1 << 1) | |
3539699c | 46 | # define IOCON_INTCC (1) |
e58b9e27 DB |
47 | #define MCP_GPPU 0x06 |
48 | #define MCP_INTF 0x07 | |
49 | #define MCP_INTCAP 0x08 | |
50 | #define MCP_GPIO 0x09 | |
51 | #define MCP_OLAT 0x0a | |
52 | ||
0b7bb77f PK |
53 | struct mcp23s08; |
54 | ||
e58b9e27 | 55 | struct mcp23s08 { |
e58b9e27 | 56 | u8 addr; |
a4e63554 | 57 | bool irq_active_high; |
3d84fdb3 | 58 | bool reg_shift; |
e58b9e27 | 59 | |
4e47f91b LP |
60 | u16 irq_rise; |
61 | u16 irq_fall; | |
62 | int irq; | |
63 | bool irq_controller; | |
8f38910b SR |
64 | int cached_gpio; |
65 | /* lock protects regmap access with bypass/cache flags */ | |
e58b9e27 | 66 | struct mutex lock; |
e58b9e27 DB |
67 | |
68 | struct gpio_chip chip; | |
19ab5ca9 | 69 | struct irq_chip irq_chip; |
e58b9e27 | 70 | |
3d84fdb3 SR |
71 | struct regmap *regmap; |
72 | struct device *dev; | |
82039d24 SR |
73 | |
74 | struct pinctrl_dev *pctldev; | |
75 | struct pinctrl_desc pinctrl_desc; | |
8f1cc3b1 DB |
76 | }; |
77 | ||
8f38910b SR |
78 | static const struct reg_default mcp23x08_defaults[] = { |
79 | {.reg = MCP_IODIR, .def = 0xff}, | |
80 | {.reg = MCP_IPOL, .def = 0x00}, | |
81 | {.reg = MCP_GPINTEN, .def = 0x00}, | |
82 | {.reg = MCP_DEFVAL, .def = 0x00}, | |
83 | {.reg = MCP_INTCON, .def = 0x00}, | |
84 | {.reg = MCP_IOCON, .def = 0x00}, | |
85 | {.reg = MCP_GPPU, .def = 0x00}, | |
86 | {.reg = MCP_OLAT, .def = 0x00}, | |
87 | }; | |
88 | ||
89 | static const struct regmap_range mcp23x08_volatile_range = { | |
90 | .range_min = MCP_INTF, | |
91 | .range_max = MCP_GPIO, | |
92 | }; | |
93 | ||
94 | static const struct regmap_access_table mcp23x08_volatile_table = { | |
95 | .yes_ranges = &mcp23x08_volatile_range, | |
96 | .n_yes_ranges = 1, | |
97 | }; | |
98 | ||
99 | static const struct regmap_range mcp23x08_precious_range = { | |
100 | .range_min = MCP_GPIO, | |
101 | .range_max = MCP_GPIO, | |
102 | }; | |
103 | ||
104 | static const struct regmap_access_table mcp23x08_precious_table = { | |
105 | .yes_ranges = &mcp23x08_precious_range, | |
106 | .n_yes_ranges = 1, | |
107 | }; | |
108 | ||
3d84fdb3 SR |
109 | static const struct regmap_config mcp23x08_regmap = { |
110 | .reg_bits = 8, | |
111 | .val_bits = 8, | |
752ad5e8 | 112 | |
3d84fdb3 | 113 | .reg_stride = 1, |
8f38910b SR |
114 | .volatile_table = &mcp23x08_volatile_table, |
115 | .precious_table = &mcp23x08_precious_table, | |
116 | .reg_defaults = mcp23x08_defaults, | |
117 | .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), | |
118 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 | 119 | .max_register = MCP_OLAT, |
752ad5e8 PK |
120 | }; |
121 | ||
8f38910b SR |
122 | static const struct reg_default mcp23x16_defaults[] = { |
123 | {.reg = MCP_IODIR << 1, .def = 0xffff}, | |
124 | {.reg = MCP_IPOL << 1, .def = 0x0000}, | |
125 | {.reg = MCP_GPINTEN << 1, .def = 0x0000}, | |
126 | {.reg = MCP_DEFVAL << 1, .def = 0x0000}, | |
127 | {.reg = MCP_INTCON << 1, .def = 0x0000}, | |
128 | {.reg = MCP_IOCON << 1, .def = 0x0000}, | |
129 | {.reg = MCP_GPPU << 1, .def = 0x0000}, | |
130 | {.reg = MCP_OLAT << 1, .def = 0x0000}, | |
131 | }; | |
132 | ||
133 | static const struct regmap_range mcp23x16_volatile_range = { | |
134 | .range_min = MCP_INTF << 1, | |
135 | .range_max = MCP_GPIO << 1, | |
136 | }; | |
137 | ||
138 | static const struct regmap_access_table mcp23x16_volatile_table = { | |
139 | .yes_ranges = &mcp23x16_volatile_range, | |
140 | .n_yes_ranges = 1, | |
141 | }; | |
142 | ||
143 | static const struct regmap_range mcp23x16_precious_range = { | |
144 | .range_min = MCP_GPIO << 1, | |
145 | .range_max = MCP_GPIO << 1, | |
146 | }; | |
147 | ||
148 | static const struct regmap_access_table mcp23x16_precious_table = { | |
149 | .yes_ranges = &mcp23x16_precious_range, | |
150 | .n_yes_ranges = 1, | |
151 | }; | |
152 | ||
3d84fdb3 SR |
153 | static const struct regmap_config mcp23x17_regmap = { |
154 | .reg_bits = 8, | |
155 | .val_bits = 16, | |
752ad5e8 | 156 | |
3d84fdb3 SR |
157 | .reg_stride = 2, |
158 | .max_register = MCP_OLAT << 1, | |
8f38910b SR |
159 | .volatile_table = &mcp23x16_volatile_table, |
160 | .precious_table = &mcp23x16_precious_table, | |
161 | .reg_defaults = mcp23x16_defaults, | |
162 | .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), | |
163 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 SR |
164 | .val_format_endian = REGMAP_ENDIAN_LITTLE, |
165 | }; | |
752ad5e8 | 166 | |
82039d24 SR |
167 | static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) |
168 | { | |
169 | return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); | |
170 | } | |
171 | ||
172 | static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) | |
173 | { | |
174 | return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); | |
175 | } | |
176 | ||
8f38910b SR |
177 | static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, |
178 | unsigned int mask, bool enabled) | |
82039d24 SR |
179 | { |
180 | u16 val = enabled ? 0xffff : 0x0000; | |
82039d24 SR |
181 | return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, |
182 | mask, val); | |
183 | } | |
184 | ||
8f38910b SR |
185 | static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, |
186 | unsigned int pin, bool enabled) | |
82039d24 | 187 | { |
8f38910b SR |
188 | u16 mask = BIT(pin); |
189 | return mcp_set_mask(mcp, reg, mask, enabled); | |
82039d24 SR |
190 | } |
191 | ||
192 | static const struct pinctrl_pin_desc mcp23x08_pins[] = { | |
193 | PINCTRL_PIN(0, "gpio0"), | |
194 | PINCTRL_PIN(1, "gpio1"), | |
195 | PINCTRL_PIN(2, "gpio2"), | |
196 | PINCTRL_PIN(3, "gpio3"), | |
197 | PINCTRL_PIN(4, "gpio4"), | |
198 | PINCTRL_PIN(5, "gpio5"), | |
199 | PINCTRL_PIN(6, "gpio6"), | |
200 | PINCTRL_PIN(7, "gpio7"), | |
201 | }; | |
202 | ||
203 | static const struct pinctrl_pin_desc mcp23x17_pins[] = { | |
204 | PINCTRL_PIN(0, "gpio0"), | |
205 | PINCTRL_PIN(1, "gpio1"), | |
206 | PINCTRL_PIN(2, "gpio2"), | |
207 | PINCTRL_PIN(3, "gpio3"), | |
208 | PINCTRL_PIN(4, "gpio4"), | |
209 | PINCTRL_PIN(5, "gpio5"), | |
210 | PINCTRL_PIN(6, "gpio6"), | |
211 | PINCTRL_PIN(7, "gpio7"), | |
212 | PINCTRL_PIN(8, "gpio8"), | |
213 | PINCTRL_PIN(9, "gpio9"), | |
214 | PINCTRL_PIN(10, "gpio10"), | |
215 | PINCTRL_PIN(11, "gpio11"), | |
216 | PINCTRL_PIN(12, "gpio12"), | |
217 | PINCTRL_PIN(13, "gpio13"), | |
218 | PINCTRL_PIN(14, "gpio14"), | |
219 | PINCTRL_PIN(15, "gpio15"), | |
220 | }; | |
221 | ||
222 | static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
223 | { | |
224 | return 0; | |
225 | } | |
226 | ||
227 | static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
228 | unsigned int group) | |
229 | { | |
230 | return NULL; | |
231 | } | |
232 | ||
233 | static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
234 | unsigned int group, | |
235 | const unsigned int **pins, | |
236 | unsigned int *num_pins) | |
237 | { | |
238 | return -ENOTSUPP; | |
239 | } | |
240 | ||
241 | static const struct pinctrl_ops mcp_pinctrl_ops = { | |
242 | .get_groups_count = mcp_pinctrl_get_groups_count, | |
243 | .get_group_name = mcp_pinctrl_get_group_name, | |
244 | .get_group_pins = mcp_pinctrl_get_group_pins, | |
245 | #ifdef CONFIG_OF | |
246 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
247 | .dt_free_map = pinconf_generic_dt_free_map, | |
248 | #endif | |
249 | }; | |
250 | ||
251 | static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
252 | unsigned long *config) | |
253 | { | |
254 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
255 | enum pin_config_param param = pinconf_to_config_param(*config); | |
256 | unsigned int data, status; | |
257 | int ret; | |
258 | ||
259 | switch (param) { | |
260 | case PIN_CONFIG_BIAS_PULL_UP: | |
261 | ret = mcp_read(mcp, MCP_GPPU, &data); | |
262 | if (ret < 0) | |
263 | return ret; | |
264 | status = (data & BIT(pin)) ? 1 : 0; | |
265 | break; | |
266 | default: | |
82039d24 SR |
267 | return -ENOTSUPP; |
268 | } | |
269 | ||
270 | *config = 0; | |
271 | ||
272 | return status ? 0 : -EINVAL; | |
273 | } | |
274 | ||
275 | static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
276 | unsigned long *configs, unsigned int num_configs) | |
277 | { | |
278 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
279 | enum pin_config_param param; | |
2a7893c8 | 280 | u32 arg; |
82039d24 SR |
281 | int ret = 0; |
282 | int i; | |
283 | ||
284 | for (i = 0; i < num_configs; i++) { | |
285 | param = pinconf_to_config_param(configs[i]); | |
286 | arg = pinconf_to_config_argument(configs[i]); | |
287 | ||
288 | switch (param) { | |
289 | case PIN_CONFIG_BIAS_PULL_UP: | |
82039d24 SR |
290 | ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); |
291 | break; | |
292 | default: | |
e0e31695 | 293 | dev_dbg(mcp->dev, "Invalid config param %04x\n", param); |
82039d24 SR |
294 | return -ENOTSUPP; |
295 | } | |
296 | } | |
297 | ||
298 | return ret; | |
299 | } | |
300 | ||
301 | static const struct pinconf_ops mcp_pinconf_ops = { | |
302 | .pin_config_get = mcp_pinconf_get, | |
303 | .pin_config_set = mcp_pinconf_set, | |
304 | .is_generic = true, | |
305 | }; | |
306 | ||
752ad5e8 PK |
307 | /*----------------------------------------------------------------------*/ |
308 | ||
e58b9e27 DB |
309 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) |
310 | { | |
9e03cf0b | 311 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
312 | int status; |
313 | ||
314 | mutex_lock(&mcp->lock); | |
8f38910b | 315 | status = mcp_set_bit(mcp, MCP_IODIR, offset, true); |
e58b9e27 | 316 | mutex_unlock(&mcp->lock); |
8f38910b | 317 | |
e58b9e27 DB |
318 | return status; |
319 | } | |
320 | ||
321 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
322 | { | |
9e03cf0b | 323 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
3d84fdb3 | 324 | int status, ret; |
e58b9e27 DB |
325 | |
326 | mutex_lock(&mcp->lock); | |
327 | ||
328 | /* REVISIT reading this clears any IRQ ... */ | |
3d84fdb3 SR |
329 | ret = mcp_read(mcp, MCP_GPIO, &status); |
330 | if (ret < 0) | |
e58b9e27 | 331 | status = 0; |
59861701 DM |
332 | else { |
333 | mcp->cached_gpio = status; | |
e58b9e27 | 334 | status = !!(status & (1 << offset)); |
59861701 | 335 | } |
8f38910b | 336 | |
e58b9e27 DB |
337 | mutex_unlock(&mcp->lock); |
338 | return status; | |
339 | } | |
340 | ||
8f38910b | 341 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) |
e58b9e27 | 342 | { |
8f38910b | 343 | return mcp_set_mask(mcp, MCP_OLAT, mask, value); |
e58b9e27 DB |
344 | } |
345 | ||
346 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
347 | { | |
9e03cf0b | 348 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 349 | unsigned mask = BIT(offset); |
e58b9e27 DB |
350 | |
351 | mutex_lock(&mcp->lock); | |
8f38910b | 352 | __mcp23s08_set(mcp, mask, !!value); |
e58b9e27 DB |
353 | mutex_unlock(&mcp->lock); |
354 | } | |
355 | ||
356 | static int | |
357 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
358 | { | |
9e03cf0b | 359 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 360 | unsigned mask = BIT(offset); |
e58b9e27 DB |
361 | int status; |
362 | ||
363 | mutex_lock(&mcp->lock); | |
364 | status = __mcp23s08_set(mcp, mask, value); | |
365 | if (status == 0) { | |
8f38910b | 366 | status = mcp_set_mask(mcp, MCP_IODIR, mask, false); |
e58b9e27 DB |
367 | } |
368 | mutex_unlock(&mcp->lock); | |
369 | return status; | |
370 | } | |
371 | ||
4e47f91b LP |
372 | /*----------------------------------------------------------------------*/ |
373 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
374 | { | |
375 | struct mcp23s08 *mcp = data; | |
8f38910b | 376 | int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; |
4e47f91b | 377 | unsigned int child_irq; |
2cd29f23 RM |
378 | bool intf_set, intcap_changed, gpio_bit_changed, |
379 | defval_changed, gpio_set; | |
4e47f91b LP |
380 | |
381 | mutex_lock(&mcp->lock); | |
7f6f50df ME |
382 | if (mcp_read(mcp, MCP_INTF, &intf)) |
383 | goto unlock; | |
4e47f91b | 384 | |
7f6f50df ME |
385 | if (mcp_read(mcp, MCP_INTCAP, &intcap)) |
386 | goto unlock; | |
4e47f91b | 387 | |
7f6f50df ME |
388 | if (mcp_read(mcp, MCP_INTCON, &intcon)) |
389 | goto unlock; | |
8f38910b | 390 | |
7f6f50df ME |
391 | if (mcp_read(mcp, MCP_DEFVAL, &defval)) |
392 | goto unlock; | |
2cd29f23 RM |
393 | |
394 | /* This clears the interrupt(configurable on S18) */ | |
7f6f50df ME |
395 | if (mcp_read(mcp, MCP_GPIO, &gpio)) |
396 | goto unlock; | |
397 | ||
8f38910b SR |
398 | gpio_orig = mcp->cached_gpio; |
399 | mcp->cached_gpio = gpio; | |
4e47f91b LP |
400 | mutex_unlock(&mcp->lock); |
401 | ||
8f38910b | 402 | if (intf == 0) { |
2cd29f23 RM |
403 | /* There is no interrupt pending */ |
404 | return IRQ_HANDLED; | |
405 | } | |
406 | ||
407 | dev_dbg(mcp->chip.parent, | |
408 | "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", | |
409 | intcap, intf, gpio_orig, gpio); | |
4e47f91b LP |
410 | |
411 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
2cd29f23 RM |
412 | /* We must check all of the inputs on the chip, |
413 | * otherwise we may not notice a change on >=2 pins. | |
414 | * | |
415 | * On at least the mcp23s17, INTCAP is only updated | |
416 | * one byte at a time(INTCAPA and INTCAPB are | |
417 | * not written to at the same time - only on a per-bank | |
418 | * basis). | |
419 | * | |
420 | * INTF only contains the single bit that caused the | |
421 | * interrupt per-bank. On the mcp23s17, there is | |
422 | * INTFA and INTFB. If two pins are changed on the A | |
423 | * side at the same time, INTF will only have one bit | |
424 | * set. If one pin on the A side and one pin on the B | |
425 | * side are changed at the same time, INTF will have | |
426 | * two bits set. Thus, INTF can't be the only check | |
427 | * to see if the input has changed. | |
428 | */ | |
429 | ||
8f38910b | 430 | intf_set = intf & BIT(i); |
2cd29f23 RM |
431 | if (i < 8 && intf_set) |
432 | intcap_mask = 0x00FF; | |
433 | else if (i >= 8 && intf_set) | |
434 | intcap_mask = 0xFF00; | |
435 | else | |
436 | intcap_mask = 0x00; | |
437 | ||
438 | intcap_changed = (intcap_mask & | |
8f38910b | 439 | (intcap & BIT(i))) != |
2cd29f23 | 440 | (intcap_mask & (BIT(i) & gpio_orig)); |
8f38910b | 441 | gpio_set = BIT(i) & gpio; |
2cd29f23 | 442 | gpio_bit_changed = (BIT(i) & gpio_orig) != |
8f38910b SR |
443 | (BIT(i) & gpio); |
444 | defval_changed = (BIT(i) & intcon) && | |
445 | ((BIT(i) & gpio) != | |
446 | (BIT(i) & defval)); | |
2cd29f23 RM |
447 | |
448 | if (((gpio_bit_changed || intcap_changed) && | |
449 | (BIT(i) & mcp->irq_rise) && gpio_set) || | |
450 | ((gpio_bit_changed || intcap_changed) && | |
451 | (BIT(i) & mcp->irq_fall) && !gpio_set) || | |
452 | defval_changed) { | |
f0fbe7bc | 453 | child_irq = irq_find_mapping(mcp->chip.irq.domain, i); |
4e47f91b LP |
454 | handle_nested_irq(child_irq); |
455 | } | |
456 | } | |
457 | ||
458 | return IRQ_HANDLED; | |
7f6f50df ME |
459 | |
460 | unlock: | |
461 | mutex_unlock(&mcp->lock); | |
462 | return IRQ_HANDLED; | |
4e47f91b LP |
463 | } |
464 | ||
4e47f91b LP |
465 | static void mcp23s08_irq_mask(struct irq_data *data) |
466 | { | |
dad3d272 PR |
467 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
468 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
469 | unsigned int pos = data->hwirq; |
470 | ||
8f38910b | 471 | mcp_set_bit(mcp, MCP_GPINTEN, pos, false); |
4e47f91b LP |
472 | } |
473 | ||
474 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
475 | { | |
dad3d272 PR |
476 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
477 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
478 | unsigned int pos = data->hwirq; |
479 | ||
8f38910b | 480 | mcp_set_bit(mcp, MCP_GPINTEN, pos, true); |
4e47f91b LP |
481 | } |
482 | ||
483 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
484 | { | |
dad3d272 PR |
485 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
486 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 487 | unsigned int pos = data->hwirq; |
4e47f91b LP |
488 | |
489 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
8f38910b | 490 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
491 | mcp->irq_rise |= BIT(pos); |
492 | mcp->irq_fall |= BIT(pos); | |
493 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
8f38910b | 494 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
495 | mcp->irq_rise |= BIT(pos); |
496 | mcp->irq_fall &= ~BIT(pos); | |
497 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
8f38910b | 498 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
499 | mcp->irq_rise &= ~BIT(pos); |
500 | mcp->irq_fall |= BIT(pos); | |
16fe1ad2 | 501 | } else if (type & IRQ_TYPE_LEVEL_HIGH) { |
8f38910b SR |
502 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
503 | mcp_set_bit(mcp, MCP_DEFVAL, pos, false); | |
16fe1ad2 | 504 | } else if (type & IRQ_TYPE_LEVEL_LOW) { |
8f38910b SR |
505 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
506 | mcp_set_bit(mcp, MCP_DEFVAL, pos, true); | |
4e47f91b LP |
507 | } else |
508 | return -EINVAL; | |
509 | ||
88af89b5 | 510 | return 0; |
4e47f91b LP |
511 | } |
512 | ||
513 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
514 | { | |
dad3d272 PR |
515 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
516 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 517 | |
8f38910b SR |
518 | mutex_lock(&mcp->lock); |
519 | regcache_cache_only(mcp->regmap, true); | |
4e47f91b LP |
520 | } |
521 | ||
522 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
523 | { | |
dad3d272 PR |
524 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
525 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 526 | |
8f38910b SR |
527 | regcache_cache_only(mcp->regmap, false); |
528 | regcache_sync(mcp->regmap); | |
529 | ||
4e47f91b | 530 | mutex_unlock(&mcp->lock); |
4e47f91b LP |
531 | } |
532 | ||
4e47f91b LP |
533 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) |
534 | { | |
535 | struct gpio_chip *chip = &mcp->chip; | |
dad3d272 | 536 | int err; |
a4e63554 | 537 | unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; |
4e47f91b | 538 | |
a4e63554 AS |
539 | if (mcp->irq_active_high) |
540 | irqflags |= IRQF_TRIGGER_HIGH; | |
541 | else | |
542 | irqflags |= IRQF_TRIGGER_LOW; | |
543 | ||
58383c78 LW |
544 | err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, |
545 | mcp23s08_irq, | |
546 | irqflags, dev_name(chip->parent), mcp); | |
4e47f91b | 547 | if (err != 0) { |
58383c78 | 548 | dev_err(chip->parent, "unable to request IRQ#%d: %d\n", |
4e47f91b LP |
549 | mcp->irq, err); |
550 | return err; | |
551 | } | |
552 | ||
f259f896 MF |
553 | return 0; |
554 | } | |
555 | ||
556 | static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp) | |
557 | { | |
558 | struct gpio_chip *chip = &mcp->chip; | |
559 | int err; | |
560 | ||
d245b3f9 | 561 | err = gpiochip_irqchip_add_nested(chip, |
19ab5ca9 | 562 | &mcp->irq_chip, |
d245b3f9 LW |
563 | 0, |
564 | handle_simple_irq, | |
565 | IRQ_TYPE_NONE); | |
dad3d272 PR |
566 | if (err) { |
567 | dev_err(chip->parent, | |
568 | "could not connect irqchip to gpiochip: %d\n", err); | |
569 | return err; | |
4e47f91b | 570 | } |
4e47f91b | 571 | |
d245b3f9 | 572 | gpiochip_set_nested_irqchip(chip, |
19ab5ca9 | 573 | &mcp->irq_chip, |
d245b3f9 | 574 | mcp->irq); |
4e47f91b | 575 | |
dad3d272 | 576 | return 0; |
4e47f91b LP |
577 | } |
578 | ||
e58b9e27 DB |
579 | /*----------------------------------------------------------------------*/ |
580 | ||
d62b98f3 | 581 | static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
d3da29b6 | 582 | unsigned int addr, unsigned int type, |
0521701c | 583 | unsigned int base) |
e58b9e27 | 584 | { |
3d84fdb3 | 585 | int status, ret; |
4e47f91b | 586 | bool mirror = false; |
fa2b7fae | 587 | bool open_drain = false; |
e58b9e27 | 588 | |
e58b9e27 DB |
589 | mutex_init(&mcp->lock); |
590 | ||
3d84fdb3 | 591 | mcp->dev = dev; |
d62b98f3 | 592 | mcp->addr = addr; |
84d02e78 | 593 | |
a4e63554 | 594 | mcp->irq_active_high = false; |
84d02e78 AS |
595 | mcp->irq_chip.name = dev_name(dev); |
596 | mcp->irq_chip.irq_mask = mcp23s08_irq_mask; | |
597 | mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; | |
598 | mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; | |
599 | mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; | |
600 | mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; | |
e58b9e27 | 601 | |
e58b9e27 DB |
602 | mcp->chip.direction_input = mcp23s08_direction_input; |
603 | mcp->chip.get = mcp23s08_get; | |
604 | mcp->chip.direction_output = mcp23s08_direction_output; | |
605 | mcp->chip.set = mcp23s08_set; | |
60f749f8 | 606 | #ifdef CONFIG_OF_GPIO |
97ddb1c8 LP |
607 | mcp->chip.of_gpio_n_cells = 2; |
608 | mcp->chip.of_node = dev->of_node; | |
609 | #endif | |
e58b9e27 | 610 | |
5b1a7e80 | 611 | mcp->chip.base = base; |
9fb1f39e | 612 | mcp->chip.can_sleep = true; |
58383c78 | 613 | mcp->chip.parent = dev; |
d72cbed0 | 614 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 615 | |
8f1cc3b1 DB |
616 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
617 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
618 | */ | |
4e47f91b | 619 | |
3d84fdb3 SR |
620 | ret = mcp_read(mcp, MCP_IOCON, &status); |
621 | if (ret < 0) | |
e58b9e27 | 622 | goto fail; |
4e47f91b | 623 | |
6dbc6e6f PR |
624 | ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); |
625 | if (ret < 0) | |
626 | goto fail; | |
627 | ||
5b1a7e80 SR |
628 | mcp->irq_controller = |
629 | device_property_read_bool(dev, "interrupt-controller"); | |
a4e63554 | 630 | if (mcp->irq && mcp->irq_controller) { |
170680ab | 631 | mcp->irq_active_high = |
5b1a7e80 | 632 | device_property_read_bool(dev, |
170680ab | 633 | "microchip,irq-active-high"); |
4e47f91b | 634 | |
5b1a7e80 | 635 | mirror = device_property_read_bool(dev, "microchip,irq-mirror"); |
fa2b7fae | 636 | open_drain = device_property_read_bool(dev, "drive-open-drain"); |
a4e63554 AS |
637 | } |
638 | ||
639 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || | |
fa2b7fae | 640 | mcp->irq_active_high || open_drain) { |
0b7bb77f PK |
641 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
642 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
643 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
a4e63554 AS |
644 | if (mcp->irq_active_high) |
645 | status |= IOCON_INTPOL | (IOCON_INTPOL << 8); | |
646 | else | |
647 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); | |
648 | ||
4e47f91b LP |
649 | if (mirror) |
650 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
651 | ||
fa2b7fae PR |
652 | if (open_drain) |
653 | status |= IOCON_ODR | (IOCON_ODR << 8); | |
654 | ||
ff0f2ce7 | 655 | if (type == MCP_TYPE_S18 || type == MCP_TYPE_018) |
3539699c PR |
656 | status |= IOCON_INTCC | (IOCON_INTCC << 8); |
657 | ||
3d84fdb3 SR |
658 | ret = mcp_write(mcp, MCP_IOCON, status); |
659 | if (ret < 0) | |
e58b9e27 DB |
660 | goto fail; |
661 | } | |
662 | ||
4e47f91b | 663 | if (mcp->irq && mcp->irq_controller) { |
f259f896 | 664 | ret = mcp23s08_irqchip_setup(mcp); |
3d84fdb3 | 665 | if (ret) |
4e47f91b | 666 | goto fail; |
4e47f91b | 667 | } |
82039d24 | 668 | |
82039d24 SR |
669 | mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; |
670 | mcp->pinctrl_desc.confops = &mcp_pinconf_ops; | |
671 | mcp->pinctrl_desc.npins = mcp->chip.ngpio; | |
672 | if (mcp->pinctrl_desc.npins == 8) | |
673 | mcp->pinctrl_desc.pins = mcp23x08_pins; | |
674 | else if (mcp->pinctrl_desc.npins == 16) | |
675 | mcp->pinctrl_desc.pins = mcp23x17_pins; | |
676 | mcp->pinctrl_desc.owner = THIS_MODULE; | |
677 | ||
678 | mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); | |
679 | if (IS_ERR(mcp->pctldev)) { | |
680 | ret = PTR_ERR(mcp->pctldev); | |
681 | goto fail; | |
682 | } | |
683 | ||
f259f896 MF |
684 | if (mcp->irq) |
685 | ret = mcp23s08_irq_setup(mcp); | |
686 | ||
8f1cc3b1 | 687 | fail: |
3d84fdb3 SR |
688 | if (ret < 0) |
689 | dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); | |
690 | return ret; | |
8f1cc3b1 DB |
691 | } |
692 | ||
752ad5e8 PK |
693 | /*----------------------------------------------------------------------*/ |
694 | ||
cbf24fad | 695 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 696 | |
3836309d | 697 | static int mcp230xx_probe(struct i2c_client *client, |
752ad5e8 PK |
698 | const struct i2c_device_id *id) |
699 | { | |
d3da29b6 AS |
700 | struct device *dev = &client->dev; |
701 | unsigned int type = id->driver_data; | |
752ad5e8 | 702 | struct mcp23s08 *mcp; |
3af0dbd5 | 703 | int status; |
97ddb1c8 | 704 | |
2f98e78b | 705 | mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); |
752ad5e8 PK |
706 | if (!mcp) |
707 | return -ENOMEM; | |
708 | ||
4e47f91b | 709 | mcp->irq = client->irq; |
19ab5ca9 | 710 | |
d3da29b6 AS |
711 | switch (type) { |
712 | case MCP_TYPE_008: | |
713 | mcp->regmap = devm_regmap_init_i2c(client, &mcp23x08_regmap); | |
714 | mcp->reg_shift = 0; | |
715 | mcp->chip.ngpio = 8; | |
716 | mcp->chip.label = "mcp23008"; | |
717 | break; | |
718 | ||
719 | case MCP_TYPE_017: | |
720 | mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); | |
721 | mcp->reg_shift = 1; | |
722 | mcp->chip.ngpio = 16; | |
723 | mcp->chip.label = "mcp23017"; | |
724 | break; | |
725 | ||
726 | case MCP_TYPE_018: | |
727 | mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); | |
728 | mcp->reg_shift = 1; | |
729 | mcp->chip.ngpio = 16; | |
730 | mcp->chip.label = "mcp23018"; | |
731 | break; | |
732 | ||
733 | default: | |
734 | dev_err(dev, "invalid device type (%d)\n", type); | |
735 | return -EINVAL; | |
736 | } | |
737 | ||
738 | if (IS_ERR(mcp->regmap)) | |
739 | return PTR_ERR(mcp->regmap); | |
740 | ||
741 | mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; | |
742 | ||
0521701c | 743 | status = mcp23s08_probe_one(mcp, dev, client->addr, type, -1); |
752ad5e8 | 744 | if (status) |
2f98e78b | 745 | return status; |
752ad5e8 PK |
746 | |
747 | i2c_set_clientdata(client, mcp); | |
748 | ||
749 | return 0; | |
752ad5e8 PK |
750 | } |
751 | ||
752ad5e8 PK |
752 | static const struct i2c_device_id mcp230xx_id[] = { |
753 | { "mcp23008", MCP_TYPE_008 }, | |
754 | { "mcp23017", MCP_TYPE_017 }, | |
ff0f2ce7 | 755 | { "mcp23018", MCP_TYPE_018 }, |
752ad5e8 PK |
756 | { }, |
757 | }; | |
758 | MODULE_DEVICE_TABLE(i2c, mcp230xx_id); | |
759 | ||
d3da29b6 AS |
760 | static const struct of_device_id mcp23s08_i2c_of_match[] = { |
761 | { | |
762 | .compatible = "microchip,mcp23008", | |
763 | .data = (void *) MCP_TYPE_008, | |
764 | }, | |
765 | { | |
766 | .compatible = "microchip,mcp23017", | |
767 | .data = (void *) MCP_TYPE_017, | |
768 | }, | |
769 | { | |
770 | .compatible = "microchip,mcp23018", | |
771 | .data = (void *) MCP_TYPE_018, | |
772 | }, | |
773 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
774 | { | |
775 | .compatible = "mcp,mcp23008", | |
776 | .data = (void *) MCP_TYPE_008, | |
777 | }, | |
778 | { | |
779 | .compatible = "mcp,mcp23017", | |
780 | .data = (void *) MCP_TYPE_017, | |
781 | }, | |
782 | { }, | |
783 | }; | |
784 | MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); | |
d3da29b6 | 785 | |
752ad5e8 PK |
786 | static struct i2c_driver mcp230xx_driver = { |
787 | .driver = { | |
788 | .name = "mcp230xx", | |
1ac30db2 | 789 | .of_match_table = mcp23s08_i2c_of_match, |
752ad5e8 PK |
790 | }, |
791 | .probe = mcp230xx_probe, | |
752ad5e8 PK |
792 | .id_table = mcp230xx_id, |
793 | }; | |
794 | ||
795 | static int __init mcp23s08_i2c_init(void) | |
796 | { | |
797 | return i2c_add_driver(&mcp230xx_driver); | |
798 | } | |
799 | ||
800 | static void mcp23s08_i2c_exit(void) | |
801 | { | |
802 | i2c_del_driver(&mcp230xx_driver); | |
803 | } | |
804 | ||
805 | #else | |
806 | ||
807 | static int __init mcp23s08_i2c_init(void) { return 0; } | |
808 | static void mcp23s08_i2c_exit(void) { } | |
809 | ||
810 | #endif /* CONFIG_I2C */ | |
811 | ||
812 | /*----------------------------------------------------------------------*/ | |
813 | ||
d62b98f3 PK |
814 | #ifdef CONFIG_SPI_MASTER |
815 | ||
d3da29b6 AS |
816 | #define MCP_MAX_DEV_PER_CS 8 |
817 | ||
818 | static int mcp23sxx_spi_write(void *context, const void *data, size_t count) | |
819 | { | |
820 | struct mcp23s08 *mcp = context; | |
821 | struct spi_device *spi = to_spi_device(mcp->dev); | |
822 | struct spi_message m; | |
823 | struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
824 | { .tx_buf = data, .len = count, }, }; | |
825 | ||
826 | spi_message_init(&m); | |
827 | spi_message_add_tail(&t[0], &m); | |
828 | spi_message_add_tail(&t[1], &m); | |
829 | ||
830 | return spi_sync(spi, &m); | |
831 | } | |
832 | ||
833 | static int mcp23sxx_spi_gather_write(void *context, | |
834 | const void *reg, size_t reg_size, | |
835 | const void *val, size_t val_size) | |
836 | { | |
837 | struct mcp23s08 *mcp = context; | |
838 | struct spi_device *spi = to_spi_device(mcp->dev); | |
839 | struct spi_message m; | |
840 | struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
841 | { .tx_buf = reg, .len = reg_size, }, | |
842 | { .tx_buf = val, .len = val_size, }, }; | |
843 | ||
844 | spi_message_init(&m); | |
845 | spi_message_add_tail(&t[0], &m); | |
846 | spi_message_add_tail(&t[1], &m); | |
847 | spi_message_add_tail(&t[2], &m); | |
848 | ||
849 | return spi_sync(spi, &m); | |
850 | } | |
851 | ||
852 | static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, | |
853 | void *val, size_t val_size) | |
854 | { | |
855 | struct mcp23s08 *mcp = context; | |
856 | struct spi_device *spi = to_spi_device(mcp->dev); | |
857 | u8 tx[2]; | |
858 | ||
859 | if (reg_size != 1) | |
860 | return -EINVAL; | |
861 | ||
862 | tx[0] = mcp->addr | 0x01; | |
863 | tx[1] = *((u8 *) reg); | |
864 | ||
865 | return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); | |
866 | } | |
867 | ||
868 | static const struct regmap_bus mcp23sxx_spi_regmap = { | |
869 | .write = mcp23sxx_spi_write, | |
870 | .gather_write = mcp23sxx_spi_gather_write, | |
871 | .read = mcp23sxx_spi_read, | |
872 | }; | |
873 | ||
874 | /* A given spi_device can represent up to eight mcp23sxx chips | |
875 | * sharing the same chipselect but using different addresses | |
876 | * (e.g. chips #0 and #3 might be populated, but not #1 or $2). | |
877 | * Driver data holds all the per-chip data. | |
878 | */ | |
879 | struct mcp23s08_driver_data { | |
880 | unsigned ngpio; | |
881 | struct mcp23s08 *mcp[8]; | |
882 | struct mcp23s08 chip[]; | |
883 | }; | |
884 | ||
885 | static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, | |
886 | unsigned int addr, unsigned int type) | |
887 | { | |
0874758e AS |
888 | const struct regmap_config *config; |
889 | struct regmap_config *copy; | |
890 | const char *name; | |
d3da29b6 AS |
891 | |
892 | switch (type) { | |
893 | case MCP_TYPE_S08: | |
0874758e AS |
894 | mcp->reg_shift = 0; |
895 | mcp->chip.ngpio = 8; | |
896 | mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", | |
897 | addr); | |
898 | ||
899 | config = &mcp23x08_regmap; | |
900 | name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); | |
901 | break; | |
902 | ||
d3da29b6 | 903 | case MCP_TYPE_S17: |
0874758e AS |
904 | mcp->reg_shift = 1; |
905 | mcp->chip.ngpio = 16; | |
906 | mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", | |
907 | addr); | |
d3da29b6 | 908 | |
0874758e AS |
909 | config = &mcp23x17_regmap; |
910 | name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); | |
d3da29b6 AS |
911 | break; |
912 | ||
913 | case MCP_TYPE_S18: | |
d3da29b6 AS |
914 | mcp->reg_shift = 1; |
915 | mcp->chip.ngpio = 16; | |
916 | mcp->chip.label = "mcp23s18"; | |
0874758e AS |
917 | |
918 | config = &mcp23x17_regmap; | |
919 | name = config->name; | |
d3da29b6 AS |
920 | break; |
921 | ||
922 | default: | |
923 | dev_err(dev, "invalid device type (%d)\n", type); | |
924 | return -EINVAL; | |
925 | } | |
926 | ||
0874758e AS |
927 | copy = devm_kmemdup(dev, &config, sizeof(config), GFP_KERNEL); |
928 | if (!copy) | |
929 | return -ENOMEM; | |
930 | ||
931 | copy->name = name; | |
932 | ||
933 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, copy); | |
d3da29b6 AS |
934 | if (IS_ERR(mcp->regmap)) |
935 | return PTR_ERR(mcp->regmap); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
8f1cc3b1 DB |
940 | static int mcp23s08_probe(struct spi_device *spi) |
941 | { | |
d3da29b6 | 942 | struct device *dev = &spi->dev; |
1ac30db2 | 943 | const void *match; |
8f1cc3b1 | 944 | unsigned addr; |
596a1c5f | 945 | int chips = 0; |
8f1cc3b1 | 946 | struct mcp23s08_driver_data *data; |
0b7bb77f | 947 | int status, type; |
3af0dbd5 | 948 | unsigned ngpio = 0; |
6aba6ed8 | 949 | u32 spi_present_mask; |
97ddb1c8 | 950 | |
1ac30db2 | 951 | match = device_get_match_data(dev); |
0d7fcd50 | 952 | if (match) |
1ac30db2 | 953 | type = (int)(uintptr_t)match; |
0d7fcd50 SR |
954 | else |
955 | type = spi_get_device_id(spi)->driver_data; | |
956 | ||
6aba6ed8 AS |
957 | status = device_property_read_u32(&spi->dev, |
958 | "microchip,spi-present-mask", &spi_present_mask); | |
959 | if (status) { | |
0d7fcd50 | 960 | status = device_property_read_u32(&spi->dev, |
6aba6ed8 | 961 | "mcp,spi-present-mask", &spi_present_mask); |
97ddb1c8 | 962 | if (status) { |
6aba6ed8 | 963 | dev_err(&spi->dev, "missing spi-present-mask"); |
88af89b5 | 964 | return status; |
97ddb1c8 | 965 | } |
8f1cc3b1 | 966 | } |
8f1cc3b1 | 967 | |
6aba6ed8 | 968 | if (!spi_present_mask || spi_present_mask > 0xff) { |
0d7fcd50 SR |
969 | dev_err(&spi->dev, "invalid spi-present-mask"); |
970 | return -ENODEV; | |
971 | } | |
972 | ||
ce9bd0a0 | 973 | for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { |
6aba6ed8 | 974 | if (spi_present_mask & BIT(addr)) |
0d7fcd50 SR |
975 | chips++; |
976 | } | |
977 | ||
99e4b98d MW |
978 | if (!chips) |
979 | return -ENODEV; | |
980 | ||
7898b31e | 981 | data = devm_kzalloc(&spi->dev, |
16f4372f | 982 | struct_size(data, chip, chips), GFP_KERNEL); |
8f1cc3b1 DB |
983 | if (!data) |
984 | return -ENOMEM; | |
7898b31e | 985 | |
8f1cc3b1 DB |
986 | spi_set_drvdata(spi, data); |
987 | ||
ce9bd0a0 | 988 | for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { |
6aba6ed8 | 989 | if (!(spi_present_mask & BIT(addr))) |
8f1cc3b1 DB |
990 | continue; |
991 | chips--; | |
992 | data->mcp[addr] = &data->chip[chips]; | |
a231b88c | 993 | data->mcp[addr]->irq = spi->irq; |
d3da29b6 AS |
994 | |
995 | status = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, type); | |
996 | if (status) | |
997 | return status; | |
998 | ||
999 | data->mcp[addr]->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, | |
1000 | "mcp23xxx-pinctrl.%d", addr); | |
1001 | if (!data->mcp[addr]->pinctrl_desc.name) | |
1002 | return -ENOMEM; | |
1003 | ||
0521701c | 1004 | status = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1); |
8f1cc3b1 | 1005 | if (status < 0) |
d0e49dab | 1006 | return status; |
0b7bb77f | 1007 | |
28c5a41e | 1008 | ngpio += data->mcp[addr]->chip.ngpio; |
8f1cc3b1 | 1009 | } |
97ddb1c8 | 1010 | data->ngpio = ngpio; |
e58b9e27 | 1011 | |
e58b9e27 | 1012 | return 0; |
e58b9e27 DB |
1013 | } |
1014 | ||
0b7bb77f PK |
1015 | static const struct spi_device_id mcp23s08_ids[] = { |
1016 | { "mcp23s08", MCP_TYPE_S08 }, | |
1017 | { "mcp23s17", MCP_TYPE_S17 }, | |
28c5a41e | 1018 | { "mcp23s18", MCP_TYPE_S18 }, |
0b7bb77f PK |
1019 | { }, |
1020 | }; | |
1021 | MODULE_DEVICE_TABLE(spi, mcp23s08_ids); | |
1022 | ||
d3da29b6 AS |
1023 | static const struct of_device_id mcp23s08_spi_of_match[] = { |
1024 | { | |
1025 | .compatible = "microchip,mcp23s08", | |
1026 | .data = (void *) MCP_TYPE_S08, | |
1027 | }, | |
1028 | { | |
1029 | .compatible = "microchip,mcp23s17", | |
1030 | .data = (void *) MCP_TYPE_S17, | |
1031 | }, | |
1032 | { | |
1033 | .compatible = "microchip,mcp23s18", | |
1034 | .data = (void *) MCP_TYPE_S18, | |
1035 | }, | |
1036 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
1037 | { | |
1038 | .compatible = "mcp,mcp23s08", | |
1039 | .data = (void *) MCP_TYPE_S08, | |
1040 | }, | |
1041 | { | |
1042 | .compatible = "mcp,mcp23s17", | |
1043 | .data = (void *) MCP_TYPE_S17, | |
1044 | }, | |
1045 | { }, | |
1046 | }; | |
1047 | MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); | |
d3da29b6 | 1048 | |
e58b9e27 DB |
1049 | static struct spi_driver mcp23s08_driver = { |
1050 | .probe = mcp23s08_probe, | |
0b7bb77f | 1051 | .id_table = mcp23s08_ids, |
e58b9e27 DB |
1052 | .driver = { |
1053 | .name = "mcp23s08", | |
1ac30db2 | 1054 | .of_match_table = mcp23s08_spi_of_match, |
e58b9e27 DB |
1055 | }, |
1056 | }; | |
1057 | ||
d62b98f3 PK |
1058 | static int __init mcp23s08_spi_init(void) |
1059 | { | |
1060 | return spi_register_driver(&mcp23s08_driver); | |
1061 | } | |
1062 | ||
1063 | static void mcp23s08_spi_exit(void) | |
1064 | { | |
1065 | spi_unregister_driver(&mcp23s08_driver); | |
1066 | } | |
1067 | ||
1068 | #else | |
1069 | ||
1070 | static int __init mcp23s08_spi_init(void) { return 0; } | |
1071 | static void mcp23s08_spi_exit(void) { } | |
1072 | ||
1073 | #endif /* CONFIG_SPI_MASTER */ | |
1074 | ||
e58b9e27 DB |
1075 | /*----------------------------------------------------------------------*/ |
1076 | ||
1077 | static int __init mcp23s08_init(void) | |
1078 | { | |
752ad5e8 PK |
1079 | int ret; |
1080 | ||
1081 | ret = mcp23s08_spi_init(); | |
1082 | if (ret) | |
1083 | goto spi_fail; | |
1084 | ||
1085 | ret = mcp23s08_i2c_init(); | |
1086 | if (ret) | |
1087 | goto i2c_fail; | |
1088 | ||
1089 | return 0; | |
1090 | ||
1091 | i2c_fail: | |
1092 | mcp23s08_spi_exit(); | |
1093 | spi_fail: | |
1094 | return ret; | |
e58b9e27 | 1095 | } |
752ad5e8 | 1096 | /* register after spi/i2c postcore initcall and before |
673c0c00 DB |
1097 | * subsys initcalls that may rely on these GPIOs |
1098 | */ | |
1099 | subsys_initcall(mcp23s08_init); | |
e58b9e27 DB |
1100 | |
1101 | static void __exit mcp23s08_exit(void) | |
1102 | { | |
d62b98f3 | 1103 | mcp23s08_spi_exit(); |
752ad5e8 | 1104 | mcp23s08_i2c_exit(); |
e58b9e27 DB |
1105 | } |
1106 | module_exit(mcp23s08_exit); | |
1107 | ||
1108 | MODULE_LICENSE("GPL"); |