Commit | Line | Data |
---|---|---|
09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d8f4494e | 2 | /* MCP23S08 SPI/I2C GPIO driver */ |
e58b9e27 | 3 | |
7b04aaaf | 4 | #include <linux/bitops.h> |
e58b9e27 DB |
5 | #include <linux/kernel.h> |
6 | #include <linux/device.h> | |
e58b9e27 | 7 | #include <linux/mutex.h> |
1ac30db2 | 8 | #include <linux/mod_devicetable.h> |
bb207ef1 | 9 | #include <linux/module.h> |
0f04a817 | 10 | #include <linux/export.h> |
1c5fb66a | 11 | #include <linux/gpio/driver.h> |
5a0e3ad6 | 12 | #include <linux/slab.h> |
0b7bb77f | 13 | #include <asm/byteorder.h> |
4e47f91b | 14 | #include <linux/interrupt.h> |
3d84fdb3 | 15 | #include <linux/regmap.h> |
82039d24 SR |
16 | #include <linux/pinctrl/pinctrl.h> |
17 | #include <linux/pinctrl/pinconf.h> | |
18 | #include <linux/pinctrl/pinconf-generic.h> | |
e58b9e27 | 19 | |
0f04a817 | 20 | #include "pinctrl-mcp23s08.h" |
e58b9e27 DB |
21 | |
22 | /* Registers are all 8 bits wide. | |
23 | * | |
24 | * The mcp23s17 has twice as many bits, and can be configured to work | |
25 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
26 | */ |
27 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
28 | #define MCP_IPOL 0x01 | |
29 | #define MCP_GPINTEN 0x02 | |
30 | #define MCP_DEFVAL 0x03 | |
31 | #define MCP_INTCON 0x04 | |
32 | #define MCP_IOCON 0x05 | |
4e47f91b | 33 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
34 | # define IOCON_SEQOP (1 << 5) |
35 | # define IOCON_HAEN (1 << 3) | |
36 | # define IOCON_ODR (1 << 2) | |
37 | # define IOCON_INTPOL (1 << 1) | |
3539699c | 38 | # define IOCON_INTCC (1) |
e58b9e27 DB |
39 | #define MCP_GPPU 0x06 |
40 | #define MCP_INTF 0x07 | |
41 | #define MCP_INTCAP 0x08 | |
42 | #define MCP_GPIO 0x09 | |
43 | #define MCP_OLAT 0x0a | |
44 | ||
8f38910b SR |
45 | static const struct reg_default mcp23x08_defaults[] = { |
46 | {.reg = MCP_IODIR, .def = 0xff}, | |
47 | {.reg = MCP_IPOL, .def = 0x00}, | |
48 | {.reg = MCP_GPINTEN, .def = 0x00}, | |
49 | {.reg = MCP_DEFVAL, .def = 0x00}, | |
50 | {.reg = MCP_INTCON, .def = 0x00}, | |
51 | {.reg = MCP_IOCON, .def = 0x00}, | |
52 | {.reg = MCP_GPPU, .def = 0x00}, | |
53 | {.reg = MCP_OLAT, .def = 0x00}, | |
54 | }; | |
55 | ||
56 | static const struct regmap_range mcp23x08_volatile_range = { | |
57 | .range_min = MCP_INTF, | |
58 | .range_max = MCP_GPIO, | |
59 | }; | |
60 | ||
61 | static const struct regmap_access_table mcp23x08_volatile_table = { | |
62 | .yes_ranges = &mcp23x08_volatile_range, | |
63 | .n_yes_ranges = 1, | |
64 | }; | |
65 | ||
66 | static const struct regmap_range mcp23x08_precious_range = { | |
67 | .range_min = MCP_GPIO, | |
68 | .range_max = MCP_GPIO, | |
69 | }; | |
70 | ||
71 | static const struct regmap_access_table mcp23x08_precious_table = { | |
72 | .yes_ranges = &mcp23x08_precious_range, | |
73 | .n_yes_ranges = 1, | |
74 | }; | |
75 | ||
0f04a817 | 76 | const struct regmap_config mcp23x08_regmap = { |
3d84fdb3 SR |
77 | .reg_bits = 8, |
78 | .val_bits = 8, | |
752ad5e8 | 79 | |
3d84fdb3 | 80 | .reg_stride = 1, |
8f38910b SR |
81 | .volatile_table = &mcp23x08_volatile_table, |
82 | .precious_table = &mcp23x08_precious_table, | |
83 | .reg_defaults = mcp23x08_defaults, | |
84 | .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), | |
85 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 | 86 | .max_register = MCP_OLAT, |
752ad5e8 | 87 | }; |
0f04a817 | 88 | EXPORT_SYMBOL_GPL(mcp23x08_regmap); |
752ad5e8 | 89 | |
b445f623 | 90 | static const struct reg_default mcp23x17_defaults[] = { |
8f38910b SR |
91 | {.reg = MCP_IODIR << 1, .def = 0xffff}, |
92 | {.reg = MCP_IPOL << 1, .def = 0x0000}, | |
93 | {.reg = MCP_GPINTEN << 1, .def = 0x0000}, | |
94 | {.reg = MCP_DEFVAL << 1, .def = 0x0000}, | |
95 | {.reg = MCP_INTCON << 1, .def = 0x0000}, | |
96 | {.reg = MCP_IOCON << 1, .def = 0x0000}, | |
97 | {.reg = MCP_GPPU << 1, .def = 0x0000}, | |
98 | {.reg = MCP_OLAT << 1, .def = 0x0000}, | |
99 | }; | |
100 | ||
b445f623 | 101 | static const struct regmap_range mcp23x17_volatile_range = { |
8f38910b SR |
102 | .range_min = MCP_INTF << 1, |
103 | .range_max = MCP_GPIO << 1, | |
104 | }; | |
105 | ||
b445f623 TP |
106 | static const struct regmap_access_table mcp23x17_volatile_table = { |
107 | .yes_ranges = &mcp23x17_volatile_range, | |
8f38910b SR |
108 | .n_yes_ranges = 1, |
109 | }; | |
110 | ||
b445f623 | 111 | static const struct regmap_range mcp23x17_precious_range = { |
b9b7fb29 | 112 | .range_min = MCP_INTCAP << 1, |
8f38910b SR |
113 | .range_max = MCP_GPIO << 1, |
114 | }; | |
115 | ||
b445f623 TP |
116 | static const struct regmap_access_table mcp23x17_precious_table = { |
117 | .yes_ranges = &mcp23x17_precious_range, | |
8f38910b SR |
118 | .n_yes_ranges = 1, |
119 | }; | |
120 | ||
0f04a817 | 121 | const struct regmap_config mcp23x17_regmap = { |
3d84fdb3 SR |
122 | .reg_bits = 8, |
123 | .val_bits = 16, | |
752ad5e8 | 124 | |
3d84fdb3 SR |
125 | .reg_stride = 2, |
126 | .max_register = MCP_OLAT << 1, | |
b445f623 TP |
127 | .volatile_table = &mcp23x17_volatile_table, |
128 | .precious_table = &mcp23x17_precious_table, | |
129 | .reg_defaults = mcp23x17_defaults, | |
130 | .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults), | |
8f38910b | 131 | .cache_type = REGCACHE_FLAT, |
3d84fdb3 SR |
132 | .val_format_endian = REGMAP_ENDIAN_LITTLE, |
133 | }; | |
0f04a817 | 134 | EXPORT_SYMBOL_GPL(mcp23x17_regmap); |
752ad5e8 | 135 | |
82039d24 SR |
136 | static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) |
137 | { | |
138 | return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); | |
139 | } | |
140 | ||
141 | static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) | |
142 | { | |
143 | return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); | |
144 | } | |
145 | ||
8f38910b SR |
146 | static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, |
147 | unsigned int mask, bool enabled) | |
82039d24 SR |
148 | { |
149 | u16 val = enabled ? 0xffff : 0x0000; | |
82039d24 SR |
150 | return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, |
151 | mask, val); | |
152 | } | |
153 | ||
8f38910b SR |
154 | static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, |
155 | unsigned int pin, bool enabled) | |
82039d24 | 156 | { |
8f38910b SR |
157 | u16 mask = BIT(pin); |
158 | return mcp_set_mask(mcp, reg, mask, enabled); | |
82039d24 SR |
159 | } |
160 | ||
161 | static const struct pinctrl_pin_desc mcp23x08_pins[] = { | |
162 | PINCTRL_PIN(0, "gpio0"), | |
163 | PINCTRL_PIN(1, "gpio1"), | |
164 | PINCTRL_PIN(2, "gpio2"), | |
165 | PINCTRL_PIN(3, "gpio3"), | |
166 | PINCTRL_PIN(4, "gpio4"), | |
167 | PINCTRL_PIN(5, "gpio5"), | |
168 | PINCTRL_PIN(6, "gpio6"), | |
169 | PINCTRL_PIN(7, "gpio7"), | |
170 | }; | |
171 | ||
172 | static const struct pinctrl_pin_desc mcp23x17_pins[] = { | |
173 | PINCTRL_PIN(0, "gpio0"), | |
174 | PINCTRL_PIN(1, "gpio1"), | |
175 | PINCTRL_PIN(2, "gpio2"), | |
176 | PINCTRL_PIN(3, "gpio3"), | |
177 | PINCTRL_PIN(4, "gpio4"), | |
178 | PINCTRL_PIN(5, "gpio5"), | |
179 | PINCTRL_PIN(6, "gpio6"), | |
180 | PINCTRL_PIN(7, "gpio7"), | |
181 | PINCTRL_PIN(8, "gpio8"), | |
182 | PINCTRL_PIN(9, "gpio9"), | |
183 | PINCTRL_PIN(10, "gpio10"), | |
184 | PINCTRL_PIN(11, "gpio11"), | |
185 | PINCTRL_PIN(12, "gpio12"), | |
186 | PINCTRL_PIN(13, "gpio13"), | |
187 | PINCTRL_PIN(14, "gpio14"), | |
188 | PINCTRL_PIN(15, "gpio15"), | |
189 | }; | |
190 | ||
191 | static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
192 | { | |
193 | return 0; | |
194 | } | |
195 | ||
196 | static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
197 | unsigned int group) | |
198 | { | |
199 | return NULL; | |
200 | } | |
201 | ||
202 | static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
203 | unsigned int group, | |
204 | const unsigned int **pins, | |
205 | unsigned int *num_pins) | |
206 | { | |
207 | return -ENOTSUPP; | |
208 | } | |
209 | ||
210 | static const struct pinctrl_ops mcp_pinctrl_ops = { | |
211 | .get_groups_count = mcp_pinctrl_get_groups_count, | |
212 | .get_group_name = mcp_pinctrl_get_group_name, | |
213 | .get_group_pins = mcp_pinctrl_get_group_pins, | |
214 | #ifdef CONFIG_OF | |
215 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
216 | .dt_free_map = pinconf_generic_dt_free_map, | |
217 | #endif | |
218 | }; | |
219 | ||
220 | static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
221 | unsigned long *config) | |
222 | { | |
223 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
224 | enum pin_config_param param = pinconf_to_config_param(*config); | |
225 | unsigned int data, status; | |
226 | int ret; | |
227 | ||
228 | switch (param) { | |
229 | case PIN_CONFIG_BIAS_PULL_UP: | |
230 | ret = mcp_read(mcp, MCP_GPPU, &data); | |
231 | if (ret < 0) | |
232 | return ret; | |
233 | status = (data & BIT(pin)) ? 1 : 0; | |
234 | break; | |
235 | default: | |
82039d24 SR |
236 | return -ENOTSUPP; |
237 | } | |
238 | ||
239 | *config = 0; | |
240 | ||
241 | return status ? 0 : -EINVAL; | |
242 | } | |
243 | ||
244 | static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
245 | unsigned long *configs, unsigned int num_configs) | |
246 | { | |
247 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
248 | enum pin_config_param param; | |
2a7893c8 | 249 | u32 arg; |
82039d24 SR |
250 | int ret = 0; |
251 | int i; | |
252 | ||
253 | for (i = 0; i < num_configs; i++) { | |
254 | param = pinconf_to_config_param(configs[i]); | |
255 | arg = pinconf_to_config_argument(configs[i]); | |
256 | ||
257 | switch (param) { | |
258 | case PIN_CONFIG_BIAS_PULL_UP: | |
82039d24 SR |
259 | ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); |
260 | break; | |
261 | default: | |
e0e31695 | 262 | dev_dbg(mcp->dev, "Invalid config param %04x\n", param); |
82039d24 SR |
263 | return -ENOTSUPP; |
264 | } | |
265 | } | |
266 | ||
267 | return ret; | |
268 | } | |
269 | ||
270 | static const struct pinconf_ops mcp_pinconf_ops = { | |
271 | .pin_config_get = mcp_pinconf_get, | |
272 | .pin_config_set = mcp_pinconf_set, | |
273 | .is_generic = true, | |
274 | }; | |
275 | ||
752ad5e8 PK |
276 | /*----------------------------------------------------------------------*/ |
277 | ||
e58b9e27 DB |
278 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) |
279 | { | |
9e03cf0b | 280 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
281 | int status; |
282 | ||
283 | mutex_lock(&mcp->lock); | |
8f38910b | 284 | status = mcp_set_bit(mcp, MCP_IODIR, offset, true); |
e58b9e27 | 285 | mutex_unlock(&mcp->lock); |
8f38910b | 286 | |
e58b9e27 DB |
287 | return status; |
288 | } | |
289 | ||
290 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
291 | { | |
9e03cf0b | 292 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
3d84fdb3 | 293 | int status, ret; |
e58b9e27 DB |
294 | |
295 | mutex_lock(&mcp->lock); | |
296 | ||
297 | /* REVISIT reading this clears any IRQ ... */ | |
3d84fdb3 SR |
298 | ret = mcp_read(mcp, MCP_GPIO, &status); |
299 | if (ret < 0) | |
e58b9e27 | 300 | status = 0; |
59861701 DM |
301 | else { |
302 | mcp->cached_gpio = status; | |
e58b9e27 | 303 | status = !!(status & (1 << offset)); |
59861701 | 304 | } |
8f38910b | 305 | |
e58b9e27 DB |
306 | mutex_unlock(&mcp->lock); |
307 | return status; | |
308 | } | |
309 | ||
8f38910b | 310 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) |
e58b9e27 | 311 | { |
8f38910b | 312 | return mcp_set_mask(mcp, MCP_OLAT, mask, value); |
e58b9e27 DB |
313 | } |
314 | ||
315 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
316 | { | |
9e03cf0b | 317 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 318 | unsigned mask = BIT(offset); |
e58b9e27 DB |
319 | |
320 | mutex_lock(&mcp->lock); | |
8f38910b | 321 | __mcp23s08_set(mcp, mask, !!value); |
e58b9e27 DB |
322 | mutex_unlock(&mcp->lock); |
323 | } | |
324 | ||
325 | static int | |
326 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
327 | { | |
9e03cf0b | 328 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 329 | unsigned mask = BIT(offset); |
e58b9e27 DB |
330 | int status; |
331 | ||
332 | mutex_lock(&mcp->lock); | |
333 | status = __mcp23s08_set(mcp, mask, value); | |
334 | if (status == 0) { | |
8f38910b | 335 | status = mcp_set_mask(mcp, MCP_IODIR, mask, false); |
e58b9e27 DB |
336 | } |
337 | mutex_unlock(&mcp->lock); | |
338 | return status; | |
339 | } | |
340 | ||
4e47f91b LP |
341 | /*----------------------------------------------------------------------*/ |
342 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
343 | { | |
344 | struct mcp23s08 *mcp = data; | |
8f38910b | 345 | int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; |
4e47f91b | 346 | unsigned int child_irq; |
2cd29f23 RM |
347 | bool intf_set, intcap_changed, gpio_bit_changed, |
348 | defval_changed, gpio_set; | |
4e47f91b LP |
349 | |
350 | mutex_lock(&mcp->lock); | |
7f6f50df ME |
351 | if (mcp_read(mcp, MCP_INTF, &intf)) |
352 | goto unlock; | |
4e47f91b | 353 | |
7f6f50df ME |
354 | if (mcp_read(mcp, MCP_INTCAP, &intcap)) |
355 | goto unlock; | |
4e47f91b | 356 | |
7f6f50df ME |
357 | if (mcp_read(mcp, MCP_INTCON, &intcon)) |
358 | goto unlock; | |
8f38910b | 359 | |
7f6f50df ME |
360 | if (mcp_read(mcp, MCP_DEFVAL, &defval)) |
361 | goto unlock; | |
2cd29f23 RM |
362 | |
363 | /* This clears the interrupt(configurable on S18) */ | |
7f6f50df ME |
364 | if (mcp_read(mcp, MCP_GPIO, &gpio)) |
365 | goto unlock; | |
366 | ||
8f38910b SR |
367 | gpio_orig = mcp->cached_gpio; |
368 | mcp->cached_gpio = gpio; | |
4e47f91b LP |
369 | mutex_unlock(&mcp->lock); |
370 | ||
8f38910b | 371 | if (intf == 0) { |
2cd29f23 RM |
372 | /* There is no interrupt pending */ |
373 | return IRQ_HANDLED; | |
374 | } | |
375 | ||
376 | dev_dbg(mcp->chip.parent, | |
377 | "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", | |
378 | intcap, intf, gpio_orig, gpio); | |
4e47f91b LP |
379 | |
380 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
2cd29f23 RM |
381 | /* We must check all of the inputs on the chip, |
382 | * otherwise we may not notice a change on >=2 pins. | |
383 | * | |
384 | * On at least the mcp23s17, INTCAP is only updated | |
385 | * one byte at a time(INTCAPA and INTCAPB are | |
386 | * not written to at the same time - only on a per-bank | |
387 | * basis). | |
388 | * | |
389 | * INTF only contains the single bit that caused the | |
390 | * interrupt per-bank. On the mcp23s17, there is | |
391 | * INTFA and INTFB. If two pins are changed on the A | |
392 | * side at the same time, INTF will only have one bit | |
393 | * set. If one pin on the A side and one pin on the B | |
394 | * side are changed at the same time, INTF will have | |
395 | * two bits set. Thus, INTF can't be the only check | |
396 | * to see if the input has changed. | |
397 | */ | |
398 | ||
8f38910b | 399 | intf_set = intf & BIT(i); |
2cd29f23 RM |
400 | if (i < 8 && intf_set) |
401 | intcap_mask = 0x00FF; | |
402 | else if (i >= 8 && intf_set) | |
403 | intcap_mask = 0xFF00; | |
404 | else | |
405 | intcap_mask = 0x00; | |
406 | ||
407 | intcap_changed = (intcap_mask & | |
8f38910b | 408 | (intcap & BIT(i))) != |
2cd29f23 | 409 | (intcap_mask & (BIT(i) & gpio_orig)); |
8f38910b | 410 | gpio_set = BIT(i) & gpio; |
2cd29f23 | 411 | gpio_bit_changed = (BIT(i) & gpio_orig) != |
8f38910b SR |
412 | (BIT(i) & gpio); |
413 | defval_changed = (BIT(i) & intcon) && | |
414 | ((BIT(i) & gpio) != | |
415 | (BIT(i) & defval)); | |
2cd29f23 RM |
416 | |
417 | if (((gpio_bit_changed || intcap_changed) && | |
418 | (BIT(i) & mcp->irq_rise) && gpio_set) || | |
419 | ((gpio_bit_changed || intcap_changed) && | |
420 | (BIT(i) & mcp->irq_fall) && !gpio_set) || | |
421 | defval_changed) { | |
f0fbe7bc | 422 | child_irq = irq_find_mapping(mcp->chip.irq.domain, i); |
4e47f91b LP |
423 | handle_nested_irq(child_irq); |
424 | } | |
425 | } | |
426 | ||
427 | return IRQ_HANDLED; | |
7f6f50df ME |
428 | |
429 | unlock: | |
430 | mutex_unlock(&mcp->lock); | |
431 | return IRQ_HANDLED; | |
4e47f91b LP |
432 | } |
433 | ||
4e47f91b LP |
434 | static void mcp23s08_irq_mask(struct irq_data *data) |
435 | { | |
dad3d272 PR |
436 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
437 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
438 | unsigned int pos = data->hwirq; |
439 | ||
8f38910b | 440 | mcp_set_bit(mcp, MCP_GPINTEN, pos, false); |
4e47f91b LP |
441 | } |
442 | ||
443 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
444 | { | |
dad3d272 PR |
445 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
446 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
447 | unsigned int pos = data->hwirq; |
448 | ||
8f38910b | 449 | mcp_set_bit(mcp, MCP_GPINTEN, pos, true); |
4e47f91b LP |
450 | } |
451 | ||
452 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
453 | { | |
dad3d272 PR |
454 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
455 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 456 | unsigned int pos = data->hwirq; |
4e47f91b LP |
457 | |
458 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
8f38910b | 459 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
460 | mcp->irq_rise |= BIT(pos); |
461 | mcp->irq_fall |= BIT(pos); | |
462 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
8f38910b | 463 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
464 | mcp->irq_rise |= BIT(pos); |
465 | mcp->irq_fall &= ~BIT(pos); | |
466 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
8f38910b | 467 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
468 | mcp->irq_rise &= ~BIT(pos); |
469 | mcp->irq_fall |= BIT(pos); | |
16fe1ad2 | 470 | } else if (type & IRQ_TYPE_LEVEL_HIGH) { |
8f38910b SR |
471 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
472 | mcp_set_bit(mcp, MCP_DEFVAL, pos, false); | |
16fe1ad2 | 473 | } else if (type & IRQ_TYPE_LEVEL_LOW) { |
8f38910b SR |
474 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
475 | mcp_set_bit(mcp, MCP_DEFVAL, pos, true); | |
4e47f91b LP |
476 | } else |
477 | return -EINVAL; | |
478 | ||
88af89b5 | 479 | return 0; |
4e47f91b LP |
480 | } |
481 | ||
482 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
483 | { | |
dad3d272 PR |
484 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
485 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 486 | |
8f38910b SR |
487 | mutex_lock(&mcp->lock); |
488 | regcache_cache_only(mcp->regmap, true); | |
4e47f91b LP |
489 | } |
490 | ||
491 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
492 | { | |
dad3d272 PR |
493 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
494 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 495 | |
8f38910b SR |
496 | regcache_cache_only(mcp->regmap, false); |
497 | regcache_sync(mcp->regmap); | |
498 | ||
4e47f91b | 499 | mutex_unlock(&mcp->lock); |
4e47f91b LP |
500 | } |
501 | ||
4e47f91b LP |
502 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) |
503 | { | |
504 | struct gpio_chip *chip = &mcp->chip; | |
dad3d272 | 505 | int err; |
a4e63554 | 506 | unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; |
4e47f91b | 507 | |
a4e63554 AS |
508 | if (mcp->irq_active_high) |
509 | irqflags |= IRQF_TRIGGER_HIGH; | |
510 | else | |
511 | irqflags |= IRQF_TRIGGER_LOW; | |
512 | ||
58383c78 LW |
513 | err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, |
514 | mcp23s08_irq, | |
515 | irqflags, dev_name(chip->parent), mcp); | |
4e47f91b | 516 | if (err != 0) { |
58383c78 | 517 | dev_err(chip->parent, "unable to request IRQ#%d: %d\n", |
4e47f91b LP |
518 | mcp->irq, err); |
519 | return err; | |
520 | } | |
521 | ||
f259f896 MF |
522 | return 0; |
523 | } | |
524 | ||
e58b9e27 DB |
525 | /*----------------------------------------------------------------------*/ |
526 | ||
0f04a817 AS |
527 | int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
528 | unsigned int addr, unsigned int type, unsigned int base) | |
e58b9e27 | 529 | { |
3d84fdb3 | 530 | int status, ret; |
4e47f91b | 531 | bool mirror = false; |
fa2b7fae | 532 | bool open_drain = false; |
e58b9e27 | 533 | |
e58b9e27 DB |
534 | mutex_init(&mcp->lock); |
535 | ||
3d84fdb3 | 536 | mcp->dev = dev; |
d62b98f3 | 537 | mcp->addr = addr; |
84d02e78 | 538 | |
a4e63554 | 539 | mcp->irq_active_high = false; |
84d02e78 AS |
540 | mcp->irq_chip.name = dev_name(dev); |
541 | mcp->irq_chip.irq_mask = mcp23s08_irq_mask; | |
542 | mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; | |
543 | mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; | |
544 | mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; | |
545 | mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; | |
e58b9e27 | 546 | |
e58b9e27 DB |
547 | mcp->chip.direction_input = mcp23s08_direction_input; |
548 | mcp->chip.get = mcp23s08_get; | |
549 | mcp->chip.direction_output = mcp23s08_direction_output; | |
550 | mcp->chip.set = mcp23s08_set; | |
60f749f8 | 551 | #ifdef CONFIG_OF_GPIO |
97ddb1c8 LP |
552 | mcp->chip.of_gpio_n_cells = 2; |
553 | mcp->chip.of_node = dev->of_node; | |
554 | #endif | |
e58b9e27 | 555 | |
5b1a7e80 | 556 | mcp->chip.base = base; |
9fb1f39e | 557 | mcp->chip.can_sleep = true; |
58383c78 | 558 | mcp->chip.parent = dev; |
d72cbed0 | 559 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 560 | |
8f1cc3b1 DB |
561 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
562 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
563 | */ | |
4e47f91b | 564 | |
3d84fdb3 SR |
565 | ret = mcp_read(mcp, MCP_IOCON, &status); |
566 | if (ret < 0) | |
ebc25991 | 567 | return dev_err_probe(dev, ret, "can't identify chip %d\n", addr); |
4e47f91b | 568 | |
5b1a7e80 SR |
569 | mcp->irq_controller = |
570 | device_property_read_bool(dev, "interrupt-controller"); | |
a4e63554 | 571 | if (mcp->irq && mcp->irq_controller) { |
170680ab | 572 | mcp->irq_active_high = |
5b1a7e80 | 573 | device_property_read_bool(dev, |
170680ab | 574 | "microchip,irq-active-high"); |
4e47f91b | 575 | |
5b1a7e80 | 576 | mirror = device_property_read_bool(dev, "microchip,irq-mirror"); |
fa2b7fae | 577 | open_drain = device_property_read_bool(dev, "drive-open-drain"); |
a4e63554 AS |
578 | } |
579 | ||
580 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || | |
fa2b7fae | 581 | mcp->irq_active_high || open_drain) { |
0b7bb77f PK |
582 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
583 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
584 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
a4e63554 AS |
585 | if (mcp->irq_active_high) |
586 | status |= IOCON_INTPOL | (IOCON_INTPOL << 8); | |
587 | else | |
588 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); | |
589 | ||
4e47f91b LP |
590 | if (mirror) |
591 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
592 | ||
fa2b7fae PR |
593 | if (open_drain) |
594 | status |= IOCON_ODR | (IOCON_ODR << 8); | |
595 | ||
ff0f2ce7 | 596 | if (type == MCP_TYPE_S18 || type == MCP_TYPE_018) |
3539699c PR |
597 | status |= IOCON_INTCC | (IOCON_INTCC << 8); |
598 | ||
3d84fdb3 SR |
599 | ret = mcp_write(mcp, MCP_IOCON, status); |
600 | if (ret < 0) | |
ebc25991 | 601 | return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr); |
e58b9e27 DB |
602 | } |
603 | ||
4e47f91b | 604 | if (mcp->irq && mcp->irq_controller) { |
57597e15 LW |
605 | struct gpio_irq_chip *girq = &mcp->chip.irq; |
606 | ||
607 | girq->chip = &mcp->irq_chip; | |
608 | /* This will let us handle the parent IRQ in the driver */ | |
609 | girq->parent_handler = NULL; | |
610 | girq->num_parents = 0; | |
611 | girq->parents = NULL; | |
612 | girq->default_type = IRQ_TYPE_NONE; | |
613 | girq->handler = handle_simple_irq; | |
614 | girq->threaded = true; | |
4e47f91b | 615 | } |
82039d24 | 616 | |
57597e15 LW |
617 | ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); |
618 | if (ret < 0) | |
ebc25991 | 619 | return dev_err_probe(dev, ret, "can't add GPIO chip\n"); |
57597e15 | 620 | |
82039d24 SR |
621 | mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; |
622 | mcp->pinctrl_desc.confops = &mcp_pinconf_ops; | |
623 | mcp->pinctrl_desc.npins = mcp->chip.ngpio; | |
624 | if (mcp->pinctrl_desc.npins == 8) | |
625 | mcp->pinctrl_desc.pins = mcp23x08_pins; | |
626 | else if (mcp->pinctrl_desc.npins == 16) | |
627 | mcp->pinctrl_desc.pins = mcp23x17_pins; | |
628 | mcp->pinctrl_desc.owner = THIS_MODULE; | |
629 | ||
630 | mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); | |
ebc25991 AS |
631 | if (IS_ERR(mcp->pctldev)) |
632 | return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n"); | |
82039d24 | 633 | |
ebc25991 | 634 | if (mcp->irq) { |
f259f896 | 635 | ret = mcp23s08_irq_setup(mcp); |
ebc25991 AS |
636 | if (ret) |
637 | return dev_err_probe(dev, ret, "can't setup IRQ\n"); | |
638 | } | |
f259f896 | 639 | |
ebc25991 | 640 | return 0; |
8f1cc3b1 | 641 | } |
0f04a817 | 642 | EXPORT_SYMBOL_GPL(mcp23s08_probe_one); |
ebc25991 | 643 | |
7045e673 | 644 | MODULE_LICENSE("GPL"); |