Commit | Line | Data |
---|---|---|
d8f4494e | 1 | /* MCP23S08 SPI/I2C GPIO driver */ |
e58b9e27 DB |
2 | |
3 | #include <linux/kernel.h> | |
4 | #include <linux/device.h> | |
e58b9e27 | 5 | #include <linux/mutex.h> |
bb207ef1 | 6 | #include <linux/module.h> |
1c5fb66a | 7 | #include <linux/gpio/driver.h> |
752ad5e8 | 8 | #include <linux/i2c.h> |
e58b9e27 DB |
9 | #include <linux/spi/spi.h> |
10 | #include <linux/spi/mcp23s08.h> | |
5a0e3ad6 | 11 | #include <linux/slab.h> |
0b7bb77f | 12 | #include <asm/byteorder.h> |
4e47f91b | 13 | #include <linux/interrupt.h> |
97ddb1c8 | 14 | #include <linux/of_device.h> |
3d84fdb3 | 15 | #include <linux/regmap.h> |
82039d24 SR |
16 | #include <linux/pinctrl/pinctrl.h> |
17 | #include <linux/pinctrl/pinconf.h> | |
18 | #include <linux/pinctrl/pinconf-generic.h> | |
e58b9e27 | 19 | |
d8f4494e | 20 | /* |
0b7bb77f PK |
21 | * MCP types supported by driver |
22 | */ | |
23 | #define MCP_TYPE_S08 0 | |
24 | #define MCP_TYPE_S17 1 | |
752ad5e8 PK |
25 | #define MCP_TYPE_008 2 |
26 | #define MCP_TYPE_017 3 | |
28c5a41e | 27 | #define MCP_TYPE_S18 4 |
ff0f2ce7 | 28 | #define MCP_TYPE_018 5 |
e58b9e27 | 29 | |
ce9bd0a0 SR |
30 | #define MCP_MAX_DEV_PER_CS 8 |
31 | ||
e58b9e27 DB |
32 | /* Registers are all 8 bits wide. |
33 | * | |
34 | * The mcp23s17 has twice as many bits, and can be configured to work | |
35 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
36 | */ |
37 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
38 | #define MCP_IPOL 0x01 | |
39 | #define MCP_GPINTEN 0x02 | |
40 | #define MCP_DEFVAL 0x03 | |
41 | #define MCP_INTCON 0x04 | |
42 | #define MCP_IOCON 0x05 | |
4e47f91b | 43 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
44 | # define IOCON_SEQOP (1 << 5) |
45 | # define IOCON_HAEN (1 << 3) | |
46 | # define IOCON_ODR (1 << 2) | |
47 | # define IOCON_INTPOL (1 << 1) | |
3539699c | 48 | # define IOCON_INTCC (1) |
e58b9e27 DB |
49 | #define MCP_GPPU 0x06 |
50 | #define MCP_INTF 0x07 | |
51 | #define MCP_INTCAP 0x08 | |
52 | #define MCP_GPIO 0x09 | |
53 | #define MCP_OLAT 0x0a | |
54 | ||
0b7bb77f PK |
55 | struct mcp23s08; |
56 | ||
e58b9e27 | 57 | struct mcp23s08 { |
e58b9e27 | 58 | u8 addr; |
a4e63554 | 59 | bool irq_active_high; |
3d84fdb3 | 60 | bool reg_shift; |
e58b9e27 | 61 | |
4e47f91b LP |
62 | u16 irq_rise; |
63 | u16 irq_fall; | |
64 | int irq; | |
65 | bool irq_controller; | |
8f38910b SR |
66 | int cached_gpio; |
67 | /* lock protects regmap access with bypass/cache flags */ | |
e58b9e27 | 68 | struct mutex lock; |
e58b9e27 DB |
69 | |
70 | struct gpio_chip chip; | |
19ab5ca9 | 71 | struct irq_chip irq_chip; |
e58b9e27 | 72 | |
3d84fdb3 SR |
73 | struct regmap *regmap; |
74 | struct device *dev; | |
82039d24 SR |
75 | |
76 | struct pinctrl_dev *pctldev; | |
77 | struct pinctrl_desc pinctrl_desc; | |
8f1cc3b1 DB |
78 | }; |
79 | ||
8f38910b SR |
80 | static const struct reg_default mcp23x08_defaults[] = { |
81 | {.reg = MCP_IODIR, .def = 0xff}, | |
82 | {.reg = MCP_IPOL, .def = 0x00}, | |
83 | {.reg = MCP_GPINTEN, .def = 0x00}, | |
84 | {.reg = MCP_DEFVAL, .def = 0x00}, | |
85 | {.reg = MCP_INTCON, .def = 0x00}, | |
86 | {.reg = MCP_IOCON, .def = 0x00}, | |
87 | {.reg = MCP_GPPU, .def = 0x00}, | |
88 | {.reg = MCP_OLAT, .def = 0x00}, | |
89 | }; | |
90 | ||
91 | static const struct regmap_range mcp23x08_volatile_range = { | |
92 | .range_min = MCP_INTF, | |
93 | .range_max = MCP_GPIO, | |
94 | }; | |
95 | ||
96 | static const struct regmap_access_table mcp23x08_volatile_table = { | |
97 | .yes_ranges = &mcp23x08_volatile_range, | |
98 | .n_yes_ranges = 1, | |
99 | }; | |
100 | ||
101 | static const struct regmap_range mcp23x08_precious_range = { | |
102 | .range_min = MCP_GPIO, | |
103 | .range_max = MCP_GPIO, | |
104 | }; | |
105 | ||
106 | static const struct regmap_access_table mcp23x08_precious_table = { | |
107 | .yes_ranges = &mcp23x08_precious_range, | |
108 | .n_yes_ranges = 1, | |
109 | }; | |
110 | ||
3d84fdb3 SR |
111 | static const struct regmap_config mcp23x08_regmap = { |
112 | .reg_bits = 8, | |
113 | .val_bits = 8, | |
752ad5e8 | 114 | |
3d84fdb3 | 115 | .reg_stride = 1, |
8f38910b SR |
116 | .volatile_table = &mcp23x08_volatile_table, |
117 | .precious_table = &mcp23x08_precious_table, | |
118 | .reg_defaults = mcp23x08_defaults, | |
119 | .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), | |
120 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 | 121 | .max_register = MCP_OLAT, |
752ad5e8 PK |
122 | }; |
123 | ||
8f38910b SR |
124 | static const struct reg_default mcp23x16_defaults[] = { |
125 | {.reg = MCP_IODIR << 1, .def = 0xffff}, | |
126 | {.reg = MCP_IPOL << 1, .def = 0x0000}, | |
127 | {.reg = MCP_GPINTEN << 1, .def = 0x0000}, | |
128 | {.reg = MCP_DEFVAL << 1, .def = 0x0000}, | |
129 | {.reg = MCP_INTCON << 1, .def = 0x0000}, | |
130 | {.reg = MCP_IOCON << 1, .def = 0x0000}, | |
131 | {.reg = MCP_GPPU << 1, .def = 0x0000}, | |
132 | {.reg = MCP_OLAT << 1, .def = 0x0000}, | |
133 | }; | |
134 | ||
135 | static const struct regmap_range mcp23x16_volatile_range = { | |
136 | .range_min = MCP_INTF << 1, | |
137 | .range_max = MCP_GPIO << 1, | |
138 | }; | |
139 | ||
140 | static const struct regmap_access_table mcp23x16_volatile_table = { | |
141 | .yes_ranges = &mcp23x16_volatile_range, | |
142 | .n_yes_ranges = 1, | |
143 | }; | |
144 | ||
145 | static const struct regmap_range mcp23x16_precious_range = { | |
146 | .range_min = MCP_GPIO << 1, | |
147 | .range_max = MCP_GPIO << 1, | |
148 | }; | |
149 | ||
150 | static const struct regmap_access_table mcp23x16_precious_table = { | |
151 | .yes_ranges = &mcp23x16_precious_range, | |
152 | .n_yes_ranges = 1, | |
153 | }; | |
154 | ||
3d84fdb3 SR |
155 | static const struct regmap_config mcp23x17_regmap = { |
156 | .reg_bits = 8, | |
157 | .val_bits = 16, | |
752ad5e8 | 158 | |
3d84fdb3 SR |
159 | .reg_stride = 2, |
160 | .max_register = MCP_OLAT << 1, | |
8f38910b SR |
161 | .volatile_table = &mcp23x16_volatile_table, |
162 | .precious_table = &mcp23x16_precious_table, | |
163 | .reg_defaults = mcp23x16_defaults, | |
164 | .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), | |
165 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 SR |
166 | .val_format_endian = REGMAP_ENDIAN_LITTLE, |
167 | }; | |
752ad5e8 | 168 | |
82039d24 SR |
169 | static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) |
170 | { | |
171 | return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); | |
172 | } | |
173 | ||
174 | static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) | |
175 | { | |
176 | return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); | |
177 | } | |
178 | ||
8f38910b SR |
179 | static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, |
180 | unsigned int mask, bool enabled) | |
82039d24 SR |
181 | { |
182 | u16 val = enabled ? 0xffff : 0x0000; | |
82039d24 SR |
183 | return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, |
184 | mask, val); | |
185 | } | |
186 | ||
8f38910b SR |
187 | static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, |
188 | unsigned int pin, bool enabled) | |
82039d24 | 189 | { |
8f38910b SR |
190 | u16 mask = BIT(pin); |
191 | return mcp_set_mask(mcp, reg, mask, enabled); | |
82039d24 SR |
192 | } |
193 | ||
194 | static const struct pinctrl_pin_desc mcp23x08_pins[] = { | |
195 | PINCTRL_PIN(0, "gpio0"), | |
196 | PINCTRL_PIN(1, "gpio1"), | |
197 | PINCTRL_PIN(2, "gpio2"), | |
198 | PINCTRL_PIN(3, "gpio3"), | |
199 | PINCTRL_PIN(4, "gpio4"), | |
200 | PINCTRL_PIN(5, "gpio5"), | |
201 | PINCTRL_PIN(6, "gpio6"), | |
202 | PINCTRL_PIN(7, "gpio7"), | |
203 | }; | |
204 | ||
205 | static const struct pinctrl_pin_desc mcp23x17_pins[] = { | |
206 | PINCTRL_PIN(0, "gpio0"), | |
207 | PINCTRL_PIN(1, "gpio1"), | |
208 | PINCTRL_PIN(2, "gpio2"), | |
209 | PINCTRL_PIN(3, "gpio3"), | |
210 | PINCTRL_PIN(4, "gpio4"), | |
211 | PINCTRL_PIN(5, "gpio5"), | |
212 | PINCTRL_PIN(6, "gpio6"), | |
213 | PINCTRL_PIN(7, "gpio7"), | |
214 | PINCTRL_PIN(8, "gpio8"), | |
215 | PINCTRL_PIN(9, "gpio9"), | |
216 | PINCTRL_PIN(10, "gpio10"), | |
217 | PINCTRL_PIN(11, "gpio11"), | |
218 | PINCTRL_PIN(12, "gpio12"), | |
219 | PINCTRL_PIN(13, "gpio13"), | |
220 | PINCTRL_PIN(14, "gpio14"), | |
221 | PINCTRL_PIN(15, "gpio15"), | |
222 | }; | |
223 | ||
224 | static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
225 | { | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
230 | unsigned int group) | |
231 | { | |
232 | return NULL; | |
233 | } | |
234 | ||
235 | static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
236 | unsigned int group, | |
237 | const unsigned int **pins, | |
238 | unsigned int *num_pins) | |
239 | { | |
240 | return -ENOTSUPP; | |
241 | } | |
242 | ||
243 | static const struct pinctrl_ops mcp_pinctrl_ops = { | |
244 | .get_groups_count = mcp_pinctrl_get_groups_count, | |
245 | .get_group_name = mcp_pinctrl_get_group_name, | |
246 | .get_group_pins = mcp_pinctrl_get_group_pins, | |
247 | #ifdef CONFIG_OF | |
248 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
249 | .dt_free_map = pinconf_generic_dt_free_map, | |
250 | #endif | |
251 | }; | |
252 | ||
253 | static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
254 | unsigned long *config) | |
255 | { | |
256 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
257 | enum pin_config_param param = pinconf_to_config_param(*config); | |
258 | unsigned int data, status; | |
259 | int ret; | |
260 | ||
261 | switch (param) { | |
262 | case PIN_CONFIG_BIAS_PULL_UP: | |
263 | ret = mcp_read(mcp, MCP_GPPU, &data); | |
264 | if (ret < 0) | |
265 | return ret; | |
266 | status = (data & BIT(pin)) ? 1 : 0; | |
267 | break; | |
268 | default: | |
269 | dev_err(mcp->dev, "Invalid config param %04x\n", param); | |
270 | return -ENOTSUPP; | |
271 | } | |
272 | ||
273 | *config = 0; | |
274 | ||
275 | return status ? 0 : -EINVAL; | |
276 | } | |
277 | ||
278 | static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
279 | unsigned long *configs, unsigned int num_configs) | |
280 | { | |
281 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
282 | enum pin_config_param param; | |
2a7893c8 | 283 | u32 arg; |
82039d24 SR |
284 | int ret = 0; |
285 | int i; | |
286 | ||
287 | for (i = 0; i < num_configs; i++) { | |
288 | param = pinconf_to_config_param(configs[i]); | |
289 | arg = pinconf_to_config_argument(configs[i]); | |
290 | ||
291 | switch (param) { | |
292 | case PIN_CONFIG_BIAS_PULL_UP: | |
82039d24 SR |
293 | ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); |
294 | break; | |
295 | default: | |
296 | dev_err(mcp->dev, "Invalid config param %04x\n", param); | |
297 | return -ENOTSUPP; | |
298 | } | |
299 | } | |
300 | ||
301 | return ret; | |
302 | } | |
303 | ||
304 | static const struct pinconf_ops mcp_pinconf_ops = { | |
305 | .pin_config_get = mcp_pinconf_get, | |
306 | .pin_config_set = mcp_pinconf_set, | |
307 | .is_generic = true, | |
308 | }; | |
309 | ||
752ad5e8 PK |
310 | /*----------------------------------------------------------------------*/ |
311 | ||
d62b98f3 PK |
312 | #ifdef CONFIG_SPI_MASTER |
313 | ||
3d84fdb3 | 314 | static int mcp23sxx_spi_write(void *context, const void *data, size_t count) |
e58b9e27 | 315 | { |
3d84fdb3 SR |
316 | struct mcp23s08 *mcp = context; |
317 | struct spi_device *spi = to_spi_device(mcp->dev); | |
318 | struct spi_message m; | |
319 | struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
320 | { .tx_buf = data, .len = count, }, }; | |
e58b9e27 | 321 | |
3d84fdb3 SR |
322 | spi_message_init(&m); |
323 | spi_message_add_tail(&t[0], &m); | |
324 | spi_message_add_tail(&t[1], &m); | |
325 | ||
326 | return spi_sync(spi, &m); | |
e58b9e27 DB |
327 | } |
328 | ||
3d84fdb3 SR |
329 | static int mcp23sxx_spi_gather_write(void *context, |
330 | const void *reg, size_t reg_size, | |
331 | const void *val, size_t val_size) | |
e58b9e27 | 332 | { |
3d84fdb3 SR |
333 | struct mcp23s08 *mcp = context; |
334 | struct spi_device *spi = to_spi_device(mcp->dev); | |
335 | struct spi_message m; | |
336 | struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
337 | { .tx_buf = reg, .len = reg_size, }, | |
338 | { .tx_buf = val, .len = val_size, }, }; | |
339 | ||
340 | spi_message_init(&m); | |
341 | spi_message_add_tail(&t[0], &m); | |
342 | spi_message_add_tail(&t[1], &m); | |
343 | spi_message_add_tail(&t[2], &m); | |
344 | ||
345 | return spi_sync(spi, &m); | |
e58b9e27 DB |
346 | } |
347 | ||
3d84fdb3 SR |
348 | static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, |
349 | void *val, size_t val_size) | |
e58b9e27 | 350 | { |
3d84fdb3 SR |
351 | struct mcp23s08 *mcp = context; |
352 | struct spi_device *spi = to_spi_device(mcp->dev); | |
353 | u8 tx[2]; | |
e58b9e27 | 354 | |
3d84fdb3 | 355 | if (reg_size != 1) |
e58b9e27 | 356 | return -EINVAL; |
3d84fdb3 | 357 | |
e58b9e27 | 358 | tx[0] = mcp->addr | 0x01; |
3d84fdb3 | 359 | tx[1] = *((u8 *) reg); |
0b7bb77f | 360 | |
3d84fdb3 | 361 | return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); |
0b7bb77f PK |
362 | } |
363 | ||
3d84fdb3 SR |
364 | static const struct regmap_bus mcp23sxx_spi_regmap = { |
365 | .write = mcp23sxx_spi_write, | |
366 | .gather_write = mcp23sxx_spi_gather_write, | |
367 | .read = mcp23sxx_spi_read, | |
368 | }; | |
0b7bb77f | 369 | |
3d84fdb3 | 370 | #endif /* CONFIG_SPI_MASTER */ |
0b7bb77f | 371 | |
3d84fdb3 | 372 | /*----------------------------------------------------------------------*/ |
0b7bb77f | 373 | |
3d84fdb3 SR |
374 | /* A given spi_device can represent up to eight mcp23sxx chips |
375 | * sharing the same chipselect but using different addresses | |
376 | * (e.g. chips #0 and #3 might be populated, but not #1 or $2). | |
377 | * Driver data holds all the per-chip data. | |
378 | */ | |
379 | struct mcp23s08_driver_data { | |
380 | unsigned ngpio; | |
381 | struct mcp23s08 *mcp[8]; | |
382 | struct mcp23s08 chip[]; | |
0b7bb77f PK |
383 | }; |
384 | ||
e58b9e27 DB |
385 | |
386 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) | |
387 | { | |
9e03cf0b | 388 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
389 | int status; |
390 | ||
391 | mutex_lock(&mcp->lock); | |
8f38910b | 392 | status = mcp_set_bit(mcp, MCP_IODIR, offset, true); |
e58b9e27 | 393 | mutex_unlock(&mcp->lock); |
8f38910b | 394 | |
e58b9e27 DB |
395 | return status; |
396 | } | |
397 | ||
398 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
399 | { | |
9e03cf0b | 400 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
3d84fdb3 | 401 | int status, ret; |
e58b9e27 DB |
402 | |
403 | mutex_lock(&mcp->lock); | |
404 | ||
405 | /* REVISIT reading this clears any IRQ ... */ | |
3d84fdb3 SR |
406 | ret = mcp_read(mcp, MCP_GPIO, &status); |
407 | if (ret < 0) | |
e58b9e27 | 408 | status = 0; |
59861701 DM |
409 | else { |
410 | mcp->cached_gpio = status; | |
e58b9e27 | 411 | status = !!(status & (1 << offset)); |
59861701 | 412 | } |
8f38910b | 413 | |
e58b9e27 DB |
414 | mutex_unlock(&mcp->lock); |
415 | return status; | |
416 | } | |
417 | ||
8f38910b | 418 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) |
e58b9e27 | 419 | { |
8f38910b | 420 | return mcp_set_mask(mcp, MCP_OLAT, mask, value); |
e58b9e27 DB |
421 | } |
422 | ||
423 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
424 | { | |
9e03cf0b | 425 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 426 | unsigned mask = BIT(offset); |
e58b9e27 DB |
427 | |
428 | mutex_lock(&mcp->lock); | |
8f38910b | 429 | __mcp23s08_set(mcp, mask, !!value); |
e58b9e27 DB |
430 | mutex_unlock(&mcp->lock); |
431 | } | |
432 | ||
433 | static int | |
434 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
435 | { | |
9e03cf0b | 436 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 437 | unsigned mask = BIT(offset); |
e58b9e27 DB |
438 | int status; |
439 | ||
440 | mutex_lock(&mcp->lock); | |
441 | status = __mcp23s08_set(mcp, mask, value); | |
442 | if (status == 0) { | |
8f38910b | 443 | status = mcp_set_mask(mcp, MCP_IODIR, mask, false); |
e58b9e27 DB |
444 | } |
445 | mutex_unlock(&mcp->lock); | |
446 | return status; | |
447 | } | |
448 | ||
4e47f91b LP |
449 | /*----------------------------------------------------------------------*/ |
450 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
451 | { | |
452 | struct mcp23s08 *mcp = data; | |
8f38910b | 453 | int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; |
4e47f91b | 454 | unsigned int child_irq; |
2cd29f23 RM |
455 | bool intf_set, intcap_changed, gpio_bit_changed, |
456 | defval_changed, gpio_set; | |
4e47f91b LP |
457 | |
458 | mutex_lock(&mcp->lock); | |
7f6f50df ME |
459 | if (mcp_read(mcp, MCP_INTF, &intf)) |
460 | goto unlock; | |
4e47f91b | 461 | |
7f6f50df ME |
462 | if (mcp_read(mcp, MCP_INTCAP, &intcap)) |
463 | goto unlock; | |
4e47f91b | 464 | |
7f6f50df ME |
465 | if (mcp_read(mcp, MCP_INTCON, &intcon)) |
466 | goto unlock; | |
8f38910b | 467 | |
7f6f50df ME |
468 | if (mcp_read(mcp, MCP_DEFVAL, &defval)) |
469 | goto unlock; | |
2cd29f23 RM |
470 | |
471 | /* This clears the interrupt(configurable on S18) */ | |
7f6f50df ME |
472 | if (mcp_read(mcp, MCP_GPIO, &gpio)) |
473 | goto unlock; | |
474 | ||
8f38910b SR |
475 | gpio_orig = mcp->cached_gpio; |
476 | mcp->cached_gpio = gpio; | |
4e47f91b LP |
477 | mutex_unlock(&mcp->lock); |
478 | ||
8f38910b | 479 | if (intf == 0) { |
2cd29f23 RM |
480 | /* There is no interrupt pending */ |
481 | return IRQ_HANDLED; | |
482 | } | |
483 | ||
484 | dev_dbg(mcp->chip.parent, | |
485 | "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", | |
486 | intcap, intf, gpio_orig, gpio); | |
4e47f91b LP |
487 | |
488 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
2cd29f23 RM |
489 | /* We must check all of the inputs on the chip, |
490 | * otherwise we may not notice a change on >=2 pins. | |
491 | * | |
492 | * On at least the mcp23s17, INTCAP is only updated | |
493 | * one byte at a time(INTCAPA and INTCAPB are | |
494 | * not written to at the same time - only on a per-bank | |
495 | * basis). | |
496 | * | |
497 | * INTF only contains the single bit that caused the | |
498 | * interrupt per-bank. On the mcp23s17, there is | |
499 | * INTFA and INTFB. If two pins are changed on the A | |
500 | * side at the same time, INTF will only have one bit | |
501 | * set. If one pin on the A side and one pin on the B | |
502 | * side are changed at the same time, INTF will have | |
503 | * two bits set. Thus, INTF can't be the only check | |
504 | * to see if the input has changed. | |
505 | */ | |
506 | ||
8f38910b | 507 | intf_set = intf & BIT(i); |
2cd29f23 RM |
508 | if (i < 8 && intf_set) |
509 | intcap_mask = 0x00FF; | |
510 | else if (i >= 8 && intf_set) | |
511 | intcap_mask = 0xFF00; | |
512 | else | |
513 | intcap_mask = 0x00; | |
514 | ||
515 | intcap_changed = (intcap_mask & | |
8f38910b | 516 | (intcap & BIT(i))) != |
2cd29f23 | 517 | (intcap_mask & (BIT(i) & gpio_orig)); |
8f38910b | 518 | gpio_set = BIT(i) & gpio; |
2cd29f23 | 519 | gpio_bit_changed = (BIT(i) & gpio_orig) != |
8f38910b SR |
520 | (BIT(i) & gpio); |
521 | defval_changed = (BIT(i) & intcon) && | |
522 | ((BIT(i) & gpio) != | |
523 | (BIT(i) & defval)); | |
2cd29f23 RM |
524 | |
525 | if (((gpio_bit_changed || intcap_changed) && | |
526 | (BIT(i) & mcp->irq_rise) && gpio_set) || | |
527 | ((gpio_bit_changed || intcap_changed) && | |
528 | (BIT(i) & mcp->irq_fall) && !gpio_set) || | |
529 | defval_changed) { | |
f0fbe7bc | 530 | child_irq = irq_find_mapping(mcp->chip.irq.domain, i); |
4e47f91b LP |
531 | handle_nested_irq(child_irq); |
532 | } | |
533 | } | |
534 | ||
535 | return IRQ_HANDLED; | |
7f6f50df ME |
536 | |
537 | unlock: | |
538 | mutex_unlock(&mcp->lock); | |
539 | return IRQ_HANDLED; | |
4e47f91b LP |
540 | } |
541 | ||
4e47f91b LP |
542 | static void mcp23s08_irq_mask(struct irq_data *data) |
543 | { | |
dad3d272 PR |
544 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
545 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
546 | unsigned int pos = data->hwirq; |
547 | ||
8f38910b | 548 | mcp_set_bit(mcp, MCP_GPINTEN, pos, false); |
4e47f91b LP |
549 | } |
550 | ||
551 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
552 | { | |
dad3d272 PR |
553 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
554 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
555 | unsigned int pos = data->hwirq; |
556 | ||
8f38910b | 557 | mcp_set_bit(mcp, MCP_GPINTEN, pos, true); |
4e47f91b LP |
558 | } |
559 | ||
560 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
561 | { | |
dad3d272 PR |
562 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
563 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
564 | unsigned int pos = data->hwirq; |
565 | int status = 0; | |
566 | ||
567 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
8f38910b | 568 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
569 | mcp->irq_rise |= BIT(pos); |
570 | mcp->irq_fall |= BIT(pos); | |
571 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
8f38910b | 572 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
573 | mcp->irq_rise |= BIT(pos); |
574 | mcp->irq_fall &= ~BIT(pos); | |
575 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
8f38910b | 576 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
577 | mcp->irq_rise &= ~BIT(pos); |
578 | mcp->irq_fall |= BIT(pos); | |
16fe1ad2 | 579 | } else if (type & IRQ_TYPE_LEVEL_HIGH) { |
8f38910b SR |
580 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
581 | mcp_set_bit(mcp, MCP_DEFVAL, pos, false); | |
16fe1ad2 | 582 | } else if (type & IRQ_TYPE_LEVEL_LOW) { |
8f38910b SR |
583 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
584 | mcp_set_bit(mcp, MCP_DEFVAL, pos, true); | |
4e47f91b LP |
585 | } else |
586 | return -EINVAL; | |
587 | ||
588 | return status; | |
589 | } | |
590 | ||
591 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
592 | { | |
dad3d272 PR |
593 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
594 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 595 | |
8f38910b SR |
596 | mutex_lock(&mcp->lock); |
597 | regcache_cache_only(mcp->regmap, true); | |
4e47f91b LP |
598 | } |
599 | ||
600 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
601 | { | |
dad3d272 PR |
602 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
603 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 604 | |
8f38910b SR |
605 | regcache_cache_only(mcp->regmap, false); |
606 | regcache_sync(mcp->regmap); | |
607 | ||
4e47f91b | 608 | mutex_unlock(&mcp->lock); |
4e47f91b LP |
609 | } |
610 | ||
4e47f91b LP |
611 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) |
612 | { | |
613 | struct gpio_chip *chip = &mcp->chip; | |
dad3d272 | 614 | int err; |
a4e63554 | 615 | unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; |
4e47f91b | 616 | |
a4e63554 AS |
617 | if (mcp->irq_active_high) |
618 | irqflags |= IRQF_TRIGGER_HIGH; | |
619 | else | |
620 | irqflags |= IRQF_TRIGGER_LOW; | |
621 | ||
58383c78 LW |
622 | err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, |
623 | mcp23s08_irq, | |
624 | irqflags, dev_name(chip->parent), mcp); | |
4e47f91b | 625 | if (err != 0) { |
58383c78 | 626 | dev_err(chip->parent, "unable to request IRQ#%d: %d\n", |
4e47f91b LP |
627 | mcp->irq, err); |
628 | return err; | |
629 | } | |
630 | ||
f259f896 MF |
631 | return 0; |
632 | } | |
633 | ||
634 | static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp) | |
635 | { | |
636 | struct gpio_chip *chip = &mcp->chip; | |
637 | int err; | |
638 | ||
d245b3f9 | 639 | err = gpiochip_irqchip_add_nested(chip, |
19ab5ca9 | 640 | &mcp->irq_chip, |
d245b3f9 LW |
641 | 0, |
642 | handle_simple_irq, | |
643 | IRQ_TYPE_NONE); | |
dad3d272 PR |
644 | if (err) { |
645 | dev_err(chip->parent, | |
646 | "could not connect irqchip to gpiochip: %d\n", err); | |
647 | return err; | |
4e47f91b | 648 | } |
4e47f91b | 649 | |
d245b3f9 | 650 | gpiochip_set_nested_irqchip(chip, |
19ab5ca9 | 651 | &mcp->irq_chip, |
d245b3f9 | 652 | mcp->irq); |
4e47f91b | 653 | |
dad3d272 | 654 | return 0; |
4e47f91b LP |
655 | } |
656 | ||
e58b9e27 DB |
657 | /*----------------------------------------------------------------------*/ |
658 | ||
659 | #ifdef CONFIG_DEBUG_FS | |
660 | ||
661 | #include <linux/seq_file.h> | |
662 | ||
8f38910b SR |
663 | /* |
664 | * This compares the chip's registers with the register | |
665 | * cache and corrects any incorrectly set register. This | |
666 | * can be used to fix state for MCP23xxx, that temporary | |
667 | * lost its power supply. | |
668 | */ | |
7547b596 | 669 | #define MCP23S08_CONFIG_REGS 7 |
8f38910b SR |
670 | static int __check_mcp23s08_reg_cache(struct mcp23s08 *mcp) |
671 | { | |
672 | int cached[MCP23S08_CONFIG_REGS]; | |
673 | int err = 0, i; | |
674 | ||
675 | /* read cached config registers */ | |
676 | for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { | |
677 | err = mcp_read(mcp, i, &cached[i]); | |
678 | if (err) | |
679 | goto out; | |
680 | } | |
681 | ||
682 | regcache_cache_bypass(mcp->regmap, true); | |
683 | ||
684 | for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { | |
685 | int uncached; | |
686 | err = mcp_read(mcp, i, &uncached); | |
687 | if (err) | |
688 | goto out; | |
689 | ||
690 | if (uncached != cached[i]) { | |
691 | dev_err(mcp->dev, "restoring reg 0x%02x from 0x%04x to 0x%04x (power-loss?)\n", | |
692 | i, uncached, cached[i]); | |
693 | mcp_write(mcp, i, cached[i]); | |
694 | } | |
695 | } | |
696 | ||
697 | out: | |
698 | if (err) | |
699 | dev_err(mcp->dev, "read error: reg=%02x, err=%d", i, err); | |
700 | regcache_cache_bypass(mcp->regmap, false); | |
701 | return err; | |
702 | } | |
703 | ||
e58b9e27 DB |
704 | /* |
705 | * This shows more info than the generic gpio dump code: | |
706 | * pullups, deglitching, open drain drive. | |
707 | */ | |
708 | static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
709 | { | |
710 | struct mcp23s08 *mcp; | |
711 | char bank; | |
1d1c1d9b | 712 | int t; |
e58b9e27 | 713 | unsigned mask; |
8f38910b | 714 | int iodir, gpio, gppu; |
e58b9e27 | 715 | |
9e03cf0b | 716 | mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
717 | |
718 | /* NOTE: we only handle one bank for now ... */ | |
0b7bb77f | 719 | bank = '0' + ((mcp->addr >> 1) & 0x7); |
e58b9e27 DB |
720 | |
721 | mutex_lock(&mcp->lock); | |
8f38910b SR |
722 | |
723 | t = __check_mcp23s08_reg_cache(mcp); | |
724 | if (t) { | |
725 | seq_printf(s, " I/O Error\n"); | |
726 | goto done; | |
727 | } | |
728 | t = mcp_read(mcp, MCP_IODIR, &iodir); | |
729 | if (t) { | |
730 | seq_printf(s, " I/O Error\n"); | |
731 | goto done; | |
732 | } | |
733 | t = mcp_read(mcp, MCP_GPIO, &gpio); | |
734 | if (t) { | |
735 | seq_printf(s, " I/O Error\n"); | |
736 | goto done; | |
737 | } | |
738 | t = mcp_read(mcp, MCP_GPPU, &gppu); | |
739 | if (t) { | |
740 | seq_printf(s, " I/O Error\n"); | |
e58b9e27 DB |
741 | goto done; |
742 | } | |
743 | ||
8f38910b SR |
744 | for (t = 0, mask = BIT(0); t < chip->ngpio; t++, mask <<= 1) { |
745 | const char *label; | |
e58b9e27 DB |
746 | |
747 | label = gpiochip_is_requested(chip, t); | |
748 | if (!label) | |
749 | continue; | |
750 | ||
7c3012c8 ME |
751 | seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s\n", |
752 | chip->base + t, bank, t, label, | |
753 | (iodir & mask) ? "in " : "out", | |
754 | (gpio & mask) ? "hi" : "lo", | |
755 | (gppu & mask) ? "up" : " "); | |
e58b9e27 | 756 | /* NOTE: ignoring the irq-related registers */ |
e58b9e27 DB |
757 | } |
758 | done: | |
759 | mutex_unlock(&mcp->lock); | |
760 | } | |
761 | ||
762 | #else | |
763 | #define mcp23s08_dbg_show NULL | |
764 | #endif | |
765 | ||
766 | /*----------------------------------------------------------------------*/ | |
767 | ||
d62b98f3 | 768 | static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
4e47f91b | 769 | void *data, unsigned addr, unsigned type, |
5b1a7e80 | 770 | unsigned int base, int cs) |
e58b9e27 | 771 | { |
3d84fdb3 | 772 | int status, ret; |
4e47f91b | 773 | bool mirror = false; |
fa2b7fae | 774 | bool open_drain = false; |
9b3e4207 | 775 | struct regmap_config *one_regmap_config = NULL; |
ed231751 | 776 | int raw_chip_address = (addr & ~0x40) >> 1; |
e58b9e27 | 777 | |
e58b9e27 DB |
778 | mutex_init(&mcp->lock); |
779 | ||
3d84fdb3 | 780 | mcp->dev = dev; |
d62b98f3 | 781 | mcp->addr = addr; |
a4e63554 | 782 | mcp->irq_active_high = false; |
e58b9e27 | 783 | |
e58b9e27 DB |
784 | mcp->chip.direction_input = mcp23s08_direction_input; |
785 | mcp->chip.get = mcp23s08_get; | |
786 | mcp->chip.direction_output = mcp23s08_direction_output; | |
787 | mcp->chip.set = mcp23s08_set; | |
788 | mcp->chip.dbg_show = mcp23s08_dbg_show; | |
60f749f8 | 789 | #ifdef CONFIG_OF_GPIO |
97ddb1c8 LP |
790 | mcp->chip.of_gpio_n_cells = 2; |
791 | mcp->chip.of_node = dev->of_node; | |
792 | #endif | |
e58b9e27 | 793 | |
d62b98f3 PK |
794 | switch (type) { |
795 | #ifdef CONFIG_SPI_MASTER | |
796 | case MCP_TYPE_S08: | |
d62b98f3 | 797 | case MCP_TYPE_S17: |
9b3e4207 JK |
798 | switch (type) { |
799 | case MCP_TYPE_S08: | |
800 | one_regmap_config = | |
801 | devm_kmemdup(dev, &mcp23x08_regmap, | |
802 | sizeof(struct regmap_config), GFP_KERNEL); | |
803 | mcp->reg_shift = 0; | |
804 | mcp->chip.ngpio = 8; | |
ed231751 JK |
805 | mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, |
806 | "mcp23s08.%d", raw_chip_address); | |
9b3e4207 JK |
807 | break; |
808 | case MCP_TYPE_S17: | |
809 | one_regmap_config = | |
810 | devm_kmemdup(dev, &mcp23x17_regmap, | |
811 | sizeof(struct regmap_config), GFP_KERNEL); | |
812 | mcp->reg_shift = 1; | |
813 | mcp->chip.ngpio = 16; | |
ed231751 JK |
814 | mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, |
815 | "mcp23s17.%d", raw_chip_address); | |
9b3e4207 JK |
816 | break; |
817 | } | |
818 | if (!one_regmap_config) | |
819 | return -ENOMEM; | |
820 | ||
ed231751 | 821 | one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address); |
3d84fdb3 | 822 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
9b3e4207 | 823 | one_regmap_config); |
d62b98f3 | 824 | break; |
28c5a41e PR |
825 | |
826 | case MCP_TYPE_S18: | |
f165988b JK |
827 | one_regmap_config = |
828 | devm_kmemdup(dev, &mcp23x17_regmap, | |
829 | sizeof(struct regmap_config), GFP_KERNEL); | |
830 | if (!one_regmap_config) | |
831 | return -ENOMEM; | |
3d84fdb3 | 832 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
f165988b | 833 | one_regmap_config); |
3d84fdb3 | 834 | mcp->reg_shift = 1; |
28c5a41e PR |
835 | mcp->chip.ngpio = 16; |
836 | mcp->chip.label = "mcp23s18"; | |
837 | break; | |
d62b98f3 PK |
838 | #endif /* CONFIG_SPI_MASTER */ |
839 | ||
cbf24fad | 840 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 841 | case MCP_TYPE_008: |
3d84fdb3 SR |
842 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); |
843 | mcp->reg_shift = 0; | |
752ad5e8 PK |
844 | mcp->chip.ngpio = 8; |
845 | mcp->chip.label = "mcp23008"; | |
846 | break; | |
847 | ||
848 | case MCP_TYPE_017: | |
3d84fdb3 SR |
849 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); |
850 | mcp->reg_shift = 1; | |
752ad5e8 PK |
851 | mcp->chip.ngpio = 16; |
852 | mcp->chip.label = "mcp23017"; | |
853 | break; | |
ff0f2ce7 PR |
854 | |
855 | case MCP_TYPE_018: | |
856 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); | |
857 | mcp->reg_shift = 1; | |
858 | mcp->chip.ngpio = 16; | |
859 | mcp->chip.label = "mcp23018"; | |
860 | break; | |
752ad5e8 PK |
861 | #endif /* CONFIG_I2C */ |
862 | ||
d62b98f3 PK |
863 | default: |
864 | dev_err(dev, "invalid device type (%d)\n", type); | |
865 | return -EINVAL; | |
0b7bb77f | 866 | } |
d62b98f3 | 867 | |
3d84fdb3 SR |
868 | if (IS_ERR(mcp->regmap)) |
869 | return PTR_ERR(mcp->regmap); | |
870 | ||
5b1a7e80 | 871 | mcp->chip.base = base; |
9fb1f39e | 872 | mcp->chip.can_sleep = true; |
58383c78 | 873 | mcp->chip.parent = dev; |
d72cbed0 | 874 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 875 | |
8f1cc3b1 DB |
876 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
877 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
878 | */ | |
4e47f91b | 879 | |
3d84fdb3 SR |
880 | ret = mcp_read(mcp, MCP_IOCON, &status); |
881 | if (ret < 0) | |
e58b9e27 | 882 | goto fail; |
4e47f91b | 883 | |
5b1a7e80 SR |
884 | mcp->irq_controller = |
885 | device_property_read_bool(dev, "interrupt-controller"); | |
a4e63554 | 886 | if (mcp->irq && mcp->irq_controller) { |
170680ab | 887 | mcp->irq_active_high = |
5b1a7e80 | 888 | device_property_read_bool(dev, |
170680ab | 889 | "microchip,irq-active-high"); |
4e47f91b | 890 | |
5b1a7e80 | 891 | mirror = device_property_read_bool(dev, "microchip,irq-mirror"); |
fa2b7fae | 892 | open_drain = device_property_read_bool(dev, "drive-open-drain"); |
a4e63554 AS |
893 | } |
894 | ||
895 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || | |
fa2b7fae | 896 | mcp->irq_active_high || open_drain) { |
0b7bb77f PK |
897 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
898 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
899 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
a4e63554 AS |
900 | if (mcp->irq_active_high) |
901 | status |= IOCON_INTPOL | (IOCON_INTPOL << 8); | |
902 | else | |
903 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); | |
904 | ||
4e47f91b LP |
905 | if (mirror) |
906 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
907 | ||
fa2b7fae PR |
908 | if (open_drain) |
909 | status |= IOCON_ODR | (IOCON_ODR << 8); | |
910 | ||
ff0f2ce7 | 911 | if (type == MCP_TYPE_S18 || type == MCP_TYPE_018) |
3539699c PR |
912 | status |= IOCON_INTCC | (IOCON_INTCC << 8); |
913 | ||
3d84fdb3 SR |
914 | ret = mcp_write(mcp, MCP_IOCON, status); |
915 | if (ret < 0) | |
e58b9e27 DB |
916 | goto fail; |
917 | } | |
918 | ||
4e47f91b | 919 | if (mcp->irq && mcp->irq_controller) { |
f259f896 | 920 | ret = mcp23s08_irqchip_setup(mcp); |
3d84fdb3 | 921 | if (ret) |
4e47f91b | 922 | goto fail; |
4e47f91b | 923 | } |
82039d24 | 924 | |
02e389e6 DM |
925 | ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); |
926 | if (ret < 0) | |
927 | goto fail; | |
928 | ||
1781af56 JK |
929 | if (one_regmap_config) { |
930 | mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, | |
931 | "mcp23xxx-pinctrl.%d", raw_chip_address); | |
932 | if (!mcp->pinctrl_desc.name) | |
933 | return -ENOMEM; | |
934 | } else { | |
935 | mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; | |
936 | } | |
82039d24 SR |
937 | mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; |
938 | mcp->pinctrl_desc.confops = &mcp_pinconf_ops; | |
939 | mcp->pinctrl_desc.npins = mcp->chip.ngpio; | |
940 | if (mcp->pinctrl_desc.npins == 8) | |
941 | mcp->pinctrl_desc.pins = mcp23x08_pins; | |
942 | else if (mcp->pinctrl_desc.npins == 16) | |
943 | mcp->pinctrl_desc.pins = mcp23x17_pins; | |
944 | mcp->pinctrl_desc.owner = THIS_MODULE; | |
945 | ||
946 | mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); | |
947 | if (IS_ERR(mcp->pctldev)) { | |
948 | ret = PTR_ERR(mcp->pctldev); | |
949 | goto fail; | |
950 | } | |
951 | ||
f259f896 MF |
952 | if (mcp->irq) |
953 | ret = mcp23s08_irq_setup(mcp); | |
954 | ||
8f1cc3b1 | 955 | fail: |
3d84fdb3 SR |
956 | if (ret < 0) |
957 | dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); | |
958 | return ret; | |
8f1cc3b1 DB |
959 | } |
960 | ||
752ad5e8 PK |
961 | /*----------------------------------------------------------------------*/ |
962 | ||
97ddb1c8 LP |
963 | #ifdef CONFIG_OF |
964 | #ifdef CONFIG_SPI_MASTER | |
ac791804 | 965 | static const struct of_device_id mcp23s08_spi_of_match[] = { |
97ddb1c8 | 966 | { |
45971686 LP |
967 | .compatible = "microchip,mcp23s08", |
968 | .data = (void *) MCP_TYPE_S08, | |
97ddb1c8 LP |
969 | }, |
970 | { | |
45971686 LP |
971 | .compatible = "microchip,mcp23s17", |
972 | .data = (void *) MCP_TYPE_S17, | |
973 | }, | |
28c5a41e PR |
974 | { |
975 | .compatible = "microchip,mcp23s18", | |
976 | .data = (void *) MCP_TYPE_S18, | |
977 | }, | |
45971686 LP |
978 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ |
979 | { | |
980 | .compatible = "mcp,mcp23s08", | |
981 | .data = (void *) MCP_TYPE_S08, | |
982 | }, | |
983 | { | |
984 | .compatible = "mcp,mcp23s17", | |
985 | .data = (void *) MCP_TYPE_S17, | |
97ddb1c8 LP |
986 | }, |
987 | { }, | |
988 | }; | |
989 | MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); | |
990 | #endif | |
991 | ||
992 | #if IS_ENABLED(CONFIG_I2C) | |
ac791804 | 993 | static const struct of_device_id mcp23s08_i2c_of_match[] = { |
97ddb1c8 | 994 | { |
45971686 LP |
995 | .compatible = "microchip,mcp23008", |
996 | .data = (void *) MCP_TYPE_008, | |
97ddb1c8 LP |
997 | }, |
998 | { | |
45971686 LP |
999 | .compatible = "microchip,mcp23017", |
1000 | .data = (void *) MCP_TYPE_017, | |
1001 | }, | |
ff0f2ce7 PR |
1002 | { |
1003 | .compatible = "microchip,mcp23018", | |
1004 | .data = (void *) MCP_TYPE_018, | |
1005 | }, | |
45971686 LP |
1006 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ |
1007 | { | |
1008 | .compatible = "mcp,mcp23008", | |
1009 | .data = (void *) MCP_TYPE_008, | |
1010 | }, | |
1011 | { | |
1012 | .compatible = "mcp,mcp23017", | |
1013 | .data = (void *) MCP_TYPE_017, | |
97ddb1c8 LP |
1014 | }, |
1015 | { }, | |
1016 | }; | |
1017 | MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); | |
1018 | #endif | |
1019 | #endif /* CONFIG_OF */ | |
1020 | ||
1021 | ||
cbf24fad | 1022 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 1023 | |
3836309d | 1024 | static int mcp230xx_probe(struct i2c_client *client, |
752ad5e8 PK |
1025 | const struct i2c_device_id *id) |
1026 | { | |
3af0dbd5 | 1027 | struct mcp23s08_platform_data *pdata, local_pdata; |
752ad5e8 | 1028 | struct mcp23s08 *mcp; |
3af0dbd5 | 1029 | int status; |
97ddb1c8 | 1030 | |
5f853acf SR |
1031 | pdata = dev_get_platdata(&client->dev); |
1032 | if (!pdata) { | |
3af0dbd5 SZ |
1033 | pdata = &local_pdata; |
1034 | pdata->base = -1; | |
752ad5e8 PK |
1035 | } |
1036 | ||
2f98e78b | 1037 | mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); |
752ad5e8 PK |
1038 | if (!mcp) |
1039 | return -ENOMEM; | |
1040 | ||
4e47f91b | 1041 | mcp->irq = client->irq; |
19ab5ca9 LP |
1042 | mcp->irq_chip.name = dev_name(&client->dev); |
1043 | mcp->irq_chip.irq_mask = mcp23s08_irq_mask; | |
1044 | mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; | |
1045 | mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; | |
1046 | mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; | |
1047 | mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; | |
1048 | ||
752ad5e8 | 1049 | status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, |
5b1a7e80 | 1050 | id->driver_data, pdata->base, 0); |
752ad5e8 | 1051 | if (status) |
2f98e78b | 1052 | return status; |
752ad5e8 PK |
1053 | |
1054 | i2c_set_clientdata(client, mcp); | |
1055 | ||
1056 | return 0; | |
752ad5e8 PK |
1057 | } |
1058 | ||
752ad5e8 PK |
1059 | static const struct i2c_device_id mcp230xx_id[] = { |
1060 | { "mcp23008", MCP_TYPE_008 }, | |
1061 | { "mcp23017", MCP_TYPE_017 }, | |
ff0f2ce7 | 1062 | { "mcp23018", MCP_TYPE_018 }, |
752ad5e8 PK |
1063 | { }, |
1064 | }; | |
1065 | MODULE_DEVICE_TABLE(i2c, mcp230xx_id); | |
1066 | ||
1067 | static struct i2c_driver mcp230xx_driver = { | |
1068 | .driver = { | |
1069 | .name = "mcp230xx", | |
97ddb1c8 | 1070 | .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), |
752ad5e8 PK |
1071 | }, |
1072 | .probe = mcp230xx_probe, | |
752ad5e8 PK |
1073 | .id_table = mcp230xx_id, |
1074 | }; | |
1075 | ||
1076 | static int __init mcp23s08_i2c_init(void) | |
1077 | { | |
1078 | return i2c_add_driver(&mcp230xx_driver); | |
1079 | } | |
1080 | ||
1081 | static void mcp23s08_i2c_exit(void) | |
1082 | { | |
1083 | i2c_del_driver(&mcp230xx_driver); | |
1084 | } | |
1085 | ||
1086 | #else | |
1087 | ||
1088 | static int __init mcp23s08_i2c_init(void) { return 0; } | |
1089 | static void mcp23s08_i2c_exit(void) { } | |
1090 | ||
1091 | #endif /* CONFIG_I2C */ | |
1092 | ||
1093 | /*----------------------------------------------------------------------*/ | |
1094 | ||
d62b98f3 PK |
1095 | #ifdef CONFIG_SPI_MASTER |
1096 | ||
8f1cc3b1 DB |
1097 | static int mcp23s08_probe(struct spi_device *spi) |
1098 | { | |
3af0dbd5 | 1099 | struct mcp23s08_platform_data *pdata, local_pdata; |
8f1cc3b1 | 1100 | unsigned addr; |
596a1c5f | 1101 | int chips = 0; |
8f1cc3b1 | 1102 | struct mcp23s08_driver_data *data; |
0b7bb77f | 1103 | int status, type; |
3af0dbd5 | 1104 | unsigned ngpio = 0; |
97ddb1c8 | 1105 | const struct of_device_id *match; |
97ddb1c8 LP |
1106 | |
1107 | match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); | |
0d7fcd50 | 1108 | if (match) |
de755c33 | 1109 | type = (int)(uintptr_t)match->data; |
0d7fcd50 SR |
1110 | else |
1111 | type = spi_get_device_id(spi)->driver_data; | |
1112 | ||
1113 | pdata = dev_get_platdata(&spi->dev); | |
1114 | if (!pdata) { | |
1115 | pdata = &local_pdata; | |
1116 | pdata->base = -1; | |
1117 | ||
0d7fcd50 | 1118 | status = device_property_read_u32(&spi->dev, |
ce9bd0a0 | 1119 | "microchip,spi-present-mask", &pdata->spi_present_mask); |
97ddb1c8 | 1120 | if (status) { |
0d7fcd50 | 1121 | status = device_property_read_u32(&spi->dev, |
ce9bd0a0 SR |
1122 | "mcp,spi-present-mask", |
1123 | &pdata->spi_present_mask); | |
0d7fcd50 | 1124 | |
45971686 | 1125 | if (status) { |
0d7fcd50 | 1126 | dev_err(&spi->dev, "missing spi-present-mask"); |
45971686 LP |
1127 | return -ENODEV; |
1128 | } | |
97ddb1c8 | 1129 | } |
8f1cc3b1 | 1130 | } |
8f1cc3b1 | 1131 | |
ce9bd0a0 | 1132 | if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { |
0d7fcd50 SR |
1133 | dev_err(&spi->dev, "invalid spi-present-mask"); |
1134 | return -ENODEV; | |
1135 | } | |
1136 | ||
ce9bd0a0 SR |
1137 | for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { |
1138 | if (pdata->spi_present_mask & BIT(addr)) | |
0d7fcd50 SR |
1139 | chips++; |
1140 | } | |
1141 | ||
99e4b98d MW |
1142 | if (!chips) |
1143 | return -ENODEV; | |
1144 | ||
7898b31e | 1145 | data = devm_kzalloc(&spi->dev, |
16f4372f | 1146 | struct_size(data, chip, chips), GFP_KERNEL); |
8f1cc3b1 DB |
1147 | if (!data) |
1148 | return -ENOMEM; | |
7898b31e | 1149 | |
8f1cc3b1 DB |
1150 | spi_set_drvdata(spi, data); |
1151 | ||
ce9bd0a0 SR |
1152 | for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { |
1153 | if (!(pdata->spi_present_mask & BIT(addr))) | |
8f1cc3b1 DB |
1154 | continue; |
1155 | chips--; | |
1156 | data->mcp[addr] = &data->chip[chips]; | |
a231b88c | 1157 | data->mcp[addr]->irq = spi->irq; |
19ab5ca9 LP |
1158 | data->mcp[addr]->irq_chip.name = dev_name(&spi->dev); |
1159 | data->mcp[addr]->irq_chip.irq_mask = mcp23s08_irq_mask; | |
1160 | data->mcp[addr]->irq_chip.irq_unmask = mcp23s08_irq_unmask; | |
1161 | data->mcp[addr]->irq_chip.irq_set_type = mcp23s08_irq_set_type; | |
1162 | data->mcp[addr]->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; | |
1163 | data->mcp[addr]->irq_chip.irq_bus_sync_unlock = | |
1164 | mcp23s08_irq_bus_unlock; | |
d62b98f3 | 1165 | status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, |
5b1a7e80 SR |
1166 | 0x40 | (addr << 1), type, |
1167 | pdata->base, addr); | |
8f1cc3b1 | 1168 | if (status < 0) |
d0e49dab | 1169 | return status; |
0b7bb77f | 1170 | |
3af0dbd5 | 1171 | if (pdata->base != -1) |
28c5a41e PR |
1172 | pdata->base += data->mcp[addr]->chip.ngpio; |
1173 | ngpio += data->mcp[addr]->chip.ngpio; | |
8f1cc3b1 | 1174 | } |
97ddb1c8 | 1175 | data->ngpio = ngpio; |
e58b9e27 | 1176 | |
e58b9e27 | 1177 | return 0; |
e58b9e27 DB |
1178 | } |
1179 | ||
0b7bb77f PK |
1180 | static const struct spi_device_id mcp23s08_ids[] = { |
1181 | { "mcp23s08", MCP_TYPE_S08 }, | |
1182 | { "mcp23s17", MCP_TYPE_S17 }, | |
28c5a41e | 1183 | { "mcp23s18", MCP_TYPE_S18 }, |
0b7bb77f PK |
1184 | { }, |
1185 | }; | |
1186 | MODULE_DEVICE_TABLE(spi, mcp23s08_ids); | |
1187 | ||
e58b9e27 DB |
1188 | static struct spi_driver mcp23s08_driver = { |
1189 | .probe = mcp23s08_probe, | |
0b7bb77f | 1190 | .id_table = mcp23s08_ids, |
e58b9e27 DB |
1191 | .driver = { |
1192 | .name = "mcp23s08", | |
97ddb1c8 | 1193 | .of_match_table = of_match_ptr(mcp23s08_spi_of_match), |
e58b9e27 DB |
1194 | }, |
1195 | }; | |
1196 | ||
d62b98f3 PK |
1197 | static int __init mcp23s08_spi_init(void) |
1198 | { | |
1199 | return spi_register_driver(&mcp23s08_driver); | |
1200 | } | |
1201 | ||
1202 | static void mcp23s08_spi_exit(void) | |
1203 | { | |
1204 | spi_unregister_driver(&mcp23s08_driver); | |
1205 | } | |
1206 | ||
1207 | #else | |
1208 | ||
1209 | static int __init mcp23s08_spi_init(void) { return 0; } | |
1210 | static void mcp23s08_spi_exit(void) { } | |
1211 | ||
1212 | #endif /* CONFIG_SPI_MASTER */ | |
1213 | ||
e58b9e27 DB |
1214 | /*----------------------------------------------------------------------*/ |
1215 | ||
1216 | static int __init mcp23s08_init(void) | |
1217 | { | |
752ad5e8 PK |
1218 | int ret; |
1219 | ||
1220 | ret = mcp23s08_spi_init(); | |
1221 | if (ret) | |
1222 | goto spi_fail; | |
1223 | ||
1224 | ret = mcp23s08_i2c_init(); | |
1225 | if (ret) | |
1226 | goto i2c_fail; | |
1227 | ||
1228 | return 0; | |
1229 | ||
1230 | i2c_fail: | |
1231 | mcp23s08_spi_exit(); | |
1232 | spi_fail: | |
1233 | return ret; | |
e58b9e27 | 1234 | } |
752ad5e8 | 1235 | /* register after spi/i2c postcore initcall and before |
673c0c00 DB |
1236 | * subsys initcalls that may rely on these GPIOs |
1237 | */ | |
1238 | subsys_initcall(mcp23s08_init); | |
e58b9e27 DB |
1239 | |
1240 | static void __exit mcp23s08_exit(void) | |
1241 | { | |
d62b98f3 | 1242 | mcp23s08_spi_exit(); |
752ad5e8 | 1243 | mcp23s08_i2c_exit(); |
e58b9e27 DB |
1244 | } |
1245 | module_exit(mcp23s08_exit); | |
1246 | ||
1247 | MODULE_LICENSE("GPL"); |