Commit | Line | Data |
---|---|---|
d8f4494e | 1 | /* MCP23S08 SPI/I2C GPIO driver */ |
e58b9e27 DB |
2 | |
3 | #include <linux/kernel.h> | |
4 | #include <linux/device.h> | |
e58b9e27 | 5 | #include <linux/mutex.h> |
bb207ef1 | 6 | #include <linux/module.h> |
d120c17f | 7 | #include <linux/gpio.h> |
752ad5e8 | 8 | #include <linux/i2c.h> |
e58b9e27 DB |
9 | #include <linux/spi/spi.h> |
10 | #include <linux/spi/mcp23s08.h> | |
5a0e3ad6 | 11 | #include <linux/slab.h> |
0b7bb77f | 12 | #include <asm/byteorder.h> |
4e47f91b | 13 | #include <linux/interrupt.h> |
97ddb1c8 | 14 | #include <linux/of_device.h> |
3d84fdb3 | 15 | #include <linux/regmap.h> |
82039d24 SR |
16 | #include <linux/pinctrl/pinctrl.h> |
17 | #include <linux/pinctrl/pinconf.h> | |
18 | #include <linux/pinctrl/pinconf-generic.h> | |
e58b9e27 | 19 | |
d8f4494e | 20 | /* |
0b7bb77f PK |
21 | * MCP types supported by driver |
22 | */ | |
23 | #define MCP_TYPE_S08 0 | |
24 | #define MCP_TYPE_S17 1 | |
752ad5e8 PK |
25 | #define MCP_TYPE_008 2 |
26 | #define MCP_TYPE_017 3 | |
28c5a41e | 27 | #define MCP_TYPE_S18 4 |
ff0f2ce7 | 28 | #define MCP_TYPE_018 5 |
e58b9e27 | 29 | |
ce9bd0a0 SR |
30 | #define MCP_MAX_DEV_PER_CS 8 |
31 | ||
e58b9e27 DB |
32 | /* Registers are all 8 bits wide. |
33 | * | |
34 | * The mcp23s17 has twice as many bits, and can be configured to work | |
35 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
36 | */ |
37 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
38 | #define MCP_IPOL 0x01 | |
39 | #define MCP_GPINTEN 0x02 | |
40 | #define MCP_DEFVAL 0x03 | |
41 | #define MCP_INTCON 0x04 | |
42 | #define MCP_IOCON 0x05 | |
4e47f91b | 43 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
44 | # define IOCON_SEQOP (1 << 5) |
45 | # define IOCON_HAEN (1 << 3) | |
46 | # define IOCON_ODR (1 << 2) | |
47 | # define IOCON_INTPOL (1 << 1) | |
3539699c | 48 | # define IOCON_INTCC (1) |
e58b9e27 DB |
49 | #define MCP_GPPU 0x06 |
50 | #define MCP_INTF 0x07 | |
51 | #define MCP_INTCAP 0x08 | |
52 | #define MCP_GPIO 0x09 | |
53 | #define MCP_OLAT 0x0a | |
54 | ||
0b7bb77f PK |
55 | struct mcp23s08; |
56 | ||
e58b9e27 | 57 | struct mcp23s08 { |
e58b9e27 | 58 | u8 addr; |
a4e63554 | 59 | bool irq_active_high; |
3d84fdb3 | 60 | bool reg_shift; |
e58b9e27 | 61 | |
4e47f91b LP |
62 | u16 irq_rise; |
63 | u16 irq_fall; | |
64 | int irq; | |
65 | bool irq_controller; | |
8f38910b SR |
66 | int cached_gpio; |
67 | /* lock protects regmap access with bypass/cache flags */ | |
e58b9e27 | 68 | struct mutex lock; |
e58b9e27 DB |
69 | |
70 | struct gpio_chip chip; | |
71 | ||
3d84fdb3 SR |
72 | struct regmap *regmap; |
73 | struct device *dev; | |
82039d24 SR |
74 | |
75 | struct pinctrl_dev *pctldev; | |
76 | struct pinctrl_desc pinctrl_desc; | |
8f1cc3b1 DB |
77 | }; |
78 | ||
8f38910b SR |
79 | static const struct reg_default mcp23x08_defaults[] = { |
80 | {.reg = MCP_IODIR, .def = 0xff}, | |
81 | {.reg = MCP_IPOL, .def = 0x00}, | |
82 | {.reg = MCP_GPINTEN, .def = 0x00}, | |
83 | {.reg = MCP_DEFVAL, .def = 0x00}, | |
84 | {.reg = MCP_INTCON, .def = 0x00}, | |
85 | {.reg = MCP_IOCON, .def = 0x00}, | |
86 | {.reg = MCP_GPPU, .def = 0x00}, | |
87 | {.reg = MCP_OLAT, .def = 0x00}, | |
88 | }; | |
89 | ||
90 | static const struct regmap_range mcp23x08_volatile_range = { | |
91 | .range_min = MCP_INTF, | |
92 | .range_max = MCP_GPIO, | |
93 | }; | |
94 | ||
95 | static const struct regmap_access_table mcp23x08_volatile_table = { | |
96 | .yes_ranges = &mcp23x08_volatile_range, | |
97 | .n_yes_ranges = 1, | |
98 | }; | |
99 | ||
100 | static const struct regmap_range mcp23x08_precious_range = { | |
101 | .range_min = MCP_GPIO, | |
102 | .range_max = MCP_GPIO, | |
103 | }; | |
104 | ||
105 | static const struct regmap_access_table mcp23x08_precious_table = { | |
106 | .yes_ranges = &mcp23x08_precious_range, | |
107 | .n_yes_ranges = 1, | |
108 | }; | |
109 | ||
3d84fdb3 SR |
110 | static const struct regmap_config mcp23x08_regmap = { |
111 | .reg_bits = 8, | |
112 | .val_bits = 8, | |
752ad5e8 | 113 | |
3d84fdb3 | 114 | .reg_stride = 1, |
8f38910b SR |
115 | .volatile_table = &mcp23x08_volatile_table, |
116 | .precious_table = &mcp23x08_precious_table, | |
117 | .reg_defaults = mcp23x08_defaults, | |
118 | .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), | |
119 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 | 120 | .max_register = MCP_OLAT, |
752ad5e8 PK |
121 | }; |
122 | ||
8f38910b SR |
123 | static const struct reg_default mcp23x16_defaults[] = { |
124 | {.reg = MCP_IODIR << 1, .def = 0xffff}, | |
125 | {.reg = MCP_IPOL << 1, .def = 0x0000}, | |
126 | {.reg = MCP_GPINTEN << 1, .def = 0x0000}, | |
127 | {.reg = MCP_DEFVAL << 1, .def = 0x0000}, | |
128 | {.reg = MCP_INTCON << 1, .def = 0x0000}, | |
129 | {.reg = MCP_IOCON << 1, .def = 0x0000}, | |
130 | {.reg = MCP_GPPU << 1, .def = 0x0000}, | |
131 | {.reg = MCP_OLAT << 1, .def = 0x0000}, | |
132 | }; | |
133 | ||
134 | static const struct regmap_range mcp23x16_volatile_range = { | |
135 | .range_min = MCP_INTF << 1, | |
136 | .range_max = MCP_GPIO << 1, | |
137 | }; | |
138 | ||
139 | static const struct regmap_access_table mcp23x16_volatile_table = { | |
140 | .yes_ranges = &mcp23x16_volatile_range, | |
141 | .n_yes_ranges = 1, | |
142 | }; | |
143 | ||
144 | static const struct regmap_range mcp23x16_precious_range = { | |
145 | .range_min = MCP_GPIO << 1, | |
146 | .range_max = MCP_GPIO << 1, | |
147 | }; | |
148 | ||
149 | static const struct regmap_access_table mcp23x16_precious_table = { | |
150 | .yes_ranges = &mcp23x16_precious_range, | |
151 | .n_yes_ranges = 1, | |
152 | }; | |
153 | ||
3d84fdb3 SR |
154 | static const struct regmap_config mcp23x17_regmap = { |
155 | .reg_bits = 8, | |
156 | .val_bits = 16, | |
752ad5e8 | 157 | |
3d84fdb3 SR |
158 | .reg_stride = 2, |
159 | .max_register = MCP_OLAT << 1, | |
8f38910b SR |
160 | .volatile_table = &mcp23x16_volatile_table, |
161 | .precious_table = &mcp23x16_precious_table, | |
162 | .reg_defaults = mcp23x16_defaults, | |
163 | .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), | |
164 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 SR |
165 | .val_format_endian = REGMAP_ENDIAN_LITTLE, |
166 | }; | |
752ad5e8 | 167 | |
82039d24 SR |
168 | static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) |
169 | { | |
170 | return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); | |
171 | } | |
172 | ||
173 | static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) | |
174 | { | |
175 | return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); | |
176 | } | |
177 | ||
8f38910b SR |
178 | static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, |
179 | unsigned int mask, bool enabled) | |
82039d24 SR |
180 | { |
181 | u16 val = enabled ? 0xffff : 0x0000; | |
82039d24 SR |
182 | return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, |
183 | mask, val); | |
184 | } | |
185 | ||
8f38910b SR |
186 | static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, |
187 | unsigned int pin, bool enabled) | |
82039d24 | 188 | { |
8f38910b SR |
189 | u16 mask = BIT(pin); |
190 | return mcp_set_mask(mcp, reg, mask, enabled); | |
82039d24 SR |
191 | } |
192 | ||
193 | static const struct pinctrl_pin_desc mcp23x08_pins[] = { | |
194 | PINCTRL_PIN(0, "gpio0"), | |
195 | PINCTRL_PIN(1, "gpio1"), | |
196 | PINCTRL_PIN(2, "gpio2"), | |
197 | PINCTRL_PIN(3, "gpio3"), | |
198 | PINCTRL_PIN(4, "gpio4"), | |
199 | PINCTRL_PIN(5, "gpio5"), | |
200 | PINCTRL_PIN(6, "gpio6"), | |
201 | PINCTRL_PIN(7, "gpio7"), | |
202 | }; | |
203 | ||
204 | static const struct pinctrl_pin_desc mcp23x17_pins[] = { | |
205 | PINCTRL_PIN(0, "gpio0"), | |
206 | PINCTRL_PIN(1, "gpio1"), | |
207 | PINCTRL_PIN(2, "gpio2"), | |
208 | PINCTRL_PIN(3, "gpio3"), | |
209 | PINCTRL_PIN(4, "gpio4"), | |
210 | PINCTRL_PIN(5, "gpio5"), | |
211 | PINCTRL_PIN(6, "gpio6"), | |
212 | PINCTRL_PIN(7, "gpio7"), | |
213 | PINCTRL_PIN(8, "gpio8"), | |
214 | PINCTRL_PIN(9, "gpio9"), | |
215 | PINCTRL_PIN(10, "gpio10"), | |
216 | PINCTRL_PIN(11, "gpio11"), | |
217 | PINCTRL_PIN(12, "gpio12"), | |
218 | PINCTRL_PIN(13, "gpio13"), | |
219 | PINCTRL_PIN(14, "gpio14"), | |
220 | PINCTRL_PIN(15, "gpio15"), | |
221 | }; | |
222 | ||
223 | static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
224 | { | |
225 | return 0; | |
226 | } | |
227 | ||
228 | static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
229 | unsigned int group) | |
230 | { | |
231 | return NULL; | |
232 | } | |
233 | ||
234 | static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
235 | unsigned int group, | |
236 | const unsigned int **pins, | |
237 | unsigned int *num_pins) | |
238 | { | |
239 | return -ENOTSUPP; | |
240 | } | |
241 | ||
242 | static const struct pinctrl_ops mcp_pinctrl_ops = { | |
243 | .get_groups_count = mcp_pinctrl_get_groups_count, | |
244 | .get_group_name = mcp_pinctrl_get_group_name, | |
245 | .get_group_pins = mcp_pinctrl_get_group_pins, | |
246 | #ifdef CONFIG_OF | |
247 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
248 | .dt_free_map = pinconf_generic_dt_free_map, | |
249 | #endif | |
250 | }; | |
251 | ||
252 | static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
253 | unsigned long *config) | |
254 | { | |
255 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
256 | enum pin_config_param param = pinconf_to_config_param(*config); | |
257 | unsigned int data, status; | |
258 | int ret; | |
259 | ||
260 | switch (param) { | |
261 | case PIN_CONFIG_BIAS_PULL_UP: | |
262 | ret = mcp_read(mcp, MCP_GPPU, &data); | |
263 | if (ret < 0) | |
264 | return ret; | |
265 | status = (data & BIT(pin)) ? 1 : 0; | |
266 | break; | |
267 | default: | |
268 | dev_err(mcp->dev, "Invalid config param %04x\n", param); | |
269 | return -ENOTSUPP; | |
270 | } | |
271 | ||
272 | *config = 0; | |
273 | ||
274 | return status ? 0 : -EINVAL; | |
275 | } | |
276 | ||
277 | static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
278 | unsigned long *configs, unsigned int num_configs) | |
279 | { | |
280 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
281 | enum pin_config_param param; | |
2a7893c8 | 282 | u32 arg; |
82039d24 SR |
283 | int ret = 0; |
284 | int i; | |
285 | ||
286 | for (i = 0; i < num_configs; i++) { | |
287 | param = pinconf_to_config_param(configs[i]); | |
288 | arg = pinconf_to_config_argument(configs[i]); | |
289 | ||
290 | switch (param) { | |
291 | case PIN_CONFIG_BIAS_PULL_UP: | |
82039d24 SR |
292 | ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); |
293 | break; | |
294 | default: | |
295 | dev_err(mcp->dev, "Invalid config param %04x\n", param); | |
296 | return -ENOTSUPP; | |
297 | } | |
298 | } | |
299 | ||
300 | return ret; | |
301 | } | |
302 | ||
303 | static const struct pinconf_ops mcp_pinconf_ops = { | |
304 | .pin_config_get = mcp_pinconf_get, | |
305 | .pin_config_set = mcp_pinconf_set, | |
306 | .is_generic = true, | |
307 | }; | |
308 | ||
752ad5e8 PK |
309 | /*----------------------------------------------------------------------*/ |
310 | ||
d62b98f3 PK |
311 | #ifdef CONFIG_SPI_MASTER |
312 | ||
3d84fdb3 | 313 | static int mcp23sxx_spi_write(void *context, const void *data, size_t count) |
e58b9e27 | 314 | { |
3d84fdb3 SR |
315 | struct mcp23s08 *mcp = context; |
316 | struct spi_device *spi = to_spi_device(mcp->dev); | |
317 | struct spi_message m; | |
318 | struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
319 | { .tx_buf = data, .len = count, }, }; | |
e58b9e27 | 320 | |
3d84fdb3 SR |
321 | spi_message_init(&m); |
322 | spi_message_add_tail(&t[0], &m); | |
323 | spi_message_add_tail(&t[1], &m); | |
324 | ||
325 | return spi_sync(spi, &m); | |
e58b9e27 DB |
326 | } |
327 | ||
3d84fdb3 SR |
328 | static int mcp23sxx_spi_gather_write(void *context, |
329 | const void *reg, size_t reg_size, | |
330 | const void *val, size_t val_size) | |
e58b9e27 | 331 | { |
3d84fdb3 SR |
332 | struct mcp23s08 *mcp = context; |
333 | struct spi_device *spi = to_spi_device(mcp->dev); | |
334 | struct spi_message m; | |
335 | struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
336 | { .tx_buf = reg, .len = reg_size, }, | |
337 | { .tx_buf = val, .len = val_size, }, }; | |
338 | ||
339 | spi_message_init(&m); | |
340 | spi_message_add_tail(&t[0], &m); | |
341 | spi_message_add_tail(&t[1], &m); | |
342 | spi_message_add_tail(&t[2], &m); | |
343 | ||
344 | return spi_sync(spi, &m); | |
e58b9e27 DB |
345 | } |
346 | ||
3d84fdb3 SR |
347 | static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, |
348 | void *val, size_t val_size) | |
e58b9e27 | 349 | { |
3d84fdb3 SR |
350 | struct mcp23s08 *mcp = context; |
351 | struct spi_device *spi = to_spi_device(mcp->dev); | |
352 | u8 tx[2]; | |
e58b9e27 | 353 | |
3d84fdb3 | 354 | if (reg_size != 1) |
e58b9e27 | 355 | return -EINVAL; |
3d84fdb3 | 356 | |
e58b9e27 | 357 | tx[0] = mcp->addr | 0x01; |
3d84fdb3 | 358 | tx[1] = *((u8 *) reg); |
0b7bb77f | 359 | |
3d84fdb3 | 360 | return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); |
0b7bb77f PK |
361 | } |
362 | ||
3d84fdb3 SR |
363 | static const struct regmap_bus mcp23sxx_spi_regmap = { |
364 | .write = mcp23sxx_spi_write, | |
365 | .gather_write = mcp23sxx_spi_gather_write, | |
366 | .read = mcp23sxx_spi_read, | |
367 | }; | |
0b7bb77f | 368 | |
3d84fdb3 | 369 | #endif /* CONFIG_SPI_MASTER */ |
0b7bb77f | 370 | |
3d84fdb3 | 371 | /*----------------------------------------------------------------------*/ |
0b7bb77f | 372 | |
3d84fdb3 SR |
373 | /* A given spi_device can represent up to eight mcp23sxx chips |
374 | * sharing the same chipselect but using different addresses | |
375 | * (e.g. chips #0 and #3 might be populated, but not #1 or $2). | |
376 | * Driver data holds all the per-chip data. | |
377 | */ | |
378 | struct mcp23s08_driver_data { | |
379 | unsigned ngpio; | |
380 | struct mcp23s08 *mcp[8]; | |
381 | struct mcp23s08 chip[]; | |
0b7bb77f PK |
382 | }; |
383 | ||
e58b9e27 DB |
384 | |
385 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) | |
386 | { | |
9e03cf0b | 387 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
388 | int status; |
389 | ||
390 | mutex_lock(&mcp->lock); | |
8f38910b | 391 | status = mcp_set_bit(mcp, MCP_IODIR, offset, true); |
e58b9e27 | 392 | mutex_unlock(&mcp->lock); |
8f38910b | 393 | |
e58b9e27 DB |
394 | return status; |
395 | } | |
396 | ||
397 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
398 | { | |
9e03cf0b | 399 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
3d84fdb3 | 400 | int status, ret; |
e58b9e27 DB |
401 | |
402 | mutex_lock(&mcp->lock); | |
403 | ||
404 | /* REVISIT reading this clears any IRQ ... */ | |
3d84fdb3 SR |
405 | ret = mcp_read(mcp, MCP_GPIO, &status); |
406 | if (ret < 0) | |
e58b9e27 | 407 | status = 0; |
59861701 DM |
408 | else { |
409 | mcp->cached_gpio = status; | |
e58b9e27 | 410 | status = !!(status & (1 << offset)); |
59861701 | 411 | } |
8f38910b | 412 | |
e58b9e27 DB |
413 | mutex_unlock(&mcp->lock); |
414 | return status; | |
415 | } | |
416 | ||
8f38910b | 417 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) |
e58b9e27 | 418 | { |
8f38910b | 419 | return mcp_set_mask(mcp, MCP_OLAT, mask, value); |
e58b9e27 DB |
420 | } |
421 | ||
422 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
423 | { | |
9e03cf0b | 424 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 425 | unsigned mask = BIT(offset); |
e58b9e27 DB |
426 | |
427 | mutex_lock(&mcp->lock); | |
8f38910b | 428 | __mcp23s08_set(mcp, mask, !!value); |
e58b9e27 DB |
429 | mutex_unlock(&mcp->lock); |
430 | } | |
431 | ||
432 | static int | |
433 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
434 | { | |
9e03cf0b | 435 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 436 | unsigned mask = BIT(offset); |
e58b9e27 DB |
437 | int status; |
438 | ||
439 | mutex_lock(&mcp->lock); | |
440 | status = __mcp23s08_set(mcp, mask, value); | |
441 | if (status == 0) { | |
8f38910b | 442 | status = mcp_set_mask(mcp, MCP_IODIR, mask, false); |
e58b9e27 DB |
443 | } |
444 | mutex_unlock(&mcp->lock); | |
445 | return status; | |
446 | } | |
447 | ||
4e47f91b LP |
448 | /*----------------------------------------------------------------------*/ |
449 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
450 | { | |
451 | struct mcp23s08 *mcp = data; | |
8f38910b | 452 | int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; |
4e47f91b | 453 | unsigned int child_irq; |
2cd29f23 RM |
454 | bool intf_set, intcap_changed, gpio_bit_changed, |
455 | defval_changed, gpio_set; | |
4e47f91b LP |
456 | |
457 | mutex_lock(&mcp->lock); | |
3d84fdb3 | 458 | if (mcp_read(mcp, MCP_INTF, &intf) < 0) { |
4e47f91b LP |
459 | mutex_unlock(&mcp->lock); |
460 | return IRQ_HANDLED; | |
461 | } | |
462 | ||
3d84fdb3 | 463 | if (mcp_read(mcp, MCP_INTCAP, &intcap) < 0) { |
4e47f91b LP |
464 | mutex_unlock(&mcp->lock); |
465 | return IRQ_HANDLED; | |
466 | } | |
467 | ||
8f38910b SR |
468 | if (mcp_read(mcp, MCP_INTCON, &intcon) < 0) { |
469 | mutex_unlock(&mcp->lock); | |
470 | return IRQ_HANDLED; | |
471 | } | |
472 | ||
473 | if (mcp_read(mcp, MCP_DEFVAL, &defval) < 0) { | |
474 | mutex_unlock(&mcp->lock); | |
475 | return IRQ_HANDLED; | |
476 | } | |
2cd29f23 RM |
477 | |
478 | /* This clears the interrupt(configurable on S18) */ | |
479 | if (mcp_read(mcp, MCP_GPIO, &gpio) < 0) { | |
480 | mutex_unlock(&mcp->lock); | |
481 | return IRQ_HANDLED; | |
482 | } | |
8f38910b SR |
483 | gpio_orig = mcp->cached_gpio; |
484 | mcp->cached_gpio = gpio; | |
4e47f91b LP |
485 | mutex_unlock(&mcp->lock); |
486 | ||
8f38910b | 487 | if (intf == 0) { |
2cd29f23 RM |
488 | /* There is no interrupt pending */ |
489 | return IRQ_HANDLED; | |
490 | } | |
491 | ||
492 | dev_dbg(mcp->chip.parent, | |
493 | "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", | |
494 | intcap, intf, gpio_orig, gpio); | |
4e47f91b LP |
495 | |
496 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
2cd29f23 RM |
497 | /* We must check all of the inputs on the chip, |
498 | * otherwise we may not notice a change on >=2 pins. | |
499 | * | |
500 | * On at least the mcp23s17, INTCAP is only updated | |
501 | * one byte at a time(INTCAPA and INTCAPB are | |
502 | * not written to at the same time - only on a per-bank | |
503 | * basis). | |
504 | * | |
505 | * INTF only contains the single bit that caused the | |
506 | * interrupt per-bank. On the mcp23s17, there is | |
507 | * INTFA and INTFB. If two pins are changed on the A | |
508 | * side at the same time, INTF will only have one bit | |
509 | * set. If one pin on the A side and one pin on the B | |
510 | * side are changed at the same time, INTF will have | |
511 | * two bits set. Thus, INTF can't be the only check | |
512 | * to see if the input has changed. | |
513 | */ | |
514 | ||
8f38910b | 515 | intf_set = intf & BIT(i); |
2cd29f23 RM |
516 | if (i < 8 && intf_set) |
517 | intcap_mask = 0x00FF; | |
518 | else if (i >= 8 && intf_set) | |
519 | intcap_mask = 0xFF00; | |
520 | else | |
521 | intcap_mask = 0x00; | |
522 | ||
523 | intcap_changed = (intcap_mask & | |
8f38910b | 524 | (intcap & BIT(i))) != |
2cd29f23 | 525 | (intcap_mask & (BIT(i) & gpio_orig)); |
8f38910b | 526 | gpio_set = BIT(i) & gpio; |
2cd29f23 | 527 | gpio_bit_changed = (BIT(i) & gpio_orig) != |
8f38910b SR |
528 | (BIT(i) & gpio); |
529 | defval_changed = (BIT(i) & intcon) && | |
530 | ((BIT(i) & gpio) != | |
531 | (BIT(i) & defval)); | |
2cd29f23 RM |
532 | |
533 | if (((gpio_bit_changed || intcap_changed) && | |
534 | (BIT(i) & mcp->irq_rise) && gpio_set) || | |
535 | ((gpio_bit_changed || intcap_changed) && | |
536 | (BIT(i) & mcp->irq_fall) && !gpio_set) || | |
537 | defval_changed) { | |
f0fbe7bc | 538 | child_irq = irq_find_mapping(mcp->chip.irq.domain, i); |
4e47f91b LP |
539 | handle_nested_irq(child_irq); |
540 | } | |
541 | } | |
542 | ||
543 | return IRQ_HANDLED; | |
544 | } | |
545 | ||
4e47f91b LP |
546 | static void mcp23s08_irq_mask(struct irq_data *data) |
547 | { | |
dad3d272 PR |
548 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
549 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
550 | unsigned int pos = data->hwirq; |
551 | ||
8f38910b | 552 | mcp_set_bit(mcp, MCP_GPINTEN, pos, false); |
4e47f91b LP |
553 | } |
554 | ||
555 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
556 | { | |
dad3d272 PR |
557 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
558 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
559 | unsigned int pos = data->hwirq; |
560 | ||
8f38910b | 561 | mcp_set_bit(mcp, MCP_GPINTEN, pos, true); |
4e47f91b LP |
562 | } |
563 | ||
564 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
565 | { | |
dad3d272 PR |
566 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
567 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
568 | unsigned int pos = data->hwirq; |
569 | int status = 0; | |
570 | ||
571 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
8f38910b | 572 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
573 | mcp->irq_rise |= BIT(pos); |
574 | mcp->irq_fall |= BIT(pos); | |
575 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
8f38910b | 576 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
577 | mcp->irq_rise |= BIT(pos); |
578 | mcp->irq_fall &= ~BIT(pos); | |
579 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
8f38910b | 580 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
581 | mcp->irq_rise &= ~BIT(pos); |
582 | mcp->irq_fall |= BIT(pos); | |
16fe1ad2 | 583 | } else if (type & IRQ_TYPE_LEVEL_HIGH) { |
8f38910b SR |
584 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
585 | mcp_set_bit(mcp, MCP_DEFVAL, pos, false); | |
16fe1ad2 | 586 | } else if (type & IRQ_TYPE_LEVEL_LOW) { |
8f38910b SR |
587 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
588 | mcp_set_bit(mcp, MCP_DEFVAL, pos, true); | |
4e47f91b LP |
589 | } else |
590 | return -EINVAL; | |
591 | ||
592 | return status; | |
593 | } | |
594 | ||
595 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
596 | { | |
dad3d272 PR |
597 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
598 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 599 | |
8f38910b SR |
600 | mutex_lock(&mcp->lock); |
601 | regcache_cache_only(mcp->regmap, true); | |
4e47f91b LP |
602 | } |
603 | ||
604 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
605 | { | |
dad3d272 PR |
606 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
607 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 608 | |
8f38910b SR |
609 | regcache_cache_only(mcp->regmap, false); |
610 | regcache_sync(mcp->regmap); | |
611 | ||
4e47f91b | 612 | mutex_unlock(&mcp->lock); |
4e47f91b LP |
613 | } |
614 | ||
4e47f91b LP |
615 | static struct irq_chip mcp23s08_irq_chip = { |
616 | .name = "gpio-mcp23xxx", | |
617 | .irq_mask = mcp23s08_irq_mask, | |
618 | .irq_unmask = mcp23s08_irq_unmask, | |
619 | .irq_set_type = mcp23s08_irq_set_type, | |
620 | .irq_bus_lock = mcp23s08_irq_bus_lock, | |
621 | .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock, | |
4e47f91b LP |
622 | }; |
623 | ||
624 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) | |
625 | { | |
626 | struct gpio_chip *chip = &mcp->chip; | |
dad3d272 | 627 | int err; |
a4e63554 | 628 | unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; |
4e47f91b | 629 | |
a4e63554 AS |
630 | if (mcp->irq_active_high) |
631 | irqflags |= IRQF_TRIGGER_HIGH; | |
632 | else | |
633 | irqflags |= IRQF_TRIGGER_LOW; | |
634 | ||
58383c78 LW |
635 | err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, |
636 | mcp23s08_irq, | |
637 | irqflags, dev_name(chip->parent), mcp); | |
4e47f91b | 638 | if (err != 0) { |
58383c78 | 639 | dev_err(chip->parent, "unable to request IRQ#%d: %d\n", |
4e47f91b LP |
640 | mcp->irq, err); |
641 | return err; | |
642 | } | |
643 | ||
d245b3f9 LW |
644 | err = gpiochip_irqchip_add_nested(chip, |
645 | &mcp23s08_irq_chip, | |
646 | 0, | |
647 | handle_simple_irq, | |
648 | IRQ_TYPE_NONE); | |
dad3d272 PR |
649 | if (err) { |
650 | dev_err(chip->parent, | |
651 | "could not connect irqchip to gpiochip: %d\n", err); | |
652 | return err; | |
4e47f91b | 653 | } |
4e47f91b | 654 | |
d245b3f9 LW |
655 | gpiochip_set_nested_irqchip(chip, |
656 | &mcp23s08_irq_chip, | |
657 | mcp->irq); | |
4e47f91b | 658 | |
dad3d272 | 659 | return 0; |
4e47f91b LP |
660 | } |
661 | ||
e58b9e27 DB |
662 | /*----------------------------------------------------------------------*/ |
663 | ||
664 | #ifdef CONFIG_DEBUG_FS | |
665 | ||
666 | #include <linux/seq_file.h> | |
667 | ||
8f38910b SR |
668 | /* |
669 | * This compares the chip's registers with the register | |
670 | * cache and corrects any incorrectly set register. This | |
671 | * can be used to fix state for MCP23xxx, that temporary | |
672 | * lost its power supply. | |
673 | */ | |
674 | #define MCP23S08_CONFIG_REGS 8 | |
675 | static int __check_mcp23s08_reg_cache(struct mcp23s08 *mcp) | |
676 | { | |
677 | int cached[MCP23S08_CONFIG_REGS]; | |
678 | int err = 0, i; | |
679 | ||
680 | /* read cached config registers */ | |
681 | for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { | |
682 | err = mcp_read(mcp, i, &cached[i]); | |
683 | if (err) | |
684 | goto out; | |
685 | } | |
686 | ||
687 | regcache_cache_bypass(mcp->regmap, true); | |
688 | ||
689 | for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { | |
690 | int uncached; | |
691 | err = mcp_read(mcp, i, &uncached); | |
692 | if (err) | |
693 | goto out; | |
694 | ||
695 | if (uncached != cached[i]) { | |
696 | dev_err(mcp->dev, "restoring reg 0x%02x from 0x%04x to 0x%04x (power-loss?)\n", | |
697 | i, uncached, cached[i]); | |
698 | mcp_write(mcp, i, cached[i]); | |
699 | } | |
700 | } | |
701 | ||
702 | out: | |
703 | if (err) | |
704 | dev_err(mcp->dev, "read error: reg=%02x, err=%d", i, err); | |
705 | regcache_cache_bypass(mcp->regmap, false); | |
706 | return err; | |
707 | } | |
708 | ||
e58b9e27 DB |
709 | /* |
710 | * This shows more info than the generic gpio dump code: | |
711 | * pullups, deglitching, open drain drive. | |
712 | */ | |
713 | static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
714 | { | |
715 | struct mcp23s08 *mcp; | |
716 | char bank; | |
1d1c1d9b | 717 | int t; |
e58b9e27 | 718 | unsigned mask; |
8f38910b | 719 | int iodir, gpio, gppu; |
e58b9e27 | 720 | |
9e03cf0b | 721 | mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
722 | |
723 | /* NOTE: we only handle one bank for now ... */ | |
0b7bb77f | 724 | bank = '0' + ((mcp->addr >> 1) & 0x7); |
e58b9e27 DB |
725 | |
726 | mutex_lock(&mcp->lock); | |
8f38910b SR |
727 | |
728 | t = __check_mcp23s08_reg_cache(mcp); | |
729 | if (t) { | |
730 | seq_printf(s, " I/O Error\n"); | |
731 | goto done; | |
732 | } | |
733 | t = mcp_read(mcp, MCP_IODIR, &iodir); | |
734 | if (t) { | |
735 | seq_printf(s, " I/O Error\n"); | |
736 | goto done; | |
737 | } | |
738 | t = mcp_read(mcp, MCP_GPIO, &gpio); | |
739 | if (t) { | |
740 | seq_printf(s, " I/O Error\n"); | |
741 | goto done; | |
742 | } | |
743 | t = mcp_read(mcp, MCP_GPPU, &gppu); | |
744 | if (t) { | |
745 | seq_printf(s, " I/O Error\n"); | |
e58b9e27 DB |
746 | goto done; |
747 | } | |
748 | ||
8f38910b SR |
749 | for (t = 0, mask = BIT(0); t < chip->ngpio; t++, mask <<= 1) { |
750 | const char *label; | |
e58b9e27 DB |
751 | |
752 | label = gpiochip_is_requested(chip, t); | |
753 | if (!label) | |
754 | continue; | |
755 | ||
756 | seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", | |
757 | chip->base + t, bank, t, label, | |
8f38910b SR |
758 | (iodir & mask) ? "in " : "out", |
759 | (gpio & mask) ? "hi" : "lo", | |
760 | (gppu & mask) ? "up" : " "); | |
e58b9e27 | 761 | /* NOTE: ignoring the irq-related registers */ |
33bc8411 | 762 | seq_puts(s, "\n"); |
e58b9e27 DB |
763 | } |
764 | done: | |
765 | mutex_unlock(&mcp->lock); | |
766 | } | |
767 | ||
768 | #else | |
769 | #define mcp23s08_dbg_show NULL | |
770 | #endif | |
771 | ||
772 | /*----------------------------------------------------------------------*/ | |
773 | ||
d62b98f3 | 774 | static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
4e47f91b | 775 | void *data, unsigned addr, unsigned type, |
5b1a7e80 | 776 | unsigned int base, int cs) |
e58b9e27 | 777 | { |
3d84fdb3 | 778 | int status, ret; |
4e47f91b | 779 | bool mirror = false; |
e58b9e27 | 780 | |
e58b9e27 DB |
781 | mutex_init(&mcp->lock); |
782 | ||
3d84fdb3 | 783 | mcp->dev = dev; |
d62b98f3 | 784 | mcp->addr = addr; |
a4e63554 | 785 | mcp->irq_active_high = false; |
e58b9e27 | 786 | |
e58b9e27 DB |
787 | mcp->chip.direction_input = mcp23s08_direction_input; |
788 | mcp->chip.get = mcp23s08_get; | |
789 | mcp->chip.direction_output = mcp23s08_direction_output; | |
790 | mcp->chip.set = mcp23s08_set; | |
791 | mcp->chip.dbg_show = mcp23s08_dbg_show; | |
60f749f8 | 792 | #ifdef CONFIG_OF_GPIO |
97ddb1c8 LP |
793 | mcp->chip.of_gpio_n_cells = 2; |
794 | mcp->chip.of_node = dev->of_node; | |
795 | #endif | |
e58b9e27 | 796 | |
d62b98f3 PK |
797 | switch (type) { |
798 | #ifdef CONFIG_SPI_MASTER | |
799 | case MCP_TYPE_S08: | |
3d84fdb3 SR |
800 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
801 | &mcp23x08_regmap); | |
802 | mcp->reg_shift = 0; | |
0b7bb77f PK |
803 | mcp->chip.ngpio = 8; |
804 | mcp->chip.label = "mcp23s08"; | |
d62b98f3 PK |
805 | break; |
806 | ||
807 | case MCP_TYPE_S17: | |
3d84fdb3 SR |
808 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
809 | &mcp23x17_regmap); | |
810 | mcp->reg_shift = 1; | |
d62b98f3 PK |
811 | mcp->chip.ngpio = 16; |
812 | mcp->chip.label = "mcp23s17"; | |
813 | break; | |
28c5a41e PR |
814 | |
815 | case MCP_TYPE_S18: | |
3d84fdb3 SR |
816 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
817 | &mcp23x17_regmap); | |
818 | mcp->reg_shift = 1; | |
28c5a41e PR |
819 | mcp->chip.ngpio = 16; |
820 | mcp->chip.label = "mcp23s18"; | |
821 | break; | |
d62b98f3 PK |
822 | #endif /* CONFIG_SPI_MASTER */ |
823 | ||
cbf24fad | 824 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 825 | case MCP_TYPE_008: |
3d84fdb3 SR |
826 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); |
827 | mcp->reg_shift = 0; | |
752ad5e8 PK |
828 | mcp->chip.ngpio = 8; |
829 | mcp->chip.label = "mcp23008"; | |
830 | break; | |
831 | ||
832 | case MCP_TYPE_017: | |
3d84fdb3 SR |
833 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); |
834 | mcp->reg_shift = 1; | |
752ad5e8 PK |
835 | mcp->chip.ngpio = 16; |
836 | mcp->chip.label = "mcp23017"; | |
837 | break; | |
ff0f2ce7 PR |
838 | |
839 | case MCP_TYPE_018: | |
840 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); | |
841 | mcp->reg_shift = 1; | |
842 | mcp->chip.ngpio = 16; | |
843 | mcp->chip.label = "mcp23018"; | |
844 | break; | |
752ad5e8 PK |
845 | #endif /* CONFIG_I2C */ |
846 | ||
d62b98f3 PK |
847 | default: |
848 | dev_err(dev, "invalid device type (%d)\n", type); | |
849 | return -EINVAL; | |
0b7bb77f | 850 | } |
d62b98f3 | 851 | |
3d84fdb3 SR |
852 | if (IS_ERR(mcp->regmap)) |
853 | return PTR_ERR(mcp->regmap); | |
854 | ||
5b1a7e80 | 855 | mcp->chip.base = base; |
9fb1f39e | 856 | mcp->chip.can_sleep = true; |
58383c78 | 857 | mcp->chip.parent = dev; |
d72cbed0 | 858 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 859 | |
8f1cc3b1 DB |
860 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
861 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
862 | */ | |
4e47f91b | 863 | |
3d84fdb3 SR |
864 | ret = mcp_read(mcp, MCP_IOCON, &status); |
865 | if (ret < 0) | |
e58b9e27 | 866 | goto fail; |
4e47f91b | 867 | |
5b1a7e80 SR |
868 | mcp->irq_controller = |
869 | device_property_read_bool(dev, "interrupt-controller"); | |
a4e63554 | 870 | if (mcp->irq && mcp->irq_controller) { |
170680ab | 871 | mcp->irq_active_high = |
5b1a7e80 | 872 | device_property_read_bool(dev, |
170680ab | 873 | "microchip,irq-active-high"); |
4e47f91b | 874 | |
5b1a7e80 | 875 | mirror = device_property_read_bool(dev, "microchip,irq-mirror"); |
a4e63554 AS |
876 | } |
877 | ||
878 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || | |
879 | mcp->irq_active_high) { | |
0b7bb77f PK |
880 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
881 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
882 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
a4e63554 AS |
883 | if (mcp->irq_active_high) |
884 | status |= IOCON_INTPOL | (IOCON_INTPOL << 8); | |
885 | else | |
886 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); | |
887 | ||
4e47f91b LP |
888 | if (mirror) |
889 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
890 | ||
ff0f2ce7 | 891 | if (type == MCP_TYPE_S18 || type == MCP_TYPE_018) |
3539699c PR |
892 | status |= IOCON_INTCC | (IOCON_INTCC << 8); |
893 | ||
3d84fdb3 SR |
894 | ret = mcp_write(mcp, MCP_IOCON, status); |
895 | if (ret < 0) | |
e58b9e27 DB |
896 | goto fail; |
897 | } | |
898 | ||
d0e49dab | 899 | ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); |
3d84fdb3 | 900 | if (ret < 0) |
4e47f91b LP |
901 | goto fail; |
902 | ||
903 | if (mcp->irq && mcp->irq_controller) { | |
3d84fdb3 SR |
904 | ret = mcp23s08_irq_setup(mcp); |
905 | if (ret) | |
4e47f91b | 906 | goto fail; |
4e47f91b | 907 | } |
82039d24 SR |
908 | |
909 | mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; | |
910 | mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; | |
911 | mcp->pinctrl_desc.confops = &mcp_pinconf_ops; | |
912 | mcp->pinctrl_desc.npins = mcp->chip.ngpio; | |
913 | if (mcp->pinctrl_desc.npins == 8) | |
914 | mcp->pinctrl_desc.pins = mcp23x08_pins; | |
915 | else if (mcp->pinctrl_desc.npins == 16) | |
916 | mcp->pinctrl_desc.pins = mcp23x17_pins; | |
917 | mcp->pinctrl_desc.owner = THIS_MODULE; | |
918 | ||
919 | mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); | |
920 | if (IS_ERR(mcp->pctldev)) { | |
921 | ret = PTR_ERR(mcp->pctldev); | |
922 | goto fail; | |
923 | } | |
924 | ||
8f1cc3b1 | 925 | fail: |
3d84fdb3 SR |
926 | if (ret < 0) |
927 | dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); | |
928 | return ret; | |
8f1cc3b1 DB |
929 | } |
930 | ||
752ad5e8 PK |
931 | /*----------------------------------------------------------------------*/ |
932 | ||
97ddb1c8 LP |
933 | #ifdef CONFIG_OF |
934 | #ifdef CONFIG_SPI_MASTER | |
ac791804 | 935 | static const struct of_device_id mcp23s08_spi_of_match[] = { |
97ddb1c8 | 936 | { |
45971686 LP |
937 | .compatible = "microchip,mcp23s08", |
938 | .data = (void *) MCP_TYPE_S08, | |
97ddb1c8 LP |
939 | }, |
940 | { | |
45971686 LP |
941 | .compatible = "microchip,mcp23s17", |
942 | .data = (void *) MCP_TYPE_S17, | |
943 | }, | |
28c5a41e PR |
944 | { |
945 | .compatible = "microchip,mcp23s18", | |
946 | .data = (void *) MCP_TYPE_S18, | |
947 | }, | |
45971686 LP |
948 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ |
949 | { | |
950 | .compatible = "mcp,mcp23s08", | |
951 | .data = (void *) MCP_TYPE_S08, | |
952 | }, | |
953 | { | |
954 | .compatible = "mcp,mcp23s17", | |
955 | .data = (void *) MCP_TYPE_S17, | |
97ddb1c8 LP |
956 | }, |
957 | { }, | |
958 | }; | |
959 | MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); | |
960 | #endif | |
961 | ||
962 | #if IS_ENABLED(CONFIG_I2C) | |
ac791804 | 963 | static const struct of_device_id mcp23s08_i2c_of_match[] = { |
97ddb1c8 | 964 | { |
45971686 LP |
965 | .compatible = "microchip,mcp23008", |
966 | .data = (void *) MCP_TYPE_008, | |
97ddb1c8 LP |
967 | }, |
968 | { | |
45971686 LP |
969 | .compatible = "microchip,mcp23017", |
970 | .data = (void *) MCP_TYPE_017, | |
971 | }, | |
ff0f2ce7 PR |
972 | { |
973 | .compatible = "microchip,mcp23018", | |
974 | .data = (void *) MCP_TYPE_018, | |
975 | }, | |
45971686 LP |
976 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ |
977 | { | |
978 | .compatible = "mcp,mcp23008", | |
979 | .data = (void *) MCP_TYPE_008, | |
980 | }, | |
981 | { | |
982 | .compatible = "mcp,mcp23017", | |
983 | .data = (void *) MCP_TYPE_017, | |
97ddb1c8 LP |
984 | }, |
985 | { }, | |
986 | }; | |
987 | MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); | |
988 | #endif | |
989 | #endif /* CONFIG_OF */ | |
990 | ||
991 | ||
cbf24fad | 992 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 993 | |
3836309d | 994 | static int mcp230xx_probe(struct i2c_client *client, |
752ad5e8 PK |
995 | const struct i2c_device_id *id) |
996 | { | |
3af0dbd5 | 997 | struct mcp23s08_platform_data *pdata, local_pdata; |
752ad5e8 | 998 | struct mcp23s08 *mcp; |
3af0dbd5 | 999 | int status; |
97ddb1c8 | 1000 | |
5f853acf SR |
1001 | pdata = dev_get_platdata(&client->dev); |
1002 | if (!pdata) { | |
3af0dbd5 SZ |
1003 | pdata = &local_pdata; |
1004 | pdata->base = -1; | |
752ad5e8 PK |
1005 | } |
1006 | ||
2f98e78b | 1007 | mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); |
752ad5e8 PK |
1008 | if (!mcp) |
1009 | return -ENOMEM; | |
1010 | ||
4e47f91b | 1011 | mcp->irq = client->irq; |
752ad5e8 | 1012 | status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, |
5b1a7e80 | 1013 | id->driver_data, pdata->base, 0); |
752ad5e8 | 1014 | if (status) |
2f98e78b | 1015 | return status; |
752ad5e8 PK |
1016 | |
1017 | i2c_set_clientdata(client, mcp); | |
1018 | ||
1019 | return 0; | |
752ad5e8 PK |
1020 | } |
1021 | ||
752ad5e8 PK |
1022 | static const struct i2c_device_id mcp230xx_id[] = { |
1023 | { "mcp23008", MCP_TYPE_008 }, | |
1024 | { "mcp23017", MCP_TYPE_017 }, | |
ff0f2ce7 | 1025 | { "mcp23018", MCP_TYPE_018 }, |
752ad5e8 PK |
1026 | { }, |
1027 | }; | |
1028 | MODULE_DEVICE_TABLE(i2c, mcp230xx_id); | |
1029 | ||
1030 | static struct i2c_driver mcp230xx_driver = { | |
1031 | .driver = { | |
1032 | .name = "mcp230xx", | |
97ddb1c8 | 1033 | .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), |
752ad5e8 PK |
1034 | }, |
1035 | .probe = mcp230xx_probe, | |
752ad5e8 PK |
1036 | .id_table = mcp230xx_id, |
1037 | }; | |
1038 | ||
1039 | static int __init mcp23s08_i2c_init(void) | |
1040 | { | |
1041 | return i2c_add_driver(&mcp230xx_driver); | |
1042 | } | |
1043 | ||
1044 | static void mcp23s08_i2c_exit(void) | |
1045 | { | |
1046 | i2c_del_driver(&mcp230xx_driver); | |
1047 | } | |
1048 | ||
1049 | #else | |
1050 | ||
1051 | static int __init mcp23s08_i2c_init(void) { return 0; } | |
1052 | static void mcp23s08_i2c_exit(void) { } | |
1053 | ||
1054 | #endif /* CONFIG_I2C */ | |
1055 | ||
1056 | /*----------------------------------------------------------------------*/ | |
1057 | ||
d62b98f3 PK |
1058 | #ifdef CONFIG_SPI_MASTER |
1059 | ||
8f1cc3b1 DB |
1060 | static int mcp23s08_probe(struct spi_device *spi) |
1061 | { | |
3af0dbd5 | 1062 | struct mcp23s08_platform_data *pdata, local_pdata; |
8f1cc3b1 | 1063 | unsigned addr; |
596a1c5f | 1064 | int chips = 0; |
8f1cc3b1 | 1065 | struct mcp23s08_driver_data *data; |
0b7bb77f | 1066 | int status, type; |
3af0dbd5 | 1067 | unsigned ngpio = 0; |
97ddb1c8 | 1068 | const struct of_device_id *match; |
97ddb1c8 LP |
1069 | |
1070 | match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); | |
0d7fcd50 | 1071 | if (match) |
de755c33 | 1072 | type = (int)(uintptr_t)match->data; |
0d7fcd50 SR |
1073 | else |
1074 | type = spi_get_device_id(spi)->driver_data; | |
1075 | ||
1076 | pdata = dev_get_platdata(&spi->dev); | |
1077 | if (!pdata) { | |
1078 | pdata = &local_pdata; | |
1079 | pdata->base = -1; | |
1080 | ||
0d7fcd50 | 1081 | status = device_property_read_u32(&spi->dev, |
ce9bd0a0 | 1082 | "microchip,spi-present-mask", &pdata->spi_present_mask); |
97ddb1c8 | 1083 | if (status) { |
0d7fcd50 | 1084 | status = device_property_read_u32(&spi->dev, |
ce9bd0a0 SR |
1085 | "mcp,spi-present-mask", |
1086 | &pdata->spi_present_mask); | |
0d7fcd50 | 1087 | |
45971686 | 1088 | if (status) { |
0d7fcd50 | 1089 | dev_err(&spi->dev, "missing spi-present-mask"); |
45971686 LP |
1090 | return -ENODEV; |
1091 | } | |
97ddb1c8 | 1092 | } |
8f1cc3b1 | 1093 | } |
8f1cc3b1 | 1094 | |
ce9bd0a0 | 1095 | if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { |
0d7fcd50 SR |
1096 | dev_err(&spi->dev, "invalid spi-present-mask"); |
1097 | return -ENODEV; | |
1098 | } | |
1099 | ||
ce9bd0a0 SR |
1100 | for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { |
1101 | if (pdata->spi_present_mask & BIT(addr)) | |
0d7fcd50 SR |
1102 | chips++; |
1103 | } | |
1104 | ||
99e4b98d MW |
1105 | if (!chips) |
1106 | return -ENODEV; | |
1107 | ||
7898b31e VB |
1108 | data = devm_kzalloc(&spi->dev, |
1109 | sizeof(*data) + chips * sizeof(struct mcp23s08), | |
1110 | GFP_KERNEL); | |
8f1cc3b1 DB |
1111 | if (!data) |
1112 | return -ENOMEM; | |
7898b31e | 1113 | |
8f1cc3b1 DB |
1114 | spi_set_drvdata(spi, data); |
1115 | ||
ce9bd0a0 SR |
1116 | for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { |
1117 | if (!(pdata->spi_present_mask & BIT(addr))) | |
8f1cc3b1 DB |
1118 | continue; |
1119 | chips--; | |
1120 | data->mcp[addr] = &data->chip[chips]; | |
a231b88c | 1121 | data->mcp[addr]->irq = spi->irq; |
d62b98f3 | 1122 | status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, |
5b1a7e80 SR |
1123 | 0x40 | (addr << 1), type, |
1124 | pdata->base, addr); | |
8f1cc3b1 | 1125 | if (status < 0) |
d0e49dab | 1126 | return status; |
0b7bb77f | 1127 | |
3af0dbd5 | 1128 | if (pdata->base != -1) |
28c5a41e PR |
1129 | pdata->base += data->mcp[addr]->chip.ngpio; |
1130 | ngpio += data->mcp[addr]->chip.ngpio; | |
8f1cc3b1 | 1131 | } |
97ddb1c8 | 1132 | data->ngpio = ngpio; |
e58b9e27 | 1133 | |
e58b9e27 | 1134 | return 0; |
e58b9e27 DB |
1135 | } |
1136 | ||
0b7bb77f PK |
1137 | static const struct spi_device_id mcp23s08_ids[] = { |
1138 | { "mcp23s08", MCP_TYPE_S08 }, | |
1139 | { "mcp23s17", MCP_TYPE_S17 }, | |
28c5a41e | 1140 | { "mcp23s18", MCP_TYPE_S18 }, |
0b7bb77f PK |
1141 | { }, |
1142 | }; | |
1143 | MODULE_DEVICE_TABLE(spi, mcp23s08_ids); | |
1144 | ||
e58b9e27 DB |
1145 | static struct spi_driver mcp23s08_driver = { |
1146 | .probe = mcp23s08_probe, | |
0b7bb77f | 1147 | .id_table = mcp23s08_ids, |
e58b9e27 DB |
1148 | .driver = { |
1149 | .name = "mcp23s08", | |
97ddb1c8 | 1150 | .of_match_table = of_match_ptr(mcp23s08_spi_of_match), |
e58b9e27 DB |
1151 | }, |
1152 | }; | |
1153 | ||
d62b98f3 PK |
1154 | static int __init mcp23s08_spi_init(void) |
1155 | { | |
1156 | return spi_register_driver(&mcp23s08_driver); | |
1157 | } | |
1158 | ||
1159 | static void mcp23s08_spi_exit(void) | |
1160 | { | |
1161 | spi_unregister_driver(&mcp23s08_driver); | |
1162 | } | |
1163 | ||
1164 | #else | |
1165 | ||
1166 | static int __init mcp23s08_spi_init(void) { return 0; } | |
1167 | static void mcp23s08_spi_exit(void) { } | |
1168 | ||
1169 | #endif /* CONFIG_SPI_MASTER */ | |
1170 | ||
e58b9e27 DB |
1171 | /*----------------------------------------------------------------------*/ |
1172 | ||
1173 | static int __init mcp23s08_init(void) | |
1174 | { | |
752ad5e8 PK |
1175 | int ret; |
1176 | ||
1177 | ret = mcp23s08_spi_init(); | |
1178 | if (ret) | |
1179 | goto spi_fail; | |
1180 | ||
1181 | ret = mcp23s08_i2c_init(); | |
1182 | if (ret) | |
1183 | goto i2c_fail; | |
1184 | ||
1185 | return 0; | |
1186 | ||
1187 | i2c_fail: | |
1188 | mcp23s08_spi_exit(); | |
1189 | spi_fail: | |
1190 | return ret; | |
e58b9e27 | 1191 | } |
752ad5e8 | 1192 | /* register after spi/i2c postcore initcall and before |
673c0c00 DB |
1193 | * subsys initcalls that may rely on these GPIOs |
1194 | */ | |
1195 | subsys_initcall(mcp23s08_init); | |
e58b9e27 DB |
1196 | |
1197 | static void __exit mcp23s08_exit(void) | |
1198 | { | |
d62b98f3 | 1199 | mcp23s08_spi_exit(); |
752ad5e8 | 1200 | mcp23s08_i2c_exit(); |
e58b9e27 DB |
1201 | } |
1202 | module_exit(mcp23s08_exit); | |
1203 | ||
1204 | MODULE_LICENSE("GPL"); |