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Merge tag 'platform-drivers-x86-v6.8-3' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / pinctrl / pinctrl-mcp23s08.c
CommitLineData
09c434b8 1// SPDX-License-Identifier: GPL-2.0-only
d8f4494e 2/* MCP23S08 SPI/I2C GPIO driver */
e58b9e27 3
7b04aaaf 4#include <linux/bitops.h>
e58b9e27
DB		 5#include <linux/kernel.h>
6#include <linux/device.h>
e58b9e27 7#include <linux/mutex.h>
1ac30db2 8#include <linux/mod_devicetable.h>
bb207ef1 9#include <linux/module.h>
0f04a817 10#include <linux/export.h>
1c5fb66a 11#include <linux/gpio/driver.h>
4e73bfa3 12#include <linux/gpio/consumer.h>
cca973a8 13#include <linux/seq_file.h>
5a0e3ad6 14#include <linux/slab.h>
0b7bb77f 15#include <asm/byteorder.h>
4e47f91b 16#include <linux/interrupt.h>
3d84fdb3 17#include <linux/regmap.h>
82039d24
SR		 18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
e58b9e27 21
0f04a817 22#include "pinctrl-mcp23s08.h"
e58b9e27
DB		 23
24/* Registers are all 8 bits wide.
25 *
26 * The mcp23s17 has twice as many bits, and can be configured to work
27 * with either 16 bit registers or with two adjacent 8 bit banks.
e58b9e27
DB		 28 */
29#define MCP_IODIR 0x00 /* init/reset: all ones */
30#define MCP_IPOL 0x01
31#define MCP_GPINTEN 0x02
32#define MCP_DEFVAL 0x03
33#define MCP_INTCON 0x04
34#define MCP_IOCON 0x05
4e47f91b 35# define IOCON_MIRROR (1 << 6)
e58b9e27
DB		 36# define IOCON_SEQOP (1 << 5)
37# define IOCON_HAEN (1 << 3)
38# define IOCON_ODR (1 << 2)
39# define IOCON_INTPOL (1 << 1)
3539699c 40# define IOCON_INTCC (1)
e58b9e27
DB		 41#define MCP_GPPU 0x06
42#define MCP_INTF 0x07
43#define MCP_INTCAP 0x08
44#define MCP_GPIO 0x09
45#define MCP_OLAT 0x0a
46
8f38910b
SR		 47static const struct reg_default mcp23x08_defaults[] = {
48 {.reg = MCP_IODIR, .def = 0xff},
49 {.reg = MCP_IPOL, .def = 0x00},
50 {.reg = MCP_GPINTEN, .def = 0x00},
51 {.reg = MCP_DEFVAL, .def = 0x00},
52 {.reg = MCP_INTCON, .def = 0x00},
53 {.reg = MCP_IOCON, .def = 0x00},
54 {.reg = MCP_GPPU, .def = 0x00},
55 {.reg = MCP_OLAT, .def = 0x00},
56};
57
58static const struct regmap_range mcp23x08_volatile_range = {
59 .range_min = MCP_INTF,
60 .range_max = MCP_GPIO,
61};
62
63static const struct regmap_access_table mcp23x08_volatile_table = {
64 .yes_ranges = &mcp23x08_volatile_range,
65 .n_yes_ranges = 1,
66};
67
68static const struct regmap_range mcp23x08_precious_range = {
69 .range_min = MCP_GPIO,
70 .range_max = MCP_GPIO,
71};
72
73static const struct regmap_access_table mcp23x08_precious_table = {
74 .yes_ranges = &mcp23x08_precious_range,
75 .n_yes_ranges = 1,
76};
77
0f04a817 78const struct regmap_config mcp23x08_regmap = {
3d84fdb3
SR		 79 .reg_bits = 8,
80 .val_bits = 8,
752ad5e8 81
3d84fdb3 82 .reg_stride = 1,
8f38910b
SR		 83 .volatile_table = &mcp23x08_volatile_table,
84 .precious_table = &mcp23x08_precious_table,
85 .reg_defaults = mcp23x08_defaults,
86 .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
87 .cache_type = REGCACHE_FLAT,
3d84fdb3 88 .max_register = MCP_OLAT,
752ad5e8 89};
0f04a817 90EXPORT_SYMBOL_GPL(mcp23x08_regmap);
752ad5e8 91
b445f623 92static const struct reg_default mcp23x17_defaults[] = {
8f38910b
SR		 93 {.reg = MCP_IODIR << 1, .def = 0xffff},
94 {.reg = MCP_IPOL << 1, .def = 0x0000},
95 {.reg = MCP_GPINTEN << 1, .def = 0x0000},
96 {.reg = MCP_DEFVAL << 1, .def = 0x0000},
97 {.reg = MCP_INTCON << 1, .def = 0x0000},
98 {.reg = MCP_IOCON << 1, .def = 0x0000},
99 {.reg = MCP_GPPU << 1, .def = 0x0000},
100 {.reg = MCP_OLAT << 1, .def = 0x0000},
101};
102
b445f623 103static const struct regmap_range mcp23x17_volatile_range = {
8f38910b
SR		 104 .range_min = MCP_INTF << 1,
105 .range_max = MCP_GPIO << 1,
106};
107
b445f623
TP		 108static const struct regmap_access_table mcp23x17_volatile_table = {
109 .yes_ranges = &mcp23x17_volatile_range,
8f38910b
SR		 110 .n_yes_ranges = 1,
111};
112
b445f623 113static const struct regmap_range mcp23x17_precious_range = {
b9b7fb29 114 .range_min = MCP_INTCAP << 1,
8f38910b
SR		 115 .range_max = MCP_GPIO << 1,
116};
117
b445f623
TP		 118static const struct regmap_access_table mcp23x17_precious_table = {
119 .yes_ranges = &mcp23x17_precious_range,
8f38910b
SR		 120 .n_yes_ranges = 1,
121};
122
0f04a817 123const struct regmap_config mcp23x17_regmap = {
3d84fdb3
SR		 124 .reg_bits = 8,
125 .val_bits = 16,
752ad5e8 126
3d84fdb3
SR		 127 .reg_stride = 2,
128 .max_register = MCP_OLAT << 1,
b445f623
TP		 129 .volatile_table = &mcp23x17_volatile_table,
130 .precious_table = &mcp23x17_precious_table,
131 .reg_defaults = mcp23x17_defaults,
132 .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
8f38910b 133 .cache_type = REGCACHE_FLAT,
3d84fdb3
SR		 134 .val_format_endian = REGMAP_ENDIAN_LITTLE,
135};
0f04a817 136EXPORT_SYMBOL_GPL(mcp23x17_regmap);
752ad5e8 137
82039d24
SR		 138static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
139{
140 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
141}
142
143static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
144{
145 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
146}
147
d490be6d
UKK		 148static int mcp_update_bits(struct mcp23s08 *mcp, unsigned int reg,
149 unsigned int mask, unsigned int val)
82039d24 150{
82039d24
SR		 151 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
152 mask, val);
153}
154
8f38910b
SR		 155static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
156 unsigned int pin, bool enabled)
82039d24 157{
8f38910b 158 u16 mask = BIT(pin);
d490be6d 159 return mcp_update_bits(mcp, reg, mask, enabled ? mask : 0);
82039d24
SR		 160}
161
162static const struct pinctrl_pin_desc mcp23x08_pins[] = {
163 PINCTRL_PIN(0, "gpio0"),
164 PINCTRL_PIN(1, "gpio1"),
165 PINCTRL_PIN(2, "gpio2"),
166 PINCTRL_PIN(3, "gpio3"),
167 PINCTRL_PIN(4, "gpio4"),
168 PINCTRL_PIN(5, "gpio5"),
169 PINCTRL_PIN(6, "gpio6"),
170 PINCTRL_PIN(7, "gpio7"),
171};
172
173static const struct pinctrl_pin_desc mcp23x17_pins[] = {
174 PINCTRL_PIN(0, "gpio0"),
175 PINCTRL_PIN(1, "gpio1"),
176 PINCTRL_PIN(2, "gpio2"),
177 PINCTRL_PIN(3, "gpio3"),
178 PINCTRL_PIN(4, "gpio4"),
179 PINCTRL_PIN(5, "gpio5"),
180 PINCTRL_PIN(6, "gpio6"),
181 PINCTRL_PIN(7, "gpio7"),
182 PINCTRL_PIN(8, "gpio8"),
183 PINCTRL_PIN(9, "gpio9"),
184 PINCTRL_PIN(10, "gpio10"),
185 PINCTRL_PIN(11, "gpio11"),
186 PINCTRL_PIN(12, "gpio12"),
187 PINCTRL_PIN(13, "gpio13"),
188 PINCTRL_PIN(14, "gpio14"),
189 PINCTRL_PIN(15, "gpio15"),
190};
191
192static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
193{
194 return 0;
195}
196
197static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
198 unsigned int group)
199{
200 return NULL;
201}
202
203static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
204 unsigned int group,
205 const unsigned int **pins,
206 unsigned int *num_pins)
207{
208 return -ENOTSUPP;
209}
210
211static const struct pinctrl_ops mcp_pinctrl_ops = {
212 .get_groups_count = mcp_pinctrl_get_groups_count,
213 .get_group_name = mcp_pinctrl_get_group_name,
214 .get_group_pins = mcp_pinctrl_get_group_pins,
215#ifdef CONFIG_OF
216 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
217 .dt_free_map = pinconf_generic_dt_free_map,
218#endif
219};
220
221static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
222 unsigned long *config)
223{
224 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
225 enum pin_config_param param = pinconf_to_config_param(*config);
226 unsigned int data, status;
227 int ret;
228
229 switch (param) {
230 case PIN_CONFIG_BIAS_PULL_UP:
231 ret = mcp_read(mcp, MCP_GPPU, &data);
232 if (ret < 0)
233 return ret;
234 status = (data & BIT(pin)) ? 1 : 0;
235 break;
236 default:
82039d24
SR		 237 return -ENOTSUPP;
238 }
239
240 *config = 0;
241
242 return status ? 0 : -EINVAL;
243}
244
245static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
246 unsigned long *configs, unsigned int num_configs)
247{
248 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
249 enum pin_config_param param;
2a7893c8 250 u32 arg;
82039d24
SR		 251 int ret = 0;
252 int i;
253
254 for (i = 0; i < num_configs; i++) {
255 param = pinconf_to_config_param(configs[i]);
256 arg = pinconf_to_config_argument(configs[i]);
257
258 switch (param) {
259 case PIN_CONFIG_BIAS_PULL_UP:
82039d24
SR		 260 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
261 break;
262 default:
e0e31695 263 dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
82039d24
SR		 264 return -ENOTSUPP;
265 }
266 }
267
268 return ret;
269}
270
271static const struct pinconf_ops mcp_pinconf_ops = {
272 .pin_config_get = mcp_pinconf_get,
273 .pin_config_set = mcp_pinconf_set,
274 .is_generic = true,
275};
276
752ad5e8
PK		 277/*----------------------------------------------------------------------*/
278
e58b9e27
DB		 279static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
280{
9e03cf0b 281 struct mcp23s08 *mcp = gpiochip_get_data(chip);
e58b9e27
DB		 282 int status;
283
284 mutex_lock(&mcp->lock);
8f38910b 285 status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
e58b9e27 286 mutex_unlock(&mcp->lock);
8f38910b 287
e58b9e27
DB		 288 return status;
289}
290
291static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
292{
9e03cf0b 293 struct mcp23s08 *mcp = gpiochip_get_data(chip);
3d84fdb3 294 int status, ret;
e58b9e27
DB		 295
296 mutex_lock(&mcp->lock);
297
298 /* REVISIT reading this clears any IRQ ... */
3d84fdb3
SR		 299 ret = mcp_read(mcp, MCP_GPIO, &status);
300 if (ret < 0)
e58b9e27 301 status = 0;
59861701
DM		 302 else {
303 mcp->cached_gpio = status;
e58b9e27 304 status = !!(status & (1 << offset));
59861701 305 }
8f38910b 306
e58b9e27
DB		 307 mutex_unlock(&mcp->lock);
308 return status;
309}
310
c4582907
UKK		 311static int mcp23s08_get_multiple(struct gpio_chip *chip,
312 unsigned long *mask, unsigned long *bits)
313{
314 struct mcp23s08 *mcp = gpiochip_get_data(chip);
315 unsigned int status;
316 int ret;
317
318 mutex_lock(&mcp->lock);
319
320 /* REVISIT reading this clears any IRQ ... */
321 ret = mcp_read(mcp, MCP_GPIO, &status);
322 if (ret < 0)
323 status = 0;
324 else {
325 mcp->cached_gpio = status;
326 *bits = status;
327 }
328
329 mutex_unlock(&mcp->lock);
330 return ret;
331}
332
8f38910b 333static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
e58b9e27 334{
d490be6d 335 return mcp_update_bits(mcp, MCP_OLAT, mask, value ? mask : 0);
e58b9e27
DB		 336}
337
338static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
339{
9e03cf0b 340 struct mcp23s08 *mcp = gpiochip_get_data(chip);
8f38910b 341 unsigned mask = BIT(offset);
e58b9e27
DB		 342
343 mutex_lock(&mcp->lock);
8f38910b 344 __mcp23s08_set(mcp, mask, !!value);
e58b9e27
DB		 345 mutex_unlock(&mcp->lock);
346}
347
c4582907
UKK		 348static void mcp23s08_set_multiple(struct gpio_chip *chip,
349 unsigned long *mask, unsigned long *bits)
350{
351 struct mcp23s08 *mcp = gpiochip_get_data(chip);
352
353 mutex_lock(&mcp->lock);
354 mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);
355 mutex_unlock(&mcp->lock);
356}
357
e58b9e27
DB		 358static int
359mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
360{
9e03cf0b 361 struct mcp23s08 *mcp = gpiochip_get_data(chip);
8f38910b 362 unsigned mask = BIT(offset);
e58b9e27
DB		 363 int status;
364
365 mutex_lock(&mcp->lock);
366 status = __mcp23s08_set(mcp, mask, value);
367 if (status == 0) {
d490be6d 368 status = mcp_update_bits(mcp, MCP_IODIR, mask, 0);
e58b9e27
DB		 369 }
370 mutex_unlock(&mcp->lock);
371 return status;
372}
373
4e47f91b
LP		 374/*----------------------------------------------------------------------*/
375static irqreturn_t mcp23s08_irq(int irq, void *data)
376{
377 struct mcp23s08 *mcp = data;
8f38910b 378 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
4e47f91b 379 unsigned int child_irq;
2cd29f23
RM		 380 bool intf_set, intcap_changed, gpio_bit_changed,
381 defval_changed, gpio_set;
4e47f91b
LP		 382
383 mutex_lock(&mcp->lock);
7f6f50df
ME		 384 if (mcp_read(mcp, MCP_INTF, &intf))
385 goto unlock;
4e47f91b 386
897120d4
RP		 387 if (intf == 0) {
388 /* There is no interrupt pending */
884af72c 389 goto unlock;
897120d4
RP		 390 }
391
7f6f50df
ME		 392 if (mcp_read(mcp, MCP_INTCAP, &intcap))
393 goto unlock;
4e47f91b 394
7f6f50df
ME		 395 if (mcp_read(mcp, MCP_INTCON, &intcon))
396 goto unlock;
8f38910b 397
7f6f50df
ME		 398 if (mcp_read(mcp, MCP_DEFVAL, &defval))
399 goto unlock;
2cd29f23
RM		 400
401 /* This clears the interrupt(configurable on S18) */
7f6f50df
ME		 402 if (mcp_read(mcp, MCP_GPIO, &gpio))
403 goto unlock;
404
8f38910b
SR		 405 gpio_orig = mcp->cached_gpio;
406 mcp->cached_gpio = gpio;
4e47f91b
LP		 407 mutex_unlock(&mcp->lock);
408
2cd29f23
RM		 409 dev_dbg(mcp->chip.parent,
410 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
411 intcap, intf, gpio_orig, gpio);
4e47f91b
LP		 412
413 for (i = 0; i < mcp->chip.ngpio; i++) {
2cd29f23
RM		 414 /* We must check all of the inputs on the chip,
415 * otherwise we may not notice a change on >=2 pins.
416 *
417 * On at least the mcp23s17, INTCAP is only updated
418 * one byte at a time(INTCAPA and INTCAPB are
419 * not written to at the same time - only on a per-bank
420 * basis).
421 *
422 * INTF only contains the single bit that caused the
423 * interrupt per-bank. On the mcp23s17, there is
424 * INTFA and INTFB. If two pins are changed on the A
425 * side at the same time, INTF will only have one bit
426 * set. If one pin on the A side and one pin on the B
427 * side are changed at the same time, INTF will have
428 * two bits set. Thus, INTF can't be the only check
429 * to see if the input has changed.
430 */
431
8f38910b 432 intf_set = intf & BIT(i);
2cd29f23
RM		 433 if (i < 8 && intf_set)
434 intcap_mask = 0x00FF;
435 else if (i >= 8 && intf_set)
436 intcap_mask = 0xFF00;
437 else
438 intcap_mask = 0x00;
439
440 intcap_changed = (intcap_mask &
8f38910b 441 (intcap & BIT(i))) !=
2cd29f23 442 (intcap_mask & (BIT(i) & gpio_orig));
8f38910b 443 gpio_set = BIT(i) & gpio;
2cd29f23 444 gpio_bit_changed = (BIT(i) & gpio_orig) !=
8f38910b
SR		 445 (BIT(i) & gpio);
446 defval_changed = (BIT(i) & intcon) &&
447 ((BIT(i) & gpio) !=
448 (BIT(i) & defval));
2cd29f23
RM		 449
450 if (((gpio_bit_changed || intcap_changed) &&
451 (BIT(i) & mcp->irq_rise) && gpio_set) ||
452 ((gpio_bit_changed || intcap_changed) &&
453 (BIT(i) & mcp->irq_fall) && !gpio_set) ||
454 defval_changed) {
f0fbe7bc 455 child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
4e47f91b
LP		 456 handle_nested_irq(child_irq);
457 }
458 }
459
460 return IRQ_HANDLED;
7f6f50df
ME		 461
462unlock:
463 mutex_unlock(&mcp->lock);
464 return IRQ_HANDLED;
4e47f91b
LP		 465}
466
4e47f91b
LP		 467static void mcp23s08_irq_mask(struct irq_data *data)
468{
dad3d272
PR		 469 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
470 struct mcp23s08 *mcp = gpiochip_get_data(gc);
cca973a8 471 unsigned int pos = irqd_to_hwirq(data);
4e47f91b 472
8f38910b 473 mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
cca973a8 474 gpiochip_disable_irq(gc, pos);
4e47f91b
LP		 475}
476
477static void mcp23s08_irq_unmask(struct irq_data *data)
478{
dad3d272
PR		 479 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
480 struct mcp23s08 *mcp = gpiochip_get_data(gc);
cca973a8 481 unsigned int pos = irqd_to_hwirq(data);
4e47f91b 482
cca973a8 483 gpiochip_enable_irq(gc, pos);
8f38910b 484 mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
4e47f91b
LP		 485}
486
487static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
488{
dad3d272
PR		 489 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
490 struct mcp23s08 *mcp = gpiochip_get_data(gc);
cca973a8 491 unsigned int pos = irqd_to_hwirq(data);
4e47f91b
LP		 492
493 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
8f38910b 494 mcp_set_bit(mcp, MCP_INTCON, pos, false);
4e47f91b
LP		 495 mcp->irq_rise |= BIT(pos);
496 mcp->irq_fall |= BIT(pos);
497 } else if (type & IRQ_TYPE_EDGE_RISING) {
8f38910b 498 mcp_set_bit(mcp, MCP_INTCON, pos, false);
4e47f91b
LP		 499 mcp->irq_rise |= BIT(pos);
500 mcp->irq_fall &= ~BIT(pos);
501 } else if (type & IRQ_TYPE_EDGE_FALLING) {
8f38910b 502 mcp_set_bit(mcp, MCP_INTCON, pos, false);
4e47f91b
LP		 503 mcp->irq_rise &= ~BIT(pos);
504 mcp->irq_fall |= BIT(pos);
16fe1ad2 505 } else if (type & IRQ_TYPE_LEVEL_HIGH) {
8f38910b
SR		 506 mcp_set_bit(mcp, MCP_INTCON, pos, true);
507 mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
16fe1ad2 508 } else if (type & IRQ_TYPE_LEVEL_LOW) {
8f38910b
SR		 509 mcp_set_bit(mcp, MCP_INTCON, pos, true);
510 mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
4e47f91b
LP		 511 } else
512 return -EINVAL;
513
88af89b5 514 return 0;
4e47f91b
LP		 515}
516
517static void mcp23s08_irq_bus_lock(struct irq_data *data)
518{
dad3d272
PR		 519 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
520 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b 521
8f38910b
SR		 522 mutex_lock(&mcp->lock);
523 regcache_cache_only(mcp->regmap, true);
4e47f91b
LP		 524}
525
526static void mcp23s08_irq_bus_unlock(struct irq_data *data)
527{
dad3d272
PR		 528 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
529 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b 530
8f38910b
SR		 531 regcache_cache_only(mcp->regmap, false);
532 regcache_sync(mcp->regmap);
533
4e47f91b 534 mutex_unlock(&mcp->lock);
4e47f91b
LP		 535}
536
4e47f91b
LP		 537static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
538{
539 struct gpio_chip *chip = &mcp->chip;
dad3d272 540 int err;
a4e63554 541 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
4e47f91b 542
a4e63554
AS		 543 if (mcp->irq_active_high)
544 irqflags |= IRQF_TRIGGER_HIGH;
545 else
546 irqflags |= IRQF_TRIGGER_LOW;
547
58383c78
LW		 548 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
549 mcp23s08_irq,
550 irqflags, dev_name(chip->parent), mcp);
4e47f91b 551 if (err != 0) {
58383c78 552 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
4e47f91b
LP		 553 mcp->irq, err);
554 return err;
555 }
556
f259f896
MF		 557 return 0;
558}
559
cca973a8
LW		 560static void mcp23s08_irq_print_chip(struct irq_data *d, struct seq_file *p)
561{
562 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
563 struct mcp23s08 *mcp = gpiochip_get_data(gc);
564
565 seq_printf(p, dev_name(mcp->dev));
566}
567
568static const struct irq_chip mcp23s08_irq_chip = {
569 .irq_mask = mcp23s08_irq_mask,
570 .irq_unmask = mcp23s08_irq_unmask,
571 .irq_set_type = mcp23s08_irq_set_type,
572 .irq_bus_lock = mcp23s08_irq_bus_lock,
573 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
574 .irq_print_chip = mcp23s08_irq_print_chip,
575 .flags = IRQCHIP_IMMUTABLE,
576 GPIOCHIP_IRQ_RESOURCE_HELPERS,
577};
578
e58b9e27
DB		 579/*----------------------------------------------------------------------*/
580
0f04a817
AS		 581int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
582 unsigned int addr, unsigned int type, unsigned int base)
e58b9e27 583{
3d84fdb3 584 int status, ret;
4e47f91b 585 bool mirror = false;
fa2b7fae 586 bool open_drain = false;
e58b9e27 587
e58b9e27
DB		 588 mutex_init(&mcp->lock);
589
3d84fdb3 590 mcp->dev = dev;
d62b98f3 591 mcp->addr = addr;
84d02e78 592
a4e63554 593 mcp->irq_active_high = false;
e58b9e27 594
e58b9e27
DB		 595 mcp->chip.direction_input = mcp23s08_direction_input;
596 mcp->chip.get = mcp23s08_get;
c4582907 597 mcp->chip.get_multiple = mcp23s08_get_multiple;
e58b9e27
DB		 598 mcp->chip.direction_output = mcp23s08_direction_output;
599 mcp->chip.set = mcp23s08_set;
c4582907 600 mcp->chip.set_multiple = mcp23s08_set_multiple;
e58b9e27 601
5b1a7e80 602 mcp->chip.base = base;
9fb1f39e 603 mcp->chip.can_sleep = true;
58383c78 604 mcp->chip.parent = dev;
d72cbed0 605 mcp->chip.owner = THIS_MODULE;
e58b9e27 606
4e73bfa3
AK		 607 mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
608
8f1cc3b1
DB		 609 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
610 * and MCP_IOCON.HAEN = 1, so we work with all chips.
611 */
4e47f91b 612
3d84fdb3
SR		 613 ret = mcp_read(mcp, MCP_IOCON, &status);
614 if (ret < 0)
ebc25991 615 return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
4e47f91b 616
5b1a7e80
SR		 617 mcp->irq_controller =
618 device_property_read_bool(dev, "interrupt-controller");
a4e63554 619 if (mcp->irq && mcp->irq_controller) {
170680ab 620 mcp->irq_active_high =
5b1a7e80 621 device_property_read_bool(dev,
170680ab 622 "microchip,irq-active-high");
4e47f91b 623
5b1a7e80 624 mirror = device_property_read_bool(dev, "microchip,irq-mirror");
fa2b7fae 625 open_drain = device_property_read_bool(dev, "drive-open-drain");
a4e63554
AS		 626 }
627
628 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
fa2b7fae 629 mcp->irq_active_high || open_drain) {
0b7bb77f
PK		 630 /* mcp23s17 has IOCON twice, make sure they are in sync */
631 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
632 status |= IOCON_HAEN | (IOCON_HAEN << 8);
a4e63554
AS		 633 if (mcp->irq_active_high)
634 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
635 else
636 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
637
4e47f91b
LP		 638 if (mirror)
639 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
640
fa2b7fae
PR		 641 if (open_drain)
642 status |= IOCON_ODR | (IOCON_ODR << 8);
643
ff0f2ce7 644 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
3539699c
PR		 645 status |= IOCON_INTCC | (IOCON_INTCC << 8);
646
3d84fdb3
SR		 647 ret = mcp_write(mcp, MCP_IOCON, status);
648 if (ret < 0)
ebc25991 649 return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
e58b9e27
DB		 650 }
651
4e47f91b 652 if (mcp->irq && mcp->irq_controller) {
57597e15
LW		 653 struct gpio_irq_chip *girq = &mcp->chip.irq;
654
cca973a8 655 gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip);
57597e15
LW		 656 /* This will let us handle the parent IRQ in the driver */
657 girq->parent_handler = NULL;
658 girq->num_parents = 0;
659 girq->parents = NULL;
660 girq->default_type = IRQ_TYPE_NONE;
661 girq->handler = handle_simple_irq;
662 girq->threaded = true;
4e47f91b 663 }
82039d24 664
57597e15
LW		 665 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
666 if (ret < 0)
ebc25991 667 return dev_err_probe(dev, ret, "can't add GPIO chip\n");
57597e15 668
82039d24
SR		 669 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
670 mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
671 mcp->pinctrl_desc.npins = mcp->chip.ngpio;
672 if (mcp->pinctrl_desc.npins == 8)
673 mcp->pinctrl_desc.pins = mcp23x08_pins;
674 else if (mcp->pinctrl_desc.npins == 16)
675 mcp->pinctrl_desc.pins = mcp23x17_pins;
676 mcp->pinctrl_desc.owner = THIS_MODULE;
677
678 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
ebc25991
AS		 679 if (IS_ERR(mcp->pctldev))
680 return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
82039d24 681
ebc25991 682 if (mcp->irq) {
f259f896 683 ret = mcp23s08_irq_setup(mcp);
ebc25991
AS		 684 if (ret)
685 return dev_err_probe(dev, ret, "can't setup IRQ\n");
686 }
f259f896 687
ebc25991 688 return 0;
8f1cc3b1 689}
0f04a817 690EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
ebc25991 691
7045e673 692MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)