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75a6faf6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2df723d4 LD |
2 | /* |
3 | * MAX77620 pin control driver. | |
4 | * | |
5 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | |
6 | * | |
7 | * Author: | |
8 | * Chaitanya Bandi <bandik@nvidia.com> | |
9 | * Laxman Dewangan <ldewangan@nvidia.com> | |
2df723d4 LD |
10 | */ |
11 | ||
12 | #include <linux/mfd/max77620.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/pinctrl/pinctrl.h> | |
16 | #include <linux/pinctrl/pinconf-generic.h> | |
17 | #include <linux/pinctrl/pinconf.h> | |
18 | #include <linux/pinctrl/pinmux.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/regmap.h> | |
21 | ||
22 | #include "core.h" | |
23 | #include "pinconf.h" | |
24 | #include "pinctrl-utils.h" | |
25 | ||
26 | #define MAX77620_PIN_NUM 8 | |
27 | ||
28 | enum max77620_pin_ppdrv { | |
29 | MAX77620_PIN_UNCONFIG_DRV, | |
30 | MAX77620_PIN_OD_DRV, | |
31 | MAX77620_PIN_PP_DRV, | |
32 | }; | |
33 | ||
1f60652d NC |
34 | #define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1) |
35 | #define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2) | |
36 | #define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3) | |
37 | #define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4) | |
38 | #define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5) | |
39 | #define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6) | |
2df723d4 LD |
40 | |
41 | struct max77620_pin_function { | |
42 | const char *name; | |
43 | const char * const *groups; | |
44 | unsigned int ngroups; | |
45 | int mux_option; | |
46 | }; | |
47 | ||
2df723d4 LD |
48 | static const struct pinconf_generic_params max77620_cfg_params[] = { |
49 | { | |
50 | .property = "maxim,active-fps-source", | |
51 | .param = MAX77620_ACTIVE_FPS_SOURCE, | |
52 | }, { | |
53 | .property = "maxim,active-fps-power-up-slot", | |
54 | .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, | |
55 | }, { | |
56 | .property = "maxim,active-fps-power-down-slot", | |
57 | .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, | |
58 | }, { | |
59 | .property = "maxim,suspend-fps-source", | |
60 | .param = MAX77620_SUSPEND_FPS_SOURCE, | |
61 | }, { | |
62 | .property = "maxim,suspend-fps-power-up-slot", | |
63 | .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, | |
64 | }, { | |
65 | .property = "maxim,suspend-fps-power-down-slot", | |
66 | .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, | |
67 | }, | |
68 | }; | |
69 | ||
70 | enum max77620_alternate_pinmux_option { | |
71 | MAX77620_PINMUX_GPIO = 0, | |
72 | MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1, | |
73 | MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2, | |
74 | MAX77620_PINMUX_32K_OUT1 = 3, | |
75 | MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4, | |
76 | MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5, | |
77 | MAX77620_PINMUX_REFERENCE_OUT = 6, | |
78 | }; | |
79 | ||
80 | struct max77620_pingroup { | |
81 | const char *name; | |
82 | const unsigned int pins[1]; | |
83 | unsigned int npins; | |
84 | enum max77620_alternate_pinmux_option alt_option; | |
85 | }; | |
86 | ||
87 | struct max77620_pin_info { | |
88 | enum max77620_pin_ppdrv drv_type; | |
89 | int pull_config; | |
90 | }; | |
91 | ||
92 | struct max77620_fps_config { | |
93 | int active_fps_src; | |
94 | int active_power_up_slots; | |
95 | int active_power_down_slots; | |
96 | int suspend_fps_src; | |
97 | int suspend_power_up_slots; | |
98 | int suspend_power_down_slots; | |
99 | }; | |
100 | ||
101 | struct max77620_pctrl_info { | |
102 | struct device *dev; | |
103 | struct pinctrl_dev *pctl; | |
104 | struct regmap *rmap; | |
105 | int pins_current_opt[MAX77620_GPIO_NR]; | |
106 | const struct max77620_pin_function *functions; | |
107 | unsigned int num_functions; | |
108 | const struct max77620_pingroup *pin_groups; | |
109 | int num_pin_groups; | |
110 | const struct pinctrl_pin_desc *pins; | |
111 | unsigned int num_pins; | |
112 | struct max77620_pin_info pin_info[MAX77620_PIN_NUM]; | |
113 | struct max77620_fps_config fps_config[MAX77620_PIN_NUM]; | |
114 | }; | |
115 | ||
116 | static const struct pinctrl_pin_desc max77620_pins_desc[] = { | |
117 | PINCTRL_PIN(MAX77620_GPIO0, "gpio0"), | |
118 | PINCTRL_PIN(MAX77620_GPIO1, "gpio1"), | |
119 | PINCTRL_PIN(MAX77620_GPIO2, "gpio2"), | |
120 | PINCTRL_PIN(MAX77620_GPIO3, "gpio3"), | |
121 | PINCTRL_PIN(MAX77620_GPIO4, "gpio4"), | |
122 | PINCTRL_PIN(MAX77620_GPIO5, "gpio5"), | |
123 | PINCTRL_PIN(MAX77620_GPIO6, "gpio6"), | |
124 | PINCTRL_PIN(MAX77620_GPIO7, "gpio7"), | |
125 | }; | |
126 | ||
127 | static const char * const gpio_groups[] = { | |
128 | "gpio0", | |
129 | "gpio1", | |
130 | "gpio2", | |
131 | "gpio3", | |
132 | "gpio4", | |
133 | "gpio5", | |
134 | "gpio6", | |
135 | "gpio7", | |
136 | }; | |
137 | ||
138 | #define FUNCTION_GROUP(fname, mux) \ | |
139 | { \ | |
140 | .name = fname, \ | |
141 | .groups = gpio_groups, \ | |
142 | .ngroups = ARRAY_SIZE(gpio_groups), \ | |
143 | .mux_option = MAX77620_PINMUX_##mux, \ | |
144 | } | |
145 | ||
146 | static const struct max77620_pin_function max77620_pin_function[] = { | |
147 | FUNCTION_GROUP("gpio", GPIO), | |
148 | FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN), | |
149 | FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT), | |
150 | FUNCTION_GROUP("32k-out1", 32K_OUT1), | |
151 | FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN), | |
152 | FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN), | |
153 | FUNCTION_GROUP("reference-out", REFERENCE_OUT), | |
154 | }; | |
155 | ||
156 | #define MAX77620_PINGROUP(pg_name, pin_id, option) \ | |
157 | { \ | |
158 | .name = #pg_name, \ | |
159 | .pins = {MAX77620_##pin_id}, \ | |
160 | .npins = 1, \ | |
161 | .alt_option = MAX77620_PINMUX_##option, \ | |
162 | } | |
163 | ||
164 | static const struct max77620_pingroup max77620_pingroups[] = { | |
165 | MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN), | |
166 | MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT), | |
167 | MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT), | |
168 | MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT), | |
169 | MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1), | |
170 | MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN), | |
171 | MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN), | |
172 | MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT), | |
173 | }; | |
174 | ||
175 | static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
176 | { | |
177 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
178 | ||
179 | return mpci->num_pin_groups; | |
180 | } | |
181 | ||
182 | static const char *max77620_pinctrl_get_group_name( | |
183 | struct pinctrl_dev *pctldev, unsigned int group) | |
184 | { | |
185 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
186 | ||
187 | return mpci->pin_groups[group].name; | |
188 | } | |
189 | ||
190 | static int max77620_pinctrl_get_group_pins( | |
191 | struct pinctrl_dev *pctldev, unsigned int group, | |
192 | const unsigned int **pins, unsigned int *num_pins) | |
193 | { | |
194 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
195 | ||
196 | *pins = mpci->pin_groups[group].pins; | |
197 | *num_pins = mpci->pin_groups[group].npins; | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | static const struct pinctrl_ops max77620_pinctrl_ops = { | |
203 | .get_groups_count = max77620_pinctrl_get_groups_count, | |
204 | .get_group_name = max77620_pinctrl_get_group_name, | |
205 | .get_group_pins = max77620_pinctrl_get_group_pins, | |
206 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
207 | .dt_free_map = pinctrl_utils_free_map, | |
208 | }; | |
209 | ||
210 | static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) | |
211 | { | |
212 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
213 | ||
214 | return mpci->num_functions; | |
215 | } | |
216 | ||
217 | static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev, | |
218 | unsigned int function) | |
219 | { | |
220 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
221 | ||
222 | return mpci->functions[function].name; | |
223 | } | |
224 | ||
225 | static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, | |
226 | unsigned int function, | |
227 | const char * const **groups, | |
228 | unsigned int * const num_groups) | |
229 | { | |
230 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
231 | ||
232 | *groups = mpci->functions[function].groups; | |
233 | *num_groups = mpci->functions[function].ngroups; | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev, | |
239 | unsigned int function, unsigned int group) | |
240 | { | |
241 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
242 | u8 val; | |
243 | int ret; | |
244 | ||
245 | if (function == MAX77620_PINMUX_GPIO) { | |
246 | val = 0; | |
247 | } else if (function == mpci->pin_groups[group].alt_option) { | |
248 | val = 1 << group; | |
249 | } else { | |
250 | dev_err(mpci->dev, "GPIO %u doesn't have function %u\n", | |
251 | group, function); | |
252 | return -EINVAL; | |
253 | } | |
254 | ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO, | |
255 | BIT(group), val); | |
256 | if (ret < 0) | |
257 | dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret); | |
258 | ||
259 | return ret; | |
260 | } | |
261 | ||
262 | static const struct pinmux_ops max77620_pinmux_ops = { | |
263 | .get_functions_count = max77620_pinctrl_get_funcs_count, | |
264 | .get_function_name = max77620_pinctrl_get_func_name, | |
265 | .get_function_groups = max77620_pinctrl_get_func_groups, | |
266 | .set_mux = max77620_pinctrl_enable, | |
267 | }; | |
268 | ||
269 | static int max77620_pinconf_get(struct pinctrl_dev *pctldev, | |
270 | unsigned int pin, unsigned long *config) | |
271 | { | |
272 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
273 | struct device *dev = mpci->dev; | |
274 | enum pin_config_param param = pinconf_to_config_param(*config); | |
275 | unsigned int val; | |
276 | int arg = 0; | |
277 | int ret; | |
278 | ||
279 | switch (param) { | |
280 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
281 | if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV) | |
282 | arg = 1; | |
283 | break; | |
284 | ||
285 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
286 | if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV) | |
287 | arg = 1; | |
288 | break; | |
289 | ||
290 | case PIN_CONFIG_BIAS_PULL_UP: | |
291 | ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val); | |
292 | if (ret < 0) { | |
293 | dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret); | |
294 | return ret; | |
295 | } | |
296 | if (val & BIT(pin)) | |
297 | arg = 1; | |
298 | break; | |
299 | ||
300 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
301 | ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val); | |
302 | if (ret < 0) { | |
303 | dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret); | |
304 | return ret; | |
305 | } | |
306 | if (val & BIT(pin)) | |
307 | arg = 1; | |
308 | break; | |
309 | ||
310 | default: | |
311 | dev_err(dev, "Properties not supported\n"); | |
312 | return -ENOTSUPP; | |
313 | } | |
314 | ||
315 | *config = pinconf_to_config_packed(param, (u16)arg); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | static int max77620_get_default_fps(struct max77620_pctrl_info *mpci, | |
321 | int addr, int *fps) | |
322 | { | |
323 | unsigned int val; | |
324 | int ret; | |
325 | ||
326 | ret = regmap_read(mpci->rmap, addr, &val); | |
327 | if (ret < 0) { | |
328 | dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret); | |
329 | return ret; | |
330 | } | |
331 | *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
336 | static int max77620_set_fps_param(struct max77620_pctrl_info *mpci, | |
337 | int pin, int param) | |
338 | { | |
339 | struct max77620_fps_config *fps_config = &mpci->fps_config[pin]; | |
340 | int addr, ret; | |
341 | int param_val; | |
342 | int mask, shift; | |
343 | ||
344 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
345 | return 0; | |
346 | ||
347 | addr = MAX77620_REG_FPS_GPIO1 + pin - 1; | |
348 | switch (param) { | |
349 | case MAX77620_ACTIVE_FPS_SOURCE: | |
350 | case MAX77620_SUSPEND_FPS_SOURCE: | |
351 | mask = MAX77620_FPS_SRC_MASK; | |
352 | shift = MAX77620_FPS_SRC_SHIFT; | |
353 | param_val = fps_config->active_fps_src; | |
354 | if (param == MAX77620_SUSPEND_FPS_SOURCE) | |
355 | param_val = fps_config->suspend_fps_src; | |
356 | break; | |
357 | ||
358 | case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS: | |
359 | case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS: | |
360 | mask = MAX77620_FPS_PU_PERIOD_MASK; | |
361 | shift = MAX77620_FPS_PU_PERIOD_SHIFT; | |
362 | param_val = fps_config->active_power_up_slots; | |
363 | if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS) | |
364 | param_val = fps_config->suspend_power_up_slots; | |
365 | break; | |
366 | ||
367 | case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS: | |
368 | case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS: | |
369 | mask = MAX77620_FPS_PD_PERIOD_MASK; | |
370 | shift = MAX77620_FPS_PD_PERIOD_SHIFT; | |
371 | param_val = fps_config->active_power_down_slots; | |
372 | if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS) | |
373 | param_val = fps_config->suspend_power_down_slots; | |
374 | break; | |
375 | ||
376 | default: | |
377 | dev_err(mpci->dev, "Invalid parameter %d for pin %d\n", | |
378 | param, pin); | |
379 | return -EINVAL; | |
380 | } | |
381 | ||
382 | if (param_val < 0) | |
383 | return 0; | |
384 | ||
385 | ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift); | |
386 | if (ret < 0) | |
387 | dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret); | |
388 | ||
389 | return ret; | |
390 | } | |
391 | ||
392 | static int max77620_pinconf_set(struct pinctrl_dev *pctldev, | |
393 | unsigned int pin, unsigned long *configs, | |
394 | unsigned int num_configs) | |
395 | { | |
396 | struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); | |
397 | struct device *dev = mpci->dev; | |
398 | struct max77620_fps_config *fps_config; | |
399 | int param; | |
58957d2e | 400 | u32 param_val; |
2df723d4 LD |
401 | unsigned int val; |
402 | unsigned int pu_val; | |
403 | unsigned int pd_val; | |
404 | int addr, ret; | |
405 | int i; | |
406 | ||
407 | for (i = 0; i < num_configs; i++) { | |
408 | param = pinconf_to_config_param(configs[i]); | |
409 | param_val = pinconf_to_config_argument(configs[i]); | |
410 | ||
411 | switch (param) { | |
412 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
413 | val = param_val ? 0 : 1; | |
414 | ret = regmap_update_bits(mpci->rmap, | |
415 | MAX77620_REG_GPIO0 + pin, | |
416 | MAX77620_CNFG_GPIO_DRV_MASK, | |
417 | val); | |
752caf9a ME |
418 | if (ret) |
419 | goto report_update_failure; | |
420 | ||
2df723d4 LD |
421 | mpci->pin_info[pin].drv_type = val ? |
422 | MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; | |
423 | break; | |
424 | ||
425 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
426 | val = param_val ? 1 : 0; | |
427 | ret = regmap_update_bits(mpci->rmap, | |
428 | MAX77620_REG_GPIO0 + pin, | |
429 | MAX77620_CNFG_GPIO_DRV_MASK, | |
430 | val); | |
752caf9a ME |
431 | if (ret) |
432 | goto report_update_failure; | |
433 | ||
2df723d4 LD |
434 | mpci->pin_info[pin].drv_type = val ? |
435 | MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; | |
436 | break; | |
437 | ||
438 | case MAX77620_ACTIVE_FPS_SOURCE: | |
439 | case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS: | |
440 | case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS: | |
441 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
442 | return -EINVAL; | |
443 | ||
444 | fps_config = &mpci->fps_config[pin]; | |
445 | ||
446 | if ((param == MAX77620_ACTIVE_FPS_SOURCE) && | |
447 | (param_val == MAX77620_FPS_SRC_DEF)) { | |
448 | addr = MAX77620_REG_FPS_GPIO1 + pin - 1; | |
449 | ret = max77620_get_default_fps( | |
450 | mpci, addr, | |
451 | &fps_config->active_fps_src); | |
452 | if (ret < 0) | |
453 | return ret; | |
454 | break; | |
455 | } | |
456 | ||
457 | if (param == MAX77620_ACTIVE_FPS_SOURCE) | |
458 | fps_config->active_fps_src = param_val; | |
459 | else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS) | |
460 | fps_config->active_power_up_slots = param_val; | |
461 | else | |
462 | fps_config->active_power_down_slots = param_val; | |
463 | ||
464 | ret = max77620_set_fps_param(mpci, pin, param); | |
465 | if (ret < 0) | |
466 | return ret; | |
467 | break; | |
468 | ||
469 | case MAX77620_SUSPEND_FPS_SOURCE: | |
470 | case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS: | |
471 | case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS: | |
472 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
473 | return -EINVAL; | |
474 | ||
475 | fps_config = &mpci->fps_config[pin]; | |
476 | ||
477 | if ((param == MAX77620_SUSPEND_FPS_SOURCE) && | |
478 | (param_val == MAX77620_FPS_SRC_DEF)) { | |
479 | addr = MAX77620_REG_FPS_GPIO1 + pin - 1; | |
480 | ret = max77620_get_default_fps( | |
481 | mpci, addr, | |
482 | &fps_config->suspend_fps_src); | |
483 | if (ret < 0) | |
484 | return ret; | |
485 | break; | |
486 | } | |
487 | ||
488 | if (param == MAX77620_SUSPEND_FPS_SOURCE) | |
489 | fps_config->suspend_fps_src = param_val; | |
490 | else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS) | |
491 | fps_config->suspend_power_up_slots = param_val; | |
492 | else | |
493 | fps_config->suspend_power_down_slots = | |
494 | param_val; | |
495 | break; | |
496 | ||
497 | case PIN_CONFIG_BIAS_PULL_UP: | |
498 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
499 | pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ? | |
500 | BIT(pin) : 0; | |
501 | pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ? | |
502 | BIT(pin) : 0; | |
503 | ||
504 | ret = regmap_update_bits(mpci->rmap, | |
505 | MAX77620_REG_PUE_GPIO, | |
506 | BIT(pin), pu_val); | |
507 | if (ret < 0) { | |
508 | dev_err(dev, "PUE_GPIO update failed: %d\n", | |
509 | ret); | |
510 | return ret; | |
511 | } | |
512 | ||
513 | ret = regmap_update_bits(mpci->rmap, | |
514 | MAX77620_REG_PDE_GPIO, | |
515 | BIT(pin), pd_val); | |
516 | if (ret < 0) { | |
517 | dev_err(dev, "PDE_GPIO update failed: %d\n", | |
518 | ret); | |
519 | return ret; | |
520 | } | |
521 | break; | |
522 | ||
523 | default: | |
524 | dev_err(dev, "Properties not supported\n"); | |
525 | return -ENOTSUPP; | |
526 | } | |
527 | } | |
528 | ||
529 | return 0; | |
752caf9a ME |
530 | |
531 | report_update_failure: | |
532 | dev_err(dev, "Reg 0x%02x update failed %d\n", | |
533 | MAX77620_REG_GPIO0 + pin, ret); | |
534 | return ret; | |
2df723d4 LD |
535 | } |
536 | ||
537 | static const struct pinconf_ops max77620_pinconf_ops = { | |
538 | .pin_config_get = max77620_pinconf_get, | |
539 | .pin_config_set = max77620_pinconf_set, | |
540 | }; | |
541 | ||
542 | static struct pinctrl_desc max77620_pinctrl_desc = { | |
543 | .pctlops = &max77620_pinctrl_ops, | |
544 | .pmxops = &max77620_pinmux_ops, | |
545 | .confops = &max77620_pinconf_ops, | |
546 | }; | |
547 | ||
548 | static int max77620_pinctrl_probe(struct platform_device *pdev) | |
549 | { | |
550 | struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent); | |
551 | struct max77620_pctrl_info *mpci; | |
552 | int i; | |
553 | ||
554 | mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL); | |
555 | if (!mpci) | |
556 | return -ENOMEM; | |
557 | ||
558 | mpci->dev = &pdev->dev; | |
559 | mpci->dev->of_node = pdev->dev.parent->of_node; | |
560 | mpci->rmap = max77620->rmap; | |
561 | ||
562 | mpci->pins = max77620_pins_desc; | |
563 | mpci->num_pins = ARRAY_SIZE(max77620_pins_desc); | |
564 | mpci->functions = max77620_pin_function; | |
565 | mpci->num_functions = ARRAY_SIZE(max77620_pin_function); | |
566 | mpci->pin_groups = max77620_pingroups; | |
567 | mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups); | |
568 | platform_set_drvdata(pdev, mpci); | |
569 | ||
570 | max77620_pinctrl_desc.name = dev_name(&pdev->dev); | |
571 | max77620_pinctrl_desc.pins = max77620_pins_desc; | |
572 | max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc); | |
573 | max77620_pinctrl_desc.num_custom_params = | |
574 | ARRAY_SIZE(max77620_cfg_params); | |
575 | max77620_pinctrl_desc.custom_params = max77620_cfg_params; | |
576 | ||
577 | for (i = 0; i < MAX77620_PIN_NUM; ++i) { | |
578 | mpci->fps_config[i].active_fps_src = -1; | |
579 | mpci->fps_config[i].active_power_up_slots = -1; | |
580 | mpci->fps_config[i].active_power_down_slots = -1; | |
581 | mpci->fps_config[i].suspend_fps_src = -1; | |
582 | mpci->fps_config[i].suspend_power_up_slots = -1; | |
583 | mpci->fps_config[i].suspend_power_down_slots = -1; | |
584 | } | |
585 | ||
586 | mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc, | |
587 | mpci); | |
588 | if (IS_ERR(mpci->pctl)) { | |
589 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | |
590 | return PTR_ERR(mpci->pctl); | |
591 | } | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | #ifdef CONFIG_PM_SLEEP | |
597 | static int max77620_suspend_fps_param[] = { | |
598 | MAX77620_SUSPEND_FPS_SOURCE, | |
599 | MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, | |
600 | MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, | |
601 | }; | |
602 | ||
603 | static int max77620_active_fps_param[] = { | |
604 | MAX77620_ACTIVE_FPS_SOURCE, | |
605 | MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, | |
606 | MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, | |
607 | }; | |
608 | ||
609 | static int max77620_pinctrl_suspend(struct device *dev) | |
610 | { | |
611 | struct max77620_pctrl_info *mpci = dev_get_drvdata(dev); | |
612 | int pin, p; | |
613 | ||
614 | for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { | |
615 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
616 | continue; | |
617 | for (p = 0; p < 3; ++p) | |
618 | max77620_set_fps_param( | |
619 | mpci, pin, max77620_suspend_fps_param[p]); | |
620 | } | |
621 | ||
622 | return 0; | |
623 | }; | |
624 | ||
625 | static int max77620_pinctrl_resume(struct device *dev) | |
626 | { | |
627 | struct max77620_pctrl_info *mpci = dev_get_drvdata(dev); | |
628 | int pin, p; | |
629 | ||
630 | for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { | |
631 | if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) | |
632 | continue; | |
633 | for (p = 0; p < 3; ++p) | |
634 | max77620_set_fps_param( | |
635 | mpci, pin, max77620_active_fps_param[p]); | |
636 | } | |
637 | ||
638 | return 0; | |
639 | } | |
640 | #endif | |
641 | ||
642 | static const struct dev_pm_ops max77620_pinctrl_pm_ops = { | |
643 | SET_SYSTEM_SLEEP_PM_OPS( | |
644 | max77620_pinctrl_suspend, max77620_pinctrl_resume) | |
645 | }; | |
646 | ||
647 | static const struct platform_device_id max77620_pinctrl_devtype[] = { | |
648 | { .name = "max77620-pinctrl", }, | |
649 | { .name = "max20024-pinctrl", }, | |
650 | {}, | |
651 | }; | |
652 | MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype); | |
653 | ||
654 | static struct platform_driver max77620_pinctrl_driver = { | |
655 | .driver = { | |
656 | .name = "max77620-pinctrl", | |
657 | .pm = &max77620_pinctrl_pm_ops, | |
658 | }, | |
659 | .probe = max77620_pinctrl_probe, | |
660 | .id_table = max77620_pinctrl_devtype, | |
661 | }; | |
662 | ||
663 | module_platform_driver(max77620_pinctrl_driver); | |
664 | ||
665 | MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver"); | |
666 | MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>"); | |
667 | MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>"); | |
668 | MODULE_ALIAS("platform:max77620-pinctrl"); | |
669 | MODULE_LICENSE("GPL v2"); |