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pinctrl-single: fix pcs_parse_pinconf() return value
[linux-block.git] / drivers / pinctrl / pinctrl-ingenic.c
CommitLineData
af873fce 1// SPDX-License-Identifier: GPL-2.0-only
b5c23aa4
PC		 2/*
3 * Ingenic SoCs pinctrl driver
4 *
5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
d7da2a1e 6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
a0bb89e8 7 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
b5c23aa4
PC		 8 */
9
10#include <linux/compiler.h>
28d6eeb4 11#include <linux/gpio/driver.h>
b5c23aa4
PC		 12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/of_device.h>
e72394e2 15#include <linux/of_irq.h>
b5c23aa4
PC		 16#include <linux/of_platform.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24
25#include "core.h"
26#include "pinconf.h"
27#include "pinmux.h"
28
e72394e2
PC		 29#define GPIO_PIN 0x00
30#define GPIO_MSK 0x20
31
b5c23aa4
PC		 32#define JZ4740_GPIO_DATA 0x10
33#define JZ4740_GPIO_PULL_DIS 0x30
34#define JZ4740_GPIO_FUNC 0x40
35#define JZ4740_GPIO_SELECT 0x50
36#define JZ4740_GPIO_DIR 0x60
37#define JZ4740_GPIO_TRIG 0x70
38#define JZ4740_GPIO_FLAG 0x80
39
0257595a
ZY		 40#define JZ4760_GPIO_INT 0x10
41#define JZ4760_GPIO_PAT1 0x30
42#define JZ4760_GPIO_PAT0 0x40
43#define JZ4760_GPIO_FLAG 0x50
44#define JZ4760_GPIO_PEN 0x70
b5c23aa4 45
d7da2a1e
ZY		 46#define X1830_GPIO_PEL 0x110
47#define X1830_GPIO_PEH 0x120
fe1ad5ee 48
b5c23aa4
PC		 49#define REG_SET(x) ((x) + 0x4)
50#define REG_CLEAR(x) ((x) + 0x8)
51
d7da2a1e
ZY		 52#define REG_PZ_BASE(x) ((x) * 7)
53#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
54
55#define GPIO_PULL_DIS 0
56#define GPIO_PULL_UP 1
57#define GPIO_PULL_DOWN 2
58
b5c23aa4
PC		 59#define PINS_PER_GPIO_CHIP 32
60
61enum jz_version {
62 ID_JZ4740,
f2a96765 63 ID_JZ4725B,
0257595a 64 ID_JZ4760,
b5c23aa4
PC		 65 ID_JZ4770,
66 ID_JZ4780,
fe1ad5ee 67 ID_X1000,
5d21595b 68 ID_X1500,
d7da2a1e 69 ID_X1830,
b5c23aa4
PC		 70};
71
72struct ingenic_chip_info {
73 unsigned int num_chips;
f742e5eb 74 unsigned int reg_offset;
baf15647 75 enum jz_version version;
b5c23aa4
PC		 76
77 const struct group_desc *groups;
78 unsigned int num_groups;
79
80 const struct function_desc *functions;
81 unsigned int num_functions;
82
83 const u32 *pull_ups, *pull_downs;
84};
85
86struct ingenic_pinctrl {
87 struct device *dev;
88 struct regmap *map;
89 struct pinctrl_dev *pctl;
90 struct pinctrl_pin_desc *pdesc;
b5c23aa4
PC		 91
92 const struct ingenic_chip_info *info;
93};
94
e72394e2
PC		 95struct ingenic_gpio_chip {
96 struct ingenic_pinctrl *jzpc;
97 struct gpio_chip gc;
98 struct irq_chip irq_chip;
99 unsigned int irq, reg_base;
100};
101
b5c23aa4
PC		 102static const u32 jz4740_pull_ups[4] = {
103 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
104};
105
106static const u32 jz4740_pull_downs[4] = {
107 0x00000000, 0x00000000, 0x00000000, 0x00000000,
108};
109
110static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
111static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
112static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
113static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
114static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
115static int jz4740_lcd_8bit_pins[] = {
116 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
117};
118static int jz4740_lcd_16bit_pins[] = {
119 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
120};
121static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
122static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
123static int jz4740_nand_cs1_pins[] = { 0x39, };
124static int jz4740_nand_cs2_pins[] = { 0x3a, };
125static int jz4740_nand_cs3_pins[] = { 0x3b, };
126static int jz4740_nand_cs4_pins[] = { 0x3c, };
bcad94d7 127static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
b5c23aa4
PC		 128static int jz4740_pwm_pwm0_pins[] = { 0x77, };
129static int jz4740_pwm_pwm1_pins[] = { 0x78, };
130static int jz4740_pwm_pwm2_pins[] = { 0x79, };
131static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
132static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
133static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
134static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
135static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
136
137static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, };
138static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, };
139static int jz4740_uart0_data_funcs[] = { 1, 1, };
140static int jz4740_uart0_hwflow_funcs[] = { 1, 1, };
141static int jz4740_uart1_data_funcs[] = { 2, 2, };
142static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
143static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, };
144static int jz4740_lcd_18bit_funcs[] = { 0, 0, };
145static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, };
146static int jz4740_nand_cs1_funcs[] = { 0, };
147static int jz4740_nand_cs2_funcs[] = { 0, };
148static int jz4740_nand_cs3_funcs[] = { 0, };
149static int jz4740_nand_cs4_funcs[] = { 0, };
bcad94d7 150static int jz4740_nand_fre_fwe_funcs[] = { 0, 0, };
b5c23aa4
PC		 151static int jz4740_pwm_pwm0_funcs[] = { 0, };
152static int jz4740_pwm_pwm1_funcs[] = { 0, };
153static int jz4740_pwm_pwm2_funcs[] = { 0, };
154static int jz4740_pwm_pwm3_funcs[] = { 0, };
155static int jz4740_pwm_pwm4_funcs[] = { 0, };
156static int jz4740_pwm_pwm5_funcs[] = { 0, };
157static int jz4740_pwm_pwm6_funcs[] = { 0, };
158static int jz4740_pwm_pwm7_funcs[] = { 0, };
159
160#define INGENIC_PIN_GROUP(name, id) \
161 { \
162 name, \
163 id##_pins, \
164 ARRAY_SIZE(id##_pins), \
165 id##_funcs, \
166 }
167
168static const struct group_desc jz4740_groups[] = {
169 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
170 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
171 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
172 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
173 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
174 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
175 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
176 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
177 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
178 { "lcd-no-pins", },
179 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
180 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
181 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
182 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
bcad94d7 183 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe),
b5c23aa4
PC		 184 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
185 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
186 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
187 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3),
188 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4),
189 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5),
190 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6),
191 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
192};
193
194static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
195static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
196static const char *jz4740_uart1_groups[] = { "uart1-data", };
197static const char *jz4740_lcd_groups[] = {
198 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
199};
200static const char *jz4740_nand_groups[] = {
bcad94d7 201 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
b5c23aa4
PC		 202};
203static const char *jz4740_pwm0_groups[] = { "pwm0", };
204static const char *jz4740_pwm1_groups[] = { "pwm1", };
205static const char *jz4740_pwm2_groups[] = { "pwm2", };
206static const char *jz4740_pwm3_groups[] = { "pwm3", };
207static const char *jz4740_pwm4_groups[] = { "pwm4", };
208static const char *jz4740_pwm5_groups[] = { "pwm5", };
209static const char *jz4740_pwm6_groups[] = { "pwm6", };
210static const char *jz4740_pwm7_groups[] = { "pwm7", };
211
212static const struct function_desc jz4740_functions[] = {
213 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
214 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
215 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
216 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
217 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
218 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
219 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
220 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
221 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
222 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
223 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
224 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
225 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
226};
227
228static const struct ingenic_chip_info jz4740_chip_info = {
229 .num_chips = 4,
f742e5eb 230 .reg_offset = 0x100,
baf15647 231 .version = ID_JZ4740,
b5c23aa4
PC		 232 .groups = jz4740_groups,
233 .num_groups = ARRAY_SIZE(jz4740_groups),
234 .functions = jz4740_functions,
235 .num_functions = ARRAY_SIZE(jz4740_functions),
236 .pull_ups = jz4740_pull_ups,
237 .pull_downs = jz4740_pull_downs,
238};
239
f2a96765
PC		 240static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
241static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
242static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
243static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
244static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
245static int jz4725b_nand_cs1_pins[] = { 0x55, };
246static int jz4725b_nand_cs2_pins[] = { 0x56, };
247static int jz4725b_nand_cs3_pins[] = { 0x57, };
248static int jz4725b_nand_cs4_pins[] = { 0x58, };
249static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
250static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
251static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
252static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
253static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
254static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
255static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
256static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
a3240f09
PC		 257static int jz4725b_lcd_8bit_pins[] = {
258 0x72, 0x73, 0x74,
259 0x60, 0x61, 0x62, 0x63,
260 0x64, 0x65, 0x66, 0x67,
261};
262static int jz4725b_lcd_16bit_pins[] = {
263 0x68, 0x69, 0x6a, 0x6b,
264 0x6c, 0x6d, 0x6e, 0x6f,
265};
266static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
267static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
268static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
269static int jz4725b_lcd_generic_pins[] = { 0x75, };
f2a96765
PC		 270
271static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, };
272static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
273static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, };
274static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, };
275static int jz4725b_uart_data_funcs[] = { 1, 1, };
276static int jz4725b_nand_cs1_funcs[] = { 0, };
277static int jz4725b_nand_cs2_funcs[] = { 0, };
278static int jz4725b_nand_cs3_funcs[] = { 0, };
279static int jz4725b_nand_cs4_funcs[] = { 0, };
280static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, };
281static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, };
282static int jz4725b_pwm_pwm0_funcs[] = { 0, };
283static int jz4725b_pwm_pwm1_funcs[] = { 0, };
284static int jz4725b_pwm_pwm2_funcs[] = { 0, };
285static int jz4725b_pwm_pwm3_funcs[] = { 0, };
286static int jz4725b_pwm_pwm4_funcs[] = { 0, };
287static int jz4725b_pwm_pwm5_funcs[] = { 0, };
a3240f09
PC		 288static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
289static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
290static int jz4725b_lcd_18bit_funcs[] = { 0, 0, };
291static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, };
292static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, };
293static int jz4725b_lcd_generic_funcs[] = { 0, };
f2a96765
PC		 294
295static const struct group_desc jz4725b_groups[] = {
296 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit),
297 INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit),
298 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit),
299 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit),
300 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data),
301 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1),
302 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2),
303 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3),
304 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4),
305 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale),
306 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe),
307 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0),
308 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1),
309 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2),
310 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3),
311 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4),
312 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
a3240f09
PC		 313 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit),
314 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit),
315 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit),
316 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit),
317 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special),
318 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic),
f2a96765
PC		 319};
320
321static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
322static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
323static const char *jz4725b_uart_groups[] = { "uart-data", };
324static const char *jz4725b_nand_groups[] = {
325 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
326 "nand-cle-ale", "nand-fre-fwe",
327};
328static const char *jz4725b_pwm0_groups[] = { "pwm0", };
329static const char *jz4725b_pwm1_groups[] = { "pwm1", };
330static const char *jz4725b_pwm2_groups[] = { "pwm2", };
331static const char *jz4725b_pwm3_groups[] = { "pwm3", };
332static const char *jz4725b_pwm4_groups[] = { "pwm4", };
333static const char *jz4725b_pwm5_groups[] = { "pwm5", };
a3240f09
PC		 334static const char *jz4725b_lcd_groups[] = {
335 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
336 "lcd-special", "lcd-generic",
337};
f2a96765
PC		 338
339static const struct function_desc jz4725b_functions[] = {
340 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
341 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
342 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
343 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
344 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
345 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
346 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
347 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
348 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
349 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
a3240f09 350 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
f2a96765
PC		 351};
352
353static const struct ingenic_chip_info jz4725b_chip_info = {
354 .num_chips = 4,
f742e5eb 355 .reg_offset = 0x100,
baf15647 356 .version = ID_JZ4725B,
f2a96765
PC		 357 .groups = jz4725b_groups,
358 .num_groups = ARRAY_SIZE(jz4725b_groups),
359 .functions = jz4725b_functions,
360 .num_functions = ARRAY_SIZE(jz4725b_functions),
361 .pull_ups = jz4740_pull_ups,
362 .pull_downs = jz4740_pull_downs,
363};
364
0257595a
ZY		 365static const u32 jz4760_pull_ups[6] = {
366 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f,
367};
368
369static const u32 jz4760_pull_downs[6] = {
370 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
371};
372
373static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
374static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
375static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
376static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
377static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
378static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
379static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
380static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
381static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
382static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
383static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
384static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
385static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
386static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
387static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
388static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
389static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
390static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
391static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
392static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
393static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
394static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
395static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
396static int jz4760_nemc_8bit_data_pins[] = {
397 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
398};
399static int jz4760_nemc_16bit_data_pins[] = {
400 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
401};
402static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
403static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
404static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
405static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
406static int jz4760_nemc_wait_pins[] = { 0x1b, };
407static int jz4760_nemc_cs1_pins[] = { 0x15, };
408static int jz4760_nemc_cs2_pins[] = { 0x16, };
409static int jz4760_nemc_cs3_pins[] = { 0x17, };
410static int jz4760_nemc_cs4_pins[] = { 0x18, };
411static int jz4760_nemc_cs5_pins[] = { 0x19, };
412static int jz4760_nemc_cs6_pins[] = { 0x1a, };
413static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
414static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
415static int jz4760_cim_pins[] = {
416 0x26, 0x27, 0x28, 0x29,
417 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
418};
419static int jz4760_lcd_24bit_pins[] = {
420 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
421 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
422 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
423 0x58, 0x59, 0x5a, 0x5b,
424};
425static int jz4760_pwm_pwm0_pins[] = { 0x80, };
426static int jz4760_pwm_pwm1_pins[] = { 0x81, };
427static int jz4760_pwm_pwm2_pins[] = { 0x82, };
428static int jz4760_pwm_pwm3_pins[] = { 0x83, };
429static int jz4760_pwm_pwm4_pins[] = { 0x84, };
430static int jz4760_pwm_pwm5_pins[] = { 0x85, };
431static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
432static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
433
434static int jz4760_uart0_data_funcs[] = { 0, 0, };
435static int jz4760_uart0_hwflow_funcs[] = { 0, 0, };
436static int jz4760_uart1_data_funcs[] = { 0, 0, };
437static int jz4760_uart1_hwflow_funcs[] = { 0, 0, };
438static int jz4760_uart2_data_funcs[] = { 0, 0, };
439static int jz4760_uart2_hwflow_funcs[] = { 0, 0, };
440static int jz4760_uart3_data_funcs[] = { 0, 1, };
441static int jz4760_uart3_hwflow_funcs[] = { 0, 0, };
442static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
443static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
444static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
445static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
446static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
447static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
448static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
449static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
450static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
451static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
452static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
453static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
454static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
455static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
456static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
457static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
458static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
459static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, };
460static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, };
461static int jz4760_nemc_rd_we_funcs[] = { 0, 0, };
462static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, };
463static int jz4760_nemc_wait_funcs[] = { 0, };
464static int jz4760_nemc_cs1_funcs[] = { 0, };
465static int jz4760_nemc_cs2_funcs[] = { 0, };
466static int jz4760_nemc_cs3_funcs[] = { 0, };
467static int jz4760_nemc_cs4_funcs[] = { 0, };
468static int jz4760_nemc_cs5_funcs[] = { 0, };
469static int jz4760_nemc_cs6_funcs[] = { 0, };
470static int jz4760_i2c0_funcs[] = { 0, 0, };
471static int jz4760_i2c1_funcs[] = { 0, 0, };
472static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
473static int jz4760_lcd_24bit_funcs[] = {
474 0, 0, 0, 0, 0, 0, 0, 0,
475 0, 0, 0, 0, 0, 0, 0, 0,
476 0, 0, 0, 0, 0, 0, 0, 0,
477 0, 0, 0, 0,
478};
479static int jz4760_pwm_pwm0_funcs[] = { 0, };
480static int jz4760_pwm_pwm1_funcs[] = { 0, };
481static int jz4760_pwm_pwm2_funcs[] = { 0, };
482static int jz4760_pwm_pwm3_funcs[] = { 0, };
483static int jz4760_pwm_pwm4_funcs[] = { 0, };
484static int jz4760_pwm_pwm5_funcs[] = { 0, };
485static int jz4760_pwm_pwm6_funcs[] = { 0, };
486static int jz4760_pwm_pwm7_funcs[] = { 0, };
487
488static const struct group_desc jz4760_groups[] = {
489 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data),
490 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow),
491 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data),
492 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow),
493 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data),
494 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow),
495 INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data),
496 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow),
497 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a),
498 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a),
499 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e),
500 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e),
501 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e),
502 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d),
503 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d),
504 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e),
505 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e),
506 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e),
507 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b),
508 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b),
509 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e),
510 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e),
511 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e),
512 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data),
513 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data),
514 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale),
515 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr),
516 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we),
517 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe),
518 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait),
519 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1),
520 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2),
521 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3),
522 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4),
523 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5),
524 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6),
525 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0),
526 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1),
527 INGENIC_PIN_GROUP("cim-data", jz4760_cim),
528 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit),
529 { "lcd-no-pins", },
530 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0),
531 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1),
532 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2),
533 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3),
534 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4),
535 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5),
536 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6),
537 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7),
538};
539
540static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
541static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
542static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
543static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
544static const char *jz4760_mmc0_groups[] = {
545 "mmc0-1bit-a", "mmc0-4bit-a",
546 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
547};
548static const char *jz4760_mmc1_groups[] = {
549 "mmc1-1bit-d", "mmc1-4bit-d",
550 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
551};
552static const char *jz4760_mmc2_groups[] = {
553 "mmc2-1bit-b", "mmc2-4bit-b",
554 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
555};
556static const char *jz4760_nemc_groups[] = {
557 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
558 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
559};
560static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
561static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
562static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
563static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
564static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
565static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
566static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
567static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
568static const char *jz4760_cim_groups[] = { "cim-data", };
569static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
570static const char *jz4760_pwm0_groups[] = { "pwm0", };
571static const char *jz4760_pwm1_groups[] = { "pwm1", };
572static const char *jz4760_pwm2_groups[] = { "pwm2", };
573static const char *jz4760_pwm3_groups[] = { "pwm3", };
574static const char *jz4760_pwm4_groups[] = { "pwm4", };
575static const char *jz4760_pwm5_groups[] = { "pwm5", };
576static const char *jz4760_pwm6_groups[] = { "pwm6", };
577static const char *jz4760_pwm7_groups[] = { "pwm7", };
578
579static const struct function_desc jz4760_functions[] = {
580 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
581 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
582 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
583 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
584 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
585 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
586 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
587 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
588 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
589 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
590 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
591 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
592 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
593 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
594 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
595 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
596 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
597 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
598 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
599 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
600 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
601 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
602 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
603 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
604 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
605 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
606};
607
608static const struct ingenic_chip_info jz4760_chip_info = {
609 .num_chips = 6,
f742e5eb 610 .reg_offset = 0x100,
baf15647 611 .version = ID_JZ4760,
0257595a
ZY		 612 .groups = jz4760_groups,
613 .num_groups = ARRAY_SIZE(jz4760_groups),
614 .functions = jz4760_functions,
615 .num_functions = ARRAY_SIZE(jz4760_functions),
616 .pull_ups = jz4760_pull_ups,
617 .pull_downs = jz4760_pull_downs,
618};
619
b5c23aa4
PC		 620static const u32 jz4770_pull_ups[6] = {
621 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
622};
623
624static const u32 jz4770_pull_downs[6] = {
625 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
626};
627
628static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
629static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
630static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
631static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
ff656e47
ZY		 632static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
633static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
b5c23aa4
PC		 634static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
635static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
b5c23aa4 636static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
ff656e47 637static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
b5c23aa4 638static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
ff656e47
ZY		 639static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
640static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
b5c23aa4 641static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
ff656e47 642static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
b5c23aa4 643static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
ff656e47
ZY		 644static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
645static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
5de1a73e
ZY		 646static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
647static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
648static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
649static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
650static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
ff656e47 651static int jz4770_nemc_8bit_data_pins[] = {
b5c23aa4
PC		 652 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
653};
ff656e47
ZY		 654static int jz4770_nemc_16bit_data_pins[] = {
655 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
656};
b5c23aa4
PC		 657static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
658static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
659static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
660static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
5de1a73e 661static int jz4770_nemc_wait_pins[] = { 0x1b, };
b5c23aa4
PC		 662static int jz4770_nemc_cs1_pins[] = { 0x15, };
663static int jz4770_nemc_cs2_pins[] = { 0x16, };
664static int jz4770_nemc_cs3_pins[] = { 0x17, };
665static int jz4770_nemc_cs4_pins[] = { 0x18, };
666static int jz4770_nemc_cs5_pins[] = { 0x19, };
667static int jz4770_nemc_cs6_pins[] = { 0x1a, };
ff656e47
ZY		 668static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
669static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
b5c23aa4 670static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
ff656e47
ZY		 671static int jz4770_cim_8bit_pins[] = {
672 0x26, 0x27, 0x28, 0x29,
673 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
674};
675static int jz4770_cim_12bit_pins[] = {
676 0x32, 0x33, 0xb0, 0xb1,
b5c23aa4 677};
ff656e47 678static int jz4770_lcd_24bit_pins[] = {
b5c23aa4
PC		 679 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
680 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
681 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
ff656e47 682 0x58, 0x59, 0x5a, 0x5b,
b5c23aa4
PC		 683};
684static int jz4770_pwm_pwm0_pins[] = { 0x80, };
685static int jz4770_pwm_pwm1_pins[] = { 0x81, };
686static int jz4770_pwm_pwm2_pins[] = { 0x82, };
687static int jz4770_pwm_pwm3_pins[] = { 0x83, };
688static int jz4770_pwm_pwm4_pins[] = { 0x84, };
689static int jz4770_pwm_pwm5_pins[] = { 0x85, };
690static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
691static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
5de1a73e
ZY		 692static int jz4770_mac_rmii_pins[] = {
693 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
694};
695static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
ae75b53e 696static int jz4770_otg_pins[] = { 0x8a, };
b5c23aa4
PC		 697
698static int jz4770_uart0_data_funcs[] = { 0, 0, };
699static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
700static int jz4770_uart1_data_funcs[] = { 0, 0, };
701static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
ff656e47
ZY		 702static int jz4770_uart2_data_funcs[] = { 0, 0, };
703static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
b5c23aa4
PC		 704static int jz4770_uart3_data_funcs[] = { 0, 1, };
705static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
b5c23aa4 706static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
ff656e47 707static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
b5c23aa4 708static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
ff656e47
ZY		 709static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
710static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
b5c23aa4 711static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
ff656e47 712static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
b5c23aa4 713static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
ff656e47
ZY		 714static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
715static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
5de1a73e
ZY		 716static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
717static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
718static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
719static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
720static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
ff656e47
ZY		 721static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
722static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
b5c23aa4
PC		 723static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
724static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
725static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
726static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
5de1a73e 727static int jz4770_nemc_wait_funcs[] = { 0, };
b5c23aa4
PC		 728static int jz4770_nemc_cs1_funcs[] = { 0, };
729static int jz4770_nemc_cs2_funcs[] = { 0, };
730static int jz4770_nemc_cs3_funcs[] = { 0, };
731static int jz4770_nemc_cs4_funcs[] = { 0, };
732static int jz4770_nemc_cs5_funcs[] = { 0, };
733static int jz4770_nemc_cs6_funcs[] = { 0, };
734static int jz4770_i2c0_funcs[] = { 0, 0, };
735static int jz4770_i2c1_funcs[] = { 0, 0, };
736static int jz4770_i2c2_funcs[] = { 2, 2, };
ff656e47
ZY		 737static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
738static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
739static int jz4770_lcd_24bit_funcs[] = {
740 0, 0, 0, 0, 0, 0, 0, 0,
b5c23aa4
PC		 741 0, 0, 0, 0, 0, 0, 0, 0,
742 0, 0, 0, 0, 0, 0, 0, 0,
ff656e47 743 0, 0, 0, 0,
b5c23aa4
PC		 744};
745static int jz4770_pwm_pwm0_funcs[] = { 0, };
746static int jz4770_pwm_pwm1_funcs[] = { 0, };
747static int jz4770_pwm_pwm2_funcs[] = { 0, };
748static int jz4770_pwm_pwm3_funcs[] = { 0, };
749static int jz4770_pwm_pwm4_funcs[] = { 0, };
750static int jz4770_pwm_pwm5_funcs[] = { 0, };
751static int jz4770_pwm_pwm6_funcs[] = { 0, };
752static int jz4770_pwm_pwm7_funcs[] = { 0, };
5de1a73e
ZY		 753static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
754static int jz4770_mac_mii_funcs[] = { 0, 0, };
ae75b53e 755static int jz4770_otg_funcs[] = { 0, };
b5c23aa4
PC		 756
757static const struct group_desc jz4770_groups[] = {
758 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
759 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
760 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
761 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
762 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
763 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
764 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
765 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
b5c23aa4 766 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
ff656e47 767 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
b5c23aa4 768 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
ff656e47
ZY		 769 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
770 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
b5c23aa4 771 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
ff656e47 772 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
b5c23aa4 773 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
ff656e47
ZY		 774 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
775 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
5de1a73e
ZY		 776 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
777 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
778 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
779 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
780 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
ff656e47
ZY		 781 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
782 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
b5c23aa4
PC		 783 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
784 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
785 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
786 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
5de1a73e 787 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
b5c23aa4
PC		 788 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
789 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
790 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
791 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
792 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
793 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
794 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
795 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
796 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
ff656e47
ZY		 797 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
798 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
799 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
b5c23aa4
PC		 800 { "lcd-no-pins", },
801 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
802 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
803 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
804 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
805 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
806 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
807 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
808 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
5de1a73e
ZY		 809 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
810 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
ae75b53e 811 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg),
b5c23aa4
PC		 812};
813
814static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
815static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
816static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
817static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
b5c23aa4 818static const char *jz4770_mmc0_groups[] = {
ff656e47
ZY		 819 "mmc0-1bit-a", "mmc0-4bit-a",
820 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
b5c23aa4
PC		 821};
822static const char *jz4770_mmc1_groups[] = {
ff656e47
ZY		 823 "mmc1-1bit-d", "mmc1-4bit-d",
824 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
b5c23aa4 825};
5de1a73e
ZY		 826static const char *jz4770_mmc2_groups[] = {
827 "mmc2-1bit-b", "mmc2-4bit-b",
828 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
829};
b5c23aa4 830static const char *jz4770_nemc_groups[] = {
ff656e47 831 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
5de1a73e 832 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
b5c23aa4
PC		 833};
834static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
ff656e47
ZY		 835static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
836static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
837static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
838static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
b5c23aa4
PC		 839static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
840static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
841static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
842static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
ff656e47
ZY		 843static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
844static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
b5c23aa4
PC		 845static const char *jz4770_pwm0_groups[] = { "pwm0", };
846static const char *jz4770_pwm1_groups[] = { "pwm1", };
847static const char *jz4770_pwm2_groups[] = { "pwm2", };
848static const char *jz4770_pwm3_groups[] = { "pwm3", };
849static const char *jz4770_pwm4_groups[] = { "pwm4", };
850static const char *jz4770_pwm5_groups[] = { "pwm5", };
851static const char *jz4770_pwm6_groups[] = { "pwm6", };
852static const char *jz4770_pwm7_groups[] = { "pwm7", };
5de1a73e 853static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
ae75b53e 854static const char *jz4770_otg_groups[] = { "otg-vbus", };
b5c23aa4
PC		 855
856static const struct function_desc jz4770_functions[] = {
857 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
858 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
859 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
860 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
b5c23aa4
PC		 861 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
862 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
5de1a73e 863 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
b5c23aa4
PC		 864 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
865 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
ff656e47
ZY		 866 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
867 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
868 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
869 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
b5c23aa4
PC		 870 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
871 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
872 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
873 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
b5c23aa4
PC		 874 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
875 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
876 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
877 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
878 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
879 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
880 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
881 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
882 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
883 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
5de1a73e 884 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
ae75b53e 885 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), },
b5c23aa4
PC		 886};
887
888static const struct ingenic_chip_info jz4770_chip_info = {
889 .num_chips = 6,
f742e5eb 890 .reg_offset = 0x100,
baf15647 891 .version = ID_JZ4770,
b5c23aa4
PC		 892 .groups = jz4770_groups,
893 .num_groups = ARRAY_SIZE(jz4770_groups),
894 .functions = jz4770_functions,
895 .num_functions = ARRAY_SIZE(jz4770_functions),
896 .pull_ups = jz4770_pull_ups,
897 .pull_downs = jz4770_pull_downs,
898};
899
ff656e47
ZY		 900static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
901static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
902static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
903static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
904static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
905static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
906static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
a0bb89e8 907static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
ff656e47
ZY		 908
909static int jz4780_uart2_data_funcs[] = { 1, 1, };
910static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
911static int jz4780_uart4_data_funcs[] = { 2, 2, };
912static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
913static int jz4780_i2c3_funcs[] = { 1, 1, };
914static int jz4780_i2c4_e_funcs[] = { 1, 1, };
915static int jz4780_i2c4_f_funcs[] = { 1, 1, };
a0bb89e8 916static int jz4780_hdmi_ddc_funcs[] = { 0, 0, };
ff656e47
ZY		 917
918static const struct group_desc jz4780_groups[] = {
919 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
920 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
921 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
922 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
923 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
924 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
925 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
926 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
927 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
928 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
929 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
930 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
931 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
932 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
933 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
934 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
935 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
936 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
5de1a73e
ZY		 937 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
938 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
939 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
940 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
ff656e47
ZY		 941 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
942 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
943 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
944 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
945 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
5de1a73e 946 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
ff656e47
ZY		 947 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
948 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
949 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
950 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
951 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
952 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
953 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
954 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
955 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
956 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
957 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
958 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
a0bb89e8 959 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc),
ff656e47
ZY		 960 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
961 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
962 { "lcd-no-pins", },
963 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
964 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
965 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
966 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
967 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
968 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
969 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
970 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
971};
972
973static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
974static const char *jz4780_uart4_groups[] = { "uart4-data", };
975static const char *jz4780_mmc0_groups[] = {
976 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
977 "mmc0-1bit-e", "mmc0-4bit-e",
978};
979static const char *jz4780_mmc1_groups[] = {
980 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
981};
5de1a73e
ZY		 982static const char *jz4780_mmc2_groups[] = {
983 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
984};
ff656e47
ZY		 985static const char *jz4780_nemc_groups[] = {
986 "nemc-data", "nemc-cle-ale", "nemc-addr",
5de1a73e 987 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
ff656e47
ZY		 988};
989static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
990static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
991static const char *jz4780_cim_groups[] = { "cim-data", };
a0bb89e8 992static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
ff656e47
ZY		 993
994static const struct function_desc jz4780_functions[] = {
995 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
996 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
997 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
998 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
999 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
1000 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
1001 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
5de1a73e 1002 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
ff656e47
ZY		 1003 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
1004 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1005 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1006 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1007 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1008 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1009 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1010 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1011 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1012 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1013 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
1014 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
1015 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
1016 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1017 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1018 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1019 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1020 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1021 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1022 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1023 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1024 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
a0bb89e8
PB		 1025 { "hdmi-ddc", jz4780_hdmi_ddc_groups,
1026 ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
ff656e47
ZY		 1027};
1028
1029static const struct ingenic_chip_info jz4780_chip_info = {
1030 .num_chips = 6,
f742e5eb 1031 .reg_offset = 0x100,
baf15647 1032 .version = ID_JZ4780,
ff656e47
ZY		 1033 .groups = jz4780_groups,
1034 .num_groups = ARRAY_SIZE(jz4780_groups),
1035 .functions = jz4780_functions,
1036 .num_functions = ARRAY_SIZE(jz4780_functions),
1037 .pull_ups = jz4770_pull_ups,
1038 .pull_downs = jz4770_pull_downs,
1039};
1040
fe1ad5ee 1041static const u32 x1000_pull_ups[4] = {
b4a9372a 1042 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
fe1ad5ee
ZY		 1043};
1044
1045static const u32 x1000_pull_downs[4] = {
1046 0x00000000, 0x02000000, 0x02000000, 0x00000000,
1047};
1048
1049static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
1050static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1051static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
1052static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
b4a9372a 1053static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
fe1ad5ee
ZY		 1054static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
1055static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
3b31e9b0
ZY		 1056static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, };
1057static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
1058static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
1059static int x1000_ssi_dt_d_pins[] = { 0x62, };
1060static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
1061static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
1062static int x1000_ssi_dr_d_pins[] = { 0x63, };
1063static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
1064static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
1065static int x1000_ssi_clk_d_pins[] = { 0x60, };
1066static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
1067static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
1068static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
1069static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
1070static int x1000_ssi_ce0_d_pins[] = { 0x61, };
1071static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
1072static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
fe1ad5ee
ZY		 1073static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
1074static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
1075static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
1076static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
1077static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
b4a9372a 1078static int x1000_emc_8bit_data_pins[] = {
fe1ad5ee
ZY		 1079 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1080};
b4a9372a 1081static int x1000_emc_16bit_data_pins[] = {
fe1ad5ee
ZY		 1082 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1083};
b4a9372a 1084static int x1000_emc_addr_pins[] = {
fe1ad5ee
ZY		 1085 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
1086 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
1087};
b4a9372a
ZY		 1088static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
1089static int x1000_emc_wait_pins[] = { 0x34, };
1090static int x1000_emc_cs1_pins[] = { 0x32, };
1091static int x1000_emc_cs2_pins[] = { 0x33, };
fe1ad5ee
ZY		 1092static int x1000_i2c0_pins[] = { 0x38, 0x37, };
1093static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
1094static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
1095static int x1000_i2c2_pins[] = { 0x61, 0x60, };
1096static int x1000_cim_pins[] = {
1097 0x08, 0x09, 0x0a, 0x0b,
1098 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1099};
1100static int x1000_lcd_8bit_pins[] = {
1101 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1102 0x30, 0x31, 0x32, 0x33, 0x34,
1103};
1104static int x1000_lcd_16bit_pins[] = {
1105 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1106};
1107static int x1000_pwm_pwm0_pins[] = { 0x59, };
1108static int x1000_pwm_pwm1_pins[] = { 0x5a, };
1109static int x1000_pwm_pwm2_pins[] = { 0x5b, };
1110static int x1000_pwm_pwm3_pins[] = { 0x26, };
1111static int x1000_pwm_pwm4_pins[] = { 0x58, };
1112static int x1000_mac_pins[] = {
1113 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
1114};
1115
1116static int x1000_uart0_data_funcs[] = { 0, 0, };
1117static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
1118static int x1000_uart1_data_a_funcs[] = { 2, 2, };
1119static int x1000_uart1_data_d_funcs[] = { 1, 1, };
b4a9372a 1120static int x1000_uart1_hwflow_funcs[] = { 1, 1, };
fe1ad5ee
ZY		 1121static int x1000_uart2_data_a_funcs[] = { 2, 2, };
1122static int x1000_uart2_data_d_funcs[] = { 0, 0, };
3b31e9b0
ZY		 1123static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
1124static int x1000_ssi_dt_a_22_funcs[] = { 2, };
1125static int x1000_ssi_dt_a_29_funcs[] = { 2, };
1126static int x1000_ssi_dt_d_funcs[] = { 0, };
1127static int x1000_ssi_dr_a_23_funcs[] = { 2, };
1128static int x1000_ssi_dr_a_28_funcs[] = { 2, };
1129static int x1000_ssi_dr_d_funcs[] = { 0, };
1130static int x1000_ssi_clk_a_24_funcs[] = { 2, };
1131static int x1000_ssi_clk_a_26_funcs[] = { 2, };
1132static int x1000_ssi_clk_d_funcs[] = { 0, };
1133static int x1000_ssi_gpc_a_20_funcs[] = { 2, };
1134static int x1000_ssi_gpc_a_31_funcs[] = { 2, };
1135static int x1000_ssi_ce0_a_25_funcs[] = { 2, };
1136static int x1000_ssi_ce0_a_27_funcs[] = { 2, };
1137static int x1000_ssi_ce0_d_funcs[] = { 0, };
1138static int x1000_ssi_ce1_a_21_funcs[] = { 2, };
1139static int x1000_ssi_ce1_a_30_funcs[] = { 2, };
fe1ad5ee
ZY		 1140static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
1141static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
1142static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
1143static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
1144static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
b4a9372a
ZY		 1145static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1146static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1147static int x1000_emc_addr_funcs[] = {
fe1ad5ee
ZY		 1148 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1149};
b4a9372a
ZY		 1150static int x1000_emc_rd_we_funcs[] = { 0, 0, };
1151static int x1000_emc_wait_funcs[] = { 0, };
1152static int x1000_emc_cs1_funcs[] = { 0, };
1153static int x1000_emc_cs2_funcs[] = { 0, };
fe1ad5ee
ZY		 1154static int x1000_i2c0_funcs[] = { 0, 0, };
1155static int x1000_i2c1_a_funcs[] = { 2, 2, };
1156static int x1000_i2c1_c_funcs[] = { 0, 0, };
1157static int x1000_i2c2_funcs[] = { 1, 1, };
1158static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
1159static int x1000_lcd_8bit_funcs[] = {
1160 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1161};
1162static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
1163static int x1000_pwm_pwm0_funcs[] = { 0, };
1164static int x1000_pwm_pwm1_funcs[] = { 1, };
1165static int x1000_pwm_pwm2_funcs[] = { 1, };
1166static int x1000_pwm_pwm3_funcs[] = { 2, };
1167static int x1000_pwm_pwm4_funcs[] = { 0, };
1168static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
1169
1170static const struct group_desc x1000_groups[] = {
1171 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
1172 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
1173 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
1174 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
b4a9372a 1175 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow),
fe1ad5ee
ZY		 1176 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
1177 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
3b31e9b0
ZY		 1178 INGENIC_PIN_GROUP("sfc", x1000_sfc),
1179 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22),
1180 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29),
1181 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d),
1182 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23),
1183 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28),
1184 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d),
1185 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24),
1186 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26),
1187 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d),
1188 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20),
1189 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31),
1190 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25),
1191 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27),
1192 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d),
1193 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21),
1194 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30),
fe1ad5ee
ZY		 1195 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
1196 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
1197 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
1198 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
1199 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
b4a9372a
ZY		 1200 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data),
1201 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data),
1202 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr),
1203 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we),
1204 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait),
1205 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1),
1206 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2),
fe1ad5ee
ZY		 1207 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
1208 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
1209 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
1210 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
1211 INGENIC_PIN_GROUP("cim-data", x1000_cim),
1212 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
1213 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
1214 { "lcd-no-pins", },
1215 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0),
1216 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1),
1217 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2),
1218 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3),
1219 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4),
1220 INGENIC_PIN_GROUP("mac", x1000_mac),
1221};
1222
1223static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1224static const char *x1000_uart1_groups[] = {
b4a9372a 1225 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
fe1ad5ee
ZY		 1226};
1227static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
3b31e9b0
ZY		 1228static const char *x1000_sfc_groups[] = { "sfc", };
1229static const char *x1000_ssi_groups[] = {
1230 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
1231 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
1232 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
1233 "ssi-gpc-a-20", "ssi-gpc-a-31",
1234 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
1235 "ssi-ce1-a-21", "ssi-ce1-a-30",
1236};
fe1ad5ee
ZY		 1237static const char *x1000_mmc0_groups[] = {
1238 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
1239};
1240static const char *x1000_mmc1_groups[] = {
b4a9372a 1241 "mmc1-1bit", "mmc1-4bit",
fe1ad5ee 1242};
b4a9372a
ZY		 1243static const char *x1000_emc_groups[] = {
1244 "emc-8bit-data", "emc-16bit-data",
1245 "emc-addr", "emc-rd-we", "emc-wait",
fe1ad5ee 1246};
b4a9372a
ZY		 1247static const char *x1000_cs1_groups[] = { "emc-cs1", };
1248static const char *x1000_cs2_groups[] = { "emc-cs2", };
fe1ad5ee
ZY		 1249static const char *x1000_i2c0_groups[] = { "i2c0-data", };
1250static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1251static const char *x1000_i2c2_groups[] = { "i2c2-data", };
1252static const char *x1000_cim_groups[] = { "cim-data", };
1253static const char *x1000_lcd_groups[] = {
1254 "lcd-8bit", "lcd-16bit", "lcd-no-pins",
1255};
1256static const char *x1000_pwm0_groups[] = { "pwm0", };
1257static const char *x1000_pwm1_groups[] = { "pwm1", };
1258static const char *x1000_pwm2_groups[] = { "pwm2", };
1259static const char *x1000_pwm3_groups[] = { "pwm3", };
1260static const char *x1000_pwm4_groups[] = { "pwm4", };
1261static const char *x1000_mac_groups[] = { "mac", };
1262
1263static const struct function_desc x1000_functions[] = {
1264 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
1265 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
1266 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
3b31e9b0
ZY		 1267 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
1268 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
fe1ad5ee
ZY		 1269 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
1270 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
b4a9372a
ZY		 1271 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
1272 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
1273 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
fe1ad5ee
ZY		 1274 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
1275 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
1276 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
1277 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
1278 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
1279 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
1280 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
1281 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
1282 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
1283 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
1284 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
1285};
1286
1287static const struct ingenic_chip_info x1000_chip_info = {
1288 .num_chips = 4,
f742e5eb 1289 .reg_offset = 0x100,
baf15647 1290 .version = ID_X1000,
fe1ad5ee
ZY		 1291 .groups = x1000_groups,
1292 .num_groups = ARRAY_SIZE(x1000_groups),
1293 .functions = x1000_functions,
1294 .num_functions = ARRAY_SIZE(x1000_functions),
1295 .pull_ups = x1000_pull_ups,
1296 .pull_downs = x1000_pull_downs,
1297};
1298
5d21595b
ZY		 1299static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
1300static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1301static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
1302static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
b4a9372a 1303static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
5d21595b
ZY		 1304static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
1305static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
b4a9372a
ZY		 1306static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
1307static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
5d21595b
ZY		 1308static int x1500_i2c0_pins[] = { 0x38, 0x37, };
1309static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
1310static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
1311static int x1500_i2c2_pins[] = { 0x61, 0x60, };
1312static int x1500_cim_pins[] = {
1313 0x08, 0x09, 0x0a, 0x0b,
1314 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1315};
1316static int x1500_pwm_pwm0_pins[] = { 0x59, };
1317static int x1500_pwm_pwm1_pins[] = { 0x5a, };
1318static int x1500_pwm_pwm2_pins[] = { 0x5b, };
1319static int x1500_pwm_pwm3_pins[] = { 0x26, };
1320static int x1500_pwm_pwm4_pins[] = { 0x58, };
1321
1322static int x1500_uart0_data_funcs[] = { 0, 0, };
1323static int x1500_uart0_hwflow_funcs[] = { 0, 0, };
1324static int x1500_uart1_data_a_funcs[] = { 2, 2, };
1325static int x1500_uart1_data_d_funcs[] = { 1, 1, };
b4a9372a 1326static int x1500_uart1_hwflow_funcs[] = { 1, 1, };
5d21595b
ZY		 1327static int x1500_uart2_data_a_funcs[] = { 2, 2, };
1328static int x1500_uart2_data_d_funcs[] = { 0, 0, };
b4a9372a
ZY		 1329static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, };
1330static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, };
5d21595b
ZY		 1331static int x1500_i2c0_funcs[] = { 0, 0, };
1332static int x1500_i2c1_a_funcs[] = { 2, 2, };
1333static int x1500_i2c1_c_funcs[] = { 0, 0, };
1334static int x1500_i2c2_funcs[] = { 1, 1, };
1335static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
1336static int x1500_pwm_pwm0_funcs[] = { 0, };
1337static int x1500_pwm_pwm1_funcs[] = { 1, };
1338static int x1500_pwm_pwm2_funcs[] = { 1, };
1339static int x1500_pwm_pwm3_funcs[] = { 2, };
1340static int x1500_pwm_pwm4_funcs[] = { 0, };
1341
1342static const struct group_desc x1500_groups[] = {
1343 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data),
1344 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
1345 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
1346 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
b4a9372a 1347 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow),
5d21595b
ZY		 1348 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
1349 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
3b31e9b0 1350 INGENIC_PIN_GROUP("sfc", x1000_sfc),
b4a9372a
ZY		 1351 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit),
1352 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit),
5d21595b
ZY		 1353 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
1354 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
1355 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
1356 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
1357 INGENIC_PIN_GROUP("cim-data", x1500_cim),
1358 { "lcd-no-pins", },
1359 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0),
1360 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1),
1361 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2),
1362 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3),
1363 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4),
1364};
1365
1366static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1367static const char *x1500_uart1_groups[] = {
b4a9372a 1368 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
5d21595b
ZY		 1369};
1370static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
b4a9372a 1371static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
5d21595b
ZY		 1372static const char *x1500_i2c0_groups[] = { "i2c0-data", };
1373static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1374static const char *x1500_i2c2_groups[] = { "i2c2-data", };
1375static const char *x1500_cim_groups[] = { "cim-data", };
1376static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
1377static const char *x1500_pwm0_groups[] = { "pwm0", };
1378static const char *x1500_pwm1_groups[] = { "pwm1", };
1379static const char *x1500_pwm2_groups[] = { "pwm2", };
1380static const char *x1500_pwm3_groups[] = { "pwm3", };
1381static const char *x1500_pwm4_groups[] = { "pwm4", };
1382
1383static const struct function_desc x1500_functions[] = {
1384 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
1385 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
1386 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
3b31e9b0 1387 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
b4a9372a 1388 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
5d21595b
ZY		 1389 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
1390 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
1391 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
1392 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
1393 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
1394 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
1395 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
1396 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
1397 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
1398 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
1399};
1400
1401static const struct ingenic_chip_info x1500_chip_info = {
1402 .num_chips = 4,
f742e5eb 1403 .reg_offset = 0x100,
baf15647 1404 .version = ID_X1500,
5d21595b
ZY		 1405 .groups = x1500_groups,
1406 .num_groups = ARRAY_SIZE(x1500_groups),
1407 .functions = x1500_functions,
1408 .num_functions = ARRAY_SIZE(x1500_functions),
1409 .pull_ups = x1000_pull_ups,
1410 .pull_downs = x1000_pull_downs,
1411};
1412
d7da2a1e
ZY		 1413static const u32 x1830_pull_ups[4] = {
1414 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1415};
1416
1417static const u32 x1830_pull_downs[4] = {
1418 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1419};
1420
1421static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
1422static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
1423static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
1424static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, };
1425static int x1830_ssi0_dt_pins[] = { 0x4c, };
1426static int x1830_ssi0_dr_pins[] = { 0x4b, };
1427static int x1830_ssi0_clk_pins[] = { 0x4f, };
1428static int x1830_ssi0_gpc_pins[] = { 0x4d, };
1429static int x1830_ssi0_ce0_pins[] = { 0x50, };
1430static int x1830_ssi0_ce1_pins[] = { 0x4e, };
1431static int x1830_ssi1_dt_c_pins[] = { 0x53, };
1432static int x1830_ssi1_dr_c_pins[] = { 0x54, };
1433static int x1830_ssi1_clk_c_pins[] = { 0x57, };
1434static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
1435static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
1436static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
1437static int x1830_ssi1_dt_d_pins[] = { 0x62, };
1438static int x1830_ssi1_dr_d_pins[] = { 0x63, };
1439static int x1830_ssi1_clk_d_pins[] = { 0x66, };
1440static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
1441static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
1442static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
1443static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
1444static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
1445static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
1446static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
1447static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
1448static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
1449static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
b2954743
ZY		 1450static int x1830_lcd_rgb_18bit_pins[] = {
1451 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
1452 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f,
1453 0x70, 0x71, 0x72, 0x73, 0x76, 0x77,
1454 0x78, 0x79, 0x7a, 0x7b,
1455};
1456static int x1830_lcd_slcd_8bit_pins[] = {
1457 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
1458 0x69, 0x72, 0x73, 0x7b, 0x7a,
1459};
1460static int x1830_lcd_slcd_16bit_pins[] = {
1461 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
1462};
d7da2a1e
ZY		 1463static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
1464static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
1465static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
1466static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
1467static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
1468static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
1469static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
1470static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
1471static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
1472static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
1473static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
1474static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
1475static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
1476static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
1477static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
1478static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
1479static int x1830_mac_pins[] = {
1480 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
1481};
1482
1483static int x1830_uart0_data_funcs[] = { 0, 0, };
1484static int x1830_uart0_hwflow_funcs[] = { 0, 0, };
1485static int x1830_uart1_data_funcs[] = { 0, 0, };
1486static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
1487static int x1830_ssi0_dt_funcs[] = { 0, };
1488static int x1830_ssi0_dr_funcs[] = { 0, };
1489static int x1830_ssi0_clk_funcs[] = { 0, };
1490static int x1830_ssi0_gpc_funcs[] = { 0, };
1491static int x1830_ssi0_ce0_funcs[] = { 0, };
1492static int x1830_ssi0_ce1_funcs[] = { 0, };
1493static int x1830_ssi1_dt_c_funcs[] = { 1, };
1494static int x1830_ssi1_dr_c_funcs[] = { 1, };
1495static int x1830_ssi1_clk_c_funcs[] = { 1, };
1496static int x1830_ssi1_gpc_c_funcs[] = { 1, };
1497static int x1830_ssi1_ce0_c_funcs[] = { 1, };
1498static int x1830_ssi1_ce1_c_funcs[] = { 1, };
1499static int x1830_ssi1_dt_d_funcs[] = { 2, };
1500static int x1830_ssi1_dr_d_funcs[] = { 2, };
1501static int x1830_ssi1_clk_d_funcs[] = { 2, };
1502static int x1830_ssi1_gpc_d_funcs[] = { 2, };
1503static int x1830_ssi1_ce0_d_funcs[] = { 2, };
1504static int x1830_ssi1_ce1_d_funcs[] = { 2, };
1505static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, };
1506static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, };
1507static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, };
1508static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, };
1509static int x1830_i2c0_funcs[] = { 1, 1, };
1510static int x1830_i2c1_funcs[] = { 0, 0, };
1511static int x1830_i2c2_funcs[] = { 1, 1, };
b2954743
ZY		 1512static int x1830_lcd_rgb_18bit_funcs[] = {
1513 0, 0, 0, 0, 0, 0,
1514 0, 0, 0, 0, 0, 0,
1515 0, 0, 0, 0, 0, 0,
1516 0, 0, 0, 0,
1517};
1518static int x1830_lcd_slcd_8bit_funcs[] = {
1519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1520};
1521static int x1830_lcd_slcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
d7da2a1e
ZY		 1522static int x1830_pwm_pwm0_b_funcs[] = { 0, };
1523static int x1830_pwm_pwm0_c_funcs[] = { 1, };
1524static int x1830_pwm_pwm1_b_funcs[] = { 0, };
1525static int x1830_pwm_pwm1_c_funcs[] = { 1, };
1526static int x1830_pwm_pwm2_c_8_funcs[] = { 0, };
1527static int x1830_pwm_pwm2_c_13_funcs[] = { 1, };
1528static int x1830_pwm_pwm3_c_9_funcs[] = { 0, };
1529static int x1830_pwm_pwm3_c_14_funcs[] = { 1, };
1530static int x1830_pwm_pwm4_c_15_funcs[] = { 1, };
1531static int x1830_pwm_pwm4_c_25_funcs[] = { 0, };
1532static int x1830_pwm_pwm5_c_16_funcs[] = { 1, };
1533static int x1830_pwm_pwm5_c_26_funcs[] = { 0, };
1534static int x1830_pwm_pwm6_c_17_funcs[] = { 1, };
1535static int x1830_pwm_pwm6_c_27_funcs[] = { 0, };
1536static int x1830_pwm_pwm7_c_18_funcs[] = { 1, };
1537static int x1830_pwm_pwm7_c_28_funcs[] = { 0, };
1538static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1539
1540static const struct group_desc x1830_groups[] = {
1541 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data),
1542 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow),
1543 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data),
1544 INGENIC_PIN_GROUP("sfc", x1830_sfc),
1545 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt),
1546 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr),
1547 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk),
1548 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc),
1549 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0),
1550 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1),
1551 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c),
1552 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c),
1553 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c),
1554 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c),
1555 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c),
1556 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c),
1557 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d),
1558 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d),
1559 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d),
1560 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d),
1561 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d),
1562 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d),
1563 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit),
1564 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit),
1565 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit),
1566 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit),
1567 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0),
1568 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1),
1569 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2),
b2954743
ZY		 1570 INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit),
1571 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit),
1572 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit),
1573 { "lcd-no-pins", },
d7da2a1e
ZY		 1574 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b),
1575 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c),
1576 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b),
1577 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c),
1578 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8),
1579 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13),
1580 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9),
1581 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14),
1582 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15),
1583 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25),
1584 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16),
1585 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26),
1586 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17),
1587 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27),
1588 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18),
1589 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28),
1590 INGENIC_PIN_GROUP("mac", x1830_mac),
1591};
1592
1593static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1594static const char *x1830_uart1_groups[] = { "uart1-data", };
1595static const char *x1830_sfc_groups[] = { "sfc", };
1596static const char *x1830_ssi0_groups[] = {
1597 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
1598};
1599static const char *x1830_ssi1_groups[] = {
1600 "ssi1-dt-c", "ssi1-dt-d",
1601 "ssi1-dr-c", "ssi1-dr-d",
1602 "ssi1-clk-c", "ssi1-clk-d",
1603 "ssi1-gpc-c", "ssi1-gpc-d",
1604 "ssi1-ce0-c", "ssi1-ce0-d",
1605 "ssi1-ce1-c", "ssi1-ce1-d",
1606};
1607static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
1608static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
1609static const char *x1830_i2c0_groups[] = { "i2c0-data", };
1610static const char *x1830_i2c1_groups[] = { "i2c1-data", };
1611static const char *x1830_i2c2_groups[] = { "i2c2-data", };
b2954743
ZY		 1612static const char *x1830_lcd_groups[] = {
1613 "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins",
1614};
d7da2a1e
ZY		 1615static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
1616static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
1617static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
1618static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
1619static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
1620static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
1621static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
1622static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
1623static const char *x1830_mac_groups[] = { "mac", };
1624
1625static const struct function_desc x1830_functions[] = {
1626 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
1627 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
1628 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
1629 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
1630 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
1631 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
1632 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
1633 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
1634 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
1635 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
b2954743 1636 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
d7da2a1e
ZY		 1637 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
1638 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
1639 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
1640 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
1641 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1642 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1643 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1644 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1645 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
1646};
1647
1648static const struct ingenic_chip_info x1830_chip_info = {
1649 .num_chips = 4,
1650 .reg_offset = 0x1000,
baf15647 1651 .version = ID_X1830,
d7da2a1e
ZY		 1652 .groups = x1830_groups,
1653 .num_groups = ARRAY_SIZE(x1830_groups),
1654 .functions = x1830_functions,
1655 .num_functions = ARRAY_SIZE(x1830_functions),
1656 .pull_ups = x1830_pull_ups,
1657 .pull_downs = x1830_pull_downs,
1658};
1659
b71c1844 1660static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
e72394e2
PC		 1661{
1662 unsigned int val;
1663
1664 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
1665
1666 return (u32) val;
1667}
1668
b71c1844 1669static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
e72394e2
PC		 1670 u8 reg, u8 offset, bool set)
1671{
1672 if (set)
1673 reg = REG_SET(reg);
1674 else
1675 reg = REG_CLEAR(reg);
1676
1677 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
1678}
1679
fe1ad5ee
ZY		 1680static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
1681 u8 reg, u8 offset, bool set)
1682{
1683 if (set)
1684 reg = REG_SET(reg);
1685 else
1686 reg = REG_CLEAR(reg);
1687
d7da2a1e
ZY		 1688 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
1689 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
fe1ad5ee
ZY		 1690}
1691
1692static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
1693{
d7da2a1e
ZY		 1694 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
1695 jzgc->jzpc->info->reg_offset),
fe1ad5ee
ZY		 1696 jzgc->gc.base / PINS_PER_GPIO_CHIP);
1697}
1698
e72394e2
PC		 1699static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
1700 u8 offset)
1701{
b71c1844 1702 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
e72394e2
PC		 1703
1704 return !!(val & BIT(offset));
1705}
1706
1707static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
1708 u8 offset, int value)
1709{
baf15647 1710 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1711 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);
e72394e2 1712 else
b71c1844 1713 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
e72394e2
PC		 1714}
1715
1716static void irq_set_type(struct ingenic_gpio_chip *jzgc,
1717 u8 offset, unsigned int type)
1718{
1719 u8 reg1, reg2;
f831f93a 1720 bool val1, val2;
e72394e2
PC		 1721
1722 switch (type) {
1723 case IRQ_TYPE_EDGE_RISING:
f831f93a 1724 val1 = val2 = true;
e72394e2
PC		 1725 break;
1726 case IRQ_TYPE_EDGE_FALLING:
f831f93a
PC		 1727 val1 = false;
1728 val2 = true;
e72394e2
PC		 1729 break;
1730 case IRQ_TYPE_LEVEL_HIGH:
f831f93a
PC		 1731 val1 = true;
1732 val2 = false;
e72394e2
PC		 1733 break;
1734 case IRQ_TYPE_LEVEL_LOW:
1735 default:
f831f93a 1736 val1 = val2 = false;
e72394e2
PC		 1737 break;
1738 }
f831f93a
PC		 1739
1740 if (jzgc->jzpc->info->version >= ID_JZ4760) {
1741 reg1 = JZ4760_GPIO_PAT1;
1742 reg2 = JZ4760_GPIO_PAT0;
1743 } else {
1744 reg1 = JZ4740_GPIO_TRIG;
1745 reg2 = JZ4740_GPIO_DIR;
1746 }
1747
1748 if (jzgc->jzpc->info->version >= ID_X1000) {
1749 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
1750 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
1751 ingenic_gpio_shadow_set_bit_load(jzgc);
1752 } else {
1753 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
1754 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
1755 }
e72394e2
PC		 1756}
1757
1758static void ingenic_gpio_irq_mask(struct irq_data *irqd)
1759{
1760 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1761 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1762
b71c1844 1763 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
e72394e2
PC		 1764}
1765
1766static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
1767{
1768 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1769 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1770
b71c1844 1771 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
e72394e2
PC		 1772}
1773
1774static void ingenic_gpio_irq_enable(struct irq_data *irqd)
1775{
1776 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1777 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1778 int irq = irqd->hwirq;
1779
baf15647 1780 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1781 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);
e72394e2 1782 else
b71c1844 1783 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
e72394e2
PC		 1784
1785 ingenic_gpio_irq_unmask(irqd);
1786}
1787
1788static void ingenic_gpio_irq_disable(struct irq_data *irqd)
1789{
1790 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1791 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1792 int irq = irqd->hwirq;
1793
1794 ingenic_gpio_irq_mask(irqd);
1795
baf15647 1796 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1797 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);
e72394e2 1798 else
b71c1844 1799 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
e72394e2
PC		 1800}
1801
1802static void ingenic_gpio_irq_ack(struct irq_data *irqd)
1803{
1804 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1805 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1806 int irq = irqd->hwirq;
1807 bool high;
1808
1809 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
1810 /*
1811 * Switch to an interrupt for the opposite edge to the one that
1812 * triggered the interrupt being ACKed.
1813 */
1814 high = ingenic_gpio_get_value(jzgc, irq);
1815 if (high)
1816 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING);
1817 else
1818 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
1819 }
1820
baf15647 1821 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1822 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);
e72394e2 1823 else
b71c1844 1824 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
e72394e2
PC		 1825}
1826
1827static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
1828{
1829 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1830 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1831
1832 switch (type) {
1833 case IRQ_TYPE_EDGE_BOTH:
1834 case IRQ_TYPE_EDGE_RISING:
1835 case IRQ_TYPE_EDGE_FALLING:
1836 irq_set_handler_locked(irqd, handle_edge_irq);
1837 break;
1838 case IRQ_TYPE_LEVEL_HIGH:
1839 case IRQ_TYPE_LEVEL_LOW:
1840 irq_set_handler_locked(irqd, handle_level_irq);
1841 break;
1842 default:
1843 irq_set_handler_locked(irqd, handle_bad_irq);
1844 }
1845
1846 if (type == IRQ_TYPE_EDGE_BOTH) {
1847 /*
1848 * The hardware does not support interrupts on both edges. The
1849 * best we can do is to set up a single-edge interrupt and then
1850 * switch to the opposing edge when ACKing the interrupt.
1851 */
1852 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
1853
1854 type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
1855 }
1856
1857 irq_set_type(jzgc, irqd->hwirq, type);
1858 return 0;
1859}
1860
1861static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
1862{
1863 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1864 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1865
1866 return irq_set_irq_wake(jzgc->irq, on);
1867}
1868
1869static void ingenic_gpio_irq_handler(struct irq_desc *desc)
1870{
1871 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1872 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1873 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
1874 unsigned long flag, i;
1875
1876 chained_irq_enter(irq_chip, desc);
1877
baf15647 1878 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1879 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);
e72394e2 1880 else
b71c1844 1881 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
e72394e2
PC		 1882
1883 for_each_set_bit(i, &flag, 32)
1884 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
1885 chained_irq_exit(irq_chip, desc);
1886}
1887
1888static void ingenic_gpio_set(struct gpio_chip *gc,
1889 unsigned int offset, int value)
1890{
1891 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1892
1893 ingenic_gpio_set_value(jzgc, offset, value);
1894}
1895
1896static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
1897{
1898 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1899
1900 return (int) ingenic_gpio_get_value(jzgc, offset);
1901}
1902
1903static int ingenic_gpio_direction_input(struct gpio_chip *gc,
1904 unsigned int offset)
1905{
1906 return pinctrl_gpio_direction_input(gc->base + offset);
1907}
1908
1909static int ingenic_gpio_direction_output(struct gpio_chip *gc,
1910 unsigned int offset, int value)
1911{
1912 ingenic_gpio_set(gc, offset, value);
1913 return pinctrl_gpio_direction_output(gc->base + offset);
1914}
1915
b5c23aa4
PC		 1916static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
1917 unsigned int pin, u8 reg, bool set)
1918{
1919 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1920 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1921
f742e5eb 1922 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
b5c23aa4
PC		 1923 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1924}
1925
fe1ad5ee
ZY		 1926static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
1927 unsigned int pin, u8 reg, bool set)
1928{
1929 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1930
f742e5eb 1931 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
fe1ad5ee
ZY		 1932 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1933}
1934
1935static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
1936 unsigned int pin)
1937{
d7da2a1e
ZY		 1938 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
1939 pin / PINS_PER_GPIO_CHIP);
fe1ad5ee
ZY		 1940}
1941
b5c23aa4
PC		 1942static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
1943 unsigned int pin, u8 reg)
1944{
1945 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1946 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1947 unsigned int val;
1948
f742e5eb 1949 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
b5c23aa4
PC		 1950
1951 return val & BIT(idx);
1952}
1953
ebd66514
PC		 1954static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1955{
1956 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1957 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
1958 unsigned int pin = gc->base + offset;
1959
3c827873
MV		 1960 if (jzpc->info->version >= ID_JZ4760) {
1961 if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1))
1962 return GPIO_LINE_DIRECTION_IN;
1963 return GPIO_LINE_DIRECTION_OUT;
1964 }
ebd66514
PC		 1965
1966 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
3c827873
MV		 1967 return GPIO_LINE_DIRECTION_IN;
1968
1969 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
1970 return GPIO_LINE_DIRECTION_OUT;
ebd66514 1971
3c827873 1972 return GPIO_LINE_DIRECTION_IN;
ebd66514
PC		 1973}
1974
5bf7b849 1975static const struct pinctrl_ops ingenic_pctlops = {
b5c23aa4
PC		 1976 .get_groups_count = pinctrl_generic_get_group_count,
1977 .get_group_name = pinctrl_generic_get_group_name,
1978 .get_group_pins = pinctrl_generic_get_group_pins,
1979 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1980 .dt_free_map = pinconf_generic_dt_free_map,
1981};
1982
9a0f1341
PC		 1983static int ingenic_gpio_irq_request(struct irq_data *data)
1984{
1985 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
1986 int ret;
1987
1988 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq);
1989 if (ret)
1990 return ret;
1991
1992 return gpiochip_reqres_irq(gpio_chip, data->hwirq);
1993}
1994
1995static void ingenic_gpio_irq_release(struct irq_data *data)
1996{
1997 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
1998
1999 return gpiochip_relres_irq(gpio_chip, data->hwirq);
2000}
2001
b5c23aa4
PC		 2002static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
2003 int pin, int func)
2004{
2005 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2006 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2007
2008 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
2009 'A' + offt, idx, func);
2010
baf15647 2011 if (jzpc->info->version >= ID_X1000) {
fe1ad5ee
ZY		 2012 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
2013 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
2014 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
2015 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
2016 ingenic_shadow_config_pin_load(jzpc, pin);
baf15647 2017 } else if (jzpc->info->version >= ID_JZ4760) {
0257595a 2018 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
e72394e2 2019 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
0257595a
ZY		 2020 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
2021 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
b5c23aa4
PC		 2022 } else {
2023 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
2024 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
2025 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0);
2026 }
2027
2028 return 0;
2029}
2030
2031static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
2032 unsigned int selector, unsigned int group)
2033{
2034 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2035 struct function_desc *func;
2036 struct group_desc *grp;
2037 unsigned int i;
2038
2039 func = pinmux_generic_get_function(pctldev, selector);
2040 if (!func)
2041 return -EINVAL;
2042
2043 grp = pinctrl_generic_get_group(pctldev, group);
2044 if (!grp)
2045 return -EINVAL;
2046
2047 dev_dbg(pctldev->dev, "enable function %s group %s\n",
2048 func->name, grp->name);
2049
2050 for (i = 0; i < grp->num_pins; i++) {
2051 int *pin_modes = grp->data;
2052
2053 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
2054 }
2055
2056 return 0;
2057}
2058
2059static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
2060 struct pinctrl_gpio_range *range,
2061 unsigned int pin, bool input)
2062{
2063 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2064 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2065 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2066
2067 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
2068 'A' + offt, idx, input ? "in" : "out");
2069
baf15647 2070 if (jzpc->info->version >= ID_X1000) {
fe1ad5ee
ZY		 2071 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
2072 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
2073 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
2074 ingenic_shadow_config_pin_load(jzpc, pin);
baf15647 2075 } else if (jzpc->info->version >= ID_JZ4760) {
0257595a 2076 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
e72394e2 2077 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
0257595a 2078 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
b5c23aa4
PC		 2079 } else {
2080 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
0084a786 2081 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
b5c23aa4
PC		 2082 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
2083 }
2084
2085 return 0;
2086}
2087
5bf7b849 2088static const struct pinmux_ops ingenic_pmxops = {
b5c23aa4
PC		 2089 .get_functions_count = pinmux_generic_get_function_count,
2090 .get_function_name = pinmux_generic_get_function_name,
2091 .get_function_groups = pinmux_generic_get_function_groups,
2092 .set_mux = ingenic_pinmux_set_mux,
2093 .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
2094};
2095
2096static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
2097 unsigned int pin, unsigned long *config)
2098{
2099 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2100 enum pin_config_param param = pinconf_to_config_param(*config);
2101 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2102 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2103 bool pull;
2104
baf15647 2105 if (jzpc->info->version >= ID_JZ4760)
0257595a 2106 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN);
b5c23aa4
PC		 2107 else
2108 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
2109
2110 switch (param) {
2111 case PIN_CONFIG_BIAS_DISABLE:
2112 if (pull)
2113 return -EINVAL;
2114 break;
2115
2116 case PIN_CONFIG_BIAS_PULL_UP:
2117 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
2118 return -EINVAL;
2119 break;
2120
2121 case PIN_CONFIG_BIAS_PULL_DOWN:
2122 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
2123 return -EINVAL;
2124 break;
2125
2126 default:
2127 return -ENOTSUPP;
2128 }
2129
2130 *config = pinconf_to_config_packed(param, 1);
2131 return 0;
2132}
2133
2134static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
d7da2a1e 2135 unsigned int pin, unsigned int bias)
b5c23aa4 2136{
baf15647 2137 if (jzpc->info->version >= ID_X1830) {
d7da2a1e
ZY		 2138 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2139 unsigned int half = PINS_PER_GPIO_CHIP / 2;
2140 unsigned int idxh = pin % half * 2;
2141 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2142
2143 if (idx < half) {
2144 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2145 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
2146 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2147 REG_SET(X1830_GPIO_PEL), bias << idxh);
2148 } else {
2149 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2150 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
2151 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2152 REG_SET(X1830_GPIO_PEH), bias << idxh);
2153 }
2154
baf15647 2155 } else if (jzpc->info->version >= ID_JZ4760) {
d7da2a1e
ZY		 2156 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias);
2157 } else {
2158 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
2159 }
b5c23aa4
PC		 2160}
2161
7009d046
PC		 2162static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
2163 unsigned int pin, bool high)
2164{
baf15647 2165 if (jzpc->info->version >= ID_JZ4760)
7009d046
PC		 2166 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high);
2167 else
2168 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
2169}
2170
b5c23aa4
PC		 2171static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2172 unsigned long *configs, unsigned int num_configs)
2173{
2174 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2175 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2176 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
7009d046
PC		 2177 unsigned int cfg, arg;
2178 int ret;
b5c23aa4
PC		 2179
2180 for (cfg = 0; cfg < num_configs; cfg++) {
2181 switch (pinconf_to_config_param(configs[cfg])) {
2182 case PIN_CONFIG_BIAS_DISABLE:
2183 case PIN_CONFIG_BIAS_PULL_UP:
2184 case PIN_CONFIG_BIAS_PULL_DOWN:
7009d046 2185 case PIN_CONFIG_OUTPUT:
b5c23aa4
PC		 2186 continue;
2187 default:
2188 return -ENOTSUPP;
2189 }
2190 }
2191
2192 for (cfg = 0; cfg < num_configs; cfg++) {
7009d046
PC		 2193 arg = pinconf_to_config_argument(configs[cfg]);
2194
b5c23aa4
PC		 2195 switch (pinconf_to_config_param(configs[cfg])) {
2196 case PIN_CONFIG_BIAS_DISABLE:
2197 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
2198 'A' + offt, idx);
d7da2a1e 2199 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
b5c23aa4
PC		 2200 break;
2201
2202 case PIN_CONFIG_BIAS_PULL_UP:
2203 if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
2204 return -EINVAL;
2205 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
2206 'A' + offt, idx);
d7da2a1e 2207 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
b5c23aa4
PC		 2208 break;
2209
2210 case PIN_CONFIG_BIAS_PULL_DOWN:
2211 if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
2212 return -EINVAL;
2213 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
2214 'A' + offt, idx);
d7da2a1e 2215 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
b5c23aa4
PC		 2216 break;
2217
7009d046
PC		 2218 case PIN_CONFIG_OUTPUT:
2219 ret = pinctrl_gpio_direction_output(pin);
2220 if (ret)
2221 return ret;
2222
2223 ingenic_set_output_level(jzpc, pin, arg);
2224 break;
2225
b5c23aa4 2226 default:
d6d43a92
JP		 2227 /* unreachable */
2228 break;
b5c23aa4
PC		 2229 }
2230 }
2231
2232 return 0;
2233}
2234
2235static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
2236 unsigned int group, unsigned long *config)
2237{
2238 const unsigned int *pins;
2239 unsigned int i, npins, old = 0;
2240 int ret;
2241
2242 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2243 if (ret)
2244 return ret;
2245
2246 for (i = 0; i < npins; i++) {
2247 if (ingenic_pinconf_get(pctldev, pins[i], config))
2248 return -ENOTSUPP;
2249
2250 /* configs do not match between two pins */
2251 if (i && (old != *config))
2252 return -ENOTSUPP;
2253
2254 old = *config;
2255 }
2256
2257 return 0;
2258}
2259
2260static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
2261 unsigned int group, unsigned long *configs,
2262 unsigned int num_configs)
2263{
2264 const unsigned int *pins;
2265 unsigned int i, npins;
2266 int ret;
2267
2268 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2269 if (ret)
2270 return ret;
2271
2272 for (i = 0; i < npins; i++) {
2273 ret = ingenic_pinconf_set(pctldev,
2274 pins[i], configs, num_configs);
2275 if (ret)
2276 return ret;
2277 }
2278
2279 return 0;
2280}
2281
5bf7b849 2282static const struct pinconf_ops ingenic_confops = {
b5c23aa4
PC		 2283 .is_generic = true,
2284 .pin_config_get = ingenic_pinconf_get,
2285 .pin_config_set = ingenic_pinconf_set,
2286 .pin_config_group_get = ingenic_pinconf_group_get,
2287 .pin_config_group_set = ingenic_pinconf_group_set,
2288};
2289
2290static const struct regmap_config ingenic_pinctrl_regmap_config = {
2291 .reg_bits = 32,
2292 .val_bits = 32,
2293 .reg_stride = 4,
2294};
2295
e72394e2
PC		 2296static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
2297 { .compatible = "ingenic,jz4740-gpio", },
0257595a 2298 { .compatible = "ingenic,jz4760-gpio", },
e72394e2
PC		 2299 { .compatible = "ingenic,jz4770-gpio", },
2300 { .compatible = "ingenic,jz4780-gpio", },
fe1ad5ee 2301 { .compatible = "ingenic,x1000-gpio", },
d7da2a1e 2302 { .compatible = "ingenic,x1830-gpio", },
e72394e2
PC		 2303 {},
2304};
2305
2306static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
2307 struct device_node *node)
2308{
2309 struct ingenic_gpio_chip *jzgc;
2310 struct device *dev = jzpc->dev;
142b8767 2311 struct gpio_irq_chip *girq;
e72394e2
PC		 2312 unsigned int bank;
2313 int err;
2314
2315 err = of_property_read_u32(node, "reg", &bank);
2316 if (err) {
2317 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
2318 return err;
2319 }
2320
2321 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
2322 if (!jzgc)
2323 return -ENOMEM;
2324
2325 jzgc->jzpc = jzpc;
f742e5eb 2326 jzgc->reg_base = bank * jzpc->info->reg_offset;
e72394e2
PC		 2327
2328 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
2329 if (!jzgc->gc.label)
2330 return -ENOMEM;
2331
2332 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
2333 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
2334 * <linux/gpio/consumer.h> INSTEAD.
2335 */
2336 jzgc->gc.base = bank * 32;
2337
2338 jzgc->gc.ngpio = 32;
2339 jzgc->gc.parent = dev;
2340 jzgc->gc.of_node = node;
2341 jzgc->gc.owner = THIS_MODULE;
2342
2343 jzgc->gc.set = ingenic_gpio_set;
2344 jzgc->gc.get = ingenic_gpio_get;
2345 jzgc->gc.direction_input = ingenic_gpio_direction_input;
2346 jzgc->gc.direction_output = ingenic_gpio_direction_output;
ebd66514 2347 jzgc->gc.get_direction = ingenic_gpio_get_direction;
d6471d6e
TR		 2348 jzgc->gc.request = gpiochip_generic_request;
2349 jzgc->gc.free = gpiochip_generic_free;
e72394e2 2350
e72394e2
PC		 2351 jzgc->irq = irq_of_parse_and_map(node, 0);
2352 if (!jzgc->irq)
2353 return -EINVAL;
2354
2355 jzgc->irq_chip.name = jzgc->gc.label;
2356 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
2357 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
2358 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
2359 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
2360 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
2361 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
2362 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
9a0f1341
PC		 2363 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request;
2364 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release;
e72394e2
PC		 2365 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
2366
142b8767
LW		 2367 girq = &jzgc->gc.irq;
2368 girq->chip = &jzgc->irq_chip;
2369 girq->parent_handler = ingenic_gpio_irq_handler;
2370 girq->num_parents = 1;
2371 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
2372 GFP_KERNEL);
2373 if (!girq->parents)
2374 return -ENOMEM;
2375 girq->parents[0] = jzgc->irq;
2376 girq->default_type = IRQ_TYPE_NONE;
2377 girq->handler = handle_level_irq;
2378
2379 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
e72394e2
PC		 2380 if (err)
2381 return err;
2382
e72394e2
PC		 2383 return 0;
2384}
2385
4717b11f 2386static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
b5c23aa4
PC		 2387{
2388 struct device *dev = &pdev->dev;
2389 struct ingenic_pinctrl *jzpc;
2390 struct pinctrl_desc *pctl_desc;
2391 void __iomem *base;
b5c23aa4 2392 const struct ingenic_chip_info *chip_info;
e72394e2 2393 struct device_node *node;
b5c23aa4
PC		 2394 unsigned int i;
2395 int err;
2396
2397 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
2398 if (!jzpc)
2399 return -ENOMEM;
2400
94f7a2cb 2401 base = devm_platform_ioremap_resource(pdev, 0);
119fcf47 2402 if (IS_ERR(base))
b5c23aa4 2403 return PTR_ERR(base);
b5c23aa4
PC		 2404
2405 jzpc->map = devm_regmap_init_mmio(dev, base,
2406 &ingenic_pinctrl_regmap_config);
2407 if (IS_ERR(jzpc->map)) {
2408 dev_err(dev, "Failed to create regmap\n");
2409 return PTR_ERR(jzpc->map);
2410 }
2411
2412 jzpc->dev = dev;
baf15647 2413 jzpc->info = chip_info = of_device_get_match_data(dev);
b5c23aa4
PC		 2414
2415 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
2416 if (!pctl_desc)
2417 return -ENOMEM;
2418
2419 /* fill in pinctrl_desc structure */
2420 pctl_desc->name = dev_name(dev);
2421 pctl_desc->owner = THIS_MODULE;
2422 pctl_desc->pctlops = &ingenic_pctlops;
2423 pctl_desc->pmxops = &ingenic_pmxops;
2424 pctl_desc->confops = &ingenic_confops;
2425 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
a86854d0
KC		 2426 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
2427 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
b5c23aa4
PC		 2428 if (!jzpc->pdesc)
2429 return -ENOMEM;
2430
2431 for (i = 0; i < pctl_desc->npins; i++) {
2432 jzpc->pdesc[i].number = i;
2433 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
2434 'A' + (i / PINS_PER_GPIO_CHIP),
2435 i % PINS_PER_GPIO_CHIP);
2436 }
2437
2438 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
e7f4c4bf 2439 if (IS_ERR(jzpc->pctl)) {
b5c23aa4 2440 dev_err(dev, "Failed to register pinctrl\n");
e7f4c4bf 2441 return PTR_ERR(jzpc->pctl);
b5c23aa4
PC		 2442 }
2443
2444 for (i = 0; i < chip_info->num_groups; i++) {
2445 const struct group_desc *group = &chip_info->groups[i];
2446
2447 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
2448 group->pins, group->num_pins, group->data);
823dd71f 2449 if (err < 0) {
b5c23aa4
PC		 2450 dev_err(dev, "Failed to register group %s\n",
2451 group->name);
2452 return err;
2453 }
2454 }
2455
2456 for (i = 0; i < chip_info->num_functions; i++) {
2457 const struct function_desc *func = &chip_info->functions[i];
2458
2459 err = pinmux_generic_add_function(jzpc->pctl, func->name,
2460 func->group_names, func->num_group_names,
2461 func->data);
823dd71f 2462 if (err < 0) {
b5c23aa4
PC		 2463 dev_err(dev, "Failed to register function %s\n",
2464 func->name);
2465 return err;
2466 }
2467 }
2468
2469 dev_set_drvdata(dev, jzpc->map);
2470
e72394e2
PC		 2471 for_each_child_of_node(dev->of_node, node) {
2472 if (of_match_node(ingenic_gpio_of_match, node)) {
2473 err = ingenic_gpio_probe(jzpc, node);
2474 if (err)
2475 return err;
b5c23aa4
PC		 2476 }
2477 }
2478
2479 return 0;
2480}
2481
baf15647
PC		 2482static const struct of_device_id ingenic_pinctrl_of_match[] = {
2483 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info },
2484 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info },
2485 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info },
5ffdbb7e 2486 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info },
baf15647
PC		 2487 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info },
2488 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info },
2489 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info },
5ffdbb7e 2490 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info },
baf15647
PC		 2491 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info },
2492 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info },
2493 {},
2494};
2495
b5c23aa4
PC		 2496static struct platform_driver ingenic_pinctrl_driver = {
2497 .driver = {
2498 .name = "pinctrl-ingenic",
5ec008bf 2499 .of_match_table = ingenic_pinctrl_of_match,
b5c23aa4 2500 },
b5c23aa4
PC		 2501};
2502
2503static int __init ingenic_pinctrl_drv_register(void)
2504{
4717b11f
PC		 2505 return platform_driver_probe(&ingenic_pinctrl_driver,
2506 ingenic_pinctrl_probe);
b5c23aa4 2507}
556a36a7 2508subsys_initcall(ingenic_pinctrl_drv_register);
Linux 6.x block layer and io_uring tree(s)