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pinctrl: Use new GPIO_LINE_DIRECTION
[linux-block.git] / drivers / pinctrl / pinctrl-ingenic.c
CommitLineData
af873fce 1// SPDX-License-Identifier: GPL-2.0-only
b5c23aa4
PC		 2/*
3 * Ingenic SoCs pinctrl driver
4 *
5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
d7da2a1e 6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
b5c23aa4
PC		 7 */
8
9#include <linux/compiler.h>
28d6eeb4 10#include <linux/gpio/driver.h>
b5c23aa4
PC		 11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/of_device.h>
e72394e2 14#include <linux/of_irq.h>
b5c23aa4
PC		 15#include <linux/of_platform.h>
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23
24#include "core.h"
25#include "pinconf.h"
26#include "pinmux.h"
27
e72394e2
PC		 28#define GPIO_PIN 0x00
29#define GPIO_MSK 0x20
30
b5c23aa4
PC		 31#define JZ4740_GPIO_DATA 0x10
32#define JZ4740_GPIO_PULL_DIS 0x30
33#define JZ4740_GPIO_FUNC 0x40
34#define JZ4740_GPIO_SELECT 0x50
35#define JZ4740_GPIO_DIR 0x60
36#define JZ4740_GPIO_TRIG 0x70
37#define JZ4740_GPIO_FLAG 0x80
38
0257595a
ZY		 39#define JZ4760_GPIO_INT 0x10
40#define JZ4760_GPIO_PAT1 0x30
41#define JZ4760_GPIO_PAT0 0x40
42#define JZ4760_GPIO_FLAG 0x50
43#define JZ4760_GPIO_PEN 0x70
b5c23aa4 44
d7da2a1e
ZY		 45#define X1830_GPIO_PEL 0x110
46#define X1830_GPIO_PEH 0x120
fe1ad5ee 47
b5c23aa4
PC		 48#define REG_SET(x) ((x) + 0x4)
49#define REG_CLEAR(x) ((x) + 0x8)
50
d7da2a1e
ZY		 51#define REG_PZ_BASE(x) ((x) * 7)
52#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
53
54#define GPIO_PULL_DIS 0
55#define GPIO_PULL_UP 1
56#define GPIO_PULL_DOWN 2
57
b5c23aa4
PC		 58#define PINS_PER_GPIO_CHIP 32
59
60enum jz_version {
61 ID_JZ4740,
f2a96765 62 ID_JZ4725B,
0257595a 63 ID_JZ4760,
b5c23aa4
PC		 64 ID_JZ4770,
65 ID_JZ4780,
fe1ad5ee 66 ID_X1000,
5d21595b 67 ID_X1500,
d7da2a1e 68 ID_X1830,
b5c23aa4
PC		 69};
70
71struct ingenic_chip_info {
72 unsigned int num_chips;
f742e5eb 73 unsigned int reg_offset;
baf15647 74 enum jz_version version;
b5c23aa4
PC		 75
76 const struct group_desc *groups;
77 unsigned int num_groups;
78
79 const struct function_desc *functions;
80 unsigned int num_functions;
81
82 const u32 *pull_ups, *pull_downs;
83};
84
85struct ingenic_pinctrl {
86 struct device *dev;
87 struct regmap *map;
88 struct pinctrl_dev *pctl;
89 struct pinctrl_pin_desc *pdesc;
b5c23aa4
PC		 90
91 const struct ingenic_chip_info *info;
92};
93
e72394e2
PC		 94struct ingenic_gpio_chip {
95 struct ingenic_pinctrl *jzpc;
96 struct gpio_chip gc;
97 struct irq_chip irq_chip;
98 unsigned int irq, reg_base;
99};
100
b5c23aa4
PC		 101static const u32 jz4740_pull_ups[4] = {
102 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
103};
104
105static const u32 jz4740_pull_downs[4] = {
106 0x00000000, 0x00000000, 0x00000000, 0x00000000,
107};
108
109static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
110static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
111static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
112static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
113static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
114static int jz4740_lcd_8bit_pins[] = {
115 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
116};
117static int jz4740_lcd_16bit_pins[] = {
118 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
119};
120static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
121static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
122static int jz4740_nand_cs1_pins[] = { 0x39, };
123static int jz4740_nand_cs2_pins[] = { 0x3a, };
124static int jz4740_nand_cs3_pins[] = { 0x3b, };
125static int jz4740_nand_cs4_pins[] = { 0x3c, };
126static int jz4740_pwm_pwm0_pins[] = { 0x77, };
127static int jz4740_pwm_pwm1_pins[] = { 0x78, };
128static int jz4740_pwm_pwm2_pins[] = { 0x79, };
129static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
130static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
131static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
132static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
133static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
134
135static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, };
136static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, };
137static int jz4740_uart0_data_funcs[] = { 1, 1, };
138static int jz4740_uart0_hwflow_funcs[] = { 1, 1, };
139static int jz4740_uart1_data_funcs[] = { 2, 2, };
140static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
141static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, };
142static int jz4740_lcd_18bit_funcs[] = { 0, 0, };
143static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, };
144static int jz4740_nand_cs1_funcs[] = { 0, };
145static int jz4740_nand_cs2_funcs[] = { 0, };
146static int jz4740_nand_cs3_funcs[] = { 0, };
147static int jz4740_nand_cs4_funcs[] = { 0, };
148static int jz4740_pwm_pwm0_funcs[] = { 0, };
149static int jz4740_pwm_pwm1_funcs[] = { 0, };
150static int jz4740_pwm_pwm2_funcs[] = { 0, };
151static int jz4740_pwm_pwm3_funcs[] = { 0, };
152static int jz4740_pwm_pwm4_funcs[] = { 0, };
153static int jz4740_pwm_pwm5_funcs[] = { 0, };
154static int jz4740_pwm_pwm6_funcs[] = { 0, };
155static int jz4740_pwm_pwm7_funcs[] = { 0, };
156
157#define INGENIC_PIN_GROUP(name, id) \
158 { \
159 name, \
160 id##_pins, \
161 ARRAY_SIZE(id##_pins), \
162 id##_funcs, \
163 }
164
165static const struct group_desc jz4740_groups[] = {
166 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
167 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
168 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
169 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
170 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
171 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
172 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
173 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
174 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
175 { "lcd-no-pins", },
176 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
177 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
178 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
179 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
180 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
181 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
182 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
183 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3),
184 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4),
185 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5),
186 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6),
187 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
188};
189
190static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
191static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
192static const char *jz4740_uart1_groups[] = { "uart1-data", };
193static const char *jz4740_lcd_groups[] = {
194 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
195};
196static const char *jz4740_nand_groups[] = {
197 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
198};
199static const char *jz4740_pwm0_groups[] = { "pwm0", };
200static const char *jz4740_pwm1_groups[] = { "pwm1", };
201static const char *jz4740_pwm2_groups[] = { "pwm2", };
202static const char *jz4740_pwm3_groups[] = { "pwm3", };
203static const char *jz4740_pwm4_groups[] = { "pwm4", };
204static const char *jz4740_pwm5_groups[] = { "pwm5", };
205static const char *jz4740_pwm6_groups[] = { "pwm6", };
206static const char *jz4740_pwm7_groups[] = { "pwm7", };
207
208static const struct function_desc jz4740_functions[] = {
209 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
210 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
211 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
212 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
213 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
214 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
215 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
216 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
217 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
218 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
219 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
220 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
221 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
222};
223
224static const struct ingenic_chip_info jz4740_chip_info = {
225 .num_chips = 4,
f742e5eb 226 .reg_offset = 0x100,
baf15647 227 .version = ID_JZ4740,
b5c23aa4
PC		 228 .groups = jz4740_groups,
229 .num_groups = ARRAY_SIZE(jz4740_groups),
230 .functions = jz4740_functions,
231 .num_functions = ARRAY_SIZE(jz4740_functions),
232 .pull_ups = jz4740_pull_ups,
233 .pull_downs = jz4740_pull_downs,
234};
235
f2a96765
PC		 236static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
237static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
238static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
239static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
240static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
241static int jz4725b_nand_cs1_pins[] = { 0x55, };
242static int jz4725b_nand_cs2_pins[] = { 0x56, };
243static int jz4725b_nand_cs3_pins[] = { 0x57, };
244static int jz4725b_nand_cs4_pins[] = { 0x58, };
245static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
246static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
247static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
248static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
249static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
250static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
251static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
252static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
a3240f09
PC		 253static int jz4725b_lcd_8bit_pins[] = {
254 0x72, 0x73, 0x74,
255 0x60, 0x61, 0x62, 0x63,
256 0x64, 0x65, 0x66, 0x67,
257};
258static int jz4725b_lcd_16bit_pins[] = {
259 0x68, 0x69, 0x6a, 0x6b,
260 0x6c, 0x6d, 0x6e, 0x6f,
261};
262static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
263static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
264static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
265static int jz4725b_lcd_generic_pins[] = { 0x75, };
f2a96765
PC		 266
267static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, };
268static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
269static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, };
270static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, };
271static int jz4725b_uart_data_funcs[] = { 1, 1, };
272static int jz4725b_nand_cs1_funcs[] = { 0, };
273static int jz4725b_nand_cs2_funcs[] = { 0, };
274static int jz4725b_nand_cs3_funcs[] = { 0, };
275static int jz4725b_nand_cs4_funcs[] = { 0, };
276static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, };
277static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, };
278static int jz4725b_pwm_pwm0_funcs[] = { 0, };
279static int jz4725b_pwm_pwm1_funcs[] = { 0, };
280static int jz4725b_pwm_pwm2_funcs[] = { 0, };
281static int jz4725b_pwm_pwm3_funcs[] = { 0, };
282static int jz4725b_pwm_pwm4_funcs[] = { 0, };
283static int jz4725b_pwm_pwm5_funcs[] = { 0, };
a3240f09
PC		 284static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
285static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
286static int jz4725b_lcd_18bit_funcs[] = { 0, 0, };
287static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, };
288static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, };
289static int jz4725b_lcd_generic_funcs[] = { 0, };
f2a96765
PC		 290
291static const struct group_desc jz4725b_groups[] = {
292 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit),
293 INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit),
294 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit),
295 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit),
296 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data),
297 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1),
298 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2),
299 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3),
300 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4),
301 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale),
302 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe),
303 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0),
304 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1),
305 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2),
306 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3),
307 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4),
308 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
a3240f09
PC		 309 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit),
310 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit),
311 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit),
312 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit),
313 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special),
314 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic),
f2a96765
PC		 315};
316
317static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
318static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
319static const char *jz4725b_uart_groups[] = { "uart-data", };
320static const char *jz4725b_nand_groups[] = {
321 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
322 "nand-cle-ale", "nand-fre-fwe",
323};
324static const char *jz4725b_pwm0_groups[] = { "pwm0", };
325static const char *jz4725b_pwm1_groups[] = { "pwm1", };
326static const char *jz4725b_pwm2_groups[] = { "pwm2", };
327static const char *jz4725b_pwm3_groups[] = { "pwm3", };
328static const char *jz4725b_pwm4_groups[] = { "pwm4", };
329static const char *jz4725b_pwm5_groups[] = { "pwm5", };
a3240f09
PC		 330static const char *jz4725b_lcd_groups[] = {
331 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
332 "lcd-special", "lcd-generic",
333};
f2a96765
PC		 334
335static const struct function_desc jz4725b_functions[] = {
336 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
337 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
338 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
339 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
340 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
341 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
342 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
343 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
344 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
345 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
a3240f09 346 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
f2a96765
PC		 347};
348
349static const struct ingenic_chip_info jz4725b_chip_info = {
350 .num_chips = 4,
f742e5eb 351 .reg_offset = 0x100,
baf15647 352 .version = ID_JZ4725B,
f2a96765
PC		 353 .groups = jz4725b_groups,
354 .num_groups = ARRAY_SIZE(jz4725b_groups),
355 .functions = jz4725b_functions,
356 .num_functions = ARRAY_SIZE(jz4725b_functions),
357 .pull_ups = jz4740_pull_ups,
358 .pull_downs = jz4740_pull_downs,
359};
360
0257595a
ZY		 361static const u32 jz4760_pull_ups[6] = {
362 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f,
363};
364
365static const u32 jz4760_pull_downs[6] = {
366 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
367};
368
369static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
370static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
371static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
372static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
373static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
374static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
375static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
376static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
377static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
378static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
379static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
380static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
381static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
382static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
383static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
384static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
385static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
386static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
387static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
388static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
389static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
390static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
391static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
392static int jz4760_nemc_8bit_data_pins[] = {
393 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
394};
395static int jz4760_nemc_16bit_data_pins[] = {
396 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
397};
398static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
399static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
400static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
401static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
402static int jz4760_nemc_wait_pins[] = { 0x1b, };
403static int jz4760_nemc_cs1_pins[] = { 0x15, };
404static int jz4760_nemc_cs2_pins[] = { 0x16, };
405static int jz4760_nemc_cs3_pins[] = { 0x17, };
406static int jz4760_nemc_cs4_pins[] = { 0x18, };
407static int jz4760_nemc_cs5_pins[] = { 0x19, };
408static int jz4760_nemc_cs6_pins[] = { 0x1a, };
409static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
410static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
411static int jz4760_cim_pins[] = {
412 0x26, 0x27, 0x28, 0x29,
413 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
414};
415static int jz4760_lcd_24bit_pins[] = {
416 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
417 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
418 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
419 0x58, 0x59, 0x5a, 0x5b,
420};
421static int jz4760_pwm_pwm0_pins[] = { 0x80, };
422static int jz4760_pwm_pwm1_pins[] = { 0x81, };
423static int jz4760_pwm_pwm2_pins[] = { 0x82, };
424static int jz4760_pwm_pwm3_pins[] = { 0x83, };
425static int jz4760_pwm_pwm4_pins[] = { 0x84, };
426static int jz4760_pwm_pwm5_pins[] = { 0x85, };
427static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
428static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
429
430static int jz4760_uart0_data_funcs[] = { 0, 0, };
431static int jz4760_uart0_hwflow_funcs[] = { 0, 0, };
432static int jz4760_uart1_data_funcs[] = { 0, 0, };
433static int jz4760_uart1_hwflow_funcs[] = { 0, 0, };
434static int jz4760_uart2_data_funcs[] = { 0, 0, };
435static int jz4760_uart2_hwflow_funcs[] = { 0, 0, };
436static int jz4760_uart3_data_funcs[] = { 0, 1, };
437static int jz4760_uart3_hwflow_funcs[] = { 0, 0, };
438static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
439static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
440static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
441static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
442static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
443static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
444static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
445static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
446static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
447static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
448static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
449static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
450static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
451static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
452static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
453static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
454static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
455static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, };
456static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, };
457static int jz4760_nemc_rd_we_funcs[] = { 0, 0, };
458static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, };
459static int jz4760_nemc_wait_funcs[] = { 0, };
460static int jz4760_nemc_cs1_funcs[] = { 0, };
461static int jz4760_nemc_cs2_funcs[] = { 0, };
462static int jz4760_nemc_cs3_funcs[] = { 0, };
463static int jz4760_nemc_cs4_funcs[] = { 0, };
464static int jz4760_nemc_cs5_funcs[] = { 0, };
465static int jz4760_nemc_cs6_funcs[] = { 0, };
466static int jz4760_i2c0_funcs[] = { 0, 0, };
467static int jz4760_i2c1_funcs[] = { 0, 0, };
468static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
469static int jz4760_lcd_24bit_funcs[] = {
470 0, 0, 0, 0, 0, 0, 0, 0,
471 0, 0, 0, 0, 0, 0, 0, 0,
472 0, 0, 0, 0, 0, 0, 0, 0,
473 0, 0, 0, 0,
474};
475static int jz4760_pwm_pwm0_funcs[] = { 0, };
476static int jz4760_pwm_pwm1_funcs[] = { 0, };
477static int jz4760_pwm_pwm2_funcs[] = { 0, };
478static int jz4760_pwm_pwm3_funcs[] = { 0, };
479static int jz4760_pwm_pwm4_funcs[] = { 0, };
480static int jz4760_pwm_pwm5_funcs[] = { 0, };
481static int jz4760_pwm_pwm6_funcs[] = { 0, };
482static int jz4760_pwm_pwm7_funcs[] = { 0, };
483
484static const struct group_desc jz4760_groups[] = {
485 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data),
486 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow),
487 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data),
488 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow),
489 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data),
490 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow),
491 INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data),
492 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow),
493 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a),
494 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a),
495 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e),
496 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e),
497 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e),
498 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d),
499 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d),
500 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e),
501 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e),
502 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e),
503 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b),
504 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b),
505 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e),
506 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e),
507 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e),
508 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data),
509 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data),
510 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale),
511 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr),
512 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we),
513 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe),
514 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait),
515 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1),
516 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2),
517 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3),
518 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4),
519 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5),
520 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6),
521 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0),
522 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1),
523 INGENIC_PIN_GROUP("cim-data", jz4760_cim),
524 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit),
525 { "lcd-no-pins", },
526 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0),
527 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1),
528 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2),
529 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3),
530 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4),
531 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5),
532 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6),
533 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7),
534};
535
536static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
537static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
538static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
539static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
540static const char *jz4760_mmc0_groups[] = {
541 "mmc0-1bit-a", "mmc0-4bit-a",
542 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
543};
544static const char *jz4760_mmc1_groups[] = {
545 "mmc1-1bit-d", "mmc1-4bit-d",
546 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
547};
548static const char *jz4760_mmc2_groups[] = {
549 "mmc2-1bit-b", "mmc2-4bit-b",
550 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
551};
552static const char *jz4760_nemc_groups[] = {
553 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
554 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
555};
556static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
557static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
558static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
559static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
560static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
561static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
562static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
563static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
564static const char *jz4760_cim_groups[] = { "cim-data", };
565static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
566static const char *jz4760_pwm0_groups[] = { "pwm0", };
567static const char *jz4760_pwm1_groups[] = { "pwm1", };
568static const char *jz4760_pwm2_groups[] = { "pwm2", };
569static const char *jz4760_pwm3_groups[] = { "pwm3", };
570static const char *jz4760_pwm4_groups[] = { "pwm4", };
571static const char *jz4760_pwm5_groups[] = { "pwm5", };
572static const char *jz4760_pwm6_groups[] = { "pwm6", };
573static const char *jz4760_pwm7_groups[] = { "pwm7", };
574
575static const struct function_desc jz4760_functions[] = {
576 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
577 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
578 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
579 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
580 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
581 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
582 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
583 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
584 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
585 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
586 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
587 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
588 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
589 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
590 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
591 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
592 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
593 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
594 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
595 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
596 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
597 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
598 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
599 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
600 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
601 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
602};
603
604static const struct ingenic_chip_info jz4760_chip_info = {
605 .num_chips = 6,
f742e5eb 606 .reg_offset = 0x100,
baf15647 607 .version = ID_JZ4760,
0257595a
ZY		 608 .groups = jz4760_groups,
609 .num_groups = ARRAY_SIZE(jz4760_groups),
610 .functions = jz4760_functions,
611 .num_functions = ARRAY_SIZE(jz4760_functions),
612 .pull_ups = jz4760_pull_ups,
613 .pull_downs = jz4760_pull_downs,
614};
615
b5c23aa4
PC		 616static const u32 jz4770_pull_ups[6] = {
617 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
618};
619
620static const u32 jz4770_pull_downs[6] = {
621 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
622};
623
624static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
625static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
626static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
627static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
ff656e47
ZY		 628static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
629static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
b5c23aa4
PC		 630static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
631static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
b5c23aa4 632static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
ff656e47 633static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
b5c23aa4 634static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
ff656e47
ZY		 635static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
636static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
b5c23aa4 637static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
ff656e47 638static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
b5c23aa4 639static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
ff656e47
ZY		 640static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
641static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
5de1a73e
ZY		 642static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
643static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
644static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
645static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
646static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
ff656e47 647static int jz4770_nemc_8bit_data_pins[] = {
b5c23aa4
PC		 648 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
649};
ff656e47
ZY		 650static int jz4770_nemc_16bit_data_pins[] = {
651 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
652};
b5c23aa4
PC		 653static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
654static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
655static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
656static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
5de1a73e 657static int jz4770_nemc_wait_pins[] = { 0x1b, };
b5c23aa4
PC		 658static int jz4770_nemc_cs1_pins[] = { 0x15, };
659static int jz4770_nemc_cs2_pins[] = { 0x16, };
660static int jz4770_nemc_cs3_pins[] = { 0x17, };
661static int jz4770_nemc_cs4_pins[] = { 0x18, };
662static int jz4770_nemc_cs5_pins[] = { 0x19, };
663static int jz4770_nemc_cs6_pins[] = { 0x1a, };
ff656e47
ZY		 664static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
665static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
b5c23aa4 666static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
ff656e47
ZY		 667static int jz4770_cim_8bit_pins[] = {
668 0x26, 0x27, 0x28, 0x29,
669 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
670};
671static int jz4770_cim_12bit_pins[] = {
672 0x32, 0x33, 0xb0, 0xb1,
b5c23aa4 673};
ff656e47 674static int jz4770_lcd_24bit_pins[] = {
b5c23aa4
PC		 675 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
676 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
677 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
ff656e47 678 0x58, 0x59, 0x5a, 0x5b,
b5c23aa4
PC		 679};
680static int jz4770_pwm_pwm0_pins[] = { 0x80, };
681static int jz4770_pwm_pwm1_pins[] = { 0x81, };
682static int jz4770_pwm_pwm2_pins[] = { 0x82, };
683static int jz4770_pwm_pwm3_pins[] = { 0x83, };
684static int jz4770_pwm_pwm4_pins[] = { 0x84, };
685static int jz4770_pwm_pwm5_pins[] = { 0x85, };
686static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
687static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
5de1a73e
ZY		 688static int jz4770_mac_rmii_pins[] = {
689 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
690};
691static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
ae75b53e 692static int jz4770_otg_pins[] = { 0x8a, };
b5c23aa4
PC		 693
694static int jz4770_uart0_data_funcs[] = { 0, 0, };
695static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
696static int jz4770_uart1_data_funcs[] = { 0, 0, };
697static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
ff656e47
ZY		 698static int jz4770_uart2_data_funcs[] = { 0, 0, };
699static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
b5c23aa4
PC		 700static int jz4770_uart3_data_funcs[] = { 0, 1, };
701static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
b5c23aa4 702static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
ff656e47 703static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
b5c23aa4 704static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
ff656e47
ZY		 705static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
706static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
b5c23aa4 707static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
ff656e47 708static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
b5c23aa4 709static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
ff656e47
ZY		 710static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
711static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
5de1a73e
ZY		 712static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
713static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
714static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
715static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
716static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
ff656e47
ZY		 717static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
718static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
b5c23aa4
PC		 719static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
720static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
721static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
722static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
5de1a73e 723static int jz4770_nemc_wait_funcs[] = { 0, };
b5c23aa4
PC		 724static int jz4770_nemc_cs1_funcs[] = { 0, };
725static int jz4770_nemc_cs2_funcs[] = { 0, };
726static int jz4770_nemc_cs3_funcs[] = { 0, };
727static int jz4770_nemc_cs4_funcs[] = { 0, };
728static int jz4770_nemc_cs5_funcs[] = { 0, };
729static int jz4770_nemc_cs6_funcs[] = { 0, };
730static int jz4770_i2c0_funcs[] = { 0, 0, };
731static int jz4770_i2c1_funcs[] = { 0, 0, };
732static int jz4770_i2c2_funcs[] = { 2, 2, };
ff656e47
ZY		 733static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
734static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
735static int jz4770_lcd_24bit_funcs[] = {
736 0, 0, 0, 0, 0, 0, 0, 0,
b5c23aa4
PC		 737 0, 0, 0, 0, 0, 0, 0, 0,
738 0, 0, 0, 0, 0, 0, 0, 0,
ff656e47 739 0, 0, 0, 0,
b5c23aa4
PC		 740};
741static int jz4770_pwm_pwm0_funcs[] = { 0, };
742static int jz4770_pwm_pwm1_funcs[] = { 0, };
743static int jz4770_pwm_pwm2_funcs[] = { 0, };
744static int jz4770_pwm_pwm3_funcs[] = { 0, };
745static int jz4770_pwm_pwm4_funcs[] = { 0, };
746static int jz4770_pwm_pwm5_funcs[] = { 0, };
747static int jz4770_pwm_pwm6_funcs[] = { 0, };
748static int jz4770_pwm_pwm7_funcs[] = { 0, };
5de1a73e
ZY		 749static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
750static int jz4770_mac_mii_funcs[] = { 0, 0, };
ae75b53e 751static int jz4770_otg_funcs[] = { 0, };
b5c23aa4
PC		 752
753static const struct group_desc jz4770_groups[] = {
754 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
755 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
756 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
757 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
758 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
759 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
760 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
761 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
b5c23aa4 762 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
ff656e47 763 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
b5c23aa4 764 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
ff656e47
ZY		 765 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
766 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
b5c23aa4 767 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
ff656e47 768 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
b5c23aa4 769 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
ff656e47
ZY		 770 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
771 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
5de1a73e
ZY		 772 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
773 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
774 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
775 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
776 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
ff656e47
ZY		 777 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
778 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
b5c23aa4
PC		 779 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
780 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
781 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
782 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
5de1a73e 783 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
b5c23aa4
PC		 784 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
785 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
786 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
787 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
788 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
789 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
790 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
791 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
792 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
ff656e47
ZY		 793 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
794 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
795 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
b5c23aa4
PC		 796 { "lcd-no-pins", },
797 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
798 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
799 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
800 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
801 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
802 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
803 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
804 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
5de1a73e
ZY		 805 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
806 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
ae75b53e 807 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg),
b5c23aa4
PC		 808};
809
810static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
811static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
812static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
813static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
b5c23aa4 814static const char *jz4770_mmc0_groups[] = {
ff656e47
ZY		 815 "mmc0-1bit-a", "mmc0-4bit-a",
816 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
b5c23aa4
PC		 817};
818static const char *jz4770_mmc1_groups[] = {
ff656e47
ZY		 819 "mmc1-1bit-d", "mmc1-4bit-d",
820 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
b5c23aa4 821};
5de1a73e
ZY		 822static const char *jz4770_mmc2_groups[] = {
823 "mmc2-1bit-b", "mmc2-4bit-b",
824 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
825};
b5c23aa4 826static const char *jz4770_nemc_groups[] = {
ff656e47 827 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
5de1a73e 828 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
b5c23aa4
PC		 829};
830static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
ff656e47
ZY		 831static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
832static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
833static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
834static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
b5c23aa4
PC		 835static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
836static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
837static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
838static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
ff656e47
ZY		 839static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
840static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
b5c23aa4
PC		 841static const char *jz4770_pwm0_groups[] = { "pwm0", };
842static const char *jz4770_pwm1_groups[] = { "pwm1", };
843static const char *jz4770_pwm2_groups[] = { "pwm2", };
844static const char *jz4770_pwm3_groups[] = { "pwm3", };
845static const char *jz4770_pwm4_groups[] = { "pwm4", };
846static const char *jz4770_pwm5_groups[] = { "pwm5", };
847static const char *jz4770_pwm6_groups[] = { "pwm6", };
848static const char *jz4770_pwm7_groups[] = { "pwm7", };
5de1a73e 849static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
ae75b53e 850static const char *jz4770_otg_groups[] = { "otg-vbus", };
b5c23aa4
PC		 851
852static const struct function_desc jz4770_functions[] = {
853 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
854 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
855 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
856 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
b5c23aa4
PC		 857 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
858 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
5de1a73e 859 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
b5c23aa4
PC		 860 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
861 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
ff656e47
ZY		 862 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
863 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
864 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
865 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
b5c23aa4
PC		 866 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
867 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
868 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
869 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
b5c23aa4
PC		 870 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
871 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
872 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
873 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
874 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
875 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
876 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
877 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
878 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
879 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
5de1a73e 880 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
ae75b53e 881 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), },
b5c23aa4
PC		 882};
883
884static const struct ingenic_chip_info jz4770_chip_info = {
885 .num_chips = 6,
f742e5eb 886 .reg_offset = 0x100,
baf15647 887 .version = ID_JZ4770,
b5c23aa4
PC		 888 .groups = jz4770_groups,
889 .num_groups = ARRAY_SIZE(jz4770_groups),
890 .functions = jz4770_functions,
891 .num_functions = ARRAY_SIZE(jz4770_functions),
892 .pull_ups = jz4770_pull_ups,
893 .pull_downs = jz4770_pull_downs,
894};
895
ff656e47
ZY		 896static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
897static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
898static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
899static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
900static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
901static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
902static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
903
904static int jz4780_uart2_data_funcs[] = { 1, 1, };
905static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
906static int jz4780_uart4_data_funcs[] = { 2, 2, };
907static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
908static int jz4780_i2c3_funcs[] = { 1, 1, };
909static int jz4780_i2c4_e_funcs[] = { 1, 1, };
910static int jz4780_i2c4_f_funcs[] = { 1, 1, };
911
912static const struct group_desc jz4780_groups[] = {
913 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
914 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
915 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
916 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
917 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
918 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
919 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
920 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
921 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
922 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
923 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
924 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
925 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
926 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
927 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
928 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
929 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
930 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
5de1a73e
ZY		 931 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
932 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
933 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
934 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
ff656e47
ZY		 935 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
936 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
937 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
938 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
939 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
5de1a73e 940 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
ff656e47
ZY		 941 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
942 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
943 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
944 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
945 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
946 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
947 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
948 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
949 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
950 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
951 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
952 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
953 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
954 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
955 { "lcd-no-pins", },
956 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
957 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
958 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
959 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
960 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
961 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
962 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
963 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
964};
965
966static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
967static const char *jz4780_uart4_groups[] = { "uart4-data", };
968static const char *jz4780_mmc0_groups[] = {
969 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
970 "mmc0-1bit-e", "mmc0-4bit-e",
971};
972static const char *jz4780_mmc1_groups[] = {
973 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
974};
5de1a73e
ZY		 975static const char *jz4780_mmc2_groups[] = {
976 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
977};
ff656e47
ZY		 978static const char *jz4780_nemc_groups[] = {
979 "nemc-data", "nemc-cle-ale", "nemc-addr",
5de1a73e 980 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
ff656e47
ZY		 981};
982static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
983static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
984static const char *jz4780_cim_groups[] = { "cim-data", };
985
986static const struct function_desc jz4780_functions[] = {
987 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
988 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
989 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
990 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
991 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
992 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
993 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
5de1a73e 994 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
ff656e47
ZY		 995 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
996 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
997 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
998 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
999 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1000 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1001 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1002 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1003 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1004 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1005 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
1006 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
1007 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
1008 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1009 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1010 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1011 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1012 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1013 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1014 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1015 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1016 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1017};
1018
1019static const struct ingenic_chip_info jz4780_chip_info = {
1020 .num_chips = 6,
f742e5eb 1021 .reg_offset = 0x100,
baf15647 1022 .version = ID_JZ4780,
ff656e47
ZY		 1023 .groups = jz4780_groups,
1024 .num_groups = ARRAY_SIZE(jz4780_groups),
1025 .functions = jz4780_functions,
1026 .num_functions = ARRAY_SIZE(jz4780_functions),
1027 .pull_ups = jz4770_pull_ups,
1028 .pull_downs = jz4770_pull_downs,
1029};
1030
fe1ad5ee 1031static const u32 x1000_pull_ups[4] = {
b4a9372a 1032 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
fe1ad5ee
ZY		 1033};
1034
1035static const u32 x1000_pull_downs[4] = {
1036 0x00000000, 0x02000000, 0x02000000, 0x00000000,
1037};
1038
1039static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
1040static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1041static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
1042static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
b4a9372a 1043static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
fe1ad5ee
ZY		 1044static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
1045static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
3b31e9b0
ZY		 1046static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, };
1047static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
1048static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
1049static int x1000_ssi_dt_d_pins[] = { 0x62, };
1050static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
1051static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
1052static int x1000_ssi_dr_d_pins[] = { 0x63, };
1053static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
1054static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
1055static int x1000_ssi_clk_d_pins[] = { 0x60, };
1056static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
1057static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
1058static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
1059static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
1060static int x1000_ssi_ce0_d_pins[] = { 0x61, };
1061static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
1062static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
fe1ad5ee
ZY		 1063static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
1064static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
1065static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
1066static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
1067static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
b4a9372a 1068static int x1000_emc_8bit_data_pins[] = {
fe1ad5ee
ZY		 1069 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1070};
b4a9372a 1071static int x1000_emc_16bit_data_pins[] = {
fe1ad5ee
ZY		 1072 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1073};
b4a9372a 1074static int x1000_emc_addr_pins[] = {
fe1ad5ee
ZY		 1075 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
1076 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
1077};
b4a9372a
ZY		 1078static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
1079static int x1000_emc_wait_pins[] = { 0x34, };
1080static int x1000_emc_cs1_pins[] = { 0x32, };
1081static int x1000_emc_cs2_pins[] = { 0x33, };
fe1ad5ee
ZY		 1082static int x1000_i2c0_pins[] = { 0x38, 0x37, };
1083static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
1084static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
1085static int x1000_i2c2_pins[] = { 0x61, 0x60, };
1086static int x1000_cim_pins[] = {
1087 0x08, 0x09, 0x0a, 0x0b,
1088 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1089};
1090static int x1000_lcd_8bit_pins[] = {
1091 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1092 0x30, 0x31, 0x32, 0x33, 0x34,
1093};
1094static int x1000_lcd_16bit_pins[] = {
1095 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1096};
1097static int x1000_pwm_pwm0_pins[] = { 0x59, };
1098static int x1000_pwm_pwm1_pins[] = { 0x5a, };
1099static int x1000_pwm_pwm2_pins[] = { 0x5b, };
1100static int x1000_pwm_pwm3_pins[] = { 0x26, };
1101static int x1000_pwm_pwm4_pins[] = { 0x58, };
1102static int x1000_mac_pins[] = {
1103 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
1104};
1105
1106static int x1000_uart0_data_funcs[] = { 0, 0, };
1107static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
1108static int x1000_uart1_data_a_funcs[] = { 2, 2, };
1109static int x1000_uart1_data_d_funcs[] = { 1, 1, };
b4a9372a 1110static int x1000_uart1_hwflow_funcs[] = { 1, 1, };
fe1ad5ee
ZY		 1111static int x1000_uart2_data_a_funcs[] = { 2, 2, };
1112static int x1000_uart2_data_d_funcs[] = { 0, 0, };
3b31e9b0
ZY		 1113static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
1114static int x1000_ssi_dt_a_22_funcs[] = { 2, };
1115static int x1000_ssi_dt_a_29_funcs[] = { 2, };
1116static int x1000_ssi_dt_d_funcs[] = { 0, };
1117static int x1000_ssi_dr_a_23_funcs[] = { 2, };
1118static int x1000_ssi_dr_a_28_funcs[] = { 2, };
1119static int x1000_ssi_dr_d_funcs[] = { 0, };
1120static int x1000_ssi_clk_a_24_funcs[] = { 2, };
1121static int x1000_ssi_clk_a_26_funcs[] = { 2, };
1122static int x1000_ssi_clk_d_funcs[] = { 0, };
1123static int x1000_ssi_gpc_a_20_funcs[] = { 2, };
1124static int x1000_ssi_gpc_a_31_funcs[] = { 2, };
1125static int x1000_ssi_ce0_a_25_funcs[] = { 2, };
1126static int x1000_ssi_ce0_a_27_funcs[] = { 2, };
1127static int x1000_ssi_ce0_d_funcs[] = { 0, };
1128static int x1000_ssi_ce1_a_21_funcs[] = { 2, };
1129static int x1000_ssi_ce1_a_30_funcs[] = { 2, };
fe1ad5ee
ZY		 1130static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
1131static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
1132static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
1133static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
1134static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
b4a9372a
ZY		 1135static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1136static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1137static int x1000_emc_addr_funcs[] = {
fe1ad5ee
ZY		 1138 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1139};
b4a9372a
ZY		 1140static int x1000_emc_rd_we_funcs[] = { 0, 0, };
1141static int x1000_emc_wait_funcs[] = { 0, };
1142static int x1000_emc_cs1_funcs[] = { 0, };
1143static int x1000_emc_cs2_funcs[] = { 0, };
fe1ad5ee
ZY		 1144static int x1000_i2c0_funcs[] = { 0, 0, };
1145static int x1000_i2c1_a_funcs[] = { 2, 2, };
1146static int x1000_i2c1_c_funcs[] = { 0, 0, };
1147static int x1000_i2c2_funcs[] = { 1, 1, };
1148static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
1149static int x1000_lcd_8bit_funcs[] = {
1150 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1151};
1152static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
1153static int x1000_pwm_pwm0_funcs[] = { 0, };
1154static int x1000_pwm_pwm1_funcs[] = { 1, };
1155static int x1000_pwm_pwm2_funcs[] = { 1, };
1156static int x1000_pwm_pwm3_funcs[] = { 2, };
1157static int x1000_pwm_pwm4_funcs[] = { 0, };
1158static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
1159
1160static const struct group_desc x1000_groups[] = {
1161 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
1162 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
1163 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
1164 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
b4a9372a 1165 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow),
fe1ad5ee
ZY		 1166 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
1167 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
3b31e9b0
ZY		 1168 INGENIC_PIN_GROUP("sfc", x1000_sfc),
1169 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22),
1170 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29),
1171 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d),
1172 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23),
1173 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28),
1174 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d),
1175 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24),
1176 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26),
1177 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d),
1178 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20),
1179 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31),
1180 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25),
1181 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27),
1182 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d),
1183 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21),
1184 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30),
fe1ad5ee
ZY		 1185 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
1186 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
1187 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
1188 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
1189 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
b4a9372a
ZY		 1190 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data),
1191 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data),
1192 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr),
1193 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we),
1194 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait),
1195 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1),
1196 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2),
fe1ad5ee
ZY		 1197 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
1198 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
1199 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
1200 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
1201 INGENIC_PIN_GROUP("cim-data", x1000_cim),
1202 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
1203 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
1204 { "lcd-no-pins", },
1205 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0),
1206 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1),
1207 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2),
1208 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3),
1209 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4),
1210 INGENIC_PIN_GROUP("mac", x1000_mac),
1211};
1212
1213static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1214static const char *x1000_uart1_groups[] = {
b4a9372a 1215 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
fe1ad5ee
ZY		 1216};
1217static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
3b31e9b0
ZY		 1218static const char *x1000_sfc_groups[] = { "sfc", };
1219static const char *x1000_ssi_groups[] = {
1220 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
1221 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
1222 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
1223 "ssi-gpc-a-20", "ssi-gpc-a-31",
1224 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
1225 "ssi-ce1-a-21", "ssi-ce1-a-30",
1226};
fe1ad5ee
ZY		 1227static const char *x1000_mmc0_groups[] = {
1228 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
1229};
1230static const char *x1000_mmc1_groups[] = {
b4a9372a 1231 "mmc1-1bit", "mmc1-4bit",
fe1ad5ee 1232};
b4a9372a
ZY		 1233static const char *x1000_emc_groups[] = {
1234 "emc-8bit-data", "emc-16bit-data",
1235 "emc-addr", "emc-rd-we", "emc-wait",
fe1ad5ee 1236};
b4a9372a
ZY		 1237static const char *x1000_cs1_groups[] = { "emc-cs1", };
1238static const char *x1000_cs2_groups[] = { "emc-cs2", };
fe1ad5ee
ZY		 1239static const char *x1000_i2c0_groups[] = { "i2c0-data", };
1240static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1241static const char *x1000_i2c2_groups[] = { "i2c2-data", };
1242static const char *x1000_cim_groups[] = { "cim-data", };
1243static const char *x1000_lcd_groups[] = {
1244 "lcd-8bit", "lcd-16bit", "lcd-no-pins",
1245};
1246static const char *x1000_pwm0_groups[] = { "pwm0", };
1247static const char *x1000_pwm1_groups[] = { "pwm1", };
1248static const char *x1000_pwm2_groups[] = { "pwm2", };
1249static const char *x1000_pwm3_groups[] = { "pwm3", };
1250static const char *x1000_pwm4_groups[] = { "pwm4", };
1251static const char *x1000_mac_groups[] = { "mac", };
1252
1253static const struct function_desc x1000_functions[] = {
1254 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
1255 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
1256 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
3b31e9b0
ZY		 1257 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
1258 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
fe1ad5ee
ZY		 1259 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
1260 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
b4a9372a
ZY		 1261 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
1262 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
1263 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
fe1ad5ee
ZY		 1264 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
1265 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
1266 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
1267 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
1268 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
1269 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
1270 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
1271 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
1272 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
1273 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
1274 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
1275};
1276
1277static const struct ingenic_chip_info x1000_chip_info = {
1278 .num_chips = 4,
f742e5eb 1279 .reg_offset = 0x100,
baf15647 1280 .version = ID_X1000,
fe1ad5ee
ZY		 1281 .groups = x1000_groups,
1282 .num_groups = ARRAY_SIZE(x1000_groups),
1283 .functions = x1000_functions,
1284 .num_functions = ARRAY_SIZE(x1000_functions),
1285 .pull_ups = x1000_pull_ups,
1286 .pull_downs = x1000_pull_downs,
1287};
1288
5d21595b
ZY		 1289static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
1290static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1291static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
1292static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
b4a9372a 1293static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
5d21595b
ZY		 1294static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
1295static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
b4a9372a
ZY		 1296static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
1297static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
5d21595b
ZY		 1298static int x1500_i2c0_pins[] = { 0x38, 0x37, };
1299static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
1300static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
1301static int x1500_i2c2_pins[] = { 0x61, 0x60, };
1302static int x1500_cim_pins[] = {
1303 0x08, 0x09, 0x0a, 0x0b,
1304 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1305};
1306static int x1500_pwm_pwm0_pins[] = { 0x59, };
1307static int x1500_pwm_pwm1_pins[] = { 0x5a, };
1308static int x1500_pwm_pwm2_pins[] = { 0x5b, };
1309static int x1500_pwm_pwm3_pins[] = { 0x26, };
1310static int x1500_pwm_pwm4_pins[] = { 0x58, };
1311
1312static int x1500_uart0_data_funcs[] = { 0, 0, };
1313static int x1500_uart0_hwflow_funcs[] = { 0, 0, };
1314static int x1500_uart1_data_a_funcs[] = { 2, 2, };
1315static int x1500_uart1_data_d_funcs[] = { 1, 1, };
b4a9372a 1316static int x1500_uart1_hwflow_funcs[] = { 1, 1, };
5d21595b
ZY		 1317static int x1500_uart2_data_a_funcs[] = { 2, 2, };
1318static int x1500_uart2_data_d_funcs[] = { 0, 0, };
b4a9372a
ZY		 1319static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, };
1320static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, };
5d21595b
ZY		 1321static int x1500_i2c0_funcs[] = { 0, 0, };
1322static int x1500_i2c1_a_funcs[] = { 2, 2, };
1323static int x1500_i2c1_c_funcs[] = { 0, 0, };
1324static int x1500_i2c2_funcs[] = { 1, 1, };
1325static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
1326static int x1500_pwm_pwm0_funcs[] = { 0, };
1327static int x1500_pwm_pwm1_funcs[] = { 1, };
1328static int x1500_pwm_pwm2_funcs[] = { 1, };
1329static int x1500_pwm_pwm3_funcs[] = { 2, };
1330static int x1500_pwm_pwm4_funcs[] = { 0, };
1331
1332static const struct group_desc x1500_groups[] = {
1333 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data),
1334 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
1335 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
1336 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
b4a9372a 1337 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow),
5d21595b
ZY		 1338 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
1339 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
3b31e9b0 1340 INGENIC_PIN_GROUP("sfc", x1000_sfc),
b4a9372a
ZY		 1341 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit),
1342 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit),
5d21595b
ZY		 1343 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
1344 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
1345 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
1346 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
1347 INGENIC_PIN_GROUP("cim-data", x1500_cim),
1348 { "lcd-no-pins", },
1349 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0),
1350 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1),
1351 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2),
1352 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3),
1353 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4),
1354};
1355
1356static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1357static const char *x1500_uart1_groups[] = {
b4a9372a 1358 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
5d21595b
ZY		 1359};
1360static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
b4a9372a 1361static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
5d21595b
ZY		 1362static const char *x1500_i2c0_groups[] = { "i2c0-data", };
1363static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1364static const char *x1500_i2c2_groups[] = { "i2c2-data", };
1365static const char *x1500_cim_groups[] = { "cim-data", };
1366static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
1367static const char *x1500_pwm0_groups[] = { "pwm0", };
1368static const char *x1500_pwm1_groups[] = { "pwm1", };
1369static const char *x1500_pwm2_groups[] = { "pwm2", };
1370static const char *x1500_pwm3_groups[] = { "pwm3", };
1371static const char *x1500_pwm4_groups[] = { "pwm4", };
1372
1373static const struct function_desc x1500_functions[] = {
1374 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
1375 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
1376 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
3b31e9b0 1377 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
b4a9372a 1378 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
5d21595b
ZY		 1379 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
1380 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
1381 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
1382 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
1383 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
1384 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
1385 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
1386 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
1387 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
1388 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
1389};
1390
1391static const struct ingenic_chip_info x1500_chip_info = {
1392 .num_chips = 4,
f742e5eb 1393 .reg_offset = 0x100,
baf15647 1394 .version = ID_X1500,
5d21595b
ZY		 1395 .groups = x1500_groups,
1396 .num_groups = ARRAY_SIZE(x1500_groups),
1397 .functions = x1500_functions,
1398 .num_functions = ARRAY_SIZE(x1500_functions),
1399 .pull_ups = x1000_pull_ups,
1400 .pull_downs = x1000_pull_downs,
1401};
1402
d7da2a1e
ZY		 1403static const u32 x1830_pull_ups[4] = {
1404 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1405};
1406
1407static const u32 x1830_pull_downs[4] = {
1408 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1409};
1410
1411static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
1412static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
1413static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
1414static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, };
1415static int x1830_ssi0_dt_pins[] = { 0x4c, };
1416static int x1830_ssi0_dr_pins[] = { 0x4b, };
1417static int x1830_ssi0_clk_pins[] = { 0x4f, };
1418static int x1830_ssi0_gpc_pins[] = { 0x4d, };
1419static int x1830_ssi0_ce0_pins[] = { 0x50, };
1420static int x1830_ssi0_ce1_pins[] = { 0x4e, };
1421static int x1830_ssi1_dt_c_pins[] = { 0x53, };
1422static int x1830_ssi1_dr_c_pins[] = { 0x54, };
1423static int x1830_ssi1_clk_c_pins[] = { 0x57, };
1424static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
1425static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
1426static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
1427static int x1830_ssi1_dt_d_pins[] = { 0x62, };
1428static int x1830_ssi1_dr_d_pins[] = { 0x63, };
1429static int x1830_ssi1_clk_d_pins[] = { 0x66, };
1430static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
1431static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
1432static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
1433static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
1434static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
1435static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
1436static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
1437static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
1438static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
1439static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
1440static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
1441static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
1442static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
1443static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
1444static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
1445static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
1446static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
1447static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
1448static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
1449static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
1450static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
1451static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
1452static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
1453static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
1454static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
1455static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
1456static int x1830_mac_pins[] = {
1457 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
1458};
1459
1460static int x1830_uart0_data_funcs[] = { 0, 0, };
1461static int x1830_uart0_hwflow_funcs[] = { 0, 0, };
1462static int x1830_uart1_data_funcs[] = { 0, 0, };
1463static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
1464static int x1830_ssi0_dt_funcs[] = { 0, };
1465static int x1830_ssi0_dr_funcs[] = { 0, };
1466static int x1830_ssi0_clk_funcs[] = { 0, };
1467static int x1830_ssi0_gpc_funcs[] = { 0, };
1468static int x1830_ssi0_ce0_funcs[] = { 0, };
1469static int x1830_ssi0_ce1_funcs[] = { 0, };
1470static int x1830_ssi1_dt_c_funcs[] = { 1, };
1471static int x1830_ssi1_dr_c_funcs[] = { 1, };
1472static int x1830_ssi1_clk_c_funcs[] = { 1, };
1473static int x1830_ssi1_gpc_c_funcs[] = { 1, };
1474static int x1830_ssi1_ce0_c_funcs[] = { 1, };
1475static int x1830_ssi1_ce1_c_funcs[] = { 1, };
1476static int x1830_ssi1_dt_d_funcs[] = { 2, };
1477static int x1830_ssi1_dr_d_funcs[] = { 2, };
1478static int x1830_ssi1_clk_d_funcs[] = { 2, };
1479static int x1830_ssi1_gpc_d_funcs[] = { 2, };
1480static int x1830_ssi1_ce0_d_funcs[] = { 2, };
1481static int x1830_ssi1_ce1_d_funcs[] = { 2, };
1482static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, };
1483static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, };
1484static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, };
1485static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, };
1486static int x1830_i2c0_funcs[] = { 1, 1, };
1487static int x1830_i2c1_funcs[] = { 0, 0, };
1488static int x1830_i2c2_funcs[] = { 1, 1, };
1489static int x1830_pwm_pwm0_b_funcs[] = { 0, };
1490static int x1830_pwm_pwm0_c_funcs[] = { 1, };
1491static int x1830_pwm_pwm1_b_funcs[] = { 0, };
1492static int x1830_pwm_pwm1_c_funcs[] = { 1, };
1493static int x1830_pwm_pwm2_c_8_funcs[] = { 0, };
1494static int x1830_pwm_pwm2_c_13_funcs[] = { 1, };
1495static int x1830_pwm_pwm3_c_9_funcs[] = { 0, };
1496static int x1830_pwm_pwm3_c_14_funcs[] = { 1, };
1497static int x1830_pwm_pwm4_c_15_funcs[] = { 1, };
1498static int x1830_pwm_pwm4_c_25_funcs[] = { 0, };
1499static int x1830_pwm_pwm5_c_16_funcs[] = { 1, };
1500static int x1830_pwm_pwm5_c_26_funcs[] = { 0, };
1501static int x1830_pwm_pwm6_c_17_funcs[] = { 1, };
1502static int x1830_pwm_pwm6_c_27_funcs[] = { 0, };
1503static int x1830_pwm_pwm7_c_18_funcs[] = { 1, };
1504static int x1830_pwm_pwm7_c_28_funcs[] = { 0, };
1505static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1506
1507static const struct group_desc x1830_groups[] = {
1508 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data),
1509 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow),
1510 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data),
1511 INGENIC_PIN_GROUP("sfc", x1830_sfc),
1512 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt),
1513 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr),
1514 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk),
1515 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc),
1516 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0),
1517 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1),
1518 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c),
1519 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c),
1520 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c),
1521 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c),
1522 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c),
1523 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c),
1524 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d),
1525 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d),
1526 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d),
1527 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d),
1528 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d),
1529 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d),
1530 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit),
1531 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit),
1532 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit),
1533 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit),
1534 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0),
1535 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1),
1536 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2),
1537 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b),
1538 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c),
1539 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b),
1540 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c),
1541 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8),
1542 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13),
1543 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9),
1544 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14),
1545 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15),
1546 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25),
1547 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16),
1548 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26),
1549 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17),
1550 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27),
1551 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18),
1552 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28),
1553 INGENIC_PIN_GROUP("mac", x1830_mac),
1554};
1555
1556static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1557static const char *x1830_uart1_groups[] = { "uart1-data", };
1558static const char *x1830_sfc_groups[] = { "sfc", };
1559static const char *x1830_ssi0_groups[] = {
1560 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
1561};
1562static const char *x1830_ssi1_groups[] = {
1563 "ssi1-dt-c", "ssi1-dt-d",
1564 "ssi1-dr-c", "ssi1-dr-d",
1565 "ssi1-clk-c", "ssi1-clk-d",
1566 "ssi1-gpc-c", "ssi1-gpc-d",
1567 "ssi1-ce0-c", "ssi1-ce0-d",
1568 "ssi1-ce1-c", "ssi1-ce1-d",
1569};
1570static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
1571static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
1572static const char *x1830_i2c0_groups[] = { "i2c0-data", };
1573static const char *x1830_i2c1_groups[] = { "i2c1-data", };
1574static const char *x1830_i2c2_groups[] = { "i2c2-data", };
1575static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
1576static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
1577static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
1578static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
1579static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
1580static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
1581static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
1582static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
1583static const char *x1830_mac_groups[] = { "mac", };
1584
1585static const struct function_desc x1830_functions[] = {
1586 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
1587 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
1588 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
1589 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
1590 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
1591 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
1592 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
1593 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
1594 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
1595 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
1596 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
1597 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
1598 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
1599 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
1600 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1601 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1602 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1603 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1604 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
1605};
1606
1607static const struct ingenic_chip_info x1830_chip_info = {
1608 .num_chips = 4,
1609 .reg_offset = 0x1000,
baf15647 1610 .version = ID_X1830,
d7da2a1e
ZY		 1611 .groups = x1830_groups,
1612 .num_groups = ARRAY_SIZE(x1830_groups),
1613 .functions = x1830_functions,
1614 .num_functions = ARRAY_SIZE(x1830_functions),
1615 .pull_ups = x1830_pull_ups,
1616 .pull_downs = x1830_pull_downs,
1617};
1618
b71c1844 1619static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
e72394e2
PC		 1620{
1621 unsigned int val;
1622
1623 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
1624
1625 return (u32) val;
1626}
1627
b71c1844 1628static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
e72394e2
PC		 1629 u8 reg, u8 offset, bool set)
1630{
1631 if (set)
1632 reg = REG_SET(reg);
1633 else
1634 reg = REG_CLEAR(reg);
1635
1636 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
1637}
1638
fe1ad5ee
ZY		 1639static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
1640 u8 reg, u8 offset, bool set)
1641{
1642 if (set)
1643 reg = REG_SET(reg);
1644 else
1645 reg = REG_CLEAR(reg);
1646
d7da2a1e
ZY		 1647 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
1648 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
fe1ad5ee
ZY		 1649}
1650
1651static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
1652{
d7da2a1e
ZY		 1653 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
1654 jzgc->jzpc->info->reg_offset),
fe1ad5ee
ZY		 1655 jzgc->gc.base / PINS_PER_GPIO_CHIP);
1656}
1657
e72394e2
PC		 1658static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
1659 u8 offset)
1660{
b71c1844 1661 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
e72394e2
PC		 1662
1663 return !!(val & BIT(offset));
1664}
1665
1666static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
1667 u8 offset, int value)
1668{
baf15647 1669 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1670 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);
e72394e2 1671 else
b71c1844 1672 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
e72394e2
PC		 1673}
1674
1675static void irq_set_type(struct ingenic_gpio_chip *jzgc,
1676 u8 offset, unsigned int type)
1677{
1678 u8 reg1, reg2;
f831f93a 1679 bool val1, val2;
e72394e2
PC		 1680
1681 switch (type) {
1682 case IRQ_TYPE_EDGE_RISING:
f831f93a 1683 val1 = val2 = true;
e72394e2
PC		 1684 break;
1685 case IRQ_TYPE_EDGE_FALLING:
f831f93a
PC		 1686 val1 = false;
1687 val2 = true;
e72394e2
PC		 1688 break;
1689 case IRQ_TYPE_LEVEL_HIGH:
f831f93a
PC		 1690 val1 = true;
1691 val2 = false;
e72394e2
PC		 1692 break;
1693 case IRQ_TYPE_LEVEL_LOW:
1694 default:
f831f93a 1695 val1 = val2 = false;
e72394e2
PC		 1696 break;
1697 }
f831f93a
PC		 1698
1699 if (jzgc->jzpc->info->version >= ID_JZ4760) {
1700 reg1 = JZ4760_GPIO_PAT1;
1701 reg2 = JZ4760_GPIO_PAT0;
1702 } else {
1703 reg1 = JZ4740_GPIO_TRIG;
1704 reg2 = JZ4740_GPIO_DIR;
1705 }
1706
1707 if (jzgc->jzpc->info->version >= ID_X1000) {
1708 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
1709 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
1710 ingenic_gpio_shadow_set_bit_load(jzgc);
1711 } else {
1712 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
1713 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
1714 }
e72394e2
PC		 1715}
1716
1717static void ingenic_gpio_irq_mask(struct irq_data *irqd)
1718{
1719 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1720 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1721
b71c1844 1722 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
e72394e2
PC		 1723}
1724
1725static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
1726{
1727 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1728 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1729
b71c1844 1730 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
e72394e2
PC		 1731}
1732
1733static void ingenic_gpio_irq_enable(struct irq_data *irqd)
1734{
1735 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1736 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1737 int irq = irqd->hwirq;
1738
baf15647 1739 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1740 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);
e72394e2 1741 else
b71c1844 1742 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
e72394e2
PC		 1743
1744 ingenic_gpio_irq_unmask(irqd);
1745}
1746
1747static void ingenic_gpio_irq_disable(struct irq_data *irqd)
1748{
1749 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1750 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1751 int irq = irqd->hwirq;
1752
1753 ingenic_gpio_irq_mask(irqd);
1754
baf15647 1755 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1756 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);
e72394e2 1757 else
b71c1844 1758 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
e72394e2
PC		 1759}
1760
1761static void ingenic_gpio_irq_ack(struct irq_data *irqd)
1762{
1763 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1764 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1765 int irq = irqd->hwirq;
1766 bool high;
1767
1768 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
1769 /*
1770 * Switch to an interrupt for the opposite edge to the one that
1771 * triggered the interrupt being ACKed.
1772 */
1773 high = ingenic_gpio_get_value(jzgc, irq);
1774 if (high)
1775 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING);
1776 else
1777 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
1778 }
1779
baf15647 1780 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1781 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);
e72394e2 1782 else
b71c1844 1783 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
e72394e2
PC		 1784}
1785
1786static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
1787{
1788 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1789 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1790
1791 switch (type) {
1792 case IRQ_TYPE_EDGE_BOTH:
1793 case IRQ_TYPE_EDGE_RISING:
1794 case IRQ_TYPE_EDGE_FALLING:
1795 irq_set_handler_locked(irqd, handle_edge_irq);
1796 break;
1797 case IRQ_TYPE_LEVEL_HIGH:
1798 case IRQ_TYPE_LEVEL_LOW:
1799 irq_set_handler_locked(irqd, handle_level_irq);
1800 break;
1801 default:
1802 irq_set_handler_locked(irqd, handle_bad_irq);
1803 }
1804
1805 if (type == IRQ_TYPE_EDGE_BOTH) {
1806 /*
1807 * The hardware does not support interrupts on both edges. The
1808 * best we can do is to set up a single-edge interrupt and then
1809 * switch to the opposing edge when ACKing the interrupt.
1810 */
1811 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
1812
1813 type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
1814 }
1815
1816 irq_set_type(jzgc, irqd->hwirq, type);
1817 return 0;
1818}
1819
1820static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
1821{
1822 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1823 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1824
1825 return irq_set_irq_wake(jzgc->irq, on);
1826}
1827
1828static void ingenic_gpio_irq_handler(struct irq_desc *desc)
1829{
1830 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1831 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1832 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
1833 unsigned long flag, i;
1834
1835 chained_irq_enter(irq_chip, desc);
1836
baf15647 1837 if (jzgc->jzpc->info->version >= ID_JZ4760)
0257595a 1838 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);
e72394e2 1839 else
b71c1844 1840 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
e72394e2
PC		 1841
1842 for_each_set_bit(i, &flag, 32)
1843 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
1844 chained_irq_exit(irq_chip, desc);
1845}
1846
1847static void ingenic_gpio_set(struct gpio_chip *gc,
1848 unsigned int offset, int value)
1849{
1850 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1851
1852 ingenic_gpio_set_value(jzgc, offset, value);
1853}
1854
1855static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
1856{
1857 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1858
1859 return (int) ingenic_gpio_get_value(jzgc, offset);
1860}
1861
1862static int ingenic_gpio_direction_input(struct gpio_chip *gc,
1863 unsigned int offset)
1864{
1865 return pinctrl_gpio_direction_input(gc->base + offset);
1866}
1867
1868static int ingenic_gpio_direction_output(struct gpio_chip *gc,
1869 unsigned int offset, int value)
1870{
1871 ingenic_gpio_set(gc, offset, value);
1872 return pinctrl_gpio_direction_output(gc->base + offset);
1873}
1874
b5c23aa4
PC		 1875static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
1876 unsigned int pin, u8 reg, bool set)
1877{
1878 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1879 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1880
f742e5eb 1881 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
b5c23aa4
PC		 1882 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1883}
1884
fe1ad5ee
ZY		 1885static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
1886 unsigned int pin, u8 reg, bool set)
1887{
1888 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1889
f742e5eb 1890 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
fe1ad5ee
ZY		 1891 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1892}
1893
1894static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
1895 unsigned int pin)
1896{
d7da2a1e
ZY		 1897 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
1898 pin / PINS_PER_GPIO_CHIP);
fe1ad5ee
ZY		 1899}
1900
b5c23aa4
PC		 1901static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
1902 unsigned int pin, u8 reg)
1903{
1904 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1905 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1906 unsigned int val;
1907
f742e5eb 1908 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
b5c23aa4
PC		 1909
1910 return val & BIT(idx);
1911}
1912
ebd66514
PC		 1913static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1914{
1915 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1916 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
1917 unsigned int pin = gc->base + offset;
1918
3c827873
MV		 1919 if (jzpc->info->version >= ID_JZ4760) {
1920 if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1))
1921 return GPIO_LINE_DIRECTION_IN;
1922 return GPIO_LINE_DIRECTION_OUT;
1923 }
ebd66514
PC		 1924
1925 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
3c827873
MV		 1926 return GPIO_LINE_DIRECTION_IN;
1927
1928 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
1929 return GPIO_LINE_DIRECTION_OUT;
ebd66514 1930
3c827873 1931 return GPIO_LINE_DIRECTION_IN;
ebd66514
PC		 1932}
1933
5bf7b849 1934static const struct pinctrl_ops ingenic_pctlops = {
b5c23aa4
PC		 1935 .get_groups_count = pinctrl_generic_get_group_count,
1936 .get_group_name = pinctrl_generic_get_group_name,
1937 .get_group_pins = pinctrl_generic_get_group_pins,
1938 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1939 .dt_free_map = pinconf_generic_dt_free_map,
1940};
1941
1942static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
1943 int pin, int func)
1944{
1945 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1946 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1947
1948 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
1949 'A' + offt, idx, func);
1950
baf15647 1951 if (jzpc->info->version >= ID_X1000) {
fe1ad5ee
ZY		 1952 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
1953 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
1954 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
1955 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
1956 ingenic_shadow_config_pin_load(jzpc, pin);
baf15647 1957 } else if (jzpc->info->version >= ID_JZ4760) {
0257595a 1958 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
e72394e2 1959 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
0257595a
ZY		 1960 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
1961 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
b5c23aa4
PC		 1962 } else {
1963 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
1964 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
1965 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0);
1966 }
1967
1968 return 0;
1969}
1970
1971static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
1972 unsigned int selector, unsigned int group)
1973{
1974 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1975 struct function_desc *func;
1976 struct group_desc *grp;
1977 unsigned int i;
1978
1979 func = pinmux_generic_get_function(pctldev, selector);
1980 if (!func)
1981 return -EINVAL;
1982
1983 grp = pinctrl_generic_get_group(pctldev, group);
1984 if (!grp)
1985 return -EINVAL;
1986
1987 dev_dbg(pctldev->dev, "enable function %s group %s\n",
1988 func->name, grp->name);
1989
1990 for (i = 0; i < grp->num_pins; i++) {
1991 int *pin_modes = grp->data;
1992
1993 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
1994 }
1995
1996 return 0;
1997}
1998
1999static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
2000 struct pinctrl_gpio_range *range,
2001 unsigned int pin, bool input)
2002{
2003 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2004 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2005 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2006
2007 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
2008 'A' + offt, idx, input ? "in" : "out");
2009
baf15647 2010 if (jzpc->info->version >= ID_X1000) {
fe1ad5ee
ZY		 2011 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
2012 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
2013 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
2014 ingenic_shadow_config_pin_load(jzpc, pin);
baf15647 2015 } else if (jzpc->info->version >= ID_JZ4760) {
0257595a 2016 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
e72394e2 2017 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
0257595a 2018 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
b5c23aa4
PC		 2019 } else {
2020 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
0084a786 2021 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
b5c23aa4
PC		 2022 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
2023 }
2024
2025 return 0;
2026}
2027
5bf7b849 2028static const struct pinmux_ops ingenic_pmxops = {
b5c23aa4
PC		 2029 .get_functions_count = pinmux_generic_get_function_count,
2030 .get_function_name = pinmux_generic_get_function_name,
2031 .get_function_groups = pinmux_generic_get_function_groups,
2032 .set_mux = ingenic_pinmux_set_mux,
2033 .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
2034};
2035
2036static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
2037 unsigned int pin, unsigned long *config)
2038{
2039 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2040 enum pin_config_param param = pinconf_to_config_param(*config);
2041 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2042 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2043 bool pull;
2044
baf15647 2045 if (jzpc->info->version >= ID_JZ4760)
0257595a 2046 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN);
b5c23aa4
PC		 2047 else
2048 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
2049
2050 switch (param) {
2051 case PIN_CONFIG_BIAS_DISABLE:
2052 if (pull)
2053 return -EINVAL;
2054 break;
2055
2056 case PIN_CONFIG_BIAS_PULL_UP:
2057 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
2058 return -EINVAL;
2059 break;
2060
2061 case PIN_CONFIG_BIAS_PULL_DOWN:
2062 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
2063 return -EINVAL;
2064 break;
2065
2066 default:
2067 return -ENOTSUPP;
2068 }
2069
2070 *config = pinconf_to_config_packed(param, 1);
2071 return 0;
2072}
2073
2074static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
d7da2a1e 2075 unsigned int pin, unsigned int bias)
b5c23aa4 2076{
baf15647 2077 if (jzpc->info->version >= ID_X1830) {
d7da2a1e
ZY		 2078 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2079 unsigned int half = PINS_PER_GPIO_CHIP / 2;
2080 unsigned int idxh = pin % half * 2;
2081 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2082
2083 if (idx < half) {
2084 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2085 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
2086 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2087 REG_SET(X1830_GPIO_PEL), bias << idxh);
2088 } else {
2089 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2090 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
2091 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2092 REG_SET(X1830_GPIO_PEH), bias << idxh);
2093 }
2094
baf15647 2095 } else if (jzpc->info->version >= ID_JZ4760) {
d7da2a1e
ZY		 2096 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias);
2097 } else {
2098 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
2099 }
b5c23aa4
PC		 2100}
2101
7009d046
PC		 2102static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
2103 unsigned int pin, bool high)
2104{
baf15647 2105 if (jzpc->info->version >= ID_JZ4760)
7009d046
PC		 2106 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high);
2107 else
2108 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
2109}
2110
b5c23aa4
PC		 2111static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2112 unsigned long *configs, unsigned int num_configs)
2113{
2114 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2115 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2116 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
7009d046
PC		 2117 unsigned int cfg, arg;
2118 int ret;
b5c23aa4
PC		 2119
2120 for (cfg = 0; cfg < num_configs; cfg++) {
2121 switch (pinconf_to_config_param(configs[cfg])) {
2122 case PIN_CONFIG_BIAS_DISABLE:
2123 case PIN_CONFIG_BIAS_PULL_UP:
2124 case PIN_CONFIG_BIAS_PULL_DOWN:
7009d046 2125 case PIN_CONFIG_OUTPUT:
b5c23aa4
PC		 2126 continue;
2127 default:
2128 return -ENOTSUPP;
2129 }
2130 }
2131
2132 for (cfg = 0; cfg < num_configs; cfg++) {
7009d046
PC		 2133 arg = pinconf_to_config_argument(configs[cfg]);
2134
b5c23aa4
PC		 2135 switch (pinconf_to_config_param(configs[cfg])) {
2136 case PIN_CONFIG_BIAS_DISABLE:
2137 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
2138 'A' + offt, idx);
d7da2a1e 2139 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
b5c23aa4
PC		 2140 break;
2141
2142 case PIN_CONFIG_BIAS_PULL_UP:
2143 if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
2144 return -EINVAL;
2145 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
2146 'A' + offt, idx);
d7da2a1e 2147 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
b5c23aa4
PC		 2148 break;
2149
2150 case PIN_CONFIG_BIAS_PULL_DOWN:
2151 if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
2152 return -EINVAL;
2153 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
2154 'A' + offt, idx);
d7da2a1e 2155 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
b5c23aa4
PC		 2156 break;
2157
7009d046
PC		 2158 case PIN_CONFIG_OUTPUT:
2159 ret = pinctrl_gpio_direction_output(pin);
2160 if (ret)
2161 return ret;
2162
2163 ingenic_set_output_level(jzpc, pin, arg);
2164 break;
2165
b5c23aa4
PC		 2166 default:
2167 unreachable();
2168 }
2169 }
2170
2171 return 0;
2172}
2173
2174static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
2175 unsigned int group, unsigned long *config)
2176{
2177 const unsigned int *pins;
2178 unsigned int i, npins, old = 0;
2179 int ret;
2180
2181 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2182 if (ret)
2183 return ret;
2184
2185 for (i = 0; i < npins; i++) {
2186 if (ingenic_pinconf_get(pctldev, pins[i], config))
2187 return -ENOTSUPP;
2188
2189 /* configs do not match between two pins */
2190 if (i && (old != *config))
2191 return -ENOTSUPP;
2192
2193 old = *config;
2194 }
2195
2196 return 0;
2197}
2198
2199static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
2200 unsigned int group, unsigned long *configs,
2201 unsigned int num_configs)
2202{
2203 const unsigned int *pins;
2204 unsigned int i, npins;
2205 int ret;
2206
2207 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2208 if (ret)
2209 return ret;
2210
2211 for (i = 0; i < npins; i++) {
2212 ret = ingenic_pinconf_set(pctldev,
2213 pins[i], configs, num_configs);
2214 if (ret)
2215 return ret;
2216 }
2217
2218 return 0;
2219}
2220
5bf7b849 2221static const struct pinconf_ops ingenic_confops = {
b5c23aa4
PC		 2222 .is_generic = true,
2223 .pin_config_get = ingenic_pinconf_get,
2224 .pin_config_set = ingenic_pinconf_set,
2225 .pin_config_group_get = ingenic_pinconf_group_get,
2226 .pin_config_group_set = ingenic_pinconf_group_set,
2227};
2228
2229static const struct regmap_config ingenic_pinctrl_regmap_config = {
2230 .reg_bits = 32,
2231 .val_bits = 32,
2232 .reg_stride = 4,
2233};
2234
e72394e2
PC		 2235static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
2236 { .compatible = "ingenic,jz4740-gpio", },
0257595a 2237 { .compatible = "ingenic,jz4760-gpio", },
e72394e2
PC		 2238 { .compatible = "ingenic,jz4770-gpio", },
2239 { .compatible = "ingenic,jz4780-gpio", },
fe1ad5ee 2240 { .compatible = "ingenic,x1000-gpio", },
d7da2a1e 2241 { .compatible = "ingenic,x1830-gpio", },
e72394e2
PC		 2242 {},
2243};
2244
2245static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
2246 struct device_node *node)
2247{
2248 struct ingenic_gpio_chip *jzgc;
2249 struct device *dev = jzpc->dev;
142b8767 2250 struct gpio_irq_chip *girq;
e72394e2
PC		 2251 unsigned int bank;
2252 int err;
2253
2254 err = of_property_read_u32(node, "reg", &bank);
2255 if (err) {
2256 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
2257 return err;
2258 }
2259
2260 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
2261 if (!jzgc)
2262 return -ENOMEM;
2263
2264 jzgc->jzpc = jzpc;
f742e5eb 2265 jzgc->reg_base = bank * jzpc->info->reg_offset;
e72394e2
PC		 2266
2267 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
2268 if (!jzgc->gc.label)
2269 return -ENOMEM;
2270
2271 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
2272 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
2273 * <linux/gpio/consumer.h> INSTEAD.
2274 */
2275 jzgc->gc.base = bank * 32;
2276
2277 jzgc->gc.ngpio = 32;
2278 jzgc->gc.parent = dev;
2279 jzgc->gc.of_node = node;
2280 jzgc->gc.owner = THIS_MODULE;
2281
2282 jzgc->gc.set = ingenic_gpio_set;
2283 jzgc->gc.get = ingenic_gpio_get;
2284 jzgc->gc.direction_input = ingenic_gpio_direction_input;
2285 jzgc->gc.direction_output = ingenic_gpio_direction_output;
ebd66514 2286 jzgc->gc.get_direction = ingenic_gpio_get_direction;
e72394e2
PC		 2287
2288 if (of_property_read_bool(node, "gpio-ranges")) {
2289 jzgc->gc.request = gpiochip_generic_request;
2290 jzgc->gc.free = gpiochip_generic_free;
2291 }
2292
e72394e2
PC		 2293 jzgc->irq = irq_of_parse_and_map(node, 0);
2294 if (!jzgc->irq)
2295 return -EINVAL;
2296
2297 jzgc->irq_chip.name = jzgc->gc.label;
2298 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
2299 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
2300 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
2301 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
2302 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
2303 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
2304 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
2305 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
2306
142b8767
LW		 2307 girq = &jzgc->gc.irq;
2308 girq->chip = &jzgc->irq_chip;
2309 girq->parent_handler = ingenic_gpio_irq_handler;
2310 girq->num_parents = 1;
2311 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
2312 GFP_KERNEL);
2313 if (!girq->parents)
2314 return -ENOMEM;
2315 girq->parents[0] = jzgc->irq;
2316 girq->default_type = IRQ_TYPE_NONE;
2317 girq->handler = handle_level_irq;
2318
2319 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
e72394e2
PC		 2320 if (err)
2321 return err;
2322
e72394e2
PC		 2323 return 0;
2324}
2325
4717b11f 2326static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
b5c23aa4
PC		 2327{
2328 struct device *dev = &pdev->dev;
2329 struct ingenic_pinctrl *jzpc;
2330 struct pinctrl_desc *pctl_desc;
2331 void __iomem *base;
b5c23aa4 2332 const struct ingenic_chip_info *chip_info;
e72394e2 2333 struct device_node *node;
b5c23aa4
PC		 2334 unsigned int i;
2335 int err;
2336
2337 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
2338 if (!jzpc)
2339 return -ENOMEM;
2340
94f7a2cb 2341 base = devm_platform_ioremap_resource(pdev, 0);
119fcf47 2342 if (IS_ERR(base))
b5c23aa4 2343 return PTR_ERR(base);
b5c23aa4
PC		 2344
2345 jzpc->map = devm_regmap_init_mmio(dev, base,
2346 &ingenic_pinctrl_regmap_config);
2347 if (IS_ERR(jzpc->map)) {
2348 dev_err(dev, "Failed to create regmap\n");
2349 return PTR_ERR(jzpc->map);
2350 }
2351
2352 jzpc->dev = dev;
baf15647 2353 jzpc->info = chip_info = of_device_get_match_data(dev);
b5c23aa4
PC		 2354
2355 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
2356 if (!pctl_desc)
2357 return -ENOMEM;
2358
2359 /* fill in pinctrl_desc structure */
2360 pctl_desc->name = dev_name(dev);
2361 pctl_desc->owner = THIS_MODULE;
2362 pctl_desc->pctlops = &ingenic_pctlops;
2363 pctl_desc->pmxops = &ingenic_pmxops;
2364 pctl_desc->confops = &ingenic_confops;
2365 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
a86854d0
KC		 2366 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
2367 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
b5c23aa4
PC		 2368 if (!jzpc->pdesc)
2369 return -ENOMEM;
2370
2371 for (i = 0; i < pctl_desc->npins; i++) {
2372 jzpc->pdesc[i].number = i;
2373 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
2374 'A' + (i / PINS_PER_GPIO_CHIP),
2375 i % PINS_PER_GPIO_CHIP);
2376 }
2377
2378 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
e7f4c4bf 2379 if (IS_ERR(jzpc->pctl)) {
b5c23aa4 2380 dev_err(dev, "Failed to register pinctrl\n");
e7f4c4bf 2381 return PTR_ERR(jzpc->pctl);
b5c23aa4
PC		 2382 }
2383
2384 for (i = 0; i < chip_info->num_groups; i++) {
2385 const struct group_desc *group = &chip_info->groups[i];
2386
2387 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
2388 group->pins, group->num_pins, group->data);
823dd71f 2389 if (err < 0) {
b5c23aa4
PC		 2390 dev_err(dev, "Failed to register group %s\n",
2391 group->name);
2392 return err;
2393 }
2394 }
2395
2396 for (i = 0; i < chip_info->num_functions; i++) {
2397 const struct function_desc *func = &chip_info->functions[i];
2398
2399 err = pinmux_generic_add_function(jzpc->pctl, func->name,
2400 func->group_names, func->num_group_names,
2401 func->data);
823dd71f 2402 if (err < 0) {
b5c23aa4
PC		 2403 dev_err(dev, "Failed to register function %s\n",
2404 func->name);
2405 return err;
2406 }
2407 }
2408
2409 dev_set_drvdata(dev, jzpc->map);
2410
e72394e2
PC		 2411 for_each_child_of_node(dev->of_node, node) {
2412 if (of_match_node(ingenic_gpio_of_match, node)) {
2413 err = ingenic_gpio_probe(jzpc, node);
2414 if (err)
2415 return err;
b5c23aa4
PC		 2416 }
2417 }
2418
2419 return 0;
2420}
2421
baf15647
PC		 2422static const struct of_device_id ingenic_pinctrl_of_match[] = {
2423 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info },
2424 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info },
2425 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info },
5ffdbb7e 2426 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info },
baf15647
PC		 2427 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info },
2428 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info },
2429 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info },
5ffdbb7e 2430 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info },
baf15647
PC		 2431 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info },
2432 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info },
2433 {},
2434};
2435
b5c23aa4
PC		 2436static struct platform_driver ingenic_pinctrl_driver = {
2437 .driver = {
2438 .name = "pinctrl-ingenic",
5ec008bf 2439 .of_match_table = ingenic_pinctrl_of_match,
b5c23aa4 2440 },
b5c23aa4
PC		 2441};
2442
2443static int __init ingenic_pinctrl_drv_register(void)
2444{
4717b11f
PC		 2445 return platform_driver_probe(&ingenic_pinctrl_driver,
2446 ingenic_pinctrl_probe);
b5c23aa4 2447}
556a36a7 2448subsys_initcall(ingenic_pinctrl_drv_register);
Linux 6.x block layer and io_uring tree(s)