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gpio: ep93xx: fix BUG_ON port F usage
[linux-block.git] / drivers / pinctrl / pinctrl-ingenic.c
CommitLineData
af873fce 1// SPDX-License-Identifier: GPL-2.0-only
b5c23aa4
PC		 2/*
3 * Ingenic SoCs pinctrl driver
4 *
5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
d7da2a1e 6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
a0bb89e8 7 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
b5c23aa4
PC		 8 */
9
10#include <linux/compiler.h>
28d6eeb4 11#include <linux/gpio/driver.h>
b5c23aa4
PC		 12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/of_device.h>
e72394e2 15#include <linux/of_irq.h>
b5c23aa4
PC		 16#include <linux/of_platform.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24
25#include "core.h"
26#include "pinconf.h"
27#include "pinmux.h"
28
e72394e2
PC		 29#define GPIO_PIN 0x00
30#define GPIO_MSK 0x20
31
b5c23aa4
PC		 32#define JZ4740_GPIO_DATA 0x10
33#define JZ4740_GPIO_PULL_DIS 0x30
34#define JZ4740_GPIO_FUNC 0x40
35#define JZ4740_GPIO_SELECT 0x50
36#define JZ4740_GPIO_DIR 0x60
37#define JZ4740_GPIO_TRIG 0x70
38#define JZ4740_GPIO_FLAG 0x80
39
b4aa4876
PC		 40#define JZ4770_GPIO_INT 0x10
41#define JZ4770_GPIO_PAT1 0x30
42#define JZ4770_GPIO_PAT0 0x40
43#define JZ4770_GPIO_FLAG 0x50
44#define JZ4770_GPIO_PEN 0x70
b5c23aa4 45
d7da2a1e
ZY		 46#define X1830_GPIO_PEL 0x110
47#define X1830_GPIO_PEH 0x120
fe1ad5ee 48
b5c23aa4
PC		 49#define REG_SET(x) ((x) + 0x4)
50#define REG_CLEAR(x) ((x) + 0x8)
51
d7da2a1e
ZY		 52#define REG_PZ_BASE(x) ((x) * 7)
53#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
54
55#define GPIO_PULL_DIS 0
56#define GPIO_PULL_UP 1
57#define GPIO_PULL_DOWN 2
58
b5c23aa4
PC		 59#define PINS_PER_GPIO_CHIP 32
60
61enum jz_version {
62 ID_JZ4740,
f2a96765 63 ID_JZ4725B,
0257595a 64 ID_JZ4760,
b5c23aa4
PC		 65 ID_JZ4770,
66 ID_JZ4780,
fe1ad5ee 67 ID_X1000,
5d21595b 68 ID_X1500,
d7da2a1e 69 ID_X1830,
b5c23aa4
PC		 70};
71
72struct ingenic_chip_info {
73 unsigned int num_chips;
f742e5eb 74 unsigned int reg_offset;
baf15647 75 enum jz_version version;
b5c23aa4
PC		 76
77 const struct group_desc *groups;
78 unsigned int num_groups;
79
80 const struct function_desc *functions;
81 unsigned int num_functions;
82
83 const u32 *pull_ups, *pull_downs;
84};
85
86struct ingenic_pinctrl {
87 struct device *dev;
88 struct regmap *map;
89 struct pinctrl_dev *pctl;
90 struct pinctrl_pin_desc *pdesc;
b5c23aa4
PC		 91
92 const struct ingenic_chip_info *info;
93};
94
e72394e2
PC		 95struct ingenic_gpio_chip {
96 struct ingenic_pinctrl *jzpc;
97 struct gpio_chip gc;
98 struct irq_chip irq_chip;
99 unsigned int irq, reg_base;
100};
101
b5c23aa4
PC		 102static const u32 jz4740_pull_ups[4] = {
103 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
104};
105
106static const u32 jz4740_pull_downs[4] = {
107 0x00000000, 0x00000000, 0x00000000, 0x00000000,
108};
109
110static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
111static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
112static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
113static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
114static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
115static int jz4740_lcd_8bit_pins[] = {
116 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
117};
118static int jz4740_lcd_16bit_pins[] = {
119 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
120};
121static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
122static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
123static int jz4740_nand_cs1_pins[] = { 0x39, };
124static int jz4740_nand_cs2_pins[] = { 0x3a, };
125static int jz4740_nand_cs3_pins[] = { 0x3b, };
126static int jz4740_nand_cs4_pins[] = { 0x3c, };
bcad94d7 127static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
b5c23aa4
PC		 128static int jz4740_pwm_pwm0_pins[] = { 0x77, };
129static int jz4740_pwm_pwm1_pins[] = { 0x78, };
130static int jz4740_pwm_pwm2_pins[] = { 0x79, };
131static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
132static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
133static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
134static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
135static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
136
bb42b593
PC		 137
138#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \
b5c23aa4
PC		 139 { \
140 name, \
141 id##_pins, \
142 ARRAY_SIZE(id##_pins), \
bb42b593 143 funcs, \
b5c23aa4
PC		 144 }
145
bb42b593
PC		 146#define INGENIC_PIN_GROUP(name, id, func) \
147 INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
148
b5c23aa4 149static const struct group_desc jz4740_groups[] = {
bb42b593
PC		 150 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
151 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
152 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
153 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
154 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
155 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
156 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
157 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
158 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft, 0),
b5c23aa4 159 { "lcd-no-pins", },
bb42b593
PC		 160 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
161 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
162 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
163 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
164 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
165 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),
166 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),
167 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),
168 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),
169 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),
170 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),
171 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),
172 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),
b5c23aa4
PC		 173};
174
175static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
176static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
177static const char *jz4740_uart1_groups[] = { "uart1-data", };
178static const char *jz4740_lcd_groups[] = {
179 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
180};
181static const char *jz4740_nand_groups[] = {
bcad94d7 182 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
b5c23aa4
PC		 183};
184static const char *jz4740_pwm0_groups[] = { "pwm0", };
185static const char *jz4740_pwm1_groups[] = { "pwm1", };
186static const char *jz4740_pwm2_groups[] = { "pwm2", };
187static const char *jz4740_pwm3_groups[] = { "pwm3", };
188static const char *jz4740_pwm4_groups[] = { "pwm4", };
189static const char *jz4740_pwm5_groups[] = { "pwm5", };
190static const char *jz4740_pwm6_groups[] = { "pwm6", };
191static const char *jz4740_pwm7_groups[] = { "pwm7", };
192
193static const struct function_desc jz4740_functions[] = {
194 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
195 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
196 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
197 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
198 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
199 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
200 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
201 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
202 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
203 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
204 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
205 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
206 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
207};
208
209static const struct ingenic_chip_info jz4740_chip_info = {
210 .num_chips = 4,
f742e5eb 211 .reg_offset = 0x100,
baf15647 212 .version = ID_JZ4740,
b5c23aa4
PC		 213 .groups = jz4740_groups,
214 .num_groups = ARRAY_SIZE(jz4740_groups),
215 .functions = jz4740_functions,
216 .num_functions = ARRAY_SIZE(jz4740_functions),
217 .pull_ups = jz4740_pull_ups,
218 .pull_downs = jz4740_pull_downs,
219};
220
f2a96765
PC		 221static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
222static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
223static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
224static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
225static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
226static int jz4725b_nand_cs1_pins[] = { 0x55, };
227static int jz4725b_nand_cs2_pins[] = { 0x56, };
228static int jz4725b_nand_cs3_pins[] = { 0x57, };
229static int jz4725b_nand_cs4_pins[] = { 0x58, };
230static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
231static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
232static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
233static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
234static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
235static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
236static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
237static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
a3240f09
PC		 238static int jz4725b_lcd_8bit_pins[] = {
239 0x72, 0x73, 0x74,
240 0x60, 0x61, 0x62, 0x63,
241 0x64, 0x65, 0x66, 0x67,
242};
243static int jz4725b_lcd_16bit_pins[] = {
244 0x68, 0x69, 0x6a, 0x6b,
245 0x6c, 0x6d, 0x6e, 0x6f,
246};
247static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
248static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
249static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
250static int jz4725b_lcd_generic_pins[] = { 0x75, };
f2a96765 251
bb42b593 252static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
f2a96765
PC		 253
254static const struct group_desc jz4725b_groups[] = {
bb42b593
PC		 255 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
256 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
257 jz4725b_mmc0_4bit_funcs),
258 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
259 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
260 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
261 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
262 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
263 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
264 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
265 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
266 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
267 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),
268 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),
269 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),
270 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),
271 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),
272 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),
273 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
274 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
275 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
276 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
277 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
278 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
f2a96765
PC		 279};
280
281static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
282static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
283static const char *jz4725b_uart_groups[] = { "uart-data", };
284static const char *jz4725b_nand_groups[] = {
285 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
286 "nand-cle-ale", "nand-fre-fwe",
287};
288static const char *jz4725b_pwm0_groups[] = { "pwm0", };
289static const char *jz4725b_pwm1_groups[] = { "pwm1", };
290static const char *jz4725b_pwm2_groups[] = { "pwm2", };
291static const char *jz4725b_pwm3_groups[] = { "pwm3", };
292static const char *jz4725b_pwm4_groups[] = { "pwm4", };
293static const char *jz4725b_pwm5_groups[] = { "pwm5", };
a3240f09
PC		 294static const char *jz4725b_lcd_groups[] = {
295 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
296 "lcd-special", "lcd-generic",
297};
f2a96765
PC		 298
299static const struct function_desc jz4725b_functions[] = {
300 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
301 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
302 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
303 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
304 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
305 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
306 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
307 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
308 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
309 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
a3240f09 310 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
f2a96765
PC		 311};
312
313static const struct ingenic_chip_info jz4725b_chip_info = {
314 .num_chips = 4,
f742e5eb 315 .reg_offset = 0x100,
baf15647 316 .version = ID_JZ4725B,
f2a96765
PC		 317 .groups = jz4725b_groups,
318 .num_groups = ARRAY_SIZE(jz4725b_groups),
319 .functions = jz4725b_functions,
320 .num_functions = ARRAY_SIZE(jz4725b_functions),
321 .pull_ups = jz4740_pull_ups,
322 .pull_downs = jz4740_pull_downs,
323};
324
0257595a
ZY		 325static const u32 jz4760_pull_ups[6] = {
326 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f,
327};
328
329static const u32 jz4760_pull_downs[6] = {
330 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
331};
332
333static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
334static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
335static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
336static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
337static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
338static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
339static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
340static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
341static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
342static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
343static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
344static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
345static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
346static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
347static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
348static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
349static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
350static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
351static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
352static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
353static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
354static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
355static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
356static int jz4760_nemc_8bit_data_pins[] = {
357 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
358};
359static int jz4760_nemc_16bit_data_pins[] = {
360 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
361};
362static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
363static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
364static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
365static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
366static int jz4760_nemc_wait_pins[] = { 0x1b, };
367static int jz4760_nemc_cs1_pins[] = { 0x15, };
368static int jz4760_nemc_cs2_pins[] = { 0x16, };
369static int jz4760_nemc_cs3_pins[] = { 0x17, };
370static int jz4760_nemc_cs4_pins[] = { 0x18, };
371static int jz4760_nemc_cs5_pins[] = { 0x19, };
372static int jz4760_nemc_cs6_pins[] = { 0x1a, };
373static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
374static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
375static int jz4760_cim_pins[] = {
376 0x26, 0x27, 0x28, 0x29,
377 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
378};
379static int jz4760_lcd_24bit_pins[] = {
380 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
381 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
382 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
383 0x58, 0x59, 0x5a, 0x5b,
384};
385static int jz4760_pwm_pwm0_pins[] = { 0x80, };
386static int jz4760_pwm_pwm1_pins[] = { 0x81, };
387static int jz4760_pwm_pwm2_pins[] = { 0x82, };
388static int jz4760_pwm_pwm3_pins[] = { 0x83, };
389static int jz4760_pwm_pwm4_pins[] = { 0x84, };
390static int jz4760_pwm_pwm5_pins[] = { 0x85, };
391static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
392static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
393
bb42b593
PC		 394static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
395static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
0257595a
ZY		 396
397static const struct group_desc jz4760_groups[] = {
bb42b593
PC		 398 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
399 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
400 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
401 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
402 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
403 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
404 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
405 jz4760_uart3_data_funcs),
406 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
407 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
408 jz4760_mmc0_1bit_a_funcs),
409 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
410 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
411 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
412 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
413 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
414 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
415 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
416 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
417 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
418 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
419 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
420 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
421 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
422 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
423 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
424 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
425 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
426 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
427 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
428 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
429 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
430 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
431 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
432 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
433 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
434 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
435 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
436 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
437 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
438 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
439 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
0257595a 440 { "lcd-no-pins", },
bb42b593
PC		 441 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
442 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
443 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
444 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),
445 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),
446 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
447 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
448 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
0257595a
ZY		 449};
450
451static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
452static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
453static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
454static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
455static const char *jz4760_mmc0_groups[] = {
456 "mmc0-1bit-a", "mmc0-4bit-a",
457 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
458};
459static const char *jz4760_mmc1_groups[] = {
460 "mmc1-1bit-d", "mmc1-4bit-d",
461 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
462};
463static const char *jz4760_mmc2_groups[] = {
464 "mmc2-1bit-b", "mmc2-4bit-b",
465 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
466};
467static const char *jz4760_nemc_groups[] = {
468 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
469 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
470};
471static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
472static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
473static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
474static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
475static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
476static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
477static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
478static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
479static const char *jz4760_cim_groups[] = { "cim-data", };
480static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
481static const char *jz4760_pwm0_groups[] = { "pwm0", };
482static const char *jz4760_pwm1_groups[] = { "pwm1", };
483static const char *jz4760_pwm2_groups[] = { "pwm2", };
484static const char *jz4760_pwm3_groups[] = { "pwm3", };
485static const char *jz4760_pwm4_groups[] = { "pwm4", };
486static const char *jz4760_pwm5_groups[] = { "pwm5", };
487static const char *jz4760_pwm6_groups[] = { "pwm6", };
488static const char *jz4760_pwm7_groups[] = { "pwm7", };
489
490static const struct function_desc jz4760_functions[] = {
491 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
492 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
493 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
494 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
495 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
496 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
497 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
498 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
499 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
500 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
501 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
502 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
503 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
504 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
505 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
506 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
507 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
508 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
509 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
510 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
511 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
512 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
513 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
514 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
515 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
516 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
517};
518
519static const struct ingenic_chip_info jz4760_chip_info = {
520 .num_chips = 6,
f742e5eb 521 .reg_offset = 0x100,
baf15647 522 .version = ID_JZ4760,
0257595a
ZY		 523 .groups = jz4760_groups,
524 .num_groups = ARRAY_SIZE(jz4760_groups),
525 .functions = jz4760_functions,
526 .num_functions = ARRAY_SIZE(jz4760_functions),
527 .pull_ups = jz4760_pull_ups,
528 .pull_downs = jz4760_pull_downs,
529};
530
b5c23aa4
PC		 531static const u32 jz4770_pull_ups[6] = {
532 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
533};
534
535static const u32 jz4770_pull_downs[6] = {
536 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
537};
538
539static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
540static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
541static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
542static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
ff656e47
ZY		 543static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
544static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
b5c23aa4
PC		 545static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
546static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
d3ef8c6b
ZY		 547static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
548static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
f83c2609
PC		 549static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
550static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
d3ef8c6b
ZY		 551static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
552static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
f83c2609
PC		 553static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
554static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
d3ef8c6b
ZY		 555static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
556static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
f83c2609
PC		 557static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
558static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
d3ef8c6b 559static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
f83c2609
PC		 560static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
561static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
d3ef8c6b
ZY		 562static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
563static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
f83c2609
PC		 564static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
565static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
d3ef8c6b 566static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
f83c2609
PC		 567static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
568static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
d3ef8c6b 569static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
f83c2609
PC		 570static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
571static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
d3ef8c6b 572static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
f83c2609
PC		 573static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
574static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
d3ef8c6b 575static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
f83c2609
PC		 576static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
577static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
d3ef8c6b 578static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
f83c2609
PC		 579static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
580static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
d3ef8c6b 581static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
f83c2609
PC		 582static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
583static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
d3ef8c6b 584static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
f83c2609
PC		 585static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
586static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
b5c23aa4 587static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
ff656e47 588static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
b5c23aa4 589static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
ff656e47
ZY		 590static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
591static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
b5c23aa4 592static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
ff656e47 593static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
b5c23aa4 594static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
ff656e47
ZY		 595static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
596static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
5de1a73e
ZY		 597static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
598static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
599static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
600static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
601static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
ff656e47 602static int jz4770_nemc_8bit_data_pins[] = {
b5c23aa4
PC		 603 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
604};
ff656e47
ZY		 605static int jz4770_nemc_16bit_data_pins[] = {
606 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
607};
b5c23aa4
PC		 608static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
609static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
610static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
611static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
5de1a73e 612static int jz4770_nemc_wait_pins[] = { 0x1b, };
b5c23aa4
PC		 613static int jz4770_nemc_cs1_pins[] = { 0x15, };
614static int jz4770_nemc_cs2_pins[] = { 0x16, };
615static int jz4770_nemc_cs3_pins[] = { 0x17, };
616static int jz4770_nemc_cs4_pins[] = { 0x18, };
617static int jz4770_nemc_cs5_pins[] = { 0x19, };
618static int jz4770_nemc_cs6_pins[] = { 0x1a, };
ff656e47
ZY		 619static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
620static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
b5c23aa4 621static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
ff656e47
ZY		 622static int jz4770_cim_8bit_pins[] = {
623 0x26, 0x27, 0x28, 0x29,
624 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
625};
626static int jz4770_cim_12bit_pins[] = {
627 0x32, 0x33, 0xb0, 0xb1,
b5c23aa4 628};
016e054d
PC		 629static int jz4770_lcd_8bit_pins[] = {
630 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
631 0x48, 0x49, 0x52, 0x53,
632};
ff656e47 633static int jz4770_lcd_24bit_pins[] = {
b5c23aa4
PC		 634 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
635 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
636 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
ff656e47 637 0x58, 0x59, 0x5a, 0x5b,
b5c23aa4
PC		 638};
639static int jz4770_pwm_pwm0_pins[] = { 0x80, };
640static int jz4770_pwm_pwm1_pins[] = { 0x81, };
641static int jz4770_pwm_pwm2_pins[] = { 0x82, };
642static int jz4770_pwm_pwm3_pins[] = { 0x83, };
643static int jz4770_pwm_pwm4_pins[] = { 0x84, };
644static int jz4770_pwm_pwm5_pins[] = { 0x85, };
645static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
646static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
5de1a73e
ZY		 647static int jz4770_mac_rmii_pins[] = {
648 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
649};
650static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
ae75b53e 651static int jz4770_otg_pins[] = { 0x8a, };
b5c23aa4 652
b5c23aa4 653static const struct group_desc jz4770_groups[] = {
bb42b593
PC		 654 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
655 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
656 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
657 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
658 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
659 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
660 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
661 jz4760_uart3_data_funcs),
662 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
663 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
664 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
665 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
666 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
667 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
668 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
669 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
670 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
671 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
672 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
673 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
674 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
675 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
676 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
677 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
678 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
679 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
680 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
681 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
682 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
683 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
684 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
685 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
686 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
687 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
688 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
689 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
690 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
691 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
692 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
693 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
694 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
695 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
696 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
697 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
698 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
699 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
700 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
701 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
702 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
703 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
704 jz4760_mmc0_1bit_a_funcs),
705 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
706 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
707 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
708 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
709 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
710 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
711 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
712 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
713 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
714 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
715 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
716 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
717 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
718 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
719 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
720 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
721 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
722 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
723 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
724 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
725 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
726 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
727 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
728 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
729 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
730 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
731 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
732 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
733 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
734 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
735 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
736 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
016e054d 737 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
bb42b593 738 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
b5c23aa4 739 { "lcd-no-pins", },
bb42b593
PC		 740 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
741 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
742 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
743 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
744 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
745 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
746 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
747 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
748 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
749 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
750 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg, 0),
b5c23aa4
PC		 751};
752
753static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
754static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
755static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
756static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
d3ef8c6b
ZY		 757static const char *jz4770_ssi0_groups[] = {
758 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
759 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
760 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
761 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
762 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
763 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
764};
765static const char *jz4770_ssi1_groups[] = {
766 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
767 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
768 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
769 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
770 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
771 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
772};
b5c23aa4 773static const char *jz4770_mmc0_groups[] = {
ff656e47
ZY		 774 "mmc0-1bit-a", "mmc0-4bit-a",
775 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
b5c23aa4
PC		 776};
777static const char *jz4770_mmc1_groups[] = {
ff656e47
ZY		 778 "mmc1-1bit-d", "mmc1-4bit-d",
779 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
b5c23aa4 780};
5de1a73e
ZY		 781static const char *jz4770_mmc2_groups[] = {
782 "mmc2-1bit-b", "mmc2-4bit-b",
783 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
784};
b5c23aa4 785static const char *jz4770_nemc_groups[] = {
ff656e47 786 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
5de1a73e 787 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
b5c23aa4
PC		 788};
789static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
ff656e47
ZY		 790static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
791static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
792static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
793static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
b5c23aa4
PC		 794static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
795static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
796static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
797static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
ff656e47 798static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
016e054d
PC		 799static const char *jz4770_lcd_groups[] = {
800 "lcd-8bit", "lcd-24bit", "lcd-no-pins",
801};
b5c23aa4
PC		 802static const char *jz4770_pwm0_groups[] = { "pwm0", };
803static const char *jz4770_pwm1_groups[] = { "pwm1", };
804static const char *jz4770_pwm2_groups[] = { "pwm2", };
805static const char *jz4770_pwm3_groups[] = { "pwm3", };
806static const char *jz4770_pwm4_groups[] = { "pwm4", };
807static const char *jz4770_pwm5_groups[] = { "pwm5", };
808static const char *jz4770_pwm6_groups[] = { "pwm6", };
809static const char *jz4770_pwm7_groups[] = { "pwm7", };
5de1a73e 810static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
ae75b53e 811static const char *jz4770_otg_groups[] = { "otg-vbus", };
b5c23aa4
PC		 812
813static const struct function_desc jz4770_functions[] = {
814 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
815 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
816 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
817 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
d3ef8c6b
ZY		 818 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
819 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
b5c23aa4
PC		 820 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
821 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
5de1a73e 822 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
b5c23aa4
PC		 823 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
824 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
ff656e47
ZY		 825 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
826 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
827 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
828 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
b5c23aa4
PC		 829 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
830 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
831 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
832 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
b5c23aa4
PC		 833 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
834 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
835 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
836 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
837 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
838 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
839 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
840 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
841 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
842 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
5de1a73e 843 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
ae75b53e 844 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), },
b5c23aa4
PC		 845};
846
847static const struct ingenic_chip_info jz4770_chip_info = {
848 .num_chips = 6,
f742e5eb 849 .reg_offset = 0x100,
baf15647 850 .version = ID_JZ4770,
b5c23aa4
PC		 851 .groups = jz4770_groups,
852 .num_groups = ARRAY_SIZE(jz4770_groups),
853 .functions = jz4770_functions,
854 .num_functions = ARRAY_SIZE(jz4770_functions),
855 .pull_ups = jz4770_pull_ups,
856 .pull_downs = jz4770_pull_downs,
857};
858
d9f5dc49
ZY		 859static const u32 jz4780_pull_ups[6] = {
860 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
861};
862
863static const u32 jz4780_pull_downs[6] = {
864 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
865};
866
ff656e47
ZY		 867static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
868static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
869static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
d3ef8c6b
ZY		 870static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
871static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
872static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
873static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
f83c2609 874static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
d3ef8c6b
ZY		 875static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
876static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
877static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
f83c2609 878static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
d3ef8c6b
ZY		 879static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
880static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
881static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
f83c2609 882static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
d3ef8c6b 883static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
f83c2609 884static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
d3ef8c6b
ZY		 885static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
886static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
887static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
f83c2609 888static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
d3ef8c6b 889static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
f83c2609 890static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
d3ef8c6b 891static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
f83c2609 892static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
d3ef8c6b 893static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
f83c2609 894static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
d3ef8c6b 895static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
f83c2609 896static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
d3ef8c6b 897static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
f83c2609 898static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
d3ef8c6b 899static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
f83c2609 900static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
d3ef8c6b 901static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
f83c2609 902static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
ff656e47
ZY		 903static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
904static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
905static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
906static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
f4b5c348
ZY		 907static int jz4780_i2s_data_tx_pins[] = { 0x87, };
908static int jz4780_i2s_data_rx_pins[] = { 0x86, };
909static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
910static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
911static int jz4780_i2s_sysclk_pins[] = { 0x85, };
a0bb89e8 912static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
ff656e47 913
bb42b593 914static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
ff656e47
ZY		 915
916static const struct group_desc jz4780_groups[] = {
bb42b593
PC		 917 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
918 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
919 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
920 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
921 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
922 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
923 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
924 jz4760_uart3_data_funcs),
925 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
926 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
927 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
928 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
929 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
930 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
931 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
932 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
933 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
934 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
935 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
936 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
937 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
938 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
939 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
940 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
941 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
942 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
943 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
944 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
945 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
946 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
947 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
948 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
949 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
950 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
951 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
952 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
953 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
954 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
955 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
956 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
957 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
958 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
959 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
960 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
961 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
962 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
963 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
964 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
965 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
966 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
967 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
968 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
969 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
970 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
971 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
972 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
973 jz4760_mmc0_1bit_a_funcs),
974 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
975 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
976 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
977 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
978 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
979 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
980 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
981 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
982 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
983 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
984 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
985 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
986 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
987 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
988 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
989 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
990 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
991 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
992 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
993 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
994 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
995 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
996 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
997 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
998 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
999 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1000 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1001 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1002 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1003 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1004 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1005 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1006 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1007 jz4780_i2s_clk_txrx_funcs),
1008 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1009 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1010 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1011 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1012 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1013 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
ff656e47 1014 { "lcd-no-pins", },
bb42b593
PC		 1015 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1016 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1017 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1018 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1019 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1020 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1021 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1022 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
ff656e47
ZY		 1023};
1024
1025static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1026static const char *jz4780_uart4_groups[] = { "uart4-data", };
d3ef8c6b
ZY		 1027static const char *jz4780_ssi0_groups[] = {
1028 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1029 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1030 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1031 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1032 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1033 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1034};
1035static const char *jz4780_ssi1_groups[] = {
1036 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1037 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1038 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1039 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1040 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1041 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1042};
ff656e47
ZY		 1043static const char *jz4780_mmc0_groups[] = {
1044 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1045 "mmc0-1bit-e", "mmc0-4bit-e",
1046};
1047static const char *jz4780_mmc1_groups[] = {
1048 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1049};
5de1a73e
ZY		 1050static const char *jz4780_mmc2_groups[] = {
1051 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1052};
ff656e47
ZY		 1053static const char *jz4780_nemc_groups[] = {
1054 "nemc-data", "nemc-cle-ale", "nemc-addr",
5de1a73e 1055 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
ff656e47
ZY		 1056};
1057static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1058static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
f4b5c348
ZY		 1059static const char *jz4780_i2s_groups[] = {
1060 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1061};
ff656e47 1062static const char *jz4780_cim_groups[] = { "cim-data", };
a0bb89e8 1063static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
ff656e47
ZY		 1064
1065static const struct function_desc jz4780_functions[] = {
1066 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1067 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1068 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
1069 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1070 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
d3ef8c6b
ZY		 1071 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
1072 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
ff656e47
ZY		 1073 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
1074 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
5de1a73e 1075 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
ff656e47
ZY		 1076 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
1077 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1078 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1079 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1080 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1081 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1082 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1083 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1084 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1085 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1086 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
1087 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
f4b5c348 1088 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
ff656e47
ZY		 1089 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
1090 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1091 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1092 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1093 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1094 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1095 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1096 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1097 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1098 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
a0bb89e8
PB		 1099 { "hdmi-ddc", jz4780_hdmi_ddc_groups,
1100 ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
ff656e47
ZY		 1101};
1102
1103static const struct ingenic_chip_info jz4780_chip_info = {
1104 .num_chips = 6,
f742e5eb 1105 .reg_offset = 0x100,
baf15647 1106 .version = ID_JZ4780,
ff656e47
ZY		 1107 .groups = jz4780_groups,
1108 .num_groups = ARRAY_SIZE(jz4780_groups),
1109 .functions = jz4780_functions,
1110 .num_functions = ARRAY_SIZE(jz4780_functions),
d9f5dc49
ZY		 1111 .pull_ups = jz4780_pull_ups,
1112 .pull_downs = jz4780_pull_downs,
ff656e47
ZY		 1113};
1114
fe1ad5ee 1115static const u32 x1000_pull_ups[4] = {
b4a9372a 1116 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
fe1ad5ee
ZY		 1117};
1118
1119static const u32 x1000_pull_downs[4] = {
1120 0x00000000, 0x02000000, 0x02000000, 0x00000000,
1121};
1122
1123static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
1124static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1125static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
1126static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
b4a9372a 1127static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
fe1ad5ee
ZY		 1128static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
1129static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
3b31e9b0
ZY		 1130static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, };
1131static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
1132static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
1133static int x1000_ssi_dt_d_pins[] = { 0x62, };
1134static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
1135static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
1136static int x1000_ssi_dr_d_pins[] = { 0x63, };
1137static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
1138static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
1139static int x1000_ssi_clk_d_pins[] = { 0x60, };
1140static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
1141static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
1142static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
1143static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
1144static int x1000_ssi_ce0_d_pins[] = { 0x61, };
1145static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
1146static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
fe1ad5ee
ZY		 1147static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
1148static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
1149static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
1150static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
1151static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
b4a9372a 1152static int x1000_emc_8bit_data_pins[] = {
fe1ad5ee
ZY		 1153 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1154};
b4a9372a 1155static int x1000_emc_16bit_data_pins[] = {
fe1ad5ee
ZY		 1156 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1157};
b4a9372a 1158static int x1000_emc_addr_pins[] = {
fe1ad5ee
ZY		 1159 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
1160 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
1161};
b4a9372a
ZY		 1162static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
1163static int x1000_emc_wait_pins[] = { 0x34, };
1164static int x1000_emc_cs1_pins[] = { 0x32, };
1165static int x1000_emc_cs2_pins[] = { 0x33, };
fe1ad5ee
ZY		 1166static int x1000_i2c0_pins[] = { 0x38, 0x37, };
1167static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
1168static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
1169static int x1000_i2c2_pins[] = { 0x61, 0x60, };
f4b5c348
ZY		 1170static int x1000_i2s_data_tx_pins[] = { 0x24, };
1171static int x1000_i2s_data_rx_pins[] = { 0x23, };
1172static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
1173static int x1000_i2s_sysclk_pins[] = { 0x20, };
fe1ad5ee
ZY		 1174static int x1000_cim_pins[] = {
1175 0x08, 0x09, 0x0a, 0x0b,
1176 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1177};
1178static int x1000_lcd_8bit_pins[] = {
1179 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1180 0x30, 0x31, 0x32, 0x33, 0x34,
1181};
1182static int x1000_lcd_16bit_pins[] = {
1183 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1184};
1185static int x1000_pwm_pwm0_pins[] = { 0x59, };
1186static int x1000_pwm_pwm1_pins[] = { 0x5a, };
1187static int x1000_pwm_pwm2_pins[] = { 0x5b, };
1188static int x1000_pwm_pwm3_pins[] = { 0x26, };
1189static int x1000_pwm_pwm4_pins[] = { 0x58, };
1190static int x1000_mac_pins[] = {
1191 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
1192};
1193
fe1ad5ee 1194static const struct group_desc x1000_groups[] = {
bb42b593
PC		 1195 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
1196 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
1197 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
1198 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
1199 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
1200 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
1201 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
1202 INGENIC_PIN_GROUP("sfc", x1000_sfc, 1),
1203 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
1204 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
1205 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
1206 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
1207 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
1208 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
1209 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
1210 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
1211 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
1212 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
1213 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
1214 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
1215 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
1216 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
1217 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
1218 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
1219 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
1220 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
1221 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
1222 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
1223 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
1224 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
1225 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
1226 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
1227 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
1228 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
1229 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
1230 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
1231 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
1232 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
1233 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
1234 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
1235 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
1236 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
1237 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
1238 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
1239 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
1240 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
1241 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
fe1ad5ee 1242 { "lcd-no-pins", },
bb42b593
PC		 1243 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),
1244 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),
1245 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),
1246 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
1247 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),
1248 INGENIC_PIN_GROUP("mac", x1000_mac, 1),
fe1ad5ee
ZY		 1249};
1250
1251static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1252static const char *x1000_uart1_groups[] = {
b4a9372a 1253 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
fe1ad5ee
ZY		 1254};
1255static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
3b31e9b0
ZY		 1256static const char *x1000_sfc_groups[] = { "sfc", };
1257static const char *x1000_ssi_groups[] = {
1258 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
1259 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
1260 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
1261 "ssi-gpc-a-20", "ssi-gpc-a-31",
1262 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
1263 "ssi-ce1-a-21", "ssi-ce1-a-30",
1264};
fe1ad5ee
ZY		 1265static const char *x1000_mmc0_groups[] = {
1266 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
1267};
1268static const char *x1000_mmc1_groups[] = {
b4a9372a 1269 "mmc1-1bit", "mmc1-4bit",
fe1ad5ee 1270};
b4a9372a
ZY		 1271static const char *x1000_emc_groups[] = {
1272 "emc-8bit-data", "emc-16bit-data",
1273 "emc-addr", "emc-rd-we", "emc-wait",
fe1ad5ee 1274};
b4a9372a
ZY		 1275static const char *x1000_cs1_groups[] = { "emc-cs1", };
1276static const char *x1000_cs2_groups[] = { "emc-cs2", };
fe1ad5ee
ZY		 1277static const char *x1000_i2c0_groups[] = { "i2c0-data", };
1278static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1279static const char *x1000_i2c2_groups[] = { "i2c2-data", };
f4b5c348
ZY		 1280static const char *x1000_i2s_groups[] = {
1281 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1282};
fe1ad5ee
ZY		 1283static const char *x1000_cim_groups[] = { "cim-data", };
1284static const char *x1000_lcd_groups[] = {
1285 "lcd-8bit", "lcd-16bit", "lcd-no-pins",
1286};
1287static const char *x1000_pwm0_groups[] = { "pwm0", };
1288static const char *x1000_pwm1_groups[] = { "pwm1", };
1289static const char *x1000_pwm2_groups[] = { "pwm2", };
1290static const char *x1000_pwm3_groups[] = { "pwm3", };
1291static const char *x1000_pwm4_groups[] = { "pwm4", };
1292static const char *x1000_mac_groups[] = { "mac", };
1293
1294static const struct function_desc x1000_functions[] = {
1295 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
1296 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
1297 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
3b31e9b0
ZY		 1298 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
1299 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
fe1ad5ee
ZY		 1300 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
1301 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
b4a9372a
ZY		 1302 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
1303 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
1304 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
fe1ad5ee
ZY		 1305 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
1306 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
1307 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
f4b5c348 1308 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
fe1ad5ee
ZY		 1309 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
1310 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
1311 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
1312 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
1313 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
1314 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
1315 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
1316 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
1317};
1318
1319static const struct ingenic_chip_info x1000_chip_info = {
1320 .num_chips = 4,
f742e5eb 1321 .reg_offset = 0x100,
baf15647 1322 .version = ID_X1000,
fe1ad5ee
ZY		 1323 .groups = x1000_groups,
1324 .num_groups = ARRAY_SIZE(x1000_groups),
1325 .functions = x1000_functions,
1326 .num_functions = ARRAY_SIZE(x1000_functions),
1327 .pull_ups = x1000_pull_ups,
1328 .pull_downs = x1000_pull_downs,
1329};
1330
5d21595b
ZY		 1331static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
1332static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1333static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
1334static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
b4a9372a 1335static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
5d21595b
ZY		 1336static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
1337static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
b4a9372a
ZY		 1338static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
1339static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
5d21595b
ZY		 1340static int x1500_i2c0_pins[] = { 0x38, 0x37, };
1341static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
1342static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
1343static int x1500_i2c2_pins[] = { 0x61, 0x60, };
f4b5c348
ZY		 1344static int x1500_i2s_data_tx_pins[] = { 0x24, };
1345static int x1500_i2s_data_rx_pins[] = { 0x23, };
1346static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
1347static int x1500_i2s_sysclk_pins[] = { 0x20, };
5d21595b
ZY		 1348static int x1500_cim_pins[] = {
1349 0x08, 0x09, 0x0a, 0x0b,
1350 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1351};
1352static int x1500_pwm_pwm0_pins[] = { 0x59, };
1353static int x1500_pwm_pwm1_pins[] = { 0x5a, };
1354static int x1500_pwm_pwm2_pins[] = { 0x5b, };
1355static int x1500_pwm_pwm3_pins[] = { 0x26, };
1356static int x1500_pwm_pwm4_pins[] = { 0x58, };
1357
5d21595b 1358static const struct group_desc x1500_groups[] = {
bb42b593
PC		 1359 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
1360 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
1361 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
1362 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
1363 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
1364 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
1365 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
1366 INGENIC_PIN_GROUP("sfc", x1000_sfc, 1),
1367 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
1368 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
1369 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
1370 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
1371 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
1372 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
1373 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
1374 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
1375 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
1376 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
1377 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
5d21595b 1378 { "lcd-no-pins", },
bb42b593
PC		 1379 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
1380 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
1381 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),
1382 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
1383 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),
5d21595b
ZY		 1384};
1385
1386static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1387static const char *x1500_uart1_groups[] = {
b4a9372a 1388 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
5d21595b
ZY		 1389};
1390static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
b4a9372a 1391static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
5d21595b
ZY		 1392static const char *x1500_i2c0_groups[] = { "i2c0-data", };
1393static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1394static const char *x1500_i2c2_groups[] = { "i2c2-data", };
f4b5c348
ZY		 1395static const char *x1500_i2s_groups[] = {
1396 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1397};
5d21595b
ZY		 1398static const char *x1500_cim_groups[] = { "cim-data", };
1399static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
1400static const char *x1500_pwm0_groups[] = { "pwm0", };
1401static const char *x1500_pwm1_groups[] = { "pwm1", };
1402static const char *x1500_pwm2_groups[] = { "pwm2", };
1403static const char *x1500_pwm3_groups[] = { "pwm3", };
1404static const char *x1500_pwm4_groups[] = { "pwm4", };
1405
1406static const struct function_desc x1500_functions[] = {
1407 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
1408 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
1409 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
3b31e9b0 1410 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
b4a9372a 1411 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
5d21595b
ZY		 1412 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
1413 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
1414 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
f4b5c348 1415 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
5d21595b
ZY		 1416 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
1417 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
1418 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
1419 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
1420 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
1421 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
1422 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
1423};
1424
1425static const struct ingenic_chip_info x1500_chip_info = {
1426 .num_chips = 4,
f742e5eb 1427 .reg_offset = 0x100,
baf15647 1428 .version = ID_X1500,
5d21595b
ZY		 1429 .groups = x1500_groups,
1430 .num_groups = ARRAY_SIZE(x1500_groups),
1431 .functions = x1500_functions,
1432 .num_functions = ARRAY_SIZE(x1500_functions),
1433 .pull_ups = x1000_pull_ups,
1434 .pull_downs = x1000_pull_downs,
1435};
1436
d7da2a1e
ZY		 1437static const u32 x1830_pull_ups[4] = {
1438 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1439};
1440
1441static const u32 x1830_pull_downs[4] = {
1442 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1443};
1444
1445static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
1446static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
1447static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
1448static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, };
1449static int x1830_ssi0_dt_pins[] = { 0x4c, };
1450static int x1830_ssi0_dr_pins[] = { 0x4b, };
1451static int x1830_ssi0_clk_pins[] = { 0x4f, };
1452static int x1830_ssi0_gpc_pins[] = { 0x4d, };
1453static int x1830_ssi0_ce0_pins[] = { 0x50, };
1454static int x1830_ssi0_ce1_pins[] = { 0x4e, };
1455static int x1830_ssi1_dt_c_pins[] = { 0x53, };
1456static int x1830_ssi1_dr_c_pins[] = { 0x54, };
1457static int x1830_ssi1_clk_c_pins[] = { 0x57, };
1458static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
1459static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
1460static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
1461static int x1830_ssi1_dt_d_pins[] = { 0x62, };
1462static int x1830_ssi1_dr_d_pins[] = { 0x63, };
1463static int x1830_ssi1_clk_d_pins[] = { 0x66, };
1464static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
1465static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
1466static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
1467static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
1468static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
1469static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
1470static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
1471static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
1472static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
1473static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
f4b5c348
ZY		 1474static int x1830_i2s_data_tx_pins[] = { 0x53, };
1475static int x1830_i2s_data_rx_pins[] = { 0x54, };
1476static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
1477static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
1478static int x1830_i2s_sysclk_pins[] = { 0x57, };
b2954743
ZY		 1479static int x1830_lcd_rgb_18bit_pins[] = {
1480 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
1481 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f,
1482 0x70, 0x71, 0x72, 0x73, 0x76, 0x77,
1483 0x78, 0x79, 0x7a, 0x7b,
1484};
1485static int x1830_lcd_slcd_8bit_pins[] = {
1486 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
1487 0x69, 0x72, 0x73, 0x7b, 0x7a,
1488};
1489static int x1830_lcd_slcd_16bit_pins[] = {
1490 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
1491};
d7da2a1e
ZY		 1492static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
1493static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
1494static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
1495static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
1496static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
1497static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
1498static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
1499static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
1500static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
1501static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
1502static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
1503static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
1504static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
1505static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
1506static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
1507static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
1508static int x1830_mac_pins[] = {
1509 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
1510};
1511
d7da2a1e 1512static const struct group_desc x1830_groups[] = {
bb42b593
PC		 1513 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
1514 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
1515 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
1516 INGENIC_PIN_GROUP("sfc", x1830_sfc, 1),
1517 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
1518 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
1519 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
1520 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
1521 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
1522 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
1523 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
1524 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
1525 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
1526 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
1527 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
1528 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
1529 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
1530 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
1531 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
1532 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
1533 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
1534 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
1535 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
1536 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
1537 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
1538 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
1539 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
1540 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
1541 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
1542 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
1543 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
1544 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
1545 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
1546 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
1547 INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit, 0),
1548 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
1549 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
b2954743 1550 { "lcd-no-pins", },
bb42b593
PC		 1551 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
1552 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
1553 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
1554 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
1555 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
1556 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
1557 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
1558 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
1559 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
1560 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
1561 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
1562 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
1563 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
1564 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
1565 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
1566 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
1567 INGENIC_PIN_GROUP("mac", x1830_mac, 0),
d7da2a1e
ZY		 1568};
1569
1570static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1571static const char *x1830_uart1_groups[] = { "uart1-data", };
1572static const char *x1830_sfc_groups[] = { "sfc", };
1573static const char *x1830_ssi0_groups[] = {
1574 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
1575};
1576static const char *x1830_ssi1_groups[] = {
1577 "ssi1-dt-c", "ssi1-dt-d",
1578 "ssi1-dr-c", "ssi1-dr-d",
1579 "ssi1-clk-c", "ssi1-clk-d",
1580 "ssi1-gpc-c", "ssi1-gpc-d",
1581 "ssi1-ce0-c", "ssi1-ce0-d",
1582 "ssi1-ce1-c", "ssi1-ce1-d",
1583};
1584static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
1585static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
1586static const char *x1830_i2c0_groups[] = { "i2c0-data", };
1587static const char *x1830_i2c1_groups[] = { "i2c1-data", };
1588static const char *x1830_i2c2_groups[] = { "i2c2-data", };
f4b5c348
ZY		 1589static const char *x1830_i2s_groups[] = {
1590 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1591};
b2954743
ZY		 1592static const char *x1830_lcd_groups[] = {
1593 "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins",
1594};
d7da2a1e
ZY		 1595static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
1596static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
1597static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
1598static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
1599static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
1600static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
1601static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
1602static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
1603static const char *x1830_mac_groups[] = { "mac", };
1604
1605static const struct function_desc x1830_functions[] = {
1606 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
1607 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
1608 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
1609 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
1610 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
1611 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
1612 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
1613 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
1614 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
1615 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
f4b5c348 1616 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
b2954743 1617 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
d7da2a1e
ZY		 1618 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
1619 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
1620 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
1621 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
1622 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1623 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1624 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1625 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1626 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
1627};
1628
1629static const struct ingenic_chip_info x1830_chip_info = {
1630 .num_chips = 4,
1631 .reg_offset = 0x1000,
baf15647 1632 .version = ID_X1830,
d7da2a1e
ZY		 1633 .groups = x1830_groups,
1634 .num_groups = ARRAY_SIZE(x1830_groups),
1635 .functions = x1830_functions,
1636 .num_functions = ARRAY_SIZE(x1830_functions),
1637 .pull_ups = x1830_pull_ups,
1638 .pull_downs = x1830_pull_downs,
1639};
1640
b71c1844 1641static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
e72394e2
PC		 1642{
1643 unsigned int val;
1644
1645 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
1646
1647 return (u32) val;
1648}
1649
b71c1844 1650static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
e72394e2
PC		 1651 u8 reg, u8 offset, bool set)
1652{
1653 if (set)
1654 reg = REG_SET(reg);
1655 else
1656 reg = REG_CLEAR(reg);
1657
1658 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
1659}
1660
fe1ad5ee
ZY		 1661static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
1662 u8 reg, u8 offset, bool set)
1663{
1664 if (set)
1665 reg = REG_SET(reg);
1666 else
1667 reg = REG_CLEAR(reg);
1668
d7da2a1e
ZY		 1669 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
1670 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
fe1ad5ee
ZY		 1671}
1672
1673static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
1674{
d7da2a1e
ZY		 1675 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
1676 jzgc->jzpc->info->reg_offset),
fe1ad5ee
ZY		 1677 jzgc->gc.base / PINS_PER_GPIO_CHIP);
1678}
1679
e72394e2
PC		 1680static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
1681 u8 offset)
1682{
b71c1844 1683 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
e72394e2
PC		 1684
1685 return !!(val & BIT(offset));
1686}
1687
1688static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
1689 u8 offset, int value)
1690{
9a85c09a 1691 if (jzgc->jzpc->info->version >= ID_JZ4770)
b4aa4876 1692 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
e72394e2 1693 else
b71c1844 1694 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
e72394e2
PC		 1695}
1696
1697static void irq_set_type(struct ingenic_gpio_chip *jzgc,
1698 u8 offset, unsigned int type)
1699{
1700 u8 reg1, reg2;
f831f93a 1701 bool val1, val2;
e72394e2
PC		 1702
1703 switch (type) {
1704 case IRQ_TYPE_EDGE_RISING:
f831f93a 1705 val1 = val2 = true;
e72394e2
PC		 1706 break;
1707 case IRQ_TYPE_EDGE_FALLING:
f831f93a
PC		 1708 val1 = false;
1709 val2 = true;
e72394e2
PC		 1710 break;
1711 case IRQ_TYPE_LEVEL_HIGH:
f831f93a
PC		 1712 val1 = true;
1713 val2 = false;
e72394e2
PC		 1714 break;
1715 case IRQ_TYPE_LEVEL_LOW:
1716 default:
f831f93a 1717 val1 = val2 = false;
e72394e2
PC		 1718 break;
1719 }
f831f93a 1720
9a85c09a 1721 if (jzgc->jzpc->info->version >= ID_JZ4770) {
b4aa4876
PC		 1722 reg1 = JZ4770_GPIO_PAT1;
1723 reg2 = JZ4770_GPIO_PAT0;
f831f93a
PC		 1724 } else {
1725 reg1 = JZ4740_GPIO_TRIG;
1726 reg2 = JZ4740_GPIO_DIR;
1727 }
1728
1729 if (jzgc->jzpc->info->version >= ID_X1000) {
1730 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
1731 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
1732 ingenic_gpio_shadow_set_bit_load(jzgc);
1733 } else {
1734 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
1735 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
1736 }
e72394e2
PC		 1737}
1738
1739static void ingenic_gpio_irq_mask(struct irq_data *irqd)
1740{
1741 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1742 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1743
b71c1844 1744 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
e72394e2
PC		 1745}
1746
1747static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
1748{
1749 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1750 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1751
b71c1844 1752 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
e72394e2
PC		 1753}
1754
1755static void ingenic_gpio_irq_enable(struct irq_data *irqd)
1756{
1757 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1758 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1759 int irq = irqd->hwirq;
1760
9a85c09a 1761 if (jzgc->jzpc->info->version >= ID_JZ4770)
b4aa4876 1762 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
e72394e2 1763 else
b71c1844 1764 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
e72394e2
PC		 1765
1766 ingenic_gpio_irq_unmask(irqd);
1767}
1768
1769static void ingenic_gpio_irq_disable(struct irq_data *irqd)
1770{
1771 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1772 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1773 int irq = irqd->hwirq;
1774
1775 ingenic_gpio_irq_mask(irqd);
1776
9a85c09a 1777 if (jzgc->jzpc->info->version >= ID_JZ4770)
b4aa4876 1778 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
e72394e2 1779 else
b71c1844 1780 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
e72394e2
PC		 1781}
1782
1783static void ingenic_gpio_irq_ack(struct irq_data *irqd)
1784{
1785 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1786 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1787 int irq = irqd->hwirq;
1788 bool high;
1789
1790 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
1791 /*
1792 * Switch to an interrupt for the opposite edge to the one that
1793 * triggered the interrupt being ACKed.
1794 */
1795 high = ingenic_gpio_get_value(jzgc, irq);
1796 if (high)
1c95348b 1797 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
e72394e2 1798 else
1c95348b 1799 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
e72394e2
PC		 1800 }
1801
9a85c09a 1802 if (jzgc->jzpc->info->version >= ID_JZ4770)
b4aa4876 1803 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
e72394e2 1804 else
b71c1844 1805 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
e72394e2
PC		 1806}
1807
1808static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
1809{
1810 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1811 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1812
1813 switch (type) {
1814 case IRQ_TYPE_EDGE_BOTH:
1815 case IRQ_TYPE_EDGE_RISING:
1816 case IRQ_TYPE_EDGE_FALLING:
1817 irq_set_handler_locked(irqd, handle_edge_irq);
1818 break;
1819 case IRQ_TYPE_LEVEL_HIGH:
1820 case IRQ_TYPE_LEVEL_LOW:
1821 irq_set_handler_locked(irqd, handle_level_irq);
1822 break;
1823 default:
1824 irq_set_handler_locked(irqd, handle_bad_irq);
1825 }
1826
1827 if (type == IRQ_TYPE_EDGE_BOTH) {
1828 /*
1829 * The hardware does not support interrupts on both edges. The
1830 * best we can do is to set up a single-edge interrupt and then
1831 * switch to the opposing edge when ACKing the interrupt.
1832 */
1833 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
1834
1c95348b 1835 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
e72394e2
PC		 1836 }
1837
1838 irq_set_type(jzgc, irqd->hwirq, type);
1839 return 0;
1840}
1841
1842static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
1843{
1844 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1845 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1846
1847 return irq_set_irq_wake(jzgc->irq, on);
1848}
1849
1850static void ingenic_gpio_irq_handler(struct irq_desc *desc)
1851{
1852 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1853 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1854 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
1855 unsigned long flag, i;
1856
1857 chained_irq_enter(irq_chip, desc);
1858
9a85c09a 1859 if (jzgc->jzpc->info->version >= ID_JZ4770)
b4aa4876 1860 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
e72394e2 1861 else
b71c1844 1862 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
e72394e2
PC		 1863
1864 for_each_set_bit(i, &flag, 32)
1865 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
1866 chained_irq_exit(irq_chip, desc);
1867}
1868
1869static void ingenic_gpio_set(struct gpio_chip *gc,
1870 unsigned int offset, int value)
1871{
1872 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1873
1874 ingenic_gpio_set_value(jzgc, offset, value);
1875}
1876
1877static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
1878{
1879 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1880
1881 return (int) ingenic_gpio_get_value(jzgc, offset);
1882}
1883
1884static int ingenic_gpio_direction_input(struct gpio_chip *gc,
1885 unsigned int offset)
1886{
1887 return pinctrl_gpio_direction_input(gc->base + offset);
1888}
1889
1890static int ingenic_gpio_direction_output(struct gpio_chip *gc,
1891 unsigned int offset, int value)
1892{
1893 ingenic_gpio_set(gc, offset, value);
1894 return pinctrl_gpio_direction_output(gc->base + offset);
1895}
1896
b5c23aa4
PC		 1897static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
1898 unsigned int pin, u8 reg, bool set)
1899{
1900 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1901 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1902
f742e5eb 1903 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
b5c23aa4
PC		 1904 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1905}
1906
fe1ad5ee
ZY		 1907static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
1908 unsigned int pin, u8 reg, bool set)
1909{
1910 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1911
f742e5eb 1912 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
fe1ad5ee
ZY		 1913 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1914}
1915
1916static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
1917 unsigned int pin)
1918{
d7da2a1e
ZY		 1919 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
1920 pin / PINS_PER_GPIO_CHIP);
fe1ad5ee
ZY		 1921}
1922
b5c23aa4
PC		 1923static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
1924 unsigned int pin, u8 reg)
1925{
1926 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1927 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1928 unsigned int val;
1929
f742e5eb 1930 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
b5c23aa4
PC		 1931
1932 return val & BIT(idx);
1933}
1934
ebd66514
PC		 1935static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1936{
1937 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1938 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
1939 unsigned int pin = gc->base + offset;
1940
9a85c09a 1941 if (jzpc->info->version >= ID_JZ4770) {
b4aa4876
PC		 1942 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||
1943 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))
3c827873
MV		 1944 return GPIO_LINE_DIRECTION_IN;
1945 return GPIO_LINE_DIRECTION_OUT;
1946 }
ebd66514
PC		 1947
1948 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
3c827873
MV		 1949 return GPIO_LINE_DIRECTION_IN;
1950
1951 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
1952 return GPIO_LINE_DIRECTION_OUT;
ebd66514 1953
3c827873 1954 return GPIO_LINE_DIRECTION_IN;
ebd66514
PC		 1955}
1956
5bf7b849 1957static const struct pinctrl_ops ingenic_pctlops = {
b5c23aa4
PC		 1958 .get_groups_count = pinctrl_generic_get_group_count,
1959 .get_group_name = pinctrl_generic_get_group_name,
1960 .get_group_pins = pinctrl_generic_get_group_pins,
1961 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1962 .dt_free_map = pinconf_generic_dt_free_map,
1963};
1964
9a0f1341
PC		 1965static int ingenic_gpio_irq_request(struct irq_data *data)
1966{
1967 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
1968 int ret;
1969
1970 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq);
1971 if (ret)
1972 return ret;
1973
1974 return gpiochip_reqres_irq(gpio_chip, data->hwirq);
1975}
1976
1977static void ingenic_gpio_irq_release(struct irq_data *data)
1978{
1979 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
1980
1981 return gpiochip_relres_irq(gpio_chip, data->hwirq);
1982}
1983
b5c23aa4
PC		 1984static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
1985 int pin, int func)
1986{
1987 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1988 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1989
1990 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
1991 'A' + offt, idx, func);
1992
baf15647 1993 if (jzpc->info->version >= ID_X1000) {
b4aa4876 1994 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
fe1ad5ee 1995 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
b4aa4876
PC		 1996 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
1997 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
fe1ad5ee 1998 ingenic_shadow_config_pin_load(jzpc, pin);
9a85c09a 1999 } else if (jzpc->info->version >= ID_JZ4770) {
b4aa4876 2000 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
e72394e2 2001 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
b4aa4876
PC		 2002 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
2003 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
b5c23aa4
PC		 2004 } else {
2005 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
2006 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
9a85c09a 2007 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
b5c23aa4
PC		 2008 }
2009
2010 return 0;
2011}
2012
2013static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
2014 unsigned int selector, unsigned int group)
2015{
2016 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2017 struct function_desc *func;
2018 struct group_desc *grp;
2019 unsigned int i;
bb42b593
PC		 2020 uintptr_t mode;
2021 u8 *pin_modes;
b5c23aa4
PC		 2022
2023 func = pinmux_generic_get_function(pctldev, selector);
2024 if (!func)
2025 return -EINVAL;
2026
2027 grp = pinctrl_generic_get_group(pctldev, group);
2028 if (!grp)
2029 return -EINVAL;
2030
2031 dev_dbg(pctldev->dev, "enable function %s group %s\n",
2032 func->name, grp->name);
2033
bb42b593
PC		 2034 mode = (uintptr_t)grp->data;
2035 if (mode <= 3) {
2036 for (i = 0; i < grp->num_pins; i++)
2037 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode);
2038 } else {
2039 pin_modes = grp->data;
b5c23aa4 2040
bb42b593
PC		 2041 for (i = 0; i < grp->num_pins; i++)
2042 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
b5c23aa4
PC		 2043 }
2044
2045 return 0;
2046}
2047
2048static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
2049 struct pinctrl_gpio_range *range,
2050 unsigned int pin, bool input)
2051{
2052 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2053 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2054 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2055
2056 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
2057 'A' + offt, idx, input ? "in" : "out");
2058
baf15647 2059 if (jzpc->info->version >= ID_X1000) {
b4aa4876 2060 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
fe1ad5ee 2061 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
b4aa4876 2062 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
fe1ad5ee 2063 ingenic_shadow_config_pin_load(jzpc, pin);
9a85c09a 2064 } else if (jzpc->info->version >= ID_JZ4770) {
b4aa4876 2065 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
e72394e2 2066 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
b4aa4876 2067 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
b5c23aa4
PC		 2068 } else {
2069 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
0084a786 2070 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
b5c23aa4
PC		 2071 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
2072 }
2073
2074 return 0;
2075}
2076
5bf7b849 2077static const struct pinmux_ops ingenic_pmxops = {
b5c23aa4
PC		 2078 .get_functions_count = pinmux_generic_get_function_count,
2079 .get_function_name = pinmux_generic_get_function_name,
2080 .get_function_groups = pinmux_generic_get_function_groups,
2081 .set_mux = ingenic_pinmux_set_mux,
2082 .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
2083};
2084
2085static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
2086 unsigned int pin, unsigned long *config)
2087{
2088 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2089 enum pin_config_param param = pinconf_to_config_param(*config);
2090 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2091 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2092 bool pull;
2093
9a85c09a 2094 if (jzpc->info->version >= ID_JZ4770)
b4aa4876 2095 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
b5c23aa4
PC		 2096 else
2097 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
2098
2099 switch (param) {
2100 case PIN_CONFIG_BIAS_DISABLE:
2101 if (pull)
2102 return -EINVAL;
2103 break;
2104
2105 case PIN_CONFIG_BIAS_PULL_UP:
2106 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
2107 return -EINVAL;
2108 break;
2109
2110 case PIN_CONFIG_BIAS_PULL_DOWN:
2111 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
2112 return -EINVAL;
2113 break;
2114
2115 default:
2116 return -ENOTSUPP;
2117 }
2118
2119 *config = pinconf_to_config_packed(param, 1);
2120 return 0;
2121}
2122
2123static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
d7da2a1e 2124 unsigned int pin, unsigned int bias)
b5c23aa4 2125{
baf15647 2126 if (jzpc->info->version >= ID_X1830) {
d7da2a1e
ZY		 2127 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2128 unsigned int half = PINS_PER_GPIO_CHIP / 2;
2129 unsigned int idxh = pin % half * 2;
2130 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2131
2132 if (idx < half) {
2133 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2134 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
2135 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2136 REG_SET(X1830_GPIO_PEL), bias << idxh);
2137 } else {
2138 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2139 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
2140 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2141 REG_SET(X1830_GPIO_PEH), bias << idxh);
2142 }
2143
9a85c09a 2144 } else if (jzpc->info->version >= ID_JZ4770) {
b4aa4876 2145 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
d7da2a1e
ZY		 2146 } else {
2147 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
2148 }
b5c23aa4
PC		 2149}
2150
7009d046
PC		 2151static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
2152 unsigned int pin, bool high)
2153{
9a85c09a 2154 if (jzpc->info->version >= ID_JZ4770)
b4aa4876 2155 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);
7009d046
PC		 2156 else
2157 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
2158}
2159
b5c23aa4
PC		 2160static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2161 unsigned long *configs, unsigned int num_configs)
2162{
2163 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2164 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2165 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
7009d046
PC		 2166 unsigned int cfg, arg;
2167 int ret;
b5c23aa4
PC		 2168
2169 for (cfg = 0; cfg < num_configs; cfg++) {
2170 switch (pinconf_to_config_param(configs[cfg])) {
2171 case PIN_CONFIG_BIAS_DISABLE:
2172 case PIN_CONFIG_BIAS_PULL_UP:
2173 case PIN_CONFIG_BIAS_PULL_DOWN:
7009d046 2174 case PIN_CONFIG_OUTPUT:
b5c23aa4
PC		 2175 continue;
2176 default:
2177 return -ENOTSUPP;
2178 }
2179 }
2180
2181 for (cfg = 0; cfg < num_configs; cfg++) {
7009d046
PC		 2182 arg = pinconf_to_config_argument(configs[cfg]);
2183
b5c23aa4
PC		 2184 switch (pinconf_to_config_param(configs[cfg])) {
2185 case PIN_CONFIG_BIAS_DISABLE:
2186 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
2187 'A' + offt, idx);
d7da2a1e 2188 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
b5c23aa4
PC		 2189 break;
2190
2191 case PIN_CONFIG_BIAS_PULL_UP:
2192 if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
2193 return -EINVAL;
2194 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
2195 'A' + offt, idx);
d7da2a1e 2196 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
b5c23aa4
PC		 2197 break;
2198
2199 case PIN_CONFIG_BIAS_PULL_DOWN:
2200 if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
2201 return -EINVAL;
2202 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
2203 'A' + offt, idx);
d7da2a1e 2204 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
b5c23aa4
PC		 2205 break;
2206
7009d046
PC		 2207 case PIN_CONFIG_OUTPUT:
2208 ret = pinctrl_gpio_direction_output(pin);
2209 if (ret)
2210 return ret;
2211
2212 ingenic_set_output_level(jzpc, pin, arg);
2213 break;
2214
b5c23aa4 2215 default:
d6d43a92
JP		 2216 /* unreachable */
2217 break;
b5c23aa4
PC		 2218 }
2219 }
2220
2221 return 0;
2222}
2223
2224static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
2225 unsigned int group, unsigned long *config)
2226{
2227 const unsigned int *pins;
2228 unsigned int i, npins, old = 0;
2229 int ret;
2230
2231 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2232 if (ret)
2233 return ret;
2234
2235 for (i = 0; i < npins; i++) {
2236 if (ingenic_pinconf_get(pctldev, pins[i], config))
2237 return -ENOTSUPP;
2238
2239 /* configs do not match between two pins */
2240 if (i && (old != *config))
2241 return -ENOTSUPP;
2242
2243 old = *config;
2244 }
2245
2246 return 0;
2247}
2248
2249static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
2250 unsigned int group, unsigned long *configs,
2251 unsigned int num_configs)
2252{
2253 const unsigned int *pins;
2254 unsigned int i, npins;
2255 int ret;
2256
2257 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2258 if (ret)
2259 return ret;
2260
2261 for (i = 0; i < npins; i++) {
2262 ret = ingenic_pinconf_set(pctldev,
2263 pins[i], configs, num_configs);
2264 if (ret)
2265 return ret;
2266 }
2267
2268 return 0;
2269}
2270
5bf7b849 2271static const struct pinconf_ops ingenic_confops = {
b5c23aa4
PC		 2272 .is_generic = true,
2273 .pin_config_get = ingenic_pinconf_get,
2274 .pin_config_set = ingenic_pinconf_set,
2275 .pin_config_group_get = ingenic_pinconf_group_get,
2276 .pin_config_group_set = ingenic_pinconf_group_set,
2277};
2278
2279static const struct regmap_config ingenic_pinctrl_regmap_config = {
2280 .reg_bits = 32,
2281 .val_bits = 32,
2282 .reg_stride = 4,
2283};
2284
e72394e2
PC		 2285static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
2286 { .compatible = "ingenic,jz4740-gpio", },
b5fc06a1 2287 { .compatible = "ingenic,jz4725b-gpio", },
0257595a 2288 { .compatible = "ingenic,jz4760-gpio", },
e72394e2
PC		 2289 { .compatible = "ingenic,jz4770-gpio", },
2290 { .compatible = "ingenic,jz4780-gpio", },
fe1ad5ee 2291 { .compatible = "ingenic,x1000-gpio", },
d7da2a1e 2292 { .compatible = "ingenic,x1830-gpio", },
e72394e2
PC		 2293 {},
2294};
2295
2296static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
2297 struct device_node *node)
2298{
2299 struct ingenic_gpio_chip *jzgc;
2300 struct device *dev = jzpc->dev;
142b8767 2301 struct gpio_irq_chip *girq;
e72394e2
PC		 2302 unsigned int bank;
2303 int err;
2304
2305 err = of_property_read_u32(node, "reg", &bank);
2306 if (err) {
2307 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
2308 return err;
2309 }
2310
2311 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
2312 if (!jzgc)
2313 return -ENOMEM;
2314
2315 jzgc->jzpc = jzpc;
f742e5eb 2316 jzgc->reg_base = bank * jzpc->info->reg_offset;
e72394e2
PC		 2317
2318 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
2319 if (!jzgc->gc.label)
2320 return -ENOMEM;
2321
2322 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
2323 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
2324 * <linux/gpio/consumer.h> INSTEAD.
2325 */
2326 jzgc->gc.base = bank * 32;
2327
2328 jzgc->gc.ngpio = 32;
2329 jzgc->gc.parent = dev;
2330 jzgc->gc.of_node = node;
2331 jzgc->gc.owner = THIS_MODULE;
2332
2333 jzgc->gc.set = ingenic_gpio_set;
2334 jzgc->gc.get = ingenic_gpio_get;
2335 jzgc->gc.direction_input = ingenic_gpio_direction_input;
2336 jzgc->gc.direction_output = ingenic_gpio_direction_output;
ebd66514 2337 jzgc->gc.get_direction = ingenic_gpio_get_direction;
d6471d6e
TR		 2338 jzgc->gc.request = gpiochip_generic_request;
2339 jzgc->gc.free = gpiochip_generic_free;
e72394e2 2340
e72394e2
PC		 2341 jzgc->irq = irq_of_parse_and_map(node, 0);
2342 if (!jzgc->irq)
2343 return -EINVAL;
2344
2345 jzgc->irq_chip.name = jzgc->gc.label;
2346 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
2347 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
2348 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
2349 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
2350 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
2351 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
2352 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
9a0f1341
PC		 2353 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request;
2354 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release;
e72394e2
PC		 2355 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
2356
142b8767
LW		 2357 girq = &jzgc->gc.irq;
2358 girq->chip = &jzgc->irq_chip;
2359 girq->parent_handler = ingenic_gpio_irq_handler;
2360 girq->num_parents = 1;
2361 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
2362 GFP_KERNEL);
2363 if (!girq->parents)
2364 return -ENOMEM;
2365 girq->parents[0] = jzgc->irq;
2366 girq->default_type = IRQ_TYPE_NONE;
2367 girq->handler = handle_level_irq;
2368
2369 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
e72394e2
PC		 2370 if (err)
2371 return err;
2372
e72394e2
PC		 2373 return 0;
2374}
2375
4717b11f 2376static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
b5c23aa4
PC		 2377{
2378 struct device *dev = &pdev->dev;
2379 struct ingenic_pinctrl *jzpc;
2380 struct pinctrl_desc *pctl_desc;
2381 void __iomem *base;
b5c23aa4 2382 const struct ingenic_chip_info *chip_info;
e72394e2 2383 struct device_node *node;
b5c23aa4
PC		 2384 unsigned int i;
2385 int err;
2386
2387 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
2388 if (!jzpc)
2389 return -ENOMEM;
2390
94f7a2cb 2391 base = devm_platform_ioremap_resource(pdev, 0);
119fcf47 2392 if (IS_ERR(base))
b5c23aa4 2393 return PTR_ERR(base);
b5c23aa4
PC		 2394
2395 jzpc->map = devm_regmap_init_mmio(dev, base,
2396 &ingenic_pinctrl_regmap_config);
2397 if (IS_ERR(jzpc->map)) {
2398 dev_err(dev, "Failed to create regmap\n");
2399 return PTR_ERR(jzpc->map);
2400 }
2401
2402 jzpc->dev = dev;
baf15647 2403 jzpc->info = chip_info = of_device_get_match_data(dev);
b5c23aa4
PC		 2404
2405 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
2406 if (!pctl_desc)
2407 return -ENOMEM;
2408
2409 /* fill in pinctrl_desc structure */
2410 pctl_desc->name = dev_name(dev);
2411 pctl_desc->owner = THIS_MODULE;
2412 pctl_desc->pctlops = &ingenic_pctlops;
2413 pctl_desc->pmxops = &ingenic_pmxops;
2414 pctl_desc->confops = &ingenic_confops;
2415 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
a86854d0
KC		 2416 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
2417 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
b5c23aa4
PC		 2418 if (!jzpc->pdesc)
2419 return -ENOMEM;
2420
2421 for (i = 0; i < pctl_desc->npins; i++) {
2422 jzpc->pdesc[i].number = i;
2423 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
2424 'A' + (i / PINS_PER_GPIO_CHIP),
2425 i % PINS_PER_GPIO_CHIP);
2426 }
2427
2428 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
e7f4c4bf 2429 if (IS_ERR(jzpc->pctl)) {
b5c23aa4 2430 dev_err(dev, "Failed to register pinctrl\n");
e7f4c4bf 2431 return PTR_ERR(jzpc->pctl);
b5c23aa4
PC		 2432 }
2433
2434 for (i = 0; i < chip_info->num_groups; i++) {
2435 const struct group_desc *group = &chip_info->groups[i];
2436
2437 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
2438 group->pins, group->num_pins, group->data);
823dd71f 2439 if (err < 0) {
b5c23aa4
PC		 2440 dev_err(dev, "Failed to register group %s\n",
2441 group->name);
2442 return err;
2443 }
2444 }
2445
2446 for (i = 0; i < chip_info->num_functions; i++) {
2447 const struct function_desc *func = &chip_info->functions[i];
2448
2449 err = pinmux_generic_add_function(jzpc->pctl, func->name,
2450 func->group_names, func->num_group_names,
2451 func->data);
823dd71f 2452 if (err < 0) {
b5c23aa4
PC		 2453 dev_err(dev, "Failed to register function %s\n",
2454 func->name);
2455 return err;
2456 }
2457 }
2458
2459 dev_set_drvdata(dev, jzpc->map);
2460
e72394e2
PC		 2461 for_each_child_of_node(dev->of_node, node) {
2462 if (of_match_node(ingenic_gpio_of_match, node)) {
2463 err = ingenic_gpio_probe(jzpc, node);
2464 if (err)
2465 return err;
b5c23aa4
PC		 2466 }
2467 }
2468
2469 return 0;
2470}
2471
baf15647
PC		 2472static const struct of_device_id ingenic_pinctrl_of_match[] = {
2473 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info },
2474 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info },
2475 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info },
5ffdbb7e 2476 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info },
baf15647
PC		 2477 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info },
2478 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info },
2479 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info },
5ffdbb7e 2480 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info },
baf15647
PC		 2481 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info },
2482 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info },
2483 {},
2484};
2485
b5c23aa4
PC		 2486static struct platform_driver ingenic_pinctrl_driver = {
2487 .driver = {
2488 .name = "pinctrl-ingenic",
5ec008bf 2489 .of_match_table = ingenic_pinctrl_of_match,
b5c23aa4 2490 },
b5c23aa4
PC		 2491};
2492
2493static int __init ingenic_pinctrl_drv_register(void)
2494{
4717b11f
PC		 2495 return platform_driver_probe(&ingenic_pinctrl_driver,
2496 ingenic_pinctrl_probe);
b5c23aa4 2497}
556a36a7 2498subsys_initcall(ingenic_pinctrl_drv_register);
Linux 6.x block layer and io_uring tree(s)