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Merge tag 'v6.4/kernel.user_worker' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / pinctrl / pinctrl-ingenic.c
CommitLineData
af873fce 1// SPDX-License-Identifier: GPL-2.0-only
b5c23aa4
PC		 2/*
3 * Ingenic SoCs pinctrl driver
4 *
5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
a0bb89e8 6 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
424f3969 7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
b5c23aa4
PC		 8 */
9
10#include <linux/compiler.h>
28d6eeb4 11#include <linux/gpio/driver.h>
b5c23aa4
PC		 12#include <linux/interrupt.h>
13#include <linux/io.h>
0ab1438b 14#include <linux/kernel.h>
8c943137
AS		 15#include <linux/mod_devicetable.h>
16#include <linux/of.h>
b5c23aa4 17#include <linux/platform_device.h>
8c943137 18#include <linux/property.h>
b5c23aa4 19#include <linux/regmap.h>
71f5e7b3 20#include <linux/seq_file.h>
b5c23aa4
PC		 21#include <linux/slab.h>
22
9b69b7d7
AS		 23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/pinconf-generic.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28
b5c23aa4
PC		 29#include "core.h"
30#include "pinconf.h"
31#include "pinmux.h"
32
863becff
ZY		 33#define GPIO_PIN 0x00
34#define GPIO_MSK 0x20
e72394e2 35
424f3969
ZY		 36#define JZ4730_GPIO_DATA 0x00
37#define JZ4730_GPIO_GPDIR 0x04
38#define JZ4730_GPIO_GPPUR 0x0c
39#define JZ4730_GPIO_GPALR 0x10
40#define JZ4730_GPIO_GPAUR 0x14
41#define JZ4730_GPIO_GPIDLR 0x18
42#define JZ4730_GPIO_GPIDUR 0x1c
43#define JZ4730_GPIO_GPIER 0x20
44#define JZ4730_GPIO_GPIMR 0x24
45#define JZ4730_GPIO_GPFR 0x28
46
863becff
ZY		 47#define JZ4740_GPIO_DATA 0x10
48#define JZ4740_GPIO_PULL_DIS 0x30
49#define JZ4740_GPIO_FUNC 0x40
50#define JZ4740_GPIO_SELECT 0x50
51#define JZ4740_GPIO_DIR 0x60
52#define JZ4740_GPIO_TRIG 0x70
53#define JZ4740_GPIO_FLAG 0x80
b5c23aa4 54
863becff
ZY		 55#define JZ4770_GPIO_INT 0x10
56#define JZ4770_GPIO_PAT1 0x30
57#define JZ4770_GPIO_PAT0 0x40
58#define JZ4770_GPIO_FLAG 0x50
59#define JZ4770_GPIO_PEN 0x70
b5c23aa4 60
863becff
ZY		 61#define X1830_GPIO_PEL 0x110
62#define X1830_GPIO_PEH 0x120
943e0da1
ZY		 63#define X1830_GPIO_SR 0x150
64#define X1830_GPIO_SMT 0x160
65
66#define X2000_GPIO_EDG 0x70
67#define X2000_GPIO_PEPU 0x80
68#define X2000_GPIO_PEPD 0x90
69#define X2000_GPIO_SR 0xd0
70#define X2000_GPIO_SMT 0xe0
fe1ad5ee 71
863becff
ZY		 72#define REG_SET(x) ((x) + 0x4)
73#define REG_CLEAR(x) ((x) + 0x8)
b5c23aa4 74
863becff
ZY		 75#define REG_PZ_BASE(x) ((x) * 7)
76#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
d7da2a1e 77
863becff
ZY		 78#define GPIO_PULL_DIS 0
79#define GPIO_PULL_UP 1
80#define GPIO_PULL_DOWN 2
d7da2a1e 81
863becff 82#define PINS_PER_GPIO_CHIP 32
424f3969 83#define JZ4730_PINS_PER_PAIRED_REG 16
863becff
ZY		 84
85#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \
86 { \
87 name, \
88 id##_pins, \
89 ARRAY_SIZE(id##_pins), \
90 funcs, \
91 }
92
93#define INGENIC_PIN_GROUP(name, id, func) \
94 INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
b5c23aa4
PC		 95
96enum jz_version {
424f3969 97 ID_JZ4730,
b5c23aa4 98 ID_JZ4740,
f2a96765 99 ID_JZ4725B,
215c81a3 100 ID_JZ4750,
b582b5a4 101 ID_JZ4755,
0257595a 102 ID_JZ4760,
b5c23aa4 103 ID_JZ4770,
0c990740 104 ID_JZ4775,
b5c23aa4 105 ID_JZ4780,
fe1ad5ee 106 ID_X1000,
5d21595b 107 ID_X1500,
d7da2a1e 108 ID_X1830,
943e0da1 109 ID_X2000,
2a18211b 110 ID_X2100,
b5c23aa4
PC		 111};
112
113struct ingenic_chip_info {
114 unsigned int num_chips;
f742e5eb 115 unsigned int reg_offset;
baf15647 116 enum jz_version version;
b5c23aa4
PC		 117
118 const struct group_desc *groups;
119 unsigned int num_groups;
120
121 const struct function_desc *functions;
122 unsigned int num_functions;
123
124 const u32 *pull_ups, *pull_downs;
9279c00f
AM		 125
126 const struct regmap_access_table *access_table;
b5c23aa4
PC		 127};
128
129struct ingenic_pinctrl {
130 struct device *dev;
131 struct regmap *map;
132 struct pinctrl_dev *pctl;
133 struct pinctrl_pin_desc *pdesc;
b5c23aa4
PC		 134
135 const struct ingenic_chip_info *info;
136};
137
e72394e2
PC		 138struct ingenic_gpio_chip {
139 struct ingenic_pinctrl *jzpc;
140 struct gpio_chip gc;
e72394e2
PC		 141 unsigned int irq, reg_base;
142};
143
8d2d607c
PC		 144static const unsigned long enabled_socs =
145 IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 |
146 IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 |
147 IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B |
148 IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 |
149 IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 |
150 IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 |
151 IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 |
152 IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 |
153 IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 |
154 IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 |
155 IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 |
156 IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 |
157 IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 |
158 IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100;
159
160static bool
161is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version)
162{
163 return (enabled_socs >> version) &&
164 (!(enabled_socs & GENMASK(version - 1, 0))
165 || jzpc->info->version >= version);
166}
167
424f3969
ZY		 168static const u32 jz4730_pull_ups[4] = {
169 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff,
170};
171
172static const u32 jz4730_pull_downs[4] = {
173 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000,
174};
175
176static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, };
177static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, };
178static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, };
179static int jz4730_uart1_data_pins[] = { 0x18, 0x19, };
180static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, };
181static int jz4730_uart3_data_pins[] = { 0x10, 0x15, };
182static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, };
183static int jz4730_lcd_8bit_pins[] = {
184 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
185 0x3a, 0x39, 0x38,
186};
187static int jz4730_lcd_16bit_pins[] = {
188 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
189};
190static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, };
191static int jz4730_lcd_generic_pins[] = { 0x3b, };
192static int jz4730_nand_cs1_pins[] = { 0x53, };
193static int jz4730_nand_cs2_pins[] = { 0x54, };
194static int jz4730_nand_cs3_pins[] = { 0x55, };
195static int jz4730_nand_cs4_pins[] = { 0x56, };
196static int jz4730_nand_cs5_pins[] = { 0x57, };
197static int jz4730_pwm_pwm0_pins[] = { 0x5e, };
198static int jz4730_pwm_pwm1_pins[] = { 0x5f, };
199
200static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, };
201
202static const struct group_desc jz4730_groups[] = {
203 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
204 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
205 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
206 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
207 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
208 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
209 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
210 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
211 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
212 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
213 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
214 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
215 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
216 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
217 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
218 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
219 INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1),
220 INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1),
221};
222
223static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
224static const char *jz4730_uart0_groups[] = { "uart0-data", };
225static const char *jz4730_uart1_groups[] = { "uart1-data", };
226static const char *jz4730_uart2_groups[] = { "uart2-data", };
227static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
228static const char *jz4730_lcd_groups[] = {
229 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
230};
231static const char *jz4730_nand_groups[] = {
232 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
233};
234static const char *jz4730_pwm0_groups[] = { "pwm0", };
235static const char *jz4730_pwm1_groups[] = { "pwm1", };
236
237static const struct function_desc jz4730_functions[] = {
238 { "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), },
239 { "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), },
240 { "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), },
241 { "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), },
242 { "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), },
243 { "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), },
244 { "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), },
245 { "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), },
246 { "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), },
247};
248
249static const struct ingenic_chip_info jz4730_chip_info = {
250 .num_chips = 4,
251 .reg_offset = 0x30,
252 .version = ID_JZ4730,
253 .groups = jz4730_groups,
254 .num_groups = ARRAY_SIZE(jz4730_groups),
255 .functions = jz4730_functions,
256 .num_functions = ARRAY_SIZE(jz4730_functions),
257 .pull_ups = jz4730_pull_ups,
258 .pull_downs = jz4730_pull_downs,
259};
260
b5c23aa4
PC		 261static const u32 jz4740_pull_ups[4] = {
262 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
263};
264
265static const u32 jz4740_pull_downs[4] = {
266 0x00000000, 0x00000000, 0x00000000, 0x00000000,
267};
268
269static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
270static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
271static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
272static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
273static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
274static int jz4740_lcd_8bit_pins[] = {
5e6332a7
ZY		 275 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
276 0x52, 0x53, 0x54,
b5c23aa4
PC		 277};
278static int jz4740_lcd_16bit_pins[] = {
5e6332a7 279 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
b5c23aa4
PC		 280};
281static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
5e6332a7
ZY		 282static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, };
283static int jz4740_lcd_generic_pins[] = { 0x55, };
b5c23aa4
PC		 284static int jz4740_nand_cs1_pins[] = { 0x39, };
285static int jz4740_nand_cs2_pins[] = { 0x3a, };
286static int jz4740_nand_cs3_pins[] = { 0x3b, };
287static int jz4740_nand_cs4_pins[] = { 0x3c, };
bcad94d7 288static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
b5c23aa4
PC		 289static int jz4740_pwm_pwm0_pins[] = { 0x77, };
290static int jz4740_pwm_pwm1_pins[] = { 0x78, };
291static int jz4740_pwm_pwm2_pins[] = { 0x79, };
292static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
293static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
294static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
295static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
296static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
297
b5c23aa4 298static const struct group_desc jz4740_groups[] = {
bb42b593
PC		 299 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
300 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
301 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
302 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
303 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
304 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
305 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
306 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
5e6332a7
ZY		 307 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
308 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
bb42b593
PC		 309 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
310 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
311 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
312 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
313 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
314 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),
315 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),
316 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),
317 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),
318 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),
319 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),
320 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),
321 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),
b5c23aa4
PC		 322};
323
324static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
325static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
326static const char *jz4740_uart1_groups[] = { "uart1-data", };
327static const char *jz4740_lcd_groups[] = {
5e6332a7 328 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
b5c23aa4
PC		 329};
330static const char *jz4740_nand_groups[] = {
bcad94d7 331 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
b5c23aa4
PC		 332};
333static const char *jz4740_pwm0_groups[] = { "pwm0", };
334static const char *jz4740_pwm1_groups[] = { "pwm1", };
335static const char *jz4740_pwm2_groups[] = { "pwm2", };
336static const char *jz4740_pwm3_groups[] = { "pwm3", };
337static const char *jz4740_pwm4_groups[] = { "pwm4", };
338static const char *jz4740_pwm5_groups[] = { "pwm5", };
339static const char *jz4740_pwm6_groups[] = { "pwm6", };
340static const char *jz4740_pwm7_groups[] = { "pwm7", };
341
342static const struct function_desc jz4740_functions[] = {
343 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
344 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
345 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
346 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
347 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
348 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
349 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
350 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
351 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
352 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
353 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
354 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
355 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
356};
357
358static const struct ingenic_chip_info jz4740_chip_info = {
359 .num_chips = 4,
f742e5eb 360 .reg_offset = 0x100,
baf15647 361 .version = ID_JZ4740,
b5c23aa4
PC		 362 .groups = jz4740_groups,
363 .num_groups = ARRAY_SIZE(jz4740_groups),
364 .functions = jz4740_functions,
365 .num_functions = ARRAY_SIZE(jz4740_functions),
366 .pull_ups = jz4740_pull_ups,
367 .pull_downs = jz4740_pull_downs,
368};
369
f2a96765
PC		 370static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
371static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
372static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
373static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
374static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
5e6332a7
ZY		 375static int jz4725b_lcd_8bit_pins[] = {
376 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
377 0x72, 0x73, 0x74,
378};
379static int jz4725b_lcd_16bit_pins[] = {
380 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
381};
382static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
383static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
384static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
385static int jz4725b_lcd_generic_pins[] = { 0x75, };
f2a96765
PC		 386static int jz4725b_nand_cs1_pins[] = { 0x55, };
387static int jz4725b_nand_cs2_pins[] = { 0x56, };
388static int jz4725b_nand_cs3_pins[] = { 0x57, };
389static int jz4725b_nand_cs4_pins[] = { 0x58, };
390static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
391static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
392static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
393static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
394static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
395static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
396static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
397static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
398
bb42b593 399static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
f2a96765
PC		 400
401static const struct group_desc jz4725b_groups[] = {
bb42b593
PC		 402 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
403 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
404 jz4725b_mmc0_4bit_funcs),
405 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
406 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
407 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
5e6332a7
ZY		 408 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
409 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
410 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
411 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
412 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
413 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
bb42b593
PC		 414 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
415 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
416 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
417 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
418 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
419 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
420 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),
421 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),
422 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),
423 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),
424 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),
425 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),
f2a96765
PC		 426};
427
428static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
429static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
430static const char *jz4725b_uart_groups[] = { "uart-data", };
5e6332a7
ZY		 431static const char *jz4725b_lcd_groups[] = {
432 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
433 "lcd-special", "lcd-generic",
434};
f2a96765
PC		 435static const char *jz4725b_nand_groups[] = {
436 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
437 "nand-cle-ale", "nand-fre-fwe",
438};
439static const char *jz4725b_pwm0_groups[] = { "pwm0", };
440static const char *jz4725b_pwm1_groups[] = { "pwm1", };
441static const char *jz4725b_pwm2_groups[] = { "pwm2", };
442static const char *jz4725b_pwm3_groups[] = { "pwm3", };
443static const char *jz4725b_pwm4_groups[] = { "pwm4", };
444static const char *jz4725b_pwm5_groups[] = { "pwm5", };
445
446static const struct function_desc jz4725b_functions[] = {
447 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
448 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
449 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
450 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
451 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
452 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
453 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
454 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
455 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
456 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
a3240f09 457 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
f2a96765
PC		 458};
459
460static const struct ingenic_chip_info jz4725b_chip_info = {
461 .num_chips = 4,
f742e5eb 462 .reg_offset = 0x100,
baf15647 463 .version = ID_JZ4725B,
f2a96765
PC		 464 .groups = jz4725b_groups,
465 .num_groups = ARRAY_SIZE(jz4725b_groups),
466 .functions = jz4725b_functions,
467 .num_functions = ARRAY_SIZE(jz4725b_functions),
468 .pull_ups = jz4740_pull_ups,
469 .pull_downs = jz4740_pull_downs,
470};
471
215c81a3
ZY		 472static const u32 jz4750_pull_ups[6] = {
473 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff,
474};
475
476static const u32 jz4750_pull_downs[6] = {
477 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
478};
479
480static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
481static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
482static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
483static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
484static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
485static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
486static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
487static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
488static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
489static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
490static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
491static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
492static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
493static int jz4750_cim_pins[] = {
494 0x89, 0x8b, 0x8a, 0x88,
495 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
496};
497static int jz4750_lcd_8bit_pins[] = {
498 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
499 0x72, 0x73, 0x74,
500};
501static int jz4750_lcd_16bit_pins[] = {
502 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
503};
504static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
505static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, };
506static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
507static int jz4750_lcd_generic_pins[] = { 0x75, };
508static int jz4750_nand_cs1_pins[] = { 0x55, };
509static int jz4750_nand_cs2_pins[] = { 0x56, };
510static int jz4750_nand_cs3_pins[] = { 0x57, };
511static int jz4750_nand_cs4_pins[] = { 0x58, };
512static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
513static int jz4750_pwm_pwm0_pins[] = { 0x94, };
514static int jz4750_pwm_pwm1_pins[] = { 0x95, };
515static int jz4750_pwm_pwm2_pins[] = { 0x96, };
516static int jz4750_pwm_pwm3_pins[] = { 0x97, };
517static int jz4750_pwm_pwm4_pins[] = { 0x98, };
518static int jz4750_pwm_pwm5_pins[] = { 0x99, };
519
520static const struct group_desc jz4750_groups[] = {
521 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
522 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
523 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
524 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
525 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
526 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
527 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
528 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
529 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
530 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
531 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
532 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
533 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
534 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
535 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
536 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
537 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
538 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
539 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
540 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
541 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
542 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
543 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
544 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
545 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
546 INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
547 INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
548 INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
549 INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
550 INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
551 INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),
552};
553
554static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
555static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
556static const char *jz4750_uart2_groups[] = { "uart2-data", };
557static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
558static const char *jz4750_mmc0_groups[] = {
559 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
560};
561static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
562static const char *jz4750_i2c_groups[] = { "i2c-data", };
563static const char *jz4750_cim_groups[] = { "cim-data", };
564static const char *jz4750_lcd_groups[] = {
565 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
566 "lcd-special", "lcd-generic",
567};
568static const char *jz4750_nand_groups[] = {
569 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
570};
571static const char *jz4750_pwm0_groups[] = { "pwm0", };
572static const char *jz4750_pwm1_groups[] = { "pwm1", };
573static const char *jz4750_pwm2_groups[] = { "pwm2", };
574static const char *jz4750_pwm3_groups[] = { "pwm3", };
575static const char *jz4750_pwm4_groups[] = { "pwm4", };
576static const char *jz4750_pwm5_groups[] = { "pwm5", };
577
578static const struct function_desc jz4750_functions[] = {
579 { "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), },
580 { "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), },
581 { "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), },
582 { "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), },
583 { "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), },
584 { "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), },
585 { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), },
586 { "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), },
587 { "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), },
588 { "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), },
589 { "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), },
590 { "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), },
591 { "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), },
592 { "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), },
593 { "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), },
594 { "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), },
595};
596
597static const struct ingenic_chip_info jz4750_chip_info = {
598 .num_chips = 6,
599 .reg_offset = 0x100,
600 .version = ID_JZ4750,
601 .groups = jz4750_groups,
602 .num_groups = ARRAY_SIZE(jz4750_groups),
603 .functions = jz4750_functions,
604 .num_functions = ARRAY_SIZE(jz4750_functions),
605 .pull_ups = jz4750_pull_ups,
606 .pull_downs = jz4750_pull_downs,
607};
608
b582b5a4
ZY		 609static const u32 jz4755_pull_ups[6] = {
610 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00,
611};
612
613static const u32 jz4755_pull_downs[6] = {
614 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
615};
616
617static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
618static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
619static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
620static int jz4755_uart2_data_pins[] = { 0x9f, };
b638e0f1
ZY		 621static int jz4755_ssi_dt_b_pins[] = { 0x3b, };
622static int jz4755_ssi_dt_f_pins[] = { 0xa1, };
623static int jz4755_ssi_dr_b_pins[] = { 0x3c, };
624static int jz4755_ssi_dr_f_pins[] = { 0xa2, };
625static int jz4755_ssi_clk_b_pins[] = { 0x3a, };
626static int jz4755_ssi_clk_f_pins[] = { 0xa0, };
627static int jz4755_ssi_gpc_b_pins[] = { 0x3e, };
628static int jz4755_ssi_gpc_f_pins[] = { 0xa4, };
629static int jz4755_ssi_ce0_b_pins[] = { 0x3d, };
630static int jz4755_ssi_ce0_f_pins[] = { 0xa3, };
631static int jz4755_ssi_ce1_b_pins[] = { 0x3f, };
632static int jz4755_ssi_ce1_f_pins[] = { 0xa5, };
b582b5a4
ZY		 633static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
634static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
635static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
636static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
637static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
638static int jz4755_cim_pins[] = {
639 0x89, 0x8b, 0x8a, 0x88,
640 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
641};
642static int jz4755_lcd_8bit_pins[] = {
643 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
644 0x72, 0x73, 0x74,
645};
646static int jz4755_lcd_16bit_pins[] = {
647 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
648};
649static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, };
650static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, };
651static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
652static int jz4755_lcd_generic_pins[] = { 0x75, };
653static int jz4755_nand_cs1_pins[] = { 0x55, };
654static int jz4755_nand_cs2_pins[] = { 0x56, };
655static int jz4755_nand_cs3_pins[] = { 0x57, };
656static int jz4755_nand_cs4_pins[] = { 0x58, };
657static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
658static int jz4755_pwm_pwm0_pins[] = { 0x94, };
659static int jz4755_pwm_pwm1_pins[] = { 0xab, };
660static int jz4755_pwm_pwm2_pins[] = { 0x96, };
661static int jz4755_pwm_pwm3_pins[] = { 0x97, };
662static int jz4755_pwm_pwm4_pins[] = { 0x98, };
663static int jz4755_pwm_pwm5_pins[] = { 0x99, };
664
665static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
666static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
667static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };
668
669static const struct group_desc jz4755_groups[] = {
670 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
671 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
17747577 672 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),
b582b5a4 673 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
b638e0f1
ZY		 674 INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
675 INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
676 INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
677 INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
678 INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
679 INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
680 INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
681 INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
682 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
683 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
684 INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
685 INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
b582b5a4
ZY		 686 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
687 jz4755_mmc0_1bit_funcs),
688 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
689 jz4755_mmc0_4bit_funcs),
690 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
691 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
692 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
693 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
694 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
695 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
696 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
697 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
698 jz4755_lcd_24bit_funcs),
699 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
700 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
701 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
702 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
703 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
704 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
705 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
706 INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),
707 INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),
708 INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),
709 INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0),
710 INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0),
711 INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0),
712};
713
714static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
715static const char *jz4755_uart1_groups[] = { "uart1-data", };
716static const char *jz4755_uart2_groups[] = { "uart2-data", };
b638e0f1
ZY		 717static const char *jz4755_ssi_groups[] = {
718 "ssi-dt-b", "ssi-dt-f",
719 "ssi-dr-b", "ssi-dr-f",
720 "ssi-clk-b", "ssi-clk-f",
721 "ssi-gpc-b", "ssi-gpc-f",
722 "ssi-ce0-b", "ssi-ce0-f",
723 "ssi-ce1-b", "ssi-ce1-f",
724};
b582b5a4 725static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
17747577 726static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
b582b5a4
ZY		 727static const char *jz4755_i2c_groups[] = { "i2c-data", };
728static const char *jz4755_cim_groups[] = { "cim-data", };
729static const char *jz4755_lcd_groups[] = {
730 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
731 "lcd-special", "lcd-generic",
732};
733static const char *jz4755_nand_groups[] = {
734 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
735};
736static const char *jz4755_pwm0_groups[] = { "pwm0", };
737static const char *jz4755_pwm1_groups[] = { "pwm1", };
738static const char *jz4755_pwm2_groups[] = { "pwm2", };
739static const char *jz4755_pwm3_groups[] = { "pwm3", };
740static const char *jz4755_pwm4_groups[] = { "pwm4", };
741static const char *jz4755_pwm5_groups[] = { "pwm5", };
742
743static const struct function_desc jz4755_functions[] = {
744 { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), },
745 { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), },
746 { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), },
b638e0f1 747 { "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), },
b582b5a4
ZY		 748 { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), },
749 { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), },
750 { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), },
751 { "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), },
752 { "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), },
753 { "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), },
754 { "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), },
755 { "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), },
756 { "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), },
757 { "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), },
758 { "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), },
759 { "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), },
760};
761
762static const struct ingenic_chip_info jz4755_chip_info = {
763 .num_chips = 6,
764 .reg_offset = 0x100,
765 .version = ID_JZ4755,
766 .groups = jz4755_groups,
767 .num_groups = ARRAY_SIZE(jz4755_groups),
768 .functions = jz4755_functions,
769 .num_functions = ARRAY_SIZE(jz4755_functions),
770 .pull_ups = jz4755_pull_ups,
771 .pull_downs = jz4755_pull_downs,
772};
773
0257595a 774static const u32 jz4760_pull_ups[6] = {
d5e93140 775 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,
0257595a
ZY		 776};
777
778static const u32 jz4760_pull_downs[6] = {
779 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
780};
781
782static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
783static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
784static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
785static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
786static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
787static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
788static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
789static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
b638e0f1
ZY		 790static int jz4760_ssi0_dt_a_pins[] = { 0x15, };
791static int jz4760_ssi0_dt_b_pins[] = { 0x35, };
792static int jz4760_ssi0_dt_d_pins[] = { 0x75, };
793static int jz4760_ssi0_dt_e_pins[] = { 0x91, };
794static int jz4760_ssi0_dr_a_pins[] = { 0x14, };
795static int jz4760_ssi0_dr_b_pins[] = { 0x34, };
796static int jz4760_ssi0_dr_d_pins[] = { 0x74, };
797static int jz4760_ssi0_dr_e_pins[] = { 0x8e, };
798static int jz4760_ssi0_clk_a_pins[] = { 0x12, };
799static int jz4760_ssi0_clk_b_pins[] = { 0x3c, };
800static int jz4760_ssi0_clk_d_pins[] = { 0x78, };
801static int jz4760_ssi0_clk_e_pins[] = { 0x8f, };
802static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, };
803static int jz4760_ssi0_gpc_d_pins[] = { 0x76, };
804static int jz4760_ssi0_gpc_e_pins[] = { 0x93, };
805static int jz4760_ssi0_ce0_a_pins[] = { 0x13, };
806static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, };
807static int jz4760_ssi0_ce0_d_pins[] = { 0x79, };
808static int jz4760_ssi0_ce0_e_pins[] = { 0x90, };
809static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, };
810static int jz4760_ssi0_ce1_d_pins[] = { 0x77, };
811static int jz4760_ssi0_ce1_e_pins[] = { 0x92, };
812static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, };
813static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, };
814static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, };
815static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, };
816static int jz4760_ssi1_dt_e_pins[] = { 0x91, };
817static int jz4760_ssi1_dt_f_pins[] = { 0xa3, };
818static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, };
819static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, };
820static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, };
821static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, };
822static int jz4760_ssi1_dr_e_pins[] = { 0x8e, };
823static int jz4760_ssi1_dr_f_pins[] = { 0xa0, };
824static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, };
825static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, };
826static int jz4760_ssi1_clk_d_pins[] = { 0x78, };
827static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, };
828static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, };
829static int jz4760_ssi1_clk_f_pins[] = { 0xa2, };
830static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, };
831static int jz4760_ssi1_gpc_d_pins[] = { 0x76, };
832static int jz4760_ssi1_gpc_e_pins[] = { 0x93, };
833static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, };
834static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, };
835static int jz4760_ssi1_ce0_d_pins[] = { 0x79, };
836static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, };
837static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, };
838static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, };
839static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, };
840static int jz4760_ssi1_ce1_d_pins[] = { 0x77, };
841static int jz4760_ssi1_ce1_e_pins[] = { 0x92, };
0257595a
ZY		 842static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
843static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
844static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
845static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
846static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
847static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
848static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
849static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
850static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
851static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
852static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
853static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
854static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
855static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
856static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
857static int jz4760_nemc_8bit_data_pins[] = {
858 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
859};
860static int jz4760_nemc_16bit_data_pins[] = {
861 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
862};
863static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
864static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
865static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
866static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
867static int jz4760_nemc_wait_pins[] = { 0x1b, };
868static int jz4760_nemc_cs1_pins[] = { 0x15, };
869static int jz4760_nemc_cs2_pins[] = { 0x16, };
870static int jz4760_nemc_cs3_pins[] = { 0x17, };
871static int jz4760_nemc_cs4_pins[] = { 0x18, };
872static int jz4760_nemc_cs5_pins[] = { 0x19, };
873static int jz4760_nemc_cs6_pins[] = { 0x1a, };
874static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
875static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
876static int jz4760_cim_pins[] = {
877 0x26, 0x27, 0x28, 0x29,
878 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
879};
dd1ccfd6
PC		 880static int jz4760_lcd_8bit_pins[] = {
881 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,
882 0x4d, 0x52, 0x53,
883};
884static int jz4760_lcd_16bit_pins[] = {
885 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
886};
887static int jz4760_lcd_18bit_pins[] = {
888 0x5a, 0x5b,
889};
0257595a 890static int jz4760_lcd_24bit_pins[] = {
dd1ccfd6 891 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
0257595a 892};
5e6332a7 893static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
dd1ccfd6 894static int jz4760_lcd_generic_pins[] = { 0x49, };
0257595a
ZY		 895static int jz4760_pwm_pwm0_pins[] = { 0x80, };
896static int jz4760_pwm_pwm1_pins[] = { 0x81, };
897static int jz4760_pwm_pwm2_pins[] = { 0x82, };
898static int jz4760_pwm_pwm3_pins[] = { 0x83, };
899static int jz4760_pwm_pwm4_pins[] = { 0x84, };
900static int jz4760_pwm_pwm5_pins[] = { 0x85, };
901static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
902static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
dd1ccfd6 903static int jz4760_otg_pins[] = { 0x8a, };
0257595a 904
bb42b593
PC		 905static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
906static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
0257595a
ZY		 907
908static const struct group_desc jz4760_groups[] = {
bb42b593
PC		 909 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
910 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
911 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
912 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
913 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
914 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
915 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
916 jz4760_uart3_data_funcs),
917 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
b638e0f1
ZY		 918 INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
919 INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
920 INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
921 INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
922 INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
923 INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
924 INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
925 INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
926 INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
927 INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
928 INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
929 INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
930 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
931 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
932 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
933 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
934 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
935 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
936 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
937 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
938 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
939 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
940 INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
941 INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
942 INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
943 INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
944 INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
945 INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
946 INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
947 INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
948 INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
949 INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
950 INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
951 INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
952 INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
953 INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
954 INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
955 INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
956 INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
957 INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
958 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
959 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
960 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
961 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
962 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
963 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
964 INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
965 INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
966 INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
967 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
968 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
969 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
bb42b593
PC		 970 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
971 jz4760_mmc0_1bit_a_funcs),
972 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
973 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
974 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
975 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
976 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
977 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
978 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
979 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
980 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
981 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
982 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
983 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
984 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
985 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
986 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
987 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
988 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
989 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
990 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
991 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
992 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
993 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
994 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
995 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
996 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
997 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
998 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
999 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
1000 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
1001 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
dd1ccfd6
PC		 1002 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
1003 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
1004 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
bb42b593 1005 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
dd1ccfd6 1006 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
5e6332a7 1007 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
bb42b593
PC		 1008 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
1009 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
1010 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
1011 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),
1012 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),
1013 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
1014 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
1015 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
dd1ccfd6 1016 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
0257595a
ZY		 1017};
1018
1019static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1020static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1021static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1022static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
b638e0f1
ZY		 1023static const char *jz4760_ssi0_groups[] = {
1024 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1025 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1026 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1027 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1028 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1029 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1030};
1031static const char *jz4760_ssi1_groups[] = {
1032 "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
1033 "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
1034 "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
1035 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1036 "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
1037 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1038};
0257595a
ZY		 1039static const char *jz4760_mmc0_groups[] = {
1040 "mmc0-1bit-a", "mmc0-4bit-a",
1041 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1042};
1043static const char *jz4760_mmc1_groups[] = {
1044 "mmc1-1bit-d", "mmc1-4bit-d",
1045 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1046};
1047static const char *jz4760_mmc2_groups[] = {
1048 "mmc2-1bit-b", "mmc2-4bit-b",
1049 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1050};
1051static const char *jz4760_nemc_groups[] = {
1052 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1053 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1054};
1055static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
1056static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
1057static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
1058static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
1059static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
1060static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
1061static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
1062static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
1063static const char *jz4760_cim_groups[] = { "cim-data", };
dd1ccfd6
PC		 1064static const char *jz4760_lcd_groups[] = {
1065 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1066 "lcd-special", "lcd-generic",
1067};
0257595a
ZY		 1068static const char *jz4760_pwm0_groups[] = { "pwm0", };
1069static const char *jz4760_pwm1_groups[] = { "pwm1", };
1070static const char *jz4760_pwm2_groups[] = { "pwm2", };
1071static const char *jz4760_pwm3_groups[] = { "pwm3", };
1072static const char *jz4760_pwm4_groups[] = { "pwm4", };
1073static const char *jz4760_pwm5_groups[] = { "pwm5", };
1074static const char *jz4760_pwm6_groups[] = { "pwm6", };
1075static const char *jz4760_pwm7_groups[] = { "pwm7", };
dd1ccfd6 1076static const char *jz4760_otg_groups[] = { "otg-vbus", };
0257595a
ZY		 1077
1078static const struct function_desc jz4760_functions[] = {
1079 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
1080 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
1081 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
1082 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
b638e0f1
ZY		 1083 { "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), },
1084 { "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), },
0257595a
ZY		 1085 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
1086 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
1087 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
1088 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
1089 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
1090 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
1091 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
1092 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
1093 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
1094 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
1095 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
1096 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
1097 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
1098 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
1099 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
1100 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
1101 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
1102 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
1103 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
1104 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
1105 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
1106 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
dd1ccfd6 1107 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
0257595a
ZY		 1108};
1109
1110static const struct ingenic_chip_info jz4760_chip_info = {
1111 .num_chips = 6,
f742e5eb 1112 .reg_offset = 0x100,
baf15647 1113 .version = ID_JZ4760,
0257595a
ZY		 1114 .groups = jz4760_groups,
1115 .num_groups = ARRAY_SIZE(jz4760_groups),
1116 .functions = jz4760_functions,
1117 .num_functions = ARRAY_SIZE(jz4760_functions),
1118 .pull_ups = jz4760_pull_ups,
1119 .pull_downs = jz4760_pull_downs,
1120};
1121
b5c23aa4 1122static const u32 jz4770_pull_ups[6] = {
d5e93140 1123 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,
b5c23aa4
PC		 1124};
1125
1126static const u32 jz4770_pull_downs[6] = {
d5e93140 1127 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,
b5c23aa4
PC		 1128};
1129
1130static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
1131static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1132static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
1133static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
ff656e47
ZY		 1134static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
1135static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
b5c23aa4
PC		 1136static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
1137static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
d3ef8c6b
ZY		 1138static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
1139static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
f83c2609
PC		 1140static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
1141static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
d3ef8c6b
ZY		 1142static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
1143static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
f83c2609
PC		 1144static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
1145static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
d3ef8c6b
ZY		 1146static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
1147static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
f83c2609
PC		 1148static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
1149static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
d3ef8c6b 1150static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
f83c2609
PC		 1151static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
1152static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
d3ef8c6b
ZY		 1153static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
1154static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
f83c2609
PC		 1155static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
1156static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
d3ef8c6b 1157static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
f83c2609
PC		 1158static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
1159static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
d3ef8c6b 1160static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
f83c2609
PC		 1161static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
1162static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
d3ef8c6b 1163static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
f83c2609
PC		 1164static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
1165static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
d3ef8c6b 1166static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
f83c2609
PC		 1167static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
1168static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
d3ef8c6b 1169static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
f83c2609
PC		 1170static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
1171static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
d3ef8c6b 1172static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
f83c2609
PC		 1173static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
1174static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
d3ef8c6b 1175static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
f83c2609
PC		 1176static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
1177static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
b5c23aa4 1178static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
ff656e47 1179static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
b5c23aa4 1180static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
ff656e47
ZY		 1181static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1182static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
b5c23aa4 1183static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
ff656e47 1184static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
b5c23aa4 1185static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
ff656e47
ZY		 1186static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1187static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
5de1a73e
ZY		 1188static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1189static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1190static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1191static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1192static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
ff656e47 1193static int jz4770_nemc_8bit_data_pins[] = {
b5c23aa4
PC		 1194 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1195};
ff656e47
ZY		 1196static int jz4770_nemc_16bit_data_pins[] = {
1197 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1198};
b5c23aa4
PC		 1199static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1200static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1201static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
1202static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
5de1a73e 1203static int jz4770_nemc_wait_pins[] = { 0x1b, };
b5c23aa4
PC		 1204static int jz4770_nemc_cs1_pins[] = { 0x15, };
1205static int jz4770_nemc_cs2_pins[] = { 0x16, };
1206static int jz4770_nemc_cs3_pins[] = { 0x17, };
1207static int jz4770_nemc_cs4_pins[] = { 0x18, };
1208static int jz4770_nemc_cs5_pins[] = { 0x19, };
1209static int jz4770_nemc_cs6_pins[] = { 0x1a, };
ff656e47
ZY		 1210static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
1211static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
b5c23aa4 1212static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
ff656e47
ZY		 1213static int jz4770_cim_8bit_pins[] = {
1214 0x26, 0x27, 0x28, 0x29,
1215 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1216};
1217static int jz4770_cim_12bit_pins[] = {
1218 0x32, 0x33, 0xb0, 0xb1,
b5c23aa4 1219};
016e054d
PC		 1220static int jz4770_lcd_8bit_pins[] = {
1221 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
5e6332a7
ZY		 1222 0x48, 0x52, 0x53,
1223};
1224static int jz4770_lcd_16bit_pins[] = {
1225 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1226};
1227static int jz4770_lcd_18bit_pins[] = {
1228 0x5a, 0x5b,
016e054d 1229};
ff656e47 1230static int jz4770_lcd_24bit_pins[] = {
b5c23aa4
PC		 1231 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
1232 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
1233 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
ff656e47 1234 0x58, 0x59, 0x5a, 0x5b,
b5c23aa4 1235};
5e6332a7
ZY		 1236static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1237static int jz4770_lcd_generic_pins[] = { 0x49, };
b5c23aa4
PC		 1238static int jz4770_pwm_pwm0_pins[] = { 0x80, };
1239static int jz4770_pwm_pwm1_pins[] = { 0x81, };
1240static int jz4770_pwm_pwm2_pins[] = { 0x82, };
1241static int jz4770_pwm_pwm3_pins[] = { 0x83, };
1242static int jz4770_pwm_pwm4_pins[] = { 0x84, };
1243static int jz4770_pwm_pwm5_pins[] = { 0x85, };
1244static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
1245static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
5de1a73e
ZY		 1246static int jz4770_mac_rmii_pins[] = {
1247 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1248};
65afd976
ZY		 1249static int jz4770_mac_mii_pins[] = {
1250 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1251};
b5c23aa4 1252
b5c23aa4 1253static const struct group_desc jz4770_groups[] = {
bb42b593
PC		 1254 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1255 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1256 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1257 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1258 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
1259 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
1260 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1261 jz4760_uart3_data_funcs),
1262 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1263 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
1264 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
1265 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
1266 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1267 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
1268 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
1269 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
1270 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1271 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
1272 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
1273 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
1274 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1275 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
1276 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
1277 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1278 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
1279 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
1280 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
1281 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1282 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
1283 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
1284 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1285 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
1286 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
1287 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1288 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
1289 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
1290 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1291 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
1292 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
1293 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1294 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
1295 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
1296 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1297 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
1298 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
1299 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1300 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
1301 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
1302 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1303 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1304 jz4760_mmc0_1bit_a_funcs),
1305 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1306 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1307 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1308 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
1309 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1310 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1311 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1312 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1313 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
1314 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1315 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1316 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1317 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1318 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
1319 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
1320 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
1321 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1322 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1323 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1324 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1325 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1326 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1327 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1328 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1329 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1330 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1331 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1332 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1333 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1334 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1335 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
1336 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
016e054d 1337 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
5e6332a7
ZY		 1338 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1339 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
bb42b593 1340 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
5e6332a7
ZY		 1341 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1342 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
bb42b593
PC		 1343 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1344 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1345 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1346 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1347 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1348 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1349 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1350 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1351 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
1352 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
dd1ccfd6 1353 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
b5c23aa4
PC		 1354};
1355
1356static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1357static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1358static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1359static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
d3ef8c6b
ZY		 1360static const char *jz4770_ssi0_groups[] = {
1361 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1362 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1363 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1364 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1365 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1366 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1367};
1368static const char *jz4770_ssi1_groups[] = {
1369 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1370 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1371 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1372 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1373 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1374 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1375};
b5c23aa4 1376static const char *jz4770_mmc0_groups[] = {
ff656e47
ZY		 1377 "mmc0-1bit-a", "mmc0-4bit-a",
1378 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
b5c23aa4
PC		 1379};
1380static const char *jz4770_mmc1_groups[] = {
ff656e47
ZY		 1381 "mmc1-1bit-d", "mmc1-4bit-d",
1382 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
b5c23aa4 1383};
5de1a73e
ZY		 1384static const char *jz4770_mmc2_groups[] = {
1385 "mmc2-1bit-b", "mmc2-4bit-b",
1386 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1387};
b5c23aa4 1388static const char *jz4770_nemc_groups[] = {
ff656e47 1389 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
5de1a73e 1390 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
b5c23aa4
PC		 1391};
1392static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
ff656e47
ZY		 1393static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
1394static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
1395static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
1396static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
b5c23aa4
PC		 1397static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
1398static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
1399static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
1400static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
ff656e47 1401static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
016e054d 1402static const char *jz4770_lcd_groups[] = {
5e6332a7
ZY		 1403 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1404 "lcd-special", "lcd-generic",
016e054d 1405};
b5c23aa4
PC		 1406static const char *jz4770_pwm0_groups[] = { "pwm0", };
1407static const char *jz4770_pwm1_groups[] = { "pwm1", };
1408static const char *jz4770_pwm2_groups[] = { "pwm2", };
1409static const char *jz4770_pwm3_groups[] = { "pwm3", };
1410static const char *jz4770_pwm4_groups[] = { "pwm4", };
1411static const char *jz4770_pwm5_groups[] = { "pwm5", };
1412static const char *jz4770_pwm6_groups[] = { "pwm6", };
1413static const char *jz4770_pwm7_groups[] = { "pwm7", };
5de1a73e 1414static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
b5c23aa4
PC		 1415
1416static const struct function_desc jz4770_functions[] = {
1417 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1418 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1419 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
1420 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
d3ef8c6b
ZY		 1421 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
1422 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
b5c23aa4
PC		 1423 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
1424 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
5de1a73e 1425 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
b5c23aa4
PC		 1426 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
1427 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
ff656e47
ZY		 1428 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1429 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1430 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1431 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
b5c23aa4
PC		 1432 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1433 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1434 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1435 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
b5c23aa4
PC		 1436 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
1437 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1438 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1439 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1440 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1441 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1442 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1443 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1444 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1445 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
5de1a73e 1446 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
dd1ccfd6 1447 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
b5c23aa4
PC		 1448};
1449
1450static const struct ingenic_chip_info jz4770_chip_info = {
1451 .num_chips = 6,
f742e5eb 1452 .reg_offset = 0x100,
baf15647 1453 .version = ID_JZ4770,
b5c23aa4
PC		 1454 .groups = jz4770_groups,
1455 .num_groups = ARRAY_SIZE(jz4770_groups),
1456 .functions = jz4770_functions,
1457 .num_functions = ARRAY_SIZE(jz4770_functions),
1458 .pull_ups = jz4770_pull_ups,
1459 .pull_downs = jz4770_pull_downs,
1460};
1461
0c990740
ZY		 1462static const u32 jz4775_pull_ups[7] = {
1463 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0,
1464};
1465
1466static const u32 jz4775_pull_downs[7] = {
1467 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00,
1468};
1469
1470static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, };
1471static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1472static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, };
1473static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
1474static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, };
1475static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, };
1476static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, };
1477static int jz4775_ssi_dt_a_pins[] = { 0x13, };
1478static int jz4775_ssi_dt_d_pins[] = { 0x75, };
1479static int jz4775_ssi_dr_a_pins[] = { 0x14, };
1480static int jz4775_ssi_dr_d_pins[] = { 0x74, };
1481static int jz4775_ssi_clk_a_pins[] = { 0x12, };
1482static int jz4775_ssi_clk_d_pins[] = { 0x78, };
1483static int jz4775_ssi_gpc_pins[] = { 0x76, };
1484static int jz4775_ssi_ce0_a_pins[] = { 0x17, };
1485static int jz4775_ssi_ce0_d_pins[] = { 0x79, };
1486static int jz4775_ssi_ce1_pins[] = { 0x77, };
1487static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
1488static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
1489static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, };
1490static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1491static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1492static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
1493static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
1494static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1495static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1496static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1497static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1498static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1499static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1500static int jz4775_nemc_8bit_data_pins[] = {
1501 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1502};
1503static int jz4775_nemc_16bit_data_pins[] = {
1504 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1,
1505};
1506static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1507static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1508static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, };
1509static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
1510static int jz4775_nemc_wait_pins[] = { 0x1b, };
1511static int jz4775_nemc_cs1_pins[] = { 0x15, };
1512static int jz4775_nemc_cs2_pins[] = { 0x16, };
1513static int jz4775_nemc_cs3_pins[] = { 0x17, };
1514static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, };
1515static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, };
1516static int jz4775_i2c2_pins[] = { 0x80, 0x83, };
1517static int jz4775_i2s_data_tx_pins[] = { 0xa3, };
1518static int jz4775_i2s_data_rx_pins[] = { 0xa2, };
1519static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, };
1520static int jz4775_i2s_sysclk_pins[] = { 0x83, };
1521static int jz4775_dmic_pins[] = { 0xaa, 0xab, };
1522static int jz4775_cim_pins[] = {
1523 0x26, 0x27, 0x28, 0x29,
1524 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1525};
1526static int jz4775_lcd_8bit_pins[] = {
1527 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
1528 0x48, 0x52, 0x53,
1529};
1530static int jz4775_lcd_16bit_pins[] = {
1531 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1532};
1533static int jz4775_lcd_18bit_pins[] = {
1534 0x5a, 0x5b,
1535};
1536static int jz4775_lcd_24bit_pins[] = {
1537 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
1538};
1539static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1540static int jz4775_lcd_generic_pins[] = { 0x49, };
1541static int jz4775_pwm_pwm0_pins[] = { 0x80, };
1542static int jz4775_pwm_pwm1_pins[] = { 0x81, };
1543static int jz4775_pwm_pwm2_pins[] = { 0x82, };
1544static int jz4775_pwm_pwm3_pins[] = { 0x83, };
1545static int jz4775_mac_rmii_pins[] = {
1546 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1547};
1548static int jz4775_mac_mii_pins[] = {
1549 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1550};
1551static int jz4775_mac_rgmii_pins[] = {
1552 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4,
1553 0xad, 0xae, 0xa7, 0xa6,
1554};
1555static int jz4775_mac_gmii_pins[] = {
1556 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a,
1557 0xa8, 0x28, 0x24, 0xaf,
1558};
1559static int jz4775_otg_pins[] = { 0x8a, };
1560
1561static u8 jz4775_uart3_data_funcs[] = { 0, 1, };
1562static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, };
1563static u8 jz4775_mac_rgmii_funcs[] = {
1564 0, 1, 1, 0, 0, 0, 1, 1, 0, 0,
1565 0, 0, 0, 0,
1566};
1567static u8 jz4775_mac_gmii_funcs[] = {
1568 1, 1, 1, 1, 1, 1, 1, 1,
1569 0, 1, 1, 0,
1570};
1571
1572static const struct group_desc jz4775_groups[] = {
1573 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
1574 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
1575 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
1576 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
1577 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
1578 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
1579 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
1580 jz4775_uart3_data_funcs),
1581 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
1582 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
1583 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
1584 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
1585 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
1586 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
1587 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
1588 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
1589 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
1590 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
1591 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
1592 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
1593 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
1594 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
1595 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
1596 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
1597 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
1598 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
1599 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
1600 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
1601 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
1602 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
1603 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
1604 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
1605 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
1606 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
1607 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
1608 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
1609 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
1610 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
1611 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
1612 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
1613 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
1614 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
1615 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
1616 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
1617 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
1618 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
1619 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
1620 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
1621 INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1),
1622 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
1623 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
1624 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
1625 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
1626 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
1627 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
1628 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
1629 INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0),
1630 INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0),
1631 INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0),
1632 INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0),
1633 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
1634 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
1635 jz4775_mac_mii_funcs),
1636 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
1637 jz4775_mac_rgmii_funcs),
1638 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
1639 jz4775_mac_gmii_funcs),
1640 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
1641};
1642
1643static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1644static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1645static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
1646static const char *jz4775_uart3_groups[] = { "uart3-data", };
1647static const char *jz4775_ssi_groups[] = {
1648 "ssi-dt-a", "ssi-dt-d",
1649 "ssi-dr-a", "ssi-dr-d",
1650 "ssi-clk-a", "ssi-clk-d",
1651 "ssi-gpc",
1652 "ssi-ce0-a", "ssi-ce0-d",
1653 "ssi-ce1",
1654};
1655static const char *jz4775_mmc0_groups[] = {
1656 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1657 "mmc0-1bit-e", "mmc0-4bit-e",
1658};
1659static const char *jz4775_mmc1_groups[] = {
1660 "mmc1-1bit-d", "mmc1-4bit-d",
1661 "mmc1-1bit-e", "mmc1-4bit-e",
1662};
1663static const char *jz4775_mmc2_groups[] = {
1664 "mmc2-1bit-b", "mmc2-4bit-b",
1665 "mmc2-1bit-e", "mmc2-4bit-e",
1666};
1667static const char *jz4775_nemc_groups[] = {
1668 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1669 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1670};
1671static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
1672static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
1673static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
1674static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
1675static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
1676static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
1677static const char *jz4775_i2s_groups[] = {
1678 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1679};
1680static const char *jz4775_dmic_groups[] = { "dmic", };
1681static const char *jz4775_cim_groups[] = { "cim-data", };
1682static const char *jz4775_lcd_groups[] = {
1683 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1684 "lcd-special", "lcd-generic",
1685};
1686static const char *jz4775_pwm0_groups[] = { "pwm0", };
1687static const char *jz4775_pwm1_groups[] = { "pwm1", };
1688static const char *jz4775_pwm2_groups[] = { "pwm2", };
1689static const char *jz4775_pwm3_groups[] = { "pwm3", };
1690static const char *jz4775_mac_groups[] = {
1691 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
1692};
1693static const char *jz4775_otg_groups[] = { "otg-vbus", };
1694
1695static const struct function_desc jz4775_functions[] = {
1696 { "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), },
1697 { "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), },
1698 { "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), },
1699 { "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), },
1700 { "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), },
1701 { "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), },
1702 { "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), },
1703 { "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), },
1704 { "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), },
1705 { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), },
1706 { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), },
1707 { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), },
1708 { "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), },
1709 { "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), },
1710 { "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), },
1711 { "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), },
1712 { "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), },
1713 { "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), },
1714 { "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), },
1715 { "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), },
1716 { "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), },
1717 { "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), },
1718 { "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), },
1719 { "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), },
1720 { "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), },
1721};
1722
1723static const struct ingenic_chip_info jz4775_chip_info = {
1724 .num_chips = 7,
1725 .reg_offset = 0x100,
1726 .version = ID_JZ4775,
1727 .groups = jz4775_groups,
1728 .num_groups = ARRAY_SIZE(jz4775_groups),
1729 .functions = jz4775_functions,
1730 .num_functions = ARRAY_SIZE(jz4775_functions),
1731 .pull_ups = jz4775_pull_ups,
1732 .pull_downs = jz4775_pull_downs,
1733};
1734
d9f5dc49
ZY		 1735static const u32 jz4780_pull_ups[6] = {
1736 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
1737};
1738
1739static const u32 jz4780_pull_downs[6] = {
1740 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
1741};
1742
ff656e47
ZY		 1743static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
1744static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
1745static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
d3ef8c6b
ZY		 1746static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
1747static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
1748static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
1749static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
f83c2609 1750static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
d3ef8c6b
ZY		 1751static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
1752static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
1753static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
f83c2609 1754static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
d3ef8c6b
ZY		 1755static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
1756static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
1757static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
f83c2609 1758static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
d3ef8c6b 1759static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
f83c2609 1760static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
d3ef8c6b
ZY		 1761static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
1762static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
1763static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
f83c2609 1764static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
d3ef8c6b 1765static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
f83c2609 1766static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
d3ef8c6b 1767static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
f83c2609 1768static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
d3ef8c6b 1769static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
f83c2609 1770static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
d3ef8c6b 1771static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
f83c2609 1772static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
d3ef8c6b 1773static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
f83c2609 1774static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
d3ef8c6b 1775static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
f83c2609 1776static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
d3ef8c6b 1777static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
f83c2609 1778static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
ff656e47
ZY		 1779static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
1780static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
1781static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
1782static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
f4b5c348
ZY		 1783static int jz4780_i2s_data_tx_pins[] = { 0x87, };
1784static int jz4780_i2s_data_rx_pins[] = { 0x86, };
1785static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
1786static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
1787static int jz4780_i2s_sysclk_pins[] = { 0x85, };
6adf2c56 1788static int jz4780_dmic_pins[] = { 0x32, 0x33, };
a0bb89e8 1789static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
ff656e47 1790
bb42b593 1791static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
ff656e47
ZY		 1792
1793static const struct group_desc jz4780_groups[] = {
bb42b593
PC		 1794 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1795 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1796 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1797 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1798 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
1799 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
1800 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1801 jz4760_uart3_data_funcs),
1802 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1803 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
1804 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
1805 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
1806 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
1807 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
1808 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
1809 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1810 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
1811 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
1812 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
1813 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
1814 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1815 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
1816 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
1817 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
1818 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
1819 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1820 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
1821 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
1822 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1823 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
1824 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
1825 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
1826 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
1827 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1828 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
1829 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
1830 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1831 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
1832 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
1833 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1834 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
1835 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
1836 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1837 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
1838 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
1839 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1840 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
1841 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
1842 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1843 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
1844 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
1845 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1846 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
1847 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
1848 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1849 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1850 jz4760_mmc0_1bit_a_funcs),
1851 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1852 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
1853 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1854 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1855 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1856 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1857 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1858 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1859 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1860 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1861 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1862 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1863 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1864 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1865 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1866 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1867 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1868 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1869 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1870 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1871 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1872 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1873 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1874 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1875 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1876 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1877 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1878 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1879 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1880 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1881 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1882 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1883 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1884 jz4780_i2s_clk_txrx_funcs),
1885 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1886 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
6adf2c56 1887 INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1),
bb42b593
PC		 1888 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1889 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1890 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
5e6332a7
ZY		 1891 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1892 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1893 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
bb42b593 1894 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
5e6332a7
ZY		 1895 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1896 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
bb42b593
PC		 1897 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1898 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1899 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1900 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1901 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1902 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1903 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1904 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
ff656e47
ZY		 1905};
1906
1907static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1908static const char *jz4780_uart4_groups[] = { "uart4-data", };
d3ef8c6b
ZY		 1909static const char *jz4780_ssi0_groups[] = {
1910 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1911 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1912 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1913 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1914 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1915 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1916};
1917static const char *jz4780_ssi1_groups[] = {
1918 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1919 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1920 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1921 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1922 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1923 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1924};
ff656e47
ZY		 1925static const char *jz4780_mmc0_groups[] = {
1926 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1927 "mmc0-1bit-e", "mmc0-4bit-e",
1928};
1929static const char *jz4780_mmc1_groups[] = {
1930 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1931};
5de1a73e
ZY		 1932static const char *jz4780_mmc2_groups[] = {
1933 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1934};
ff656e47
ZY		 1935static const char *jz4780_nemc_groups[] = {
1936 "nemc-data", "nemc-cle-ale", "nemc-addr",
5de1a73e 1937 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
ff656e47
ZY		 1938};
1939static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1940static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
f4b5c348
ZY		 1941static const char *jz4780_i2s_groups[] = {
1942 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1943};
6adf2c56 1944static const char *jz4780_dmic_groups[] = { "dmic", };
ff656e47 1945static const char *jz4780_cim_groups[] = { "cim-data", };
a0bb89e8 1946static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
ff656e47
ZY		 1947
1948static const struct function_desc jz4780_functions[] = {
1949 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1950 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1951 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
1952 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1953 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
d3ef8c6b
ZY		 1954 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
1955 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
ff656e47
ZY		 1956 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
1957 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
5de1a73e 1958 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
ff656e47
ZY		 1959 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
1960 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1961 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1962 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1963 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1964 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1965 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1966 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1967 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1968 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1969 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
1970 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
f4b5c348 1971 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
6adf2c56 1972 { "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), },
ff656e47
ZY		 1973 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
1974 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1975 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1976 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1977 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1978 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1979 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1980 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1981 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1982 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
a0bb89e8
PB		 1983 { "hdmi-ddc", jz4780_hdmi_ddc_groups,
1984 ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
ff656e47
ZY		 1985};
1986
1987static const struct ingenic_chip_info jz4780_chip_info = {
1988 .num_chips = 6,
f742e5eb 1989 .reg_offset = 0x100,
baf15647 1990 .version = ID_JZ4780,
ff656e47
ZY		 1991 .groups = jz4780_groups,
1992 .num_groups = ARRAY_SIZE(jz4780_groups),
1993 .functions = jz4780_functions,
1994 .num_functions = ARRAY_SIZE(jz4780_functions),
d9f5dc49
ZY		 1995 .pull_ups = jz4780_pull_ups,
1996 .pull_downs = jz4780_pull_downs,
ff656e47
ZY		 1997};
1998
fe1ad5ee 1999static const u32 x1000_pull_ups[4] = {
b4a9372a 2000 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
fe1ad5ee
ZY		 2001};
2002
2003static const u32 x1000_pull_downs[4] = {
2004 0x00000000, 0x02000000, 0x02000000, 0x00000000,
2005};
2006
2007static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
2008static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
2009static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
2010static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
b4a9372a 2011static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
fe1ad5ee
ZY		 2012static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
2013static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
28c1caaf
ZY		 2014static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, };
2015static int x1000_sfc_clk_pins[] = { 0x1a, };
2016static int x1000_sfc_ce_pins[] = { 0x1b, };
3b31e9b0
ZY		 2017static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
2018static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
2019static int x1000_ssi_dt_d_pins[] = { 0x62, };
2020static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
2021static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
2022static int x1000_ssi_dr_d_pins[] = { 0x63, };
2023static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
2024static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
2025static int x1000_ssi_clk_d_pins[] = { 0x60, };
2026static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
2027static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
2028static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
2029static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
2030static int x1000_ssi_ce0_d_pins[] = { 0x61, };
2031static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
2032static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
fe1ad5ee
ZY		 2033static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
2034static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
2035static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
2036static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
2037static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
b4a9372a 2038static int x1000_emc_8bit_data_pins[] = {
fe1ad5ee
ZY		 2039 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2040};
b4a9372a 2041static int x1000_emc_16bit_data_pins[] = {
fe1ad5ee
ZY		 2042 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2043};
b4a9372a 2044static int x1000_emc_addr_pins[] = {
fe1ad5ee
ZY		 2045 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2046 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2047};
b4a9372a
ZY		 2048static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
2049static int x1000_emc_wait_pins[] = { 0x34, };
2050static int x1000_emc_cs1_pins[] = { 0x32, };
2051static int x1000_emc_cs2_pins[] = { 0x33, };
fe1ad5ee
ZY		 2052static int x1000_i2c0_pins[] = { 0x38, 0x37, };
2053static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
2054static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
2055static int x1000_i2c2_pins[] = { 0x61, 0x60, };
f4b5c348
ZY		 2056static int x1000_i2s_data_tx_pins[] = { 0x24, };
2057static int x1000_i2s_data_rx_pins[] = { 0x23, };
2058static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2059static int x1000_i2s_sysclk_pins[] = { 0x20, };
28c1caaf
ZY		 2060static int x1000_dmic_if0_pins[] = { 0x35, 0x36, };
2061static int x1000_dmic_if1_pins[] = { 0x25, };
fe1ad5ee
ZY		 2062static int x1000_cim_pins[] = {
2063 0x08, 0x09, 0x0a, 0x0b,
2064 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2065};
2066static int x1000_lcd_8bit_pins[] = {
2067 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2068 0x30, 0x31, 0x32, 0x33, 0x34,
2069};
2070static int x1000_lcd_16bit_pins[] = {
2071 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2072};
2073static int x1000_pwm_pwm0_pins[] = { 0x59, };
2074static int x1000_pwm_pwm1_pins[] = { 0x5a, };
2075static int x1000_pwm_pwm2_pins[] = { 0x5b, };
2076static int x1000_pwm_pwm3_pins[] = { 0x26, };
2077static int x1000_pwm_pwm4_pins[] = { 0x58, };
2078static int x1000_mac_pins[] = {
2079 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
2080};
2081
fe1ad5ee 2082static const struct group_desc x1000_groups[] = {
bb42b593
PC		 2083 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
2084 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
2085 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
2086 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
2087 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
2088 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
2089 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
28c1caaf
ZY		 2090 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2091 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2092 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
bb42b593
PC		 2093 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
2094 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
2095 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
2096 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
2097 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
2098 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
2099 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
2100 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
2101 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
2102 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
2103 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
2104 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
2105 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
2106 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
2107 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
2108 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
2109 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
2110 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
2111 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
2112 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
2113 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
2114 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
2115 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
2116 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
2117 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
2118 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
2119 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
2120 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
2121 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
2122 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
2123 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
2124 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
2125 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
2126 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
2127 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
2128 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
28c1caaf
ZY		 2129 INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
2130 INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
bb42b593
PC		 2131 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
2132 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
2133 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
bb42b593
PC		 2134 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),
2135 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),
2136 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),
2137 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
2138 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),
2139 INGENIC_PIN_GROUP("mac", x1000_mac, 1),
fe1ad5ee
ZY		 2140};
2141
2142static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2143static const char *x1000_uart1_groups[] = {
b4a9372a 2144 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
fe1ad5ee
ZY		 2145};
2146static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
28c1caaf 2147static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
3b31e9b0
ZY		 2148static const char *x1000_ssi_groups[] = {
2149 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
2150 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
2151 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
2152 "ssi-gpc-a-20", "ssi-gpc-a-31",
2153 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
2154 "ssi-ce1-a-21", "ssi-ce1-a-30",
2155};
fe1ad5ee
ZY		 2156static const char *x1000_mmc0_groups[] = {
2157 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
2158};
2159static const char *x1000_mmc1_groups[] = {
b4a9372a 2160 "mmc1-1bit", "mmc1-4bit",
fe1ad5ee 2161};
b4a9372a
ZY		 2162static const char *x1000_emc_groups[] = {
2163 "emc-8bit-data", "emc-16bit-data",
2164 "emc-addr", "emc-rd-we", "emc-wait",
fe1ad5ee 2165};
b4a9372a
ZY		 2166static const char *x1000_cs1_groups[] = { "emc-cs1", };
2167static const char *x1000_cs2_groups[] = { "emc-cs2", };
fe1ad5ee
ZY		 2168static const char *x1000_i2c0_groups[] = { "i2c0-data", };
2169static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2170static const char *x1000_i2c2_groups[] = { "i2c2-data", };
f4b5c348
ZY		 2171static const char *x1000_i2s_groups[] = {
2172 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2173};
28c1caaf 2174static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
fe1ad5ee 2175static const char *x1000_cim_groups[] = { "cim-data", };
5e6332a7 2176static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
fe1ad5ee
ZY		 2177static const char *x1000_pwm0_groups[] = { "pwm0", };
2178static const char *x1000_pwm1_groups[] = { "pwm1", };
2179static const char *x1000_pwm2_groups[] = { "pwm2", };
2180static const char *x1000_pwm3_groups[] = { "pwm3", };
2181static const char *x1000_pwm4_groups[] = { "pwm4", };
2182static const char *x1000_mac_groups[] = { "mac", };
2183
2184static const struct function_desc x1000_functions[] = {
2185 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
2186 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
2187 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
3b31e9b0
ZY		 2188 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
2189 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
fe1ad5ee
ZY		 2190 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
2191 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
b4a9372a
ZY		 2192 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
2193 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
2194 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
fe1ad5ee
ZY		 2195 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
2196 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
2197 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
f4b5c348 2198 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
6adf2c56 2199 { "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), },
fe1ad5ee
ZY		 2200 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
2201 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
2202 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
2203 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
2204 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
2205 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
2206 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
2207 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
2208};
2209
9279c00f
AM		 2210static const struct regmap_range x1000_access_ranges[] = {
2211 regmap_reg_range(0x000, 0x400 - 4),
2212 regmap_reg_range(0x700, 0x800 - 4),
2213};
2214
2215/* shared with X1500 */
2216static const struct regmap_access_table x1000_access_table = {
2217 .yes_ranges = x1000_access_ranges,
2218 .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges),
2219};
2220
fe1ad5ee
ZY		 2221static const struct ingenic_chip_info x1000_chip_info = {
2222 .num_chips = 4,
f742e5eb 2223 .reg_offset = 0x100,
baf15647 2224 .version = ID_X1000,
fe1ad5ee
ZY		 2225 .groups = x1000_groups,
2226 .num_groups = ARRAY_SIZE(x1000_groups),
2227 .functions = x1000_functions,
2228 .num_functions = ARRAY_SIZE(x1000_functions),
2229 .pull_ups = x1000_pull_ups,
2230 .pull_downs = x1000_pull_downs,
9279c00f 2231 .access_table = &x1000_access_table,
fe1ad5ee
ZY		 2232};
2233
5d21595b
ZY		 2234static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
2235static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
2236static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
2237static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
b4a9372a 2238static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
5d21595b
ZY		 2239static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
2240static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
b4a9372a
ZY		 2241static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
2242static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
5d21595b
ZY		 2243static int x1500_i2c0_pins[] = { 0x38, 0x37, };
2244static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
2245static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
2246static int x1500_i2c2_pins[] = { 0x61, 0x60, };
f4b5c348
ZY		 2247static int x1500_i2s_data_tx_pins[] = { 0x24, };
2248static int x1500_i2s_data_rx_pins[] = { 0x23, };
2249static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2250static int x1500_i2s_sysclk_pins[] = { 0x20, };
28c1caaf
ZY		 2251static int x1500_dmic_if0_pins[] = { 0x35, 0x36, };
2252static int x1500_dmic_if1_pins[] = { 0x25, };
5d21595b
ZY		 2253static int x1500_cim_pins[] = {
2254 0x08, 0x09, 0x0a, 0x0b,
2255 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2256};
2257static int x1500_pwm_pwm0_pins[] = { 0x59, };
2258static int x1500_pwm_pwm1_pins[] = { 0x5a, };
2259static int x1500_pwm_pwm2_pins[] = { 0x5b, };
2260static int x1500_pwm_pwm3_pins[] = { 0x26, };
2261static int x1500_pwm_pwm4_pins[] = { 0x58, };
2262
5d21595b 2263static const struct group_desc x1500_groups[] = {
bb42b593
PC		 2264 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
2265 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
2266 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
2267 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
2268 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
2269 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
2270 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
28c1caaf
ZY		 2271 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2272 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2273 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
bb42b593
PC		 2274 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
2275 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
2276 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
2277 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
2278 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
2279 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
2280 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
2281 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
2282 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
2283 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
28c1caaf
ZY		 2284 INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
2285 INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
bb42b593 2286 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
bb42b593
PC		 2287 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
2288 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
2289 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),
2290 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
2291 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),
5d21595b
ZY		 2292};
2293
2294static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2295static const char *x1500_uart1_groups[] = {
b4a9372a 2296 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
5d21595b
ZY		 2297};
2298static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
b4a9372a 2299static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
5d21595b
ZY		 2300static const char *x1500_i2c0_groups[] = { "i2c0-data", };
2301static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2302static const char *x1500_i2c2_groups[] = { "i2c2-data", };
f4b5c348
ZY		 2303static const char *x1500_i2s_groups[] = {
2304 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2305};
28c1caaf 2306static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
5d21595b 2307static const char *x1500_cim_groups[] = { "cim-data", };
5d21595b
ZY		 2308static const char *x1500_pwm0_groups[] = { "pwm0", };
2309static const char *x1500_pwm1_groups[] = { "pwm1", };
2310static const char *x1500_pwm2_groups[] = { "pwm2", };
2311static const char *x1500_pwm3_groups[] = { "pwm3", };
2312static const char *x1500_pwm4_groups[] = { "pwm4", };
2313
2314static const struct function_desc x1500_functions[] = {
2315 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
2316 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
2317 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
3b31e9b0 2318 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
b4a9372a 2319 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
5d21595b
ZY		 2320 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
2321 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
2322 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
f4b5c348 2323 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
6adf2c56 2324 { "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), },
5d21595b 2325 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
5d21595b
ZY		 2326 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
2327 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
2328 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
2329 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
2330 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
2331};
2332
2333static const struct ingenic_chip_info x1500_chip_info = {
2334 .num_chips = 4,
f742e5eb 2335 .reg_offset = 0x100,
baf15647 2336 .version = ID_X1500,
5d21595b
ZY		 2337 .groups = x1500_groups,
2338 .num_groups = ARRAY_SIZE(x1500_groups),
2339 .functions = x1500_functions,
2340 .num_functions = ARRAY_SIZE(x1500_functions),
2341 .pull_ups = x1000_pull_ups,
2342 .pull_downs = x1000_pull_downs,
9279c00f 2343 .access_table = &x1000_access_table,
5d21595b
ZY		 2344};
2345
d7da2a1e
ZY		 2346static const u32 x1830_pull_ups[4] = {
2347 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2348};
2349
2350static const u32 x1830_pull_downs[4] = {
2351 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2352};
2353
2354static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
2355static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
2356static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
28c1caaf
ZY		 2357static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, };
2358static int x1830_sfc_clk_pins[] = { 0x1b, };
2359static int x1830_sfc_ce_pins[] = { 0x1c, };
d7da2a1e
ZY		 2360static int x1830_ssi0_dt_pins[] = { 0x4c, };
2361static int x1830_ssi0_dr_pins[] = { 0x4b, };
2362static int x1830_ssi0_clk_pins[] = { 0x4f, };
2363static int x1830_ssi0_gpc_pins[] = { 0x4d, };
2364static int x1830_ssi0_ce0_pins[] = { 0x50, };
2365static int x1830_ssi0_ce1_pins[] = { 0x4e, };
2366static int x1830_ssi1_dt_c_pins[] = { 0x53, };
d7da2a1e 2367static int x1830_ssi1_dt_d_pins[] = { 0x62, };
11015196 2368static int x1830_ssi1_dr_c_pins[] = { 0x54, };
d7da2a1e 2369static int x1830_ssi1_dr_d_pins[] = { 0x63, };
11015196 2370static int x1830_ssi1_clk_c_pins[] = { 0x57, };
d7da2a1e 2371static int x1830_ssi1_clk_d_pins[] = { 0x66, };
11015196 2372static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
d7da2a1e 2373static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
11015196 2374static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
d7da2a1e 2375static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
11015196 2376static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
d7da2a1e
ZY		 2377static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
2378static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
2379static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
2380static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
2381static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
2382static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
2383static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
2384static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
f4b5c348
ZY		 2385static int x1830_i2s_data_tx_pins[] = { 0x53, };
2386static int x1830_i2s_data_rx_pins[] = { 0x54, };
2387static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
2388static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
2389static int x1830_i2s_sysclk_pins[] = { 0x57, };
28c1caaf
ZY		 2390static int x1830_dmic_if0_pins[] = { 0x48, 0x59, };
2391static int x1830_dmic_if1_pins[] = { 0x5a, };
5e6332a7 2392static int x1830_lcd_tft_8bit_pins[] = {
b2954743 2393 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
5e6332a7
ZY		 2394 0x68, 0x73, 0x72, 0x69,
2395};
2396static int x1830_lcd_tft_24bit_pins[] = {
2397 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71,
2398 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b,
b2954743
ZY		 2399};
2400static int x1830_lcd_slcd_8bit_pins[] = {
2401 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
2402 0x69, 0x72, 0x73, 0x7b, 0x7a,
2403};
2404static int x1830_lcd_slcd_16bit_pins[] = {
2405 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
2406};
d7da2a1e
ZY		 2407static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
2408static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
2409static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
2410static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
2411static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
2412static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
2413static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
2414static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
2415static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
2416static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
2417static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
2418static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
2419static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
2420static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
2421static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
2422static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
2423static int x1830_mac_pins[] = {
2424 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
2425};
2426
d7da2a1e 2427static const struct group_desc x1830_groups[] = {
bb42b593
PC		 2428 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
2429 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
2430 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
28c1caaf
ZY		 2431 INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
2432 INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
2433 INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
bb42b593
PC		 2434 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
2435 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
2436 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
2437 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
2438 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
2439 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
2440 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
2441 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
2442 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
2443 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
2444 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
2445 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
2446 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
2447 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
2448 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
2449 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
2450 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
2451 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
2452 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
2453 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
2454 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
2455 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
2456 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
2457 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
2458 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
2459 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
2460 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
2461 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
2462 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
2463 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
28c1caaf
ZY		 2464 INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
2465 INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
5e6332a7
ZY		 2466 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
2467 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
bb42b593
PC		 2468 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
2469 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
bb42b593
PC		 2470 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
2471 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
2472 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
2473 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
2474 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
2475 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
2476 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
2477 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
2478 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
2479 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
2480 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
2481 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
2482 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
2483 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
2484 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
2485 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
2486 INGENIC_PIN_GROUP("mac", x1830_mac, 0),
d7da2a1e
ZY		 2487};
2488
2489static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2490static const char *x1830_uart1_groups[] = { "uart1-data", };
28c1caaf 2491static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
d7da2a1e
ZY		 2492static const char *x1830_ssi0_groups[] = {
2493 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
2494};
2495static const char *x1830_ssi1_groups[] = {
2496 "ssi1-dt-c", "ssi1-dt-d",
2497 "ssi1-dr-c", "ssi1-dr-d",
2498 "ssi1-clk-c", "ssi1-clk-d",
2499 "ssi1-gpc-c", "ssi1-gpc-d",
2500 "ssi1-ce0-c", "ssi1-ce0-d",
2501 "ssi1-ce1-c", "ssi1-ce1-d",
2502};
2503static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
2504static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2505static const char *x1830_i2c0_groups[] = { "i2c0-data", };
2506static const char *x1830_i2c1_groups[] = { "i2c1-data", };
2507static const char *x1830_i2c2_groups[] = { "i2c2-data", };
f4b5c348
ZY		 2508static const char *x1830_i2s_groups[] = {
2509 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
2510};
28c1caaf 2511static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
b2954743 2512static const char *x1830_lcd_groups[] = {
5e6332a7 2513 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
b2954743 2514};
d7da2a1e
ZY		 2515static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
2516static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
2517static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
2518static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
2519static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
2520static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
2521static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
2522static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2523static const char *x1830_mac_groups[] = { "mac", };
2524
2525static const struct function_desc x1830_functions[] = {
2526 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
2527 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
2528 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
2529 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
2530 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
2531 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
2532 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
2533 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
2534 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
2535 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
f4b5c348 2536 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
6adf2c56 2537 { "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), },
b2954743 2538 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
d7da2a1e
ZY		 2539 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
2540 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
2541 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
2542 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
2543 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2544 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2545 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2546 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2547 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
2548};
2549
9279c00f
AM		 2550static const struct regmap_range x1830_access_ranges[] = {
2551 regmap_reg_range(0x0000, 0x4000 - 4),
2552 regmap_reg_range(0x7000, 0x8000 - 4),
2553};
2554
2555static const struct regmap_access_table x1830_access_table = {
2556 .yes_ranges = x1830_access_ranges,
2557 .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges),
2558};
2559
d7da2a1e
ZY		 2560static const struct ingenic_chip_info x1830_chip_info = {
2561 .num_chips = 4,
2562 .reg_offset = 0x1000,
baf15647 2563 .version = ID_X1830,
d7da2a1e
ZY		 2564 .groups = x1830_groups,
2565 .num_groups = ARRAY_SIZE(x1830_groups),
2566 .functions = x1830_functions,
2567 .num_functions = ARRAY_SIZE(x1830_functions),
2568 .pull_ups = x1830_pull_ups,
2569 .pull_downs = x1830_pull_downs,
9279c00f 2570 .access_table = &x1830_access_table,
d7da2a1e
ZY		 2571};
2572
943e0da1
ZY		 2573static const u32 x2000_pull_ups[5] = {
2574 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f,
2575};
2576
2577static const u32 x2000_pull_downs[5] = {
2578 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f,
2579};
2580
2581static int x2000_uart0_data_pins[] = { 0x77, 0x78, };
2582static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, };
2583static int x2000_uart1_data_pins[] = { 0x57, 0x58, };
2584static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, };
2585static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, };
2586static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, };
2587static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, };
2588static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, };
2589static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, };
2590static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, };
2591static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, };
2592static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, };
2593static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, };
2594static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, };
2595static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, };
2596static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, };
2597static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, };
2598static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };
2599static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };
2600static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };
2601static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };
28c1caaf
ZY		 2602static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, };
2603static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, };
2604static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2605static int x2000_sfc_clk_d_pins[] = { 0x71, };
2606static int x2000_sfc_clk_e_pins[] = { 0x90, };
2607static int x2000_sfc_ce_d_pins[] = { 0x72, };
2608static int x2000_sfc_ce_e_pins[] = { 0x91, };
943e0da1
ZY		 2609static int x2000_ssi0_dt_b_pins[] = { 0x3e, };
2610static int x2000_ssi0_dt_d_pins[] = { 0x69, };
2611static int x2000_ssi0_dr_b_pins[] = { 0x3d, };
2612static int x2000_ssi0_dr_d_pins[] = { 0x6a, };
2613static int x2000_ssi0_clk_b_pins[] = { 0x3f, };
2614static int x2000_ssi0_clk_d_pins[] = { 0x68, };
28c1caaf
ZY		 2615static int x2000_ssi0_ce_b_pins[] = { 0x3c, };
2616static int x2000_ssi0_ce_d_pins[] = { 0x6d, };
943e0da1
ZY		 2617static int x2000_ssi1_dt_c_pins[] = { 0x4b, };
2618static int x2000_ssi1_dt_d_pins[] = { 0x72, };
2619static int x2000_ssi1_dt_e_pins[] = { 0x91, };
2620static int x2000_ssi1_dr_c_pins[] = { 0x4a, };
2621static int x2000_ssi1_dr_d_pins[] = { 0x73, };
2622static int x2000_ssi1_dr_e_pins[] = { 0x92, };
2623static int x2000_ssi1_clk_c_pins[] = { 0x4c, };
2624static int x2000_ssi1_clk_d_pins[] = { 0x71, };
2625static int x2000_ssi1_clk_e_pins[] = { 0x90, };
28c1caaf
ZY		 2626static int x2000_ssi1_ce_c_pins[] = { 0x49, };
2627static int x2000_ssi1_ce_d_pins[] = { 0x76, };
2628static int x2000_ssi1_ce_e_pins[] = { 0x95, };
943e0da1
ZY		 2629static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };
2630static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };
2631static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2632static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, };
2633static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
2634static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, };
2635static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, };
2636static int x2000_emc_8bit_data_pins[] = {
2637 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2638};
2639static int x2000_emc_16bit_data_pins[] = {
2640 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
2641};
2642static int x2000_emc_addr_pins[] = {
2643 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2644 0x28, 0x29, 0x2a, 0x2b, 0x2c,
2645};
2646static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, };
2647static int x2000_emc_wait_pins[] = { 0x2f, };
2648static int x2000_emc_cs1_pins[] = { 0x57, };
2649static int x2000_emc_cs2_pins[] = { 0x58, };
2650static int x2000_i2c0_pins[] = { 0x4e, 0x4d, };
2651static int x2000_i2c1_c_pins[] = { 0x58, 0x57, };
2652static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, };
2653static int x2000_i2c2_b_pins[] = { 0x37, 0x36, };
2654static int x2000_i2c2_d_pins[] = { 0x75, 0x74, };
2655static int x2000_i2c2_e_pins[] = { 0x94, 0x93, };
2656static int x2000_i2c3_a_pins[] = { 0x11, 0x10, };
2657static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, };
2658static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, };
2659static int x2000_i2c4_d_pins[] = { 0x61, 0x60, };
2660static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, };
2661static int x2000_i2c5_d_pins[] = { 0x65, 0x64, };
2662static int x2000_i2s1_data_tx_pins[] = { 0x47, };
2663static int x2000_i2s1_data_rx_pins[] = { 0x44, };
2664static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, };
2665static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, };
2666static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, };
2667static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, };
2668static int x2000_i2s2_data_rx0_pins[] = { 0x0a, };
2669static int x2000_i2s2_data_rx1_pins[] = { 0x0b, };
2670static int x2000_i2s2_data_rx2_pins[] = { 0x0c, };
2671static int x2000_i2s2_data_rx3_pins[] = { 0x0d, };
2672static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, };
2673static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, };
2674static int x2000_i2s3_data_tx0_pins[] = { 0x03, };
2675static int x2000_i2s3_data_tx1_pins[] = { 0x04, };
2676static int x2000_i2s3_data_tx2_pins[] = { 0x05, };
2677static int x2000_i2s3_data_tx3_pins[] = { 0x06, };
2678static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, };
2679static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, };
28c1caaf
ZY		 2680static int x2000_dmic_if0_pins[] = { 0x54, 0x55, };
2681static int x2000_dmic_if1_pins[] = { 0x56, };
2682static int x2000_dmic_if2_pins[] = { 0x57, };
2683static int x2000_dmic_if3_pins[] = { 0x58, };
943e0da1
ZY		 2684static int x2000_cim_8bit_pins[] = {
2685 0x0e, 0x0c, 0x0d, 0x4f,
2686 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2687};
2688static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, };
2689static int x2000_lcd_tft_8bit_pins[] = {
2690 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2691 0x38, 0x3a, 0x39, 0x3b,
2692};
2693static int x2000_lcd_tft_16bit_pins[] = {
2694 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2695};
2696static int x2000_lcd_tft_18bit_pins[] = {
2697 0x30, 0x31,
2698};
2699static int x2000_lcd_tft_24bit_pins[] = {
2700 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2701};
2702static int x2000_lcd_slcd_8bit_pins[] = {
2703 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2704 0x3a, 0x38, 0x3b, 0x30, 0x39,
2705};
2706static int x2000_pwm_pwm0_c_pins[] = { 0x40, };
2707static int x2000_pwm_pwm0_d_pins[] = { 0x7e, };
2708static int x2000_pwm_pwm1_c_pins[] = { 0x41, };
2709static int x2000_pwm_pwm1_d_pins[] = { 0x7f, };
2710static int x2000_pwm_pwm2_c_pins[] = { 0x42, };
2711static int x2000_pwm_pwm2_e_pins[] = { 0x80, };
2712static int x2000_pwm_pwm3_c_pins[] = { 0x43, };
2713static int x2000_pwm_pwm3_e_pins[] = { 0x81, };
2714static int x2000_pwm_pwm4_c_pins[] = { 0x44, };
2715static int x2000_pwm_pwm4_e_pins[] = { 0x82, };
2716static int x2000_pwm_pwm5_c_pins[] = { 0x45, };
2717static int x2000_pwm_pwm5_e_pins[] = { 0x83, };
2718static int x2000_pwm_pwm6_c_pins[] = { 0x46, };
2719static int x2000_pwm_pwm6_e_pins[] = { 0x84, };
2720static int x2000_pwm_pwm7_c_pins[] = { 0x47, };
2721static int x2000_pwm_pwm7_e_pins[] = { 0x85, };
2722static int x2000_pwm_pwm8_pins[] = { 0x48, };
2723static int x2000_pwm_pwm9_pins[] = { 0x49, };
2724static int x2000_pwm_pwm10_pins[] = { 0x4a, };
2725static int x2000_pwm_pwm11_pins[] = { 0x4b, };
2726static int x2000_pwm_pwm12_pins[] = { 0x4c, };
2727static int x2000_pwm_pwm13_pins[] = { 0x4d, };
2728static int x2000_pwm_pwm14_pins[] = { 0x4e, };
2729static int x2000_pwm_pwm15_pins[] = { 0x4f, };
2730static int x2000_mac0_rmii_pins[] = {
2731 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41,
2732};
2733static int x2000_mac0_rgmii_pins[] = {
2734 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42,
2735 0x4c, 0x4d, 0x4f, 0x4e, 0x41,
2736};
2737static int x2000_mac1_rmii_pins[] = {
2738 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37,
2739};
2740static int x2000_mac1_rgmii_pins[] = {
2741 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28,
2742 0x33, 0x34, 0x36, 0x35, 0x37,
2743};
2744static int x2000_otg_pins[] = { 0x96, };
2745
2746static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, };
2747
2748static const struct group_desc x2000_groups[] = {
2749 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
2750 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
2751 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
2752 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
2753 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
2754 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
2755 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
2756 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
2757 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
2758 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
2759 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
2760 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
2761 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
2762 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
2763 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
2764 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
2765 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
2766 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
2767 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
2768 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
2769 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
28c1caaf
ZY		 2770 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
2771 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
2772 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
2773 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
2774 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
2775 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
2776 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
943e0da1
ZY		 2777 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
2778 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
2779 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
2780 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
2781 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
2782 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
28c1caaf
ZY		 2783 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
2784 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
943e0da1
ZY		 2785 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
2786 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
2787 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
2788 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
2789 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
2790 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
2791 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
2792 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
2793 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
28c1caaf
ZY		 2794 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
2795 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
2796 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
943e0da1
ZY		 2797 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
2798 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
2799 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
2800 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
2801 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
2802 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
2803 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
2804 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
2805 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
2806 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
2807 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
2808 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
2809 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
2810 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
2811 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
2812 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
2813 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
2814 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
2815 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
2816 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
2817 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
2818 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
2819 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
2820 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
2821 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
2822 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
2823 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
2824 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
2825 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
2826 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
2827 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
2828 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
2829 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
2830 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
2831 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
2832 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
2833 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
2834 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
2835 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
2836 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
2837 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
2838 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
2839 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
2840 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
28c1caaf
ZY		 2841 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
2842 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
2843 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
2844 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
943e0da1
ZY		 2845 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
2846 x2000_cim_8bit_funcs),
2847 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
2848 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
2849 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
2850 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
2851 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
2852 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
2853 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
2854 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
2855 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
2856 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
2857 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
2858 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
2859 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
2860 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
2861 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
2862 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
2863 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
2864 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
2865 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
2866 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
2867 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
2868 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
2869 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
2870 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
2871 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
2872 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
2873 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
2874 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
2875 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
2876 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
2877 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
2878 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
2879 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
2880 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
2881 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
2882 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
2883};
2884
2885static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2886static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2887static const char *x2000_uart2_groups[] = { "uart2-data", };
2888static const char *x2000_uart3_groups[] = {
2889 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
2890};
2891static const char *x2000_uart4_groups[] = {
2892 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
2893};
2894static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
2895static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
2896static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
2897static const char *x2000_uart8_groups[] = { "uart8-data", };
2898static const char *x2000_uart9_groups[] = { "uart9-data", };
28c1caaf
ZY		 2899static const char *x2000_sfc_groups[] = {
2900 "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
2901 "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
2902};
943e0da1
ZY		 2903static const char *x2000_ssi0_groups[] = {
2904 "ssi0-dt-b", "ssi0-dt-d",
2905 "ssi0-dr-b", "ssi0-dr-d",
2906 "ssi0-clk-b", "ssi0-clk-d",
28c1caaf 2907 "ssi0-ce-b", "ssi0-ce-d",
943e0da1
ZY		 2908};
2909static const char *x2000_ssi1_groups[] = {
2910 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
2911 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
2912 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
28c1caaf 2913 "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
943e0da1
ZY		 2914};
2915static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
2916static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2917static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
2918static const char *x2000_emc_groups[] = {
2919 "emc-8bit-data", "emc-16bit-data",
2920 "emc-addr", "emc-rd-we", "emc-wait",
2921};
2922static const char *x2000_cs1_groups[] = { "emc-cs1", };
2923static const char *x2000_cs2_groups[] = { "emc-cs2", };
2924static const char *x2000_i2c0_groups[] = { "i2c0-data", };
2925static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
2926static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
2927static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
2928static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
2929static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
2930static const char *x2000_i2s1_groups[] = {
2931 "i2s1-data-tx", "i2s1-data-rx",
2932 "i2s1-clk-tx", "i2s1-clk-rx",
2933 "i2s1-sysclk-tx", "i2s1-sysclk-rx",
2934};
2935static const char *x2000_i2s2_groups[] = {
2936 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
2937 "i2s2-clk-rx", "i2s2-sysclk-rx",
2938};
2939static const char *x2000_i2s3_groups[] = {
2940 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
2941 "i2s3-clk-tx", "i2s3-sysclk-tx",
2942};
28c1caaf
ZY		 2943static const char *x2000_dmic_groups[] = {
2944 "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
2945};
943e0da1
ZY		 2946static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
2947static const char *x2000_lcd_groups[] = {
2948 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
2949 "lcd-slcd-8bit", "lcd-slcd-16bit",
2950};
2951static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
2952static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
2953static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
2954static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
2955static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
2956static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
2957static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
2958static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
2959static const char *x2000_pwm8_groups[] = { "pwm8", };
2960static const char *x2000_pwm9_groups[] = { "pwm9", };
2961static const char *x2000_pwm10_groups[] = { "pwm10", };
2962static const char *x2000_pwm11_groups[] = { "pwm11", };
2963static const char *x2000_pwm12_groups[] = { "pwm12", };
2964static const char *x2000_pwm13_groups[] = { "pwm13", };
2965static const char *x2000_pwm14_groups[] = { "pwm14", };
2966static const char *x2000_pwm15_groups[] = { "pwm15", };
2967static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
2968static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
2969static const char *x2000_otg_groups[] = { "otg-vbus", };
2970
2971static const struct function_desc x2000_functions[] = {
2972 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
2973 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
2974 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
2975 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
2976 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
2977 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
2978 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
2979 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
2980 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
2981 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
2982 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
2983 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
2984 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
2985 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
2986 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
2987 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
2988 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
2989 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
2990 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
2991 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
2992 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
2993 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
2994 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
2995 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
2996 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
2997 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
2998 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
2999 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
3000 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
3001 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
3002 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
3003 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
3004 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
3005 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
3006 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
3007 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
3008 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
3009 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
3010 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
3011 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
3012 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
3013 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
3014 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
3015 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
3016 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
3017 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
3018 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
3019 { "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), },
3020 { "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), },
3021 { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), },
3022};
3023
9279c00f
AM		 3024static const struct regmap_range x2000_access_ranges[] = {
3025 regmap_reg_range(0x000, 0x500 - 4),
3026 regmap_reg_range(0x700, 0x800 - 4),
3027};
3028
3029/* shared with X2100 */
3030static const struct regmap_access_table x2000_access_table = {
3031 .yes_ranges = x2000_access_ranges,
3032 .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges),
3033};
3034
943e0da1
ZY		 3035static const struct ingenic_chip_info x2000_chip_info = {
3036 .num_chips = 5,
3037 .reg_offset = 0x100,
3038 .version = ID_X2000,
3039 .groups = x2000_groups,
3040 .num_groups = ARRAY_SIZE(x2000_groups),
3041 .functions = x2000_functions,
3042 .num_functions = ARRAY_SIZE(x2000_functions),
3043 .pull_ups = x2000_pull_ups,
3044 .pull_downs = x2000_pull_downs,
9279c00f 3045 .access_table = &x2000_access_table,
943e0da1
ZY		 3046};
3047
2a18211b
ZY		 3048static const u32 x2100_pull_ups[5] = {
3049 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f,
3050};
3051
3052static const u32 x2100_pull_downs[5] = {
3053 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f,
3054};
3055
3056static int x2100_mac_pins[] = {
3057 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41,
3058};
3059
3060static const struct group_desc x2100_groups[] = {
3061 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
3062 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
3063 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3064 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3065 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3066 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3067 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3068 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3069 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3070 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3071 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3072 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3073 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3074 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3075 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3076 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3077 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3078 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3079 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3080 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3081 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3082 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3083 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3084 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3085 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3086 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3087 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3088 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3089 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3090 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3091 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3092 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3093 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3094 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3095 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3096 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3097 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3098 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3099 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3100 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3101 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3102 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3103 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3104 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3105 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3106 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3107 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3108 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3109 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3110 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3111 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3112 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3113 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3114 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3115 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3116 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3117 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3118 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3119 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3120 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3121 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3122 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3123 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3124 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3125 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3126 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3127 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3128 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3129 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3130 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3131 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3132 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3133 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3134 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3135 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3136 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3137 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3138 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3139 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3140 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3141 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3142 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3143 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3144 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3145 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3146 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3147 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3148 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3149 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3150 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3151 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3152 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3153 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3154 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3155 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3156 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3157 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3158 x2000_cim_8bit_funcs),
3159 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3160 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3161 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3162 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3163 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3164 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3165 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3166 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3167 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3168 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3169 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3170 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3171 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3172 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3173 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3174 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3175 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3176 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3177 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3178 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3179 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3180 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3181 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3182 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
3183 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
3184 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
3185 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
3186 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
3187 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
3188 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
3189 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
3190 INGENIC_PIN_GROUP("mac", x2100_mac, 1),
3191};
3192
3193static const char *x2100_mac_groups[] = { "mac", };
3194
3195static const struct function_desc x2100_functions[] = {
3196 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
3197 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
3198 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
3199 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
3200 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
3201 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
3202 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
3203 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
3204 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
3205 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
3206 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
3207 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
3208 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
3209 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
3210 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
3211 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
3212 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
3213 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
3214 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
3215 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
3216 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
3217 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
3218 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
3219 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
3220 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
3221 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
3222 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
3223 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
3224 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
3225 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
3226 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
3227 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
3228 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
3229 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
3230 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
3231 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
3232 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
3233 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
3234 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
3235 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
3236 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
3237 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
3238 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
3239 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
3240 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
3241 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
3242 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
3243 { "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), },
3244};
3245
3246static const struct ingenic_chip_info x2100_chip_info = {
3247 .num_chips = 5,
3248 .reg_offset = 0x100,
3249 .version = ID_X2100,
3250 .groups = x2100_groups,
3251 .num_groups = ARRAY_SIZE(x2100_groups),
3252 .functions = x2100_functions,
3253 .num_functions = ARRAY_SIZE(x2100_functions),
3254 .pull_ups = x2100_pull_ups,
3255 .pull_downs = x2100_pull_downs,
9279c00f 3256 .access_table = &x2000_access_table,
2a18211b
ZY		 3257};
3258
b71c1844 3259static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
e72394e2
PC		 3260{
3261 unsigned int val;
3262
3263 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
3264
3265 return (u32) val;
3266}
3267
b71c1844 3268static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
e72394e2
PC		 3269 u8 reg, u8 offset, bool set)
3270{
8d2d607c 3271 if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
424f3969
ZY		 3272 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,
3273 BIT(offset), set ? BIT(offset) : 0);
3274 return;
3275 }
3276
e72394e2
PC		 3277 if (set)
3278 reg = REG_SET(reg);
3279 else
3280 reg = REG_CLEAR(reg);
3281
3282 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
3283}
3284
fe1ad5ee
ZY		 3285static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
3286 u8 reg, u8 offset, bool set)
3287{
3288 if (set)
3289 reg = REG_SET(reg);
3290 else
3291 reg = REG_CLEAR(reg);
3292
d7da2a1e
ZY		 3293 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
3294 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
fe1ad5ee
ZY		 3295}
3296
3297static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
3298{
d7da2a1e
ZY		 3299 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
3300 jzgc->jzpc->info->reg_offset),
fe1ad5ee
ZY		 3301 jzgc->gc.base / PINS_PER_GPIO_CHIP);
3302}
3303
424f3969
ZY		 3304static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc,
3305 u8 reg_upper, u8 reg_lower, u8 offset, u8 value)
3306{
3307 /*
3308 * JZ4730 function and IRQ registers support two-bits-per-pin
3309 * definitions, split into two groups of 16.
3310 */
3311 u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3312 unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG;
3313 unsigned int mask = GENMASK(1, 0) << idx * 2;
3314
3315 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));
3316}
3317
e72394e2
PC		 3318static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
3319 u8 offset)
3320{
b71c1844 3321 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
e72394e2
PC		 3322
3323 return !!(val & BIT(offset));
3324}
3325
3326static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
3327 u8 offset, int value)
3328{
8d2d607c 3329 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
b4aa4876 3330 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
8d2d607c 3331 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
b71c1844 3332 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
424f3969
ZY		 3333 else
3334 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);
e72394e2
PC		 3335}
3336
3337static void irq_set_type(struct ingenic_gpio_chip *jzgc,
3338 u8 offset, unsigned int type)
3339{
3340 u8 reg1, reg2;
943e0da1 3341 bool val1, val2, val3;
e72394e2
PC		 3342
3343 switch (type) {
943e0da1
ZY		 3344 case IRQ_TYPE_EDGE_BOTH:
3345 val1 = val2 = false;
3346 val3 = true;
3347 break;
e72394e2 3348 case IRQ_TYPE_EDGE_RISING:
f831f93a 3349 val1 = val2 = true;
943e0da1 3350 val3 = false;
e72394e2
PC		 3351 break;
3352 case IRQ_TYPE_EDGE_FALLING:
943e0da1 3353 val1 = val3 = false;
f831f93a 3354 val2 = true;
e72394e2
PC		 3355 break;
3356 case IRQ_TYPE_LEVEL_HIGH:
f831f93a 3357 val1 = true;
943e0da1 3358 val2 = val3 = false;
e72394e2
PC		 3359 break;
3360 case IRQ_TYPE_LEVEL_LOW:
3361 default:
943e0da1 3362 val1 = val2 = val3 = false;
e72394e2
PC		 3363 break;
3364 }
f831f93a 3365
8d2d607c 3366 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {
b4aa4876
PC		 3367 reg1 = JZ4770_GPIO_PAT1;
3368 reg2 = JZ4770_GPIO_PAT0;
8d2d607c 3369 } else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
f831f93a
PC		 3370 reg1 = JZ4740_GPIO_TRIG;
3371 reg2 = JZ4740_GPIO_DIR;
424f3969
ZY		 3372 } else {
3373 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false);
3374 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR,
3375 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1);
3376 return;
f831f93a
PC		 3377 }
3378
8d2d607c 3379 if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {
943e0da1
ZY		 3380 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3381 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3382 ingenic_gpio_shadow_set_bit_load(jzgc);
3383 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);
8d2d607c 3384 } else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {
f831f93a
PC		 3385 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3386 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3387 ingenic_gpio_shadow_set_bit_load(jzgc);
3388 } else {
3389 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
3390 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
3391 }
e72394e2
PC		 3392}
3393
3394static void ingenic_gpio_irq_mask(struct irq_data *irqd)
3395{
3396 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3397 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
4c76a7fc 3398 irq_hw_number_t irq = irqd_to_hwirq(irqd);
e72394e2 3399
8d2d607c 3400 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
424f3969
ZY		 3401 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
3402 else
3403 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);
e72394e2
PC		 3404}
3405
3406static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
3407{
3408 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3409 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
4c76a7fc 3410 irq_hw_number_t irq = irqd_to_hwirq(irqd);
e72394e2 3411
8d2d607c 3412 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
424f3969
ZY		 3413 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
3414 else
3415 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);
e72394e2
PC		 3416}
3417
3418static void ingenic_gpio_irq_enable(struct irq_data *irqd)
3419{
3420 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3421 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
4c76a7fc 3422 irq_hw_number_t irq = irqd_to_hwirq(irqd);
e72394e2 3423
71f5e7b3
AM		 3424 gpiochip_enable_irq(gc, irq);
3425
8d2d607c 3426 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
b4aa4876 3427 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
8d2d607c 3428 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
b71c1844 3429 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
424f3969
ZY		 3430 else
3431 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);
e72394e2
PC		 3432
3433 ingenic_gpio_irq_unmask(irqd);
3434}
3435
3436static void ingenic_gpio_irq_disable(struct irq_data *irqd)
3437{
3438 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3439 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
4c76a7fc 3440 irq_hw_number_t irq = irqd_to_hwirq(irqd);
e72394e2
PC		 3441
3442 ingenic_gpio_irq_mask(irqd);
3443
8d2d607c 3444 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
b4aa4876 3445 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
8d2d607c 3446 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
b71c1844 3447 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
424f3969
ZY		 3448 else
3449 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
71f5e7b3
AM		 3450
3451 gpiochip_disable_irq(gc, irq);
e72394e2
PC		 3452}
3453
3454static void ingenic_gpio_irq_ack(struct irq_data *irqd)
3455{
3456 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3457 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
4c76a7fc 3458 irq_hw_number_t irq = irqd_to_hwirq(irqd);
e72394e2
PC		 3459 bool high;
3460
943e0da1 3461 if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) &&
8d2d607c 3462 !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
e72394e2
PC		 3463 /*
3464 * Switch to an interrupt for the opposite edge to the one that
3465 * triggered the interrupt being ACKed.
3466 */
3467 high = ingenic_gpio_get_value(jzgc, irq);
3468 if (high)
1c95348b 3469 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
e72394e2 3470 else
1c95348b 3471 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
e72394e2
PC		 3472 }
3473
8d2d607c 3474 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
b4aa4876 3475 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
8d2d607c 3476 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
b71c1844 3477 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
424f3969
ZY		 3478 else
3479 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);
e72394e2
PC		 3480}
3481
3482static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
3483{
3484 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3485 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
4c76a7fc 3486 irq_hw_number_t irq = irqd_to_hwirq(irqd);
e72394e2
PC		 3487
3488 switch (type) {
3489 case IRQ_TYPE_EDGE_BOTH:
3490 case IRQ_TYPE_EDGE_RISING:
3491 case IRQ_TYPE_EDGE_FALLING:
3492 irq_set_handler_locked(irqd, handle_edge_irq);
3493 break;
3494 case IRQ_TYPE_LEVEL_HIGH:
3495 case IRQ_TYPE_LEVEL_LOW:
3496 irq_set_handler_locked(irqd, handle_level_irq);
3497 break;
3498 default:
3499 irq_set_handler_locked(irqd, handle_bad_irq);
3500 }
3501
8d2d607c 3502 if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
e72394e2
PC		 3503 /*
3504 * The hardware does not support interrupts on both edges. The
3505 * best we can do is to set up a single-edge interrupt and then
3506 * switch to the opposing edge when ACKing the interrupt.
3507 */
4c76a7fc 3508 bool high = ingenic_gpio_get_value(jzgc, irq);
e72394e2 3509
1c95348b 3510 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
e72394e2
PC		 3511 }
3512
4c76a7fc 3513 irq_set_type(jzgc, irq, type);
e72394e2
PC		 3514 return 0;
3515}
3516
3517static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
3518{
3519 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3520 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3521
3522 return irq_set_irq_wake(jzgc->irq, on);
3523}
3524
3525static void ingenic_gpio_irq_handler(struct irq_desc *desc)
3526{
3527 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
3528 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3529 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
3530 unsigned long flag, i;
3531
3532 chained_irq_enter(irq_chip, desc);
3533
8d2d607c 3534 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
b4aa4876 3535 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
8d2d607c 3536 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
b71c1844 3537 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
424f3969
ZY		 3538 else
3539 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
e72394e2
PC		 3540
3541 for_each_set_bit(i, &flag, 32)
a9cb09b7 3542 generic_handle_domain_irq(gc->irq.domain, i);
e72394e2
PC		 3543 chained_irq_exit(irq_chip, desc);
3544}
3545
3546static void ingenic_gpio_set(struct gpio_chip *gc,
3547 unsigned int offset, int value)
3548{
3549 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3550
3551 ingenic_gpio_set_value(jzgc, offset, value);
3552}
3553
3554static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
3555{
3556 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3557
3558 return (int) ingenic_gpio_get_value(jzgc, offset);
3559}
3560
3561static int ingenic_gpio_direction_input(struct gpio_chip *gc,
3562 unsigned int offset)
3563{
3564 return pinctrl_gpio_direction_input(gc->base + offset);
3565}
3566
3567static int ingenic_gpio_direction_output(struct gpio_chip *gc,
3568 unsigned int offset, int value)
3569{
3570 ingenic_gpio_set(gc, offset, value);
3571 return pinctrl_gpio_direction_output(gc->base + offset);
3572}
3573
b5c23aa4 3574static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
943e0da1 3575 unsigned int pin, unsigned int reg, bool set)
b5c23aa4
PC		 3576{
3577 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3578 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3579
424f3969 3580 if (set) {
8d2d607c 3581 if (is_soc_or_above(jzpc, ID_JZ4740))
424f3969
ZY		 3582 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3583 REG_SET(reg), BIT(idx));
3584 else
3585 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +
3586 reg, BIT(idx));
3587 } else {
8d2d607c 3588 if (is_soc_or_above(jzpc, ID_JZ4740))
424f3969
ZY		 3589 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3590 REG_CLEAR(reg), BIT(idx));
3591 else
3592 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +
3593 reg, BIT(idx));
3594 }
b5c23aa4
PC		 3595}
3596
fe1ad5ee
ZY		 3597static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
3598 unsigned int pin, u8 reg, bool set)
3599{
3600 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3601
f742e5eb 3602 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
fe1ad5ee
ZY		 3603 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
3604}
3605
3606static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
3607 unsigned int pin)
3608{
d7da2a1e
ZY		 3609 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
3610 pin / PINS_PER_GPIO_CHIP);
fe1ad5ee
ZY		 3611}
3612
424f3969
ZY		 3613static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc,
3614 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value)
3615{
3616 /*
3617 * JZ4730 function and IRQ registers support two-bits-per-pin
3618 * definitions, split into two groups of 16.
3619 */
3620 unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG;
3621 unsigned int mask = GENMASK(1, 0) << idx * 2;
3622 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3623 u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3624
3625 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,
3626 mask, value << (idx * 2));
3627}
3628
b5c23aa4 3629static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
943e0da1 3630 unsigned int pin, unsigned int reg)
b5c23aa4
PC		 3631{
3632 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3633 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3634 unsigned int val;
3635
f742e5eb 3636 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
b5c23aa4
PC		 3637
3638 return val & BIT(idx);
3639}
3640
ebd66514
PC		 3641static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
3642{
3643 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3644 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
3645 unsigned int pin = gc->base + offset;
3646
8d2d607c 3647 if (is_soc_or_above(jzpc, ID_JZ4770)) {
b4aa4876
PC		 3648 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||
3649 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))
3c827873
MV		 3650 return GPIO_LINE_DIRECTION_IN;
3651 return GPIO_LINE_DIRECTION_OUT;
8d2d607c 3652 } else if (!is_soc_or_above(jzpc, ID_JZ4740)) {
424f3969
ZY		 3653 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR))
3654 return GPIO_LINE_DIRECTION_IN;
3655 return GPIO_LINE_DIRECTION_OUT;
3c827873 3656 }
ebd66514
PC		 3657
3658 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
3c827873
MV		 3659 return GPIO_LINE_DIRECTION_IN;
3660
3661 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
3662 return GPIO_LINE_DIRECTION_OUT;
ebd66514 3663
3c827873 3664 return GPIO_LINE_DIRECTION_IN;
ebd66514
PC		 3665}
3666
5bf7b849 3667static const struct pinctrl_ops ingenic_pctlops = {
b5c23aa4
PC		 3668 .get_groups_count = pinctrl_generic_get_group_count,
3669 .get_group_name = pinctrl_generic_get_group_name,
3670 .get_group_pins = pinctrl_generic_get_group_pins,
3671 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
3672 .dt_free_map = pinconf_generic_dt_free_map,
3673};
3674
9a0f1341
PC		 3675static int ingenic_gpio_irq_request(struct irq_data *data)
3676{
3677 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
4c76a7fc 3678 irq_hw_number_t irq = irqd_to_hwirq(data);
9a0f1341
PC		 3679 int ret;
3680
4c76a7fc 3681 ret = ingenic_gpio_direction_input(gpio_chip, irq);
9a0f1341
PC		 3682 if (ret)
3683 return ret;
3684
4c76a7fc 3685 return gpiochip_reqres_irq(gpio_chip, irq);
9a0f1341
PC		 3686}
3687
3688static void ingenic_gpio_irq_release(struct irq_data *data)
3689{
3690 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
4c76a7fc 3691 irq_hw_number_t irq = irqd_to_hwirq(data);
9a0f1341 3692
4c76a7fc 3693 return gpiochip_relres_irq(gpio_chip, irq);
9a0f1341
PC		 3694}
3695
71f5e7b3
AM		 3696static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
3697{
3698 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3699
3700 seq_printf(p, "%s", gpio_chip->label);
3701}
3702
3703static const struct irq_chip ingenic_gpio_irqchip = {
3704 .irq_enable = ingenic_gpio_irq_enable,
3705 .irq_disable = ingenic_gpio_irq_disable,
3706 .irq_unmask = ingenic_gpio_irq_unmask,
3707 .irq_mask = ingenic_gpio_irq_mask,
3708 .irq_ack = ingenic_gpio_irq_ack,
3709 .irq_set_type = ingenic_gpio_irq_set_type,
3710 .irq_set_wake = ingenic_gpio_irq_set_wake,
3711 .irq_request_resources = ingenic_gpio_irq_request,
3712 .irq_release_resources = ingenic_gpio_irq_release,
3713 .irq_print_chip = ingenic_gpio_irq_print_chip,
3714 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
3715};
3716
b5c23aa4
PC		 3717static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
3718 int pin, int func)
3719{
3720 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3721 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3722
3723 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
3724 'A' + offt, idx, func);
3725
8d2d607c 3726 if (is_soc_or_above(jzpc, ID_X1000)) {
b4aa4876 3727 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
fe1ad5ee 3728 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
b4aa4876
PC		 3729 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3730 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
fe1ad5ee 3731 ingenic_shadow_config_pin_load(jzpc, pin);
8d2d607c 3732 } else if (is_soc_or_above(jzpc, ID_JZ4770)) {
b4aa4876 3733 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
e72394e2 3734 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
b4aa4876
PC		 3735 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3736 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
8d2d607c 3737 } else if (is_soc_or_above(jzpc, ID_JZ4740)) {
b5c23aa4
PC		 3738 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
3739 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
9a85c09a 3740 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
424f3969
ZY		 3741 } else {
3742 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
3743 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func);
b5c23aa4
PC		 3744 }
3745
3746 return 0;
3747}
3748
3749static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
3750 unsigned int selector, unsigned int group)
3751{
3752 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3753 struct function_desc *func;
3754 struct group_desc *grp;
3755 unsigned int i;
bb42b593
PC		 3756 uintptr_t mode;
3757 u8 *pin_modes;
b5c23aa4
PC		 3758
3759 func = pinmux_generic_get_function(pctldev, selector);
3760 if (!func)
3761 return -EINVAL;
3762
3763 grp = pinctrl_generic_get_group(pctldev, group);
3764 if (!grp)
3765 return -EINVAL;
3766
3767 dev_dbg(pctldev->dev, "enable function %s group %s\n",
3768 func->name, grp->name);
3769
bb42b593
PC		 3770 mode = (uintptr_t)grp->data;
3771 if (mode <= 3) {
3772 for (i = 0; i < grp->num_pins; i++)
3773 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode);
3774 } else {
3775 pin_modes = grp->data;
b5c23aa4 3776
bb42b593
PC		 3777 for (i = 0; i < grp->num_pins; i++)
3778 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
b5c23aa4
PC		 3779 }
3780
3781 return 0;
3782}
3783
3784static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
3785 struct pinctrl_gpio_range *range,
3786 unsigned int pin, bool input)
3787{
3788 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3789 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3790 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3791
3792 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
3793 'A' + offt, idx, input ? "in" : "out");
3794
8d2d607c 3795 if (is_soc_or_above(jzpc, ID_X1000)) {
b4aa4876 3796 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
fe1ad5ee 3797 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
b4aa4876 3798 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
fe1ad5ee 3799 ingenic_shadow_config_pin_load(jzpc, pin);
8d2d607c 3800 } else if (is_soc_or_above(jzpc, ID_JZ4770)) {
b4aa4876 3801 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
e72394e2 3802 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
b4aa4876 3803 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
8d2d607c 3804 } else if (is_soc_or_above(jzpc, ID_JZ4740)) {
b5c23aa4 3805 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
0084a786 3806 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
b5c23aa4 3807 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
424f3969
ZY		 3808 } else {
3809 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
3810 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input);
3811 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0);
b5c23aa4
PC		 3812 }
3813
3814 return 0;
3815}
3816
5bf7b849 3817static const struct pinmux_ops ingenic_pmxops = {
b5c23aa4
PC		 3818 .get_functions_count = pinmux_generic_get_function_count,
3819 .get_function_name = pinmux_generic_get_function_name,
3820 .get_function_groups = pinmux_generic_get_function_groups,
3821 .set_mux = ingenic_pinmux_set_mux,
3822 .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
3823};
3824
3825static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
3826 unsigned int pin, unsigned long *config)
3827{
3828 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3829 enum pin_config_param param = pinconf_to_config_param(*config);
3830 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3831 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
943e0da1
ZY		 3832 unsigned int arg = 1;
3833 unsigned int bias, reg;
1d0bd580 3834 bool pull, pullup, pulldown;
b5c23aa4 3835
8d2d607c 3836 if (is_soc_or_above(jzpc, ID_X2000)) {
943e0da1
ZY		 3837 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
3838 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
3839 (jzpc->info->pull_ups[offt] & BIT(idx));
3840 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
3841 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
3842 (jzpc->info->pull_downs[offt] & BIT(idx));
3843
8d2d607c 3844 } else if (is_soc_or_above(jzpc, ID_X1830)) {
1d0bd580
ZY		 3845 unsigned int half = PINS_PER_GPIO_CHIP / 2;
3846 unsigned int idxh = (pin % half) * 2;
3847
3848 if (idx < half)
3849 regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
3850 X1830_GPIO_PEL, &bias);
3851 else
3852 regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
3853 X1830_GPIO_PEH, &bias);
3854
3855 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);
3856
3857 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx));
3858 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));
3859
3860 } else {
8d2d607c 3861 if (is_soc_or_above(jzpc, ID_JZ4770))
1d0bd580 3862 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
8d2d607c 3863 else if (is_soc_or_above(jzpc, ID_JZ4740))
1d0bd580 3864 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
424f3969
ZY		 3865 else
3866 pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR);
1d0bd580
ZY		 3867
3868 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));
3869 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));
3870 }
b5c23aa4
PC		 3871
3872 switch (param) {
3873 case PIN_CONFIG_BIAS_DISABLE:
1d0bd580 3874 if (pullup || pulldown)
b5c23aa4 3875 return -EINVAL;
943e0da1 3876
b5c23aa4
PC		 3877 break;
3878
3879 case PIN_CONFIG_BIAS_PULL_UP:
1d0bd580 3880 if (!pullup)
b5c23aa4 3881 return -EINVAL;
943e0da1 3882
b5c23aa4
PC		 3883 break;
3884
3885 case PIN_CONFIG_BIAS_PULL_DOWN:
1d0bd580 3886 if (!pulldown)
b5c23aa4 3887 return -EINVAL;
943e0da1
ZY		 3888
3889 break;
3890
3891 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
8d2d607c 3892 if (is_soc_or_above(jzpc, ID_X2000))
943e0da1 3893 reg = X2000_GPIO_SMT;
8d2d607c 3894 else if (is_soc_or_above(jzpc, ID_X1830))
943e0da1
ZY		 3895 reg = X1830_GPIO_SMT;
3896 else
3897 return -EINVAL;
3898
3899 arg = !!ingenic_get_pin_config(jzpc, pin, reg);
3900 break;
3901
3902 case PIN_CONFIG_SLEW_RATE:
8d2d607c 3903 if (is_soc_or_above(jzpc, ID_X2000))
943e0da1 3904 reg = X2000_GPIO_SR;
8d2d607c 3905 else if (is_soc_or_above(jzpc, ID_X1830))
943e0da1
ZY		 3906 reg = X1830_GPIO_SR;
3907 else
3908 return -EINVAL;
3909
3910 arg = !!ingenic_get_pin_config(jzpc, pin, reg);
b5c23aa4
PC		 3911 break;
3912
3913 default:
3914 return -ENOTSUPP;
3915 }
3916
943e0da1 3917 *config = pinconf_to_config_packed(param, arg);
b5c23aa4
PC		 3918 return 0;
3919}
3920
3921static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
d7da2a1e 3922 unsigned int pin, unsigned int bias)
b5c23aa4 3923{
8d2d607c 3924 if (is_soc_or_above(jzpc, ID_X2000)) {
943e0da1 3925 switch (bias) {
7261851e 3926 case GPIO_PULL_UP:
943e0da1
ZY		 3927 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
3928 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true);
3929 break;
3930
7261851e 3931 case GPIO_PULL_DOWN:
943e0da1
ZY		 3932 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
3933 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true);
3934 break;
3935
7261851e 3936 case GPIO_PULL_DIS:
943e0da1
ZY		 3937 default:
3938 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
3939 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
3940 }
3941
8d2d607c 3942 } else if (is_soc_or_above(jzpc, ID_X1830)) {
d7da2a1e
ZY		 3943 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3944 unsigned int half = PINS_PER_GPIO_CHIP / 2;
1d0bd580 3945 unsigned int idxh = (pin % half) * 2;
d7da2a1e
ZY		 3946 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3947
3948 if (idx < half) {
3949 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3950 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
3951 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3952 REG_SET(X1830_GPIO_PEL), bias << idxh);
3953 } else {
3954 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3955 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
3956 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3957 REG_SET(X1830_GPIO_PEH), bias << idxh);
3958 }
3959
8d2d607c 3960 } else if (is_soc_or_above(jzpc, ID_JZ4770)) {
b4aa4876 3961 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
8d2d607c 3962 } else if (is_soc_or_above(jzpc, ID_JZ4740)) {
d7da2a1e 3963 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
424f3969
ZY		 3964 } else {
3965 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias);
d7da2a1e 3966 }
b5c23aa4
PC		 3967}
3968
943e0da1
ZY		 3969static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc,
3970 unsigned int pin, bool enable)
3971{
8d2d607c 3972 if (is_soc_or_above(jzpc, ID_X2000))
943e0da1
ZY		 3973 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable);
3974 else
3975 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable);
3976}
3977
7009d046
PC		 3978static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
3979 unsigned int pin, bool high)
3980{
8d2d607c 3981 if (is_soc_or_above(jzpc, ID_JZ4770))
b4aa4876 3982 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);
8d2d607c 3983 else if (is_soc_or_above(jzpc, ID_JZ4740))
7009d046 3984 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
424f3969
ZY		 3985 else
3986 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high);
7009d046
PC		 3987}
3988
943e0da1
ZY		 3989static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc,
3990 unsigned int pin, unsigned int slew)
3991{
8d2d607c 3992 if (is_soc_or_above(jzpc, ID_X2000))
943e0da1
ZY		 3993 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew);
3994 else
3995 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew);
3996}
3997
b5c23aa4
PC		 3998static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
3999 unsigned long *configs, unsigned int num_configs)
4000{
4001 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
4002 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
4003 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
7009d046
PC		 4004 unsigned int cfg, arg;
4005 int ret;
b5c23aa4
PC		 4006
4007 for (cfg = 0; cfg < num_configs; cfg++) {
4008 switch (pinconf_to_config_param(configs[cfg])) {
4009 case PIN_CONFIG_BIAS_DISABLE:
4010 case PIN_CONFIG_BIAS_PULL_UP:
4011 case PIN_CONFIG_BIAS_PULL_DOWN:
943e0da1 4012 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
7009d046 4013 case PIN_CONFIG_OUTPUT:
943e0da1 4014 case PIN_CONFIG_SLEW_RATE:
b5c23aa4
PC		 4015 continue;
4016 default:
4017 return -ENOTSUPP;
4018 }
4019 }
4020
4021 for (cfg = 0; cfg < num_configs; cfg++) {
7009d046
PC		 4022 arg = pinconf_to_config_argument(configs[cfg]);
4023
b5c23aa4
PC		 4024 switch (pinconf_to_config_param(configs[cfg])) {
4025 case PIN_CONFIG_BIAS_DISABLE:
4026 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
4027 'A' + offt, idx);
d7da2a1e 4028 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
b5c23aa4
PC		 4029 break;
4030
4031 case PIN_CONFIG_BIAS_PULL_UP:
4032 if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
4033 return -EINVAL;
4034 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
4035 'A' + offt, idx);
d7da2a1e 4036 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
b5c23aa4
PC		 4037 break;
4038
4039 case PIN_CONFIG_BIAS_PULL_DOWN:
4040 if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
4041 return -EINVAL;
4042 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
4043 'A' + offt, idx);
d7da2a1e 4044 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
b5c23aa4
PC		 4045 break;
4046
943e0da1 4047 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
8d2d607c 4048 if (!is_soc_or_above(jzpc, ID_X1830))
943e0da1
ZY		 4049 return -EINVAL;
4050
4051 ingenic_set_schmitt_trigger(jzpc, pin, arg);
4052 break;
4053
7009d046
PC		 4054 case PIN_CONFIG_OUTPUT:
4055 ret = pinctrl_gpio_direction_output(pin);
4056 if (ret)
4057 return ret;
4058
4059 ingenic_set_output_level(jzpc, pin, arg);
4060 break;
4061
943e0da1 4062 case PIN_CONFIG_SLEW_RATE:
8d2d607c 4063 if (!is_soc_or_above(jzpc, ID_X1830))
943e0da1
ZY		 4064 return -EINVAL;
4065
4066 ingenic_set_slew_rate(jzpc, pin, arg);
4067 break;
4068
b5c23aa4 4069 default:
d6d43a92
JP		 4070 /* unreachable */
4071 break;
b5c23aa4
PC		 4072 }
4073 }
4074
4075 return 0;
4076}
4077
4078static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
4079 unsigned int group, unsigned long *config)
4080{
4081 const unsigned int *pins;
4082 unsigned int i, npins, old = 0;
4083 int ret;
4084
4085 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
4086 if (ret)
4087 return ret;
4088
4089 for (i = 0; i < npins; i++) {
4090 if (ingenic_pinconf_get(pctldev, pins[i], config))
4091 return -ENOTSUPP;
4092
4093 /* configs do not match between two pins */
4094 if (i && (old != *config))
4095 return -ENOTSUPP;
4096
4097 old = *config;
4098 }
4099
4100 return 0;
4101}
4102
4103static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
4104 unsigned int group, unsigned long *configs,
4105 unsigned int num_configs)
4106{
4107 const unsigned int *pins;
4108 unsigned int i, npins;
4109 int ret;
4110
4111 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
4112 if (ret)
4113 return ret;
4114
4115 for (i = 0; i < npins; i++) {
4116 ret = ingenic_pinconf_set(pctldev,
4117 pins[i], configs, num_configs);
4118 if (ret)
4119 return ret;
4120 }
4121
4122 return 0;
4123}
4124
5bf7b849 4125static const struct pinconf_ops ingenic_confops = {
b5c23aa4
PC		 4126 .is_generic = true,
4127 .pin_config_get = ingenic_pinconf_get,
4128 .pin_config_set = ingenic_pinconf_set,
4129 .pin_config_group_get = ingenic_pinconf_group_get,
4130 .pin_config_group_set = ingenic_pinconf_group_set,
4131};
4132
4133static const struct regmap_config ingenic_pinctrl_regmap_config = {
4134 .reg_bits = 32,
4135 .val_bits = 32,
4136 .reg_stride = 4,
4137};
4138
28c1caaf
ZY		 4139static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {
4140 { .compatible = "ingenic,jz4730-gpio" },
4141 { .compatible = "ingenic,jz4740-gpio" },
4142 { .compatible = "ingenic,jz4725b-gpio" },
4143 { .compatible = "ingenic,jz4750-gpio" },
4144 { .compatible = "ingenic,jz4755-gpio" },
4145 { .compatible = "ingenic,jz4760-gpio" },
4146 { .compatible = "ingenic,jz4770-gpio" },
4147 { .compatible = "ingenic,jz4775-gpio" },
4148 { .compatible = "ingenic,jz4780-gpio" },
4149 { .compatible = "ingenic,x1000-gpio" },
4150 { .compatible = "ingenic,x1830-gpio" },
4151 { .compatible = "ingenic,x2000-gpio" },
2a18211b 4152 { .compatible = "ingenic,x2100-gpio" },
e72394e2
PC		 4153 {},
4154};
4155
4156static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
8c943137 4157 struct fwnode_handle *fwnode)
e72394e2
PC		 4158{
4159 struct ingenic_gpio_chip *jzgc;
4160 struct device *dev = jzpc->dev;
142b8767 4161 struct gpio_irq_chip *girq;
e72394e2
PC		 4162 unsigned int bank;
4163 int err;
4164
8c943137 4165 err = fwnode_property_read_u32(fwnode, "reg", &bank);
e72394e2
PC		 4166 if (err) {
4167 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
4168 return err;
4169 }
4170
4171 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
4172 if (!jzgc)
4173 return -ENOMEM;
4174
4175 jzgc->jzpc = jzpc;
f742e5eb 4176 jzgc->reg_base = bank * jzpc->info->reg_offset;
e72394e2
PC		 4177
4178 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
4179 if (!jzgc->gc.label)
4180 return -ENOMEM;
4181
4182 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
4183 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
4184 * <linux/gpio/consumer.h> INSTEAD.
4185 */
4186 jzgc->gc.base = bank * 32;
4187
4188 jzgc->gc.ngpio = 32;
4189 jzgc->gc.parent = dev;
8c943137 4190 jzgc->gc.fwnode = fwnode;
e72394e2
PC		 4191 jzgc->gc.owner = THIS_MODULE;
4192
4193 jzgc->gc.set = ingenic_gpio_set;
4194 jzgc->gc.get = ingenic_gpio_get;
4195 jzgc->gc.direction_input = ingenic_gpio_direction_input;
4196 jzgc->gc.direction_output = ingenic_gpio_direction_output;
ebd66514 4197 jzgc->gc.get_direction = ingenic_gpio_get_direction;
d6471d6e
TR		 4198 jzgc->gc.request = gpiochip_generic_request;
4199 jzgc->gc.free = gpiochip_generic_free;
e72394e2 4200
8c943137
AS		 4201 err = fwnode_irq_get(fwnode, 0);
4202 if (err < 0)
4203 return err;
4204 if (!err)
e72394e2 4205 return -EINVAL;
8c943137 4206 jzgc->irq = err;
e72394e2 4207
142b8767 4208 girq = &jzgc->gc.irq;
71f5e7b3 4209 gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip);
142b8767
LW		 4210 girq->parent_handler = ingenic_gpio_irq_handler;
4211 girq->num_parents = 1;
4212 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
4213 GFP_KERNEL);
4214 if (!girq->parents)
4215 return -ENOMEM;
943e0da1 4216
142b8767
LW		 4217 girq->parents[0] = jzgc->irq;
4218 girq->default_type = IRQ_TYPE_NONE;
4219 girq->handler = handle_level_irq;
4220
4221 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
e72394e2
PC		 4222 if (err)
4223 return err;
4224
e72394e2
PC		 4225 return 0;
4226}
4227
4717b11f 4228static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
b5c23aa4
PC		 4229{
4230 struct device *dev = &pdev->dev;
4231 struct ingenic_pinctrl *jzpc;
4232 struct pinctrl_desc *pctl_desc;
4233 void __iomem *base;
b5c23aa4 4234 const struct ingenic_chip_info *chip_info;
6626a76e 4235 struct regmap_config regmap_config;
8c943137 4236 struct fwnode_handle *fwnode;
b5c23aa4
PC		 4237 unsigned int i;
4238 int err;
4239
8c943137 4240 chip_info = device_get_match_data(dev);
9aa35178
PC		 4241 if (!chip_info) {
4242 dev_err(dev, "Unsupported SoC\n");
4243 return -EINVAL;
4244 }
4245
b5c23aa4
PC		 4246 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
4247 if (!jzpc)
4248 return -ENOMEM;
4249
94f7a2cb 4250 base = devm_platform_ioremap_resource(pdev, 0);
119fcf47 4251 if (IS_ERR(base))
b5c23aa4 4252 return PTR_ERR(base);
b5c23aa4 4253
6626a76e 4254 regmap_config = ingenic_pinctrl_regmap_config;
9279c00f
AM		 4255 if (chip_info->access_table) {
4256 regmap_config.rd_table = chip_info->access_table;
4257 regmap_config.wr_table = chip_info->access_table;
4258 } else {
4259 regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;
4260 }
6626a76e
PC		 4261
4262 jzpc->map = devm_regmap_init_mmio(dev, base, &regmap_config);
b5c23aa4
PC		 4263 if (IS_ERR(jzpc->map)) {
4264 dev_err(dev, "Failed to create regmap\n");
4265 return PTR_ERR(jzpc->map);
4266 }
4267
4268 jzpc->dev = dev;
9aa35178 4269 jzpc->info = chip_info;
b5c23aa4
PC		 4270
4271 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
4272 if (!pctl_desc)
4273 return -ENOMEM;
4274
4275 /* fill in pinctrl_desc structure */
4276 pctl_desc->name = dev_name(dev);
4277 pctl_desc->owner = THIS_MODULE;
4278 pctl_desc->pctlops = &ingenic_pctlops;
4279 pctl_desc->pmxops = &ingenic_pmxops;
4280 pctl_desc->confops = &ingenic_confops;
4281 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
a86854d0
KC		 4282 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
4283 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
b5c23aa4
PC		 4284 if (!jzpc->pdesc)
4285 return -ENOMEM;
4286
4287 for (i = 0; i < pctl_desc->npins; i++) {
4288 jzpc->pdesc[i].number = i;
4289 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
4290 'A' + (i / PINS_PER_GPIO_CHIP),
4291 i % PINS_PER_GPIO_CHIP);
4292 }
4293
4294 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
e7f4c4bf 4295 if (IS_ERR(jzpc->pctl)) {
b5c23aa4 4296 dev_err(dev, "Failed to register pinctrl\n");
e7f4c4bf 4297 return PTR_ERR(jzpc->pctl);
b5c23aa4
PC		 4298 }
4299
4300 for (i = 0; i < chip_info->num_groups; i++) {
4301 const struct group_desc *group = &chip_info->groups[i];
4302
4303 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
4304 group->pins, group->num_pins, group->data);
823dd71f 4305 if (err < 0) {
b5c23aa4
PC		 4306 dev_err(dev, "Failed to register group %s\n",
4307 group->name);
4308 return err;
4309 }
4310 }
4311
4312 for (i = 0; i < chip_info->num_functions; i++) {
4313 const struct function_desc *func = &chip_info->functions[i];
4314
4315 err = pinmux_generic_add_function(jzpc->pctl, func->name,
4316 func->group_names, func->num_group_names,
4317 func->data);
823dd71f 4318 if (err < 0) {
b5c23aa4
PC		 4319 dev_err(dev, "Failed to register function %s\n",
4320 func->name);
4321 return err;
4322 }
4323 }
4324
4325 dev_set_drvdata(dev, jzpc->map);
4326
8c943137
AS		 4327 device_for_each_child_node(dev, fwnode) {
4328 if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) {
4329 err = ingenic_gpio_probe(jzpc, fwnode);
d2cd54c2 4330 if (err) {
8c943137 4331 fwnode_handle_put(fwnode);
e72394e2 4332 return err;
d2cd54c2 4333 }
b5c23aa4
PC		 4334 }
4335 }
4336
4337 return 0;
4338}
4339
0ab1438b
MY		 4340#define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr))
4341
28c1caaf 4342static const struct of_device_id ingenic_pinctrl_of_matches[] = {
424f3969
ZY		 4343 {
4344 .compatible = "ingenic,jz4730-pinctrl",
4345 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info)
4346 },
9aa35178
PC		 4347 {
4348 .compatible = "ingenic,jz4740-pinctrl",
4349 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)
4350 },
4351 {
4352 .compatible = "ingenic,jz4725b-pinctrl",
4353 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)
4354 },
4355 {
215c81a3
ZY		 4356 .compatible = "ingenic,jz4750-pinctrl",
4357 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info)
4358 },
b582b5a4
ZY		 4359 {
4360 .compatible = "ingenic,jz4755-pinctrl",
4361 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info)
4362 },
4363 {
9aa35178
PC		 4364 .compatible = "ingenic,jz4760-pinctrl",
4365 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4366 },
4367 {
4368 .compatible = "ingenic,jz4760b-pinctrl",
4369 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4370 },
4371 {
4372 .compatible = "ingenic,jz4770-pinctrl",
4373 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)
4374 },
0c990740
ZY		 4375 {
4376 .compatible = "ingenic,jz4775-pinctrl",
4377 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info)
4378 },
9aa35178
PC		 4379 {
4380 .compatible = "ingenic,jz4780-pinctrl",
4381 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)
4382 },
4383 {
4384 .compatible = "ingenic,x1000-pinctrl",
4385 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4386 },
4387 {
4388 .compatible = "ingenic,x1000e-pinctrl",
4389 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4390 },
4391 {
4392 .compatible = "ingenic,x1500-pinctrl",
4393 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
4394 },
4395 {
4396 .compatible = "ingenic,x1830-pinctrl",
4397 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)
4398 },
943e0da1
ZY		 4399 {
4400 .compatible = "ingenic,x2000-pinctrl",
4401 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4402 },
4403 {
4404 .compatible = "ingenic,x2000e-pinctrl",
4405 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4406 },
2a18211b
ZY		 4407 {
4408 .compatible = "ingenic,x2100-pinctrl",
4409 .data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info)
4410 },
9aa35178 4411 { /* sentinel */ },
baf15647
PC		 4412};
4413
b5c23aa4
PC		 4414static struct platform_driver ingenic_pinctrl_driver = {
4415 .driver = {
4416 .name = "pinctrl-ingenic",
28c1caaf 4417 .of_match_table = ingenic_pinctrl_of_matches,
b5c23aa4 4418 },
b5c23aa4
PC		 4419};
4420
4421static int __init ingenic_pinctrl_drv_register(void)
4422{
4717b11f
PC		 4423 return platform_driver_probe(&ingenic_pinctrl_driver,
4424 ingenic_pinctrl_probe);
b5c23aa4 4425}
556a36a7 4426subsys_initcall(ingenic_pinctrl_drv_register);
Linux 6.x block layer and io_uring tree(s)