[linux-2.6-block.git] / drivers / pinctrl / pinctrl-imx.c

/*
 * Core driver for the imx pin controller
 *
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 * Copyright (C) 2012 Linaro Ltd.
 *
 * Author: Dong Aisheng <dong.aisheng@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>

#include "core.h"
#include "pinctrl-imx.h"

/* The bits in CONFIG cell defined in binding doc*/
#define IMX_NO_PAD_CTL	0x80000000	/* no pin config need */
#define IMX_PAD_SION 0x40000000		/* set SION */

/**
 * @dev: a pointer back to containing device
 * @base: the offset to the controller in virtual memory
 */
struct imx_pinctrl {
	struct device *dev;
	struct pinctrl_dev *pctl;
	void __iomem *base;
	const struct imx_pinctrl_soc_info *info;
};

static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
				const struct imx_pinctrl_soc_info *info,
				const char *name)
{
	const struct imx_pin_group *grp = NULL;
	int i;

	for (i = 0; i < info->ngroups; i++) {
		if (!strcmp(info->groups[i].name, name)) {
			grp = &info->groups[i];
			break;
		}
	}

	return grp;
}

static int imx_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->ngroups;
}

static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
				       unsigned selector)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->groups[selector].name;
}

static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
			       const unsigned **pins,
			       unsigned *npins)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	if (selector >= info->ngroups)
		return -EINVAL;

	*pins = info->groups[selector].pin_ids;
	*npins = info->groups[selector].npins;

	return 0;
}

static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
		   unsigned offset)
{
	seq_printf(s, "%s", dev_name(pctldev->dev));
}

static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
			struct device_node *np,
			struct pinctrl_map **map, unsigned *num_maps)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_group *grp;
	struct pinctrl_map *new_map;
	struct device_node *parent;
	int map_num = 1;
	int i, j;

	/*
	 * first find the group of this node and check if we need create
	 * config maps for pins
	 */
	grp = imx_pinctrl_find_group_by_name(info, np->name);
	if (!grp) {
		dev_err(info->dev, "unable to find group for node %s\n",
			np->name);
		return -EINVAL;
	}

	for (i = 0; i < grp->npins; i++) {
		if (!(grp->pins[i].config & IMX_NO_PAD_CTL))
			map_num++;
	}

	new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
	if (!new_map)
		return -ENOMEM;

	*map = new_map;
	*num_maps = map_num;

	/* create mux map */
	parent = of_get_parent(np);
	if (!parent) {
		kfree(new_map);
		return -EINVAL;
	}
	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	new_map[0].data.mux.function = parent->name;
	new_map[0].data.mux.group = np->name;
	of_node_put(parent);

	/* create config map */
	new_map++;
	for (i = j = 0; i < grp->npins; i++) {
		if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) {
			new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
			new_map[j].data.configs.group_or_pin =
					pin_get_name(pctldev, grp->pins[i].pin);
			new_map[j].data.configs.configs = &grp->pins[i].config;
			new_map[j].data.configs.num_configs = 1;
			j++;
		}
	}

	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
		(*map)->data.mux.function, (*map)->data.mux.group, map_num);

	return 0;
}

static void imx_dt_free_map(struct pinctrl_dev *pctldev,
				struct pinctrl_map *map, unsigned num_maps)
{
	kfree(map);
}

static const struct pinctrl_ops imx_pctrl_ops = {
	.get_groups_count = imx_get_groups_count,
	.get_group_name = imx_get_group_name,
	.get_group_pins = imx_get_group_pins,
	.pin_dbg_show = imx_pin_dbg_show,
	.dt_node_to_map = imx_dt_node_to_map,
	.dt_free_map = imx_dt_free_map,

};

static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
			   unsigned group)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg;
	unsigned int npins, pin_id;
	int i;
	struct imx_pin_group *grp;

	/*
	 * Configure the mux mode for each pin in the group for a specific
	 * function.
	 */
	grp = &info->groups[group];
	npins = grp->npins;

	dev_dbg(ipctl->dev, "enable function %s group %s\n",
		info->functions[selector].name, grp->name);

	for (i = 0; i < npins; i++) {
		struct imx_pin *pin = &grp->pins[i];
		pin_id = pin->pin;
		pin_reg = &info->pin_regs[pin_id];

		if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
				info->pins[pin_id].name);
			return -EINVAL;
		}

		if (info->flags & SHARE_MUX_CONF_REG) {
			u32 reg;
			reg = readl(ipctl->base + pin_reg->mux_reg);
			reg &= ~(0x7 << 20);
			reg |= (pin->mux_mode << 20);
			writel(reg, ipctl->base + pin_reg->mux_reg);
		} else {
			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
		}
		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
			pin_reg->mux_reg, pin->mux_mode);

		/*
		 * If the select input value begins with 0xff, it's a quirky
		 * select input and the value should be interpreted as below.
		 *     31     23      15      7        0
		 *     | 0xff | shift | width | select |
		 * It's used to work around the problem that the select
		 * input for some pin is not implemented in the select
		 * input register but in some general purpose register.
		 * We encode the select input value, width and shift of
		 * the bit field into input_val cell of pin function ID
		 * in device tree, and then decode them here for setting
		 * up the select input bits in general purpose register.
		 */
		if (pin->input_val >> 24 == 0xff) {
			u32 val = pin->input_val;
			u8 select = val & 0xff;
			u8 width = (val >> 8) & 0xff;
			u8 shift = (val >> 16) & 0xff;
			u32 mask = ((1 << width) - 1) << shift;
			/*
			 * The input_reg[i] here is actually some IOMUXC general
			 * purpose register, not regular select input register.
			 */
			val = readl(ipctl->base + pin->input_reg);
			val &= ~mask;
			val |= select << shift;
			writel(val, ipctl->base + pin->input_reg);
		} else if (pin->input_reg) {
			/*
			 * Regular select input register can never be at offset
			 * 0, and we only print register value for regular case.
			 */
			writel(pin->input_val, ipctl->base + pin->input_reg);
			dev_dbg(ipctl->dev,
				"==>select_input: offset 0x%x val 0x%x\n",
				pin->input_reg, pin->input_val);
		}
	}

	return 0;
}

static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->nfunctions;
}

static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
					  unsigned selector)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->functions[selector].name;
}

static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
			       const char * const **groups,
			       unsigned * const num_groups)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	*groups = info->functions[selector].groups;
	*num_groups = info->functions[selector].num_groups;

	return 0;
}

static const struct pinmux_ops imx_pmx_ops = {
	.get_functions_count = imx_pmx_get_funcs_count,
	.get_function_name = imx_pmx_get_func_name,
	.get_function_groups = imx_pmx_get_groups,
	.enable = imx_pmx_enable,
};

static int imx_pinconf_get(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long *config)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];

	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
		dev_err(info->dev, "Pin(%s) does not support config function\n",
			info->pins[pin_id].name);
		return -EINVAL;
	}

	*config = readl(ipctl->base + pin_reg->conf_reg);

	if (info->flags & SHARE_MUX_CONF_REG)
		*config &= 0xffff;

	return 0;
}

static int imx_pinconf_set(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long *configs,
			     unsigned num_configs)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
	int i;

	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
		dev_err(info->dev, "Pin(%s) does not support config function\n",
			info->pins[pin_id].name);
		return -EINVAL;
	}

	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
		info->pins[pin_id].name);

	for (i = 0; i < num_configs; i++) {
		if (info->flags & SHARE_MUX_CONF_REG) {
			u32 reg;
			reg = readl(ipctl->base + pin_reg->conf_reg);
			reg &= ~0xffff;
			reg |= configs[i];
			writel(reg, ipctl->base + pin_reg->conf_reg);
		} else {
			writel(configs[i], ipctl->base + pin_reg->conf_reg);
		}
		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
			pin_reg->conf_reg, configs[i]);
	} /* for each config */

	return 0;
}

static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
				   struct seq_file *s, unsigned pin_id)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
	unsigned long config;

	if (!pin_reg || !pin_reg->conf_reg) {
		seq_printf(s, "N/A");
		return;
	}

	config = readl(ipctl->base + pin_reg->conf_reg);
	seq_printf(s, "0x%lx", config);
}

static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
					 struct seq_file *s, unsigned group)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	struct imx_pin_group *grp;
	unsigned long config;
	const char *name;
	int i, ret;

	if (group > info->ngroups)
		return;

	seq_printf(s, "\n");
	grp = &info->groups[group];
	for (i = 0; i < grp->npins; i++) {
		struct imx_pin *pin = &grp->pins[i];
		name = pin_get_name(pctldev, pin->pin);
		ret = imx_pinconf_get(pctldev, pin->pin, &config);
		if (ret)
			return;
		seq_printf(s, "%s: 0x%lx", name, config);
	}
}

static const struct pinconf_ops imx_pinconf_ops = {
	.pin_config_get = imx_pinconf_get,
	.pin_config_set = imx_pinconf_set,
	.pin_config_dbg_show = imx_pinconf_dbg_show,
	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
};

static struct pinctrl_desc imx_pinctrl_desc = {
	.pctlops = &imx_pctrl_ops,
	.pmxops = &imx_pmx_ops,
	.confops = &imx_pinconf_ops,
	.owner = THIS_MODULE,
};

/*
 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
 * 1 u32 CONFIG, so 24 types in total for each pin.
 */
#define FSL_PIN_SIZE 24
#define SHARE_FSL_PIN_SIZE 20

static int imx_pinctrl_parse_groups(struct device_node *np,
				    struct imx_pin_group *grp,
				    struct imx_pinctrl_soc_info *info,
				    u32 index)
{
	int size, pin_size;
	const __be32 *list;
	int i;
	u32 config;

	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);

	if (info->flags & SHARE_MUX_CONF_REG)
		pin_size = SHARE_FSL_PIN_SIZE;
	else
		pin_size = FSL_PIN_SIZE;
	/* Initialise group */
	grp->name = np->name;

	/*
	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
	 * do sanity check and calculate pins number
	 */
	list = of_get_property(np, "fsl,pins", &size);
	if (!list) {
		dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
		return -EINVAL;
	}

	/* we do not check return since it's safe node passed down */
	if (!size || size % pin_size) {
		dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
		return -EINVAL;
	}

	grp->npins = size / pin_size;
	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin),
				GFP_KERNEL);
	grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
				GFP_KERNEL);
	if (!grp->pins || ! grp->pin_ids)
		return -ENOMEM;

	for (i = 0; i < grp->npins; i++) {
		u32 mux_reg = be32_to_cpu(*list++);
		u32 conf_reg;
		unsigned int pin_id;
		struct imx_pin_reg *pin_reg;
		struct imx_pin *pin = &grp->pins[i];

		if (info->flags & SHARE_MUX_CONF_REG)
			conf_reg = mux_reg;
		else
			conf_reg = be32_to_cpu(*list++);

		pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
		pin_reg = &info->pin_regs[pin_id];
		pin->pin = pin_id;
		grp->pin_ids[i] = pin_id;
		pin_reg->mux_reg = mux_reg;
		pin_reg->conf_reg = conf_reg;
		pin->input_reg = be32_to_cpu(*list++);
		pin->mux_mode = be32_to_cpu(*list++);
		pin->input_val = be32_to_cpu(*list++);

		/* SION bit is in mux register */
		config = be32_to_cpu(*list++);
		if (config & IMX_PAD_SION)
			pin->mux_mode |= IOMUXC_CONFIG_SION;
		pin->config = config & ~IMX_PAD_SION;

		dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[pin_id].name,
				pin->mux_mode, pin->config);
	}

	return 0;
}

static int imx_pinctrl_parse_functions(struct device_node *np,
				       struct imx_pinctrl_soc_info *info,
				       u32 index)
{
	struct device_node *child;
	struct imx_pmx_func *func;
	struct imx_pin_group *grp;
	static u32 grp_index;
	u32 i = 0;

	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);

	func = &info->functions[index];

	/* Initialise function */
	func->name = np->name;
	func->num_groups = of_get_child_count(np);
	if (func->num_groups <= 0) {
		dev_err(info->dev, "no groups defined in %s\n", np->full_name);
		return -EINVAL;
	}
	func->groups = devm_kzalloc(info->dev,
			func->num_groups * sizeof(char *), GFP_KERNEL);

	for_each_child_of_node(np, child) {
		func->groups[i] = child->name;
		grp = &info->groups[grp_index++];
		imx_pinctrl_parse_groups(child, grp, info, i++);
	}

	return 0;
}

static int imx_pinctrl_probe_dt(struct platform_device *pdev,
				struct imx_pinctrl_soc_info *info)
{
	struct device_node *np = pdev->dev.of_node;
	struct device_node *child;
	u32 nfuncs = 0;
	u32 i = 0;

	if (!np)
		return -ENODEV;

	nfuncs = of_get_child_count(np);
	if (nfuncs <= 0) {
		dev_err(&pdev->dev, "no functions defined\n");
		return -EINVAL;
	}

	info->nfunctions = nfuncs;
	info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
					GFP_KERNEL);
	if (!info->functions)
		return -ENOMEM;

	info->ngroups = 0;
	for_each_child_of_node(np, child)
		info->ngroups += of_get_child_count(child);
	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
					GFP_KERNEL);
	if (!info->groups)
		return -ENOMEM;

	for_each_child_of_node(np, child)
		imx_pinctrl_parse_functions(child, info, i++);

	return 0;
}

int imx_pinctrl_probe(struct platform_device *pdev,
		      struct imx_pinctrl_soc_info *info)
{
	struct imx_pinctrl *ipctl;
	struct resource *res;
	int ret;

	if (!info || !info->pins || !info->npins) {
		dev_err(&pdev->dev, "wrong pinctrl info\n");
		return -EINVAL;
	}
	info->dev = &pdev->dev;

	/* Create state holders etc for this driver */
	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
	if (!ipctl)
		return -ENOMEM;

	info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) *
				      info->npins, GFP_KERNEL);
	if (!info->pin_regs)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ipctl->base))
		return PTR_ERR(ipctl->base);

	imx_pinctrl_desc.name = dev_name(&pdev->dev);
	imx_pinctrl_desc.pins = info->pins;
	imx_pinctrl_desc.npins = info->npins;

	ret = imx_pinctrl_probe_dt(pdev, info);
	if (ret) {
		dev_err(&pdev->dev, "fail to probe dt properties\n");
		return ret;
	}

	ipctl->info = info;
	ipctl->dev = info->dev;
	platform_set_drvdata(pdev, ipctl);
	ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
	if (!ipctl->pctl) {
		dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
		return -EINVAL;
	}

	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");

	return 0;
}

int imx_pinctrl_remove(struct platform_device *pdev)
{
	struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);

	pinctrl_unregister(ipctl->pctl);

	return 0;
}
Commit	Line	Data
ae75ff81 DA	1	/*
	2	* Core driver for the imx pin controller
	3	*
	4	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	5	* Copyright (C) 2012 Linaro Ltd.
	6	*
	7	* Author: Dong Aisheng <dong.aisheng@linaro.org>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*/
	14
	15	#include <linux/err.h>
	16	#include <linux/init.h>
	17	#include <linux/io.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/pinctrl/machine.h>
	22	#include <linux/pinctrl/pinconf.h>
	23	#include <linux/pinctrl/pinctrl.h>
	24	#include <linux/pinctrl/pinmux.h>
	25	#include <linux/slab.h>
	26
	27	#include "core.h"
	28	#include "pinctrl-imx.h"
	29
ae75ff81 DA	30	/* The bits in CONFIG cell defined in binding doc*/
	31	#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
	32	#define IMX_PAD_SION 0x40000000 /* set SION */
	33
	34	/**
	35	* @dev: a pointer back to containing device
	36	* @base: the offset to the controller in virtual memory
	37	*/
	38	struct imx_pinctrl {
	39	struct device *dev;
	40	struct pinctrl_dev *pctl;
	41	void __iomem *base;
	42	const struct imx_pinctrl_soc_info *info;
	43	};
	44
ae75ff81 DA	45	static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
	46	const struct imx_pinctrl_soc_info *info,
	47	const char *name)
	48	{
	49	const struct imx_pin_group *grp = NULL;
	50	int i;
	51
	52	for (i = 0; i < info->ngroups; i++) {
	53	if (!strcmp(info->groups[i].name, name)) {
	54	grp = &info->groups[i];
	55	break;
	56	}
	57	}
	58
	59	return grp;
	60	}
	61
	62	static int imx_get_groups_count(struct pinctrl_dev *pctldev)
	63	{
	64	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	65	const struct imx_pinctrl_soc_info *info = ipctl->info;
	66
	67	return info->ngroups;
	68	}
	69
	70	static const char imx_get_group_name(struct pinctrl_dev pctldev,
	71	unsigned selector)
	72	{
	73	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	74	const struct imx_pinctrl_soc_info *info = ipctl->info;
	75
	76	return info->groups[selector].name;
	77	}
	78
	79	static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
	80	const unsigned **pins,
	81	unsigned *npins)
	82	{
	83	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	84	const struct imx_pinctrl_soc_info *info = ipctl->info;
	85
	86	if (selector >= info->ngroups)
	87	return -EINVAL;
	88
8f903f8a	89	*pins = info->groups[selector].pin_ids;
ae75ff81 DA	90	*npins = info->groups[selector].npins;
	91
	92	return 0;
	93	}
	94
	95	static void imx_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	96	unsigned offset)
	97	{
	98	seq_printf(s, "%s", dev_name(pctldev->dev));
	99	}
	100
	101	static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
	102	struct device_node *np,
	103	struct pinctrl_map *map, unsigned num_maps)
	104	{
	105	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	106	const struct imx_pinctrl_soc_info *info = ipctl->info;
	107	const struct imx_pin_group *grp;
	108	struct pinctrl_map *new_map;
	109	struct device_node *parent;
	110	int map_num = 1;
18071610	111	int i, j;
ae75ff81 DA	112
	113	/*
	114	* first find the group of this node and check if we need create
	115	* config maps for pins
	116	*/
	117	grp = imx_pinctrl_find_group_by_name(info, np->name);
	118	if (!grp) {
	119	dev_err(info->dev, "unable to find group for node %s\n",
	120	np->name);
	121	return -EINVAL;
	122	}
	123
	124	for (i = 0; i < grp->npins; i++) {
8f903f8a	125	if (!(grp->pins[i].config & IMX_NO_PAD_CTL))
ae75ff81 DA	126	map_num++;
	127	}
	128
	129	new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
	130	if (!new_map)
	131	return -ENOMEM;
	132
	133	*map = new_map;
	134	*num_maps = map_num;
	135
	136	/* create mux map */
	137	parent = of_get_parent(np);
c71157c5 DN	138	if (!parent) {
c71157c5 DN	139	kfree(new_map);
ae75ff81	140	return -EINVAL;
c71157c5	141	}
ae75ff81 DA	142	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	143	new_map[0].data.mux.function = parent->name;
	144	new_map[0].data.mux.group = np->name;
	145	of_node_put(parent);
	146
	147	/* create config map */
	148	new_map++;
18071610	149	for (i = j = 0; i < grp->npins; i++) {
8f903f8a	150	if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) {
18071610 HW	151	new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
18071610 HW	152	new_map[j].data.configs.group_or_pin =
8f903f8a SH	153	pin_get_name(pctldev, grp->pins[i].pin);
8f903f8a SH	154	new_map[j].data.configs.configs = &grp->pins[i].config;
18071610 HW	155	new_map[j].data.configs.num_configs = 1;
18071610 HW	156	j++;
ae75ff81 DA	157	}
	158	}
	159
	160	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
67695f2e	161	(map)->data.mux.function, (map)->data.mux.group, map_num);
ae75ff81 DA	162
	163	return 0;
	164	}
	165
	166	static void imx_dt_free_map(struct pinctrl_dev *pctldev,
	167	struct pinctrl_map *map, unsigned num_maps)
	168	{
3a86a5f8	169	kfree(map);
ae75ff81 DA	170	}
ae75ff81 DA	171
022ab148	172	static const struct pinctrl_ops imx_pctrl_ops = {
ae75ff81 DA	173	.get_groups_count = imx_get_groups_count,
	174	.get_group_name = imx_get_group_name,
	175	.get_group_pins = imx_get_group_pins,
	176	.pin_dbg_show = imx_pin_dbg_show,
	177	.dt_node_to_map = imx_dt_node_to_map,
	178	.dt_free_map = imx_dt_free_map,
	179
	180	};
	181
	182	static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
	183	unsigned group)
	184	{
	185	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	186	const struct imx_pinctrl_soc_info *info = ipctl->info;
	187	const struct imx_pin_reg *pin_reg;
ae75ff81 DA	188	unsigned int npins, pin_id;
ae75ff81 DA	189	int i;
8f903f8a	190	struct imx_pin_group *grp;
ae75ff81 DA	191
	192	/*
	193	* Configure the mux mode for each pin in the group for a specific
	194	* function.
	195	*/
8f903f8a SH	196	grp = &info->groups[group];
8f903f8a SH	197	npins = grp->npins;
ae75ff81 DA	198
ae75ff81 DA	199	dev_dbg(ipctl->dev, "enable function %s group %s\n",
8f903f8a	200	info->functions[selector].name, grp->name);
ae75ff81 DA	201
ae75ff81 DA	202	for (i = 0; i < npins; i++) {
8f903f8a SH	203	struct imx_pin *pin = &grp->pins[i];
8f903f8a SH	204	pin_id = pin->pin;
e1641531	205	pin_reg = &info->pin_regs[pin_id];
ae75ff81	206
bf5a5309	207	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
ae75ff81 DA	208	dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
	209	info->pins[pin_id].name);
	210	return -EINVAL;
	211	}
	212
bf5a5309 JL	213	if (info->flags & SHARE_MUX_CONF_REG) {
	214	u32 reg;
	215	reg = readl(ipctl->base + pin_reg->mux_reg);
	216	reg &= ~(0x7 << 20);
8f903f8a	217	reg \|= (pin->mux_mode << 20);
bf5a5309 JL	218	writel(reg, ipctl->base + pin_reg->mux_reg);
bf5a5309 JL	219	} else {
8f903f8a	220	writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
bf5a5309	221	}
ae75ff81	222	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
8f903f8a	223	pin_reg->mux_reg, pin->mux_mode);
ae75ff81	224
94176faf SG	225	/*
	226	* If the select input value begins with 0xff, it's a quirky
	227	* select input and the value should be interpreted as below.
	228	* 31 23 15 7 0
	229	* \| 0xff \| shift \| width \| select \|
	230	* It's used to work around the problem that the select
	231	* input for some pin is not implemented in the select
	232	* input register but in some general purpose register.
	233	* We encode the select input value, width and shift of
	234	* the bit field into input_val cell of pin function ID
	235	* in device tree, and then decode them here for setting
	236	* up the select input bits in general purpose register.
	237	*/
8f903f8a SH	238	if (pin->input_val >> 24 == 0xff) {
8f903f8a SH	239	u32 val = pin->input_val;
94176faf SG	240	u8 select = val & 0xff;
	241	u8 width = (val >> 8) & 0xff;
	242	u8 shift = (val >> 16) & 0xff;
	243	u32 mask = ((1 << width) - 1) << shift;
	244	/*
	245	* The input_reg[i] here is actually some IOMUXC general
	246	* purpose register, not regular select input register.
	247	*/
a3183c60	248	val = readl(ipctl->base + pin->input_reg);
94176faf SG	249	val &= ~mask;
94176faf SG	250	val \|= select << shift;
a3183c60 PC	251	writel(val, ipctl->base + pin->input_reg);
a3183c60 PC	252	} else if (pin->input_reg) {
94176faf SG	253	/*
	254	* Regular select input register can never be at offset
	255	* 0, and we only print register value for regular case.
	256	*/
8f903f8a	257	writel(pin->input_val, ipctl->base + pin->input_reg);
ae75ff81 DA	258	dev_dbg(ipctl->dev,
ae75ff81 DA	259	"==>select_input: offset 0x%x val 0x%x\n",
8f903f8a	260	pin->input_reg, pin->input_val);
ae75ff81 DA	261	}
	262	}
	263
	264	return 0;
	265	}
	266
ae75ff81 DA	267	static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
	268	{
	269	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	270	const struct imx_pinctrl_soc_info *info = ipctl->info;
	271
	272	return info->nfunctions;
	273	}
	274
	275	static const char imx_pmx_get_func_name(struct pinctrl_dev pctldev,
	276	unsigned selector)
	277	{
	278	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	279	const struct imx_pinctrl_soc_info *info = ipctl->info;
	280
	281	return info->functions[selector].name;
	282	}
	283
	284	static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
	285	const char * const **groups,
	286	unsigned * const num_groups)
	287	{
	288	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	289	const struct imx_pinctrl_soc_info *info = ipctl->info;
	290
	291	*groups = info->functions[selector].groups;
	292	*num_groups = info->functions[selector].num_groups;
	293
	294	return 0;
	295	}
	296
022ab148	297	static const struct pinmux_ops imx_pmx_ops = {
ae75ff81 DA	298	.get_functions_count = imx_pmx_get_funcs_count,
	299	.get_function_name = imx_pmx_get_func_name,
	300	.get_function_groups = imx_pmx_get_groups,
	301	.enable = imx_pmx_enable,
ae75ff81 DA	302	};
	303
	304	static int imx_pinconf_get(struct pinctrl_dev *pctldev,
	305	unsigned pin_id, unsigned long *config)
	306	{
	307	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	308	const struct imx_pinctrl_soc_info *info = ipctl->info;
e1641531	309	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
ae75ff81	310
bf5a5309	311	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
ae75ff81 DA	312	dev_err(info->dev, "Pin(%s) does not support config function\n",
	313	info->pins[pin_id].name);
	314	return -EINVAL;
	315	}
	316
	317	*config = readl(ipctl->base + pin_reg->conf_reg);
	318
bf5a5309 JL	319	if (info->flags & SHARE_MUX_CONF_REG)
	320	*config &= 0xffff;
	321
ae75ff81 DA	322	return 0;
	323	}
	324
	325	static int imx_pinconf_set(struct pinctrl_dev *pctldev,
03b054e9 SY	326	unsigned pin_id, unsigned long *configs,
03b054e9 SY	327	unsigned num_configs)
ae75ff81 DA	328	{
	329	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	330	const struct imx_pinctrl_soc_info *info = ipctl->info;
e1641531	331	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
03b054e9	332	int i;
ae75ff81	333
bf5a5309	334	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
ae75ff81 DA	335	dev_err(info->dev, "Pin(%s) does not support config function\n",
	336	info->pins[pin_id].name);
	337	return -EINVAL;
	338	}
	339
	340	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
	341	info->pins[pin_id].name);
	342
03b054e9 SY	343	for (i = 0; i < num_configs; i++) {
	344	if (info->flags & SHARE_MUX_CONF_REG) {
	345	u32 reg;
	346	reg = readl(ipctl->base + pin_reg->conf_reg);
	347	reg &= ~0xffff;
	348	reg \|= configs[i];
	349	writel(reg, ipctl->base + pin_reg->conf_reg);
	350	} else {
	351	writel(configs[i], ipctl->base + pin_reg->conf_reg);
	352	}
	353	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
	354	pin_reg->conf_reg, configs[i]);
	355	} /* for each config */
ae75ff81 DA	356
	357	return 0;
	358	}
	359
	360	static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
	361	struct seq_file *s, unsigned pin_id)
	362	{
	363	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	364	const struct imx_pinctrl_soc_info *info = ipctl->info;
e1641531	365	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
ae75ff81 DA	366	unsigned long config;
ae75ff81 DA	367
ae75ff81 DA	368	if (!pin_reg \|\| !pin_reg->conf_reg) {
	369	seq_printf(s, "N/A");
	370	return;
	371	}
	372
	373	config = readl(ipctl->base + pin_reg->conf_reg);
	374	seq_printf(s, "0x%lx", config);
	375	}
	376
	377	static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
	378	struct seq_file *s, unsigned group)
	379	{
	380	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	381	const struct imx_pinctrl_soc_info *info = ipctl->info;
	382	struct imx_pin_group *grp;
	383	unsigned long config;
	384	const char *name;
	385	int i, ret;
	386
	387	if (group > info->ngroups)
	388	return;
	389
	390	seq_printf(s, "\n");
	391	grp = &info->groups[group];
	392	for (i = 0; i < grp->npins; i++) {
8f903f8a SH	393	struct imx_pin *pin = &grp->pins[i];
	394	name = pin_get_name(pctldev, pin->pin);
	395	ret = imx_pinconf_get(pctldev, pin->pin, &config);
ae75ff81 DA	396	if (ret)
	397	return;
	398	seq_printf(s, "%s: 0x%lx", name, config);
	399	}
	400	}
	401
022ab148	402	static const struct pinconf_ops imx_pinconf_ops = {
ae75ff81 DA	403	.pin_config_get = imx_pinconf_get,
	404	.pin_config_set = imx_pinconf_set,
	405	.pin_config_dbg_show = imx_pinconf_dbg_show,
	406	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
	407	};
	408
	409	static struct pinctrl_desc imx_pinctrl_desc = {
	410	.pctlops = &imx_pctrl_ops,
	411	.pmxops = &imx_pmx_ops,
	412	.confops = &imx_pinconf_ops,
	413	.owner = THIS_MODULE,
	414	};
	415
e1641531 SG	416	/*
	417	* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
	418	* 1 u32 CONFIG, so 24 types in total for each pin.
	419	*/
	420	#define FSL_PIN_SIZE 24
bf5a5309	421	#define SHARE_FSL_PIN_SIZE 20
ae75ff81	422
150632b0 GKH	423	static int imx_pinctrl_parse_groups(struct device_node *np,
	424	struct imx_pin_group *grp,
	425	struct imx_pinctrl_soc_info *info,
	426	u32 index)
ae75ff81	427	{
bf5a5309	428	int size, pin_size;
a695145b	429	const __be32 *list;
e1641531	430	int i;
ae75ff81 DA	431	u32 config;
	432
	433	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
	434
bf5a5309 JL	435	if (info->flags & SHARE_MUX_CONF_REG)
	436	pin_size = SHARE_FSL_PIN_SIZE;
	437	else
	438	pin_size = FSL_PIN_SIZE;
ae75ff81 DA	439	/* Initialise group */
	440	grp->name = np->name;
	441
	442	/*
	443	* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
	444	* do sanity check and calculate pins number
	445	*/
	446	list = of_get_property(np, "fsl,pins", &size);
1bf1fea9 SH	447	if (!list) {
	448	dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
	449	return -EINVAL;
	450	}
	451
ae75ff81	452	/* we do not check return since it's safe node passed down */
bf5a5309	453	if (!size \|\| size % pin_size) {
01312513	454	dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
ae75ff81 DA	455	return -EINVAL;
	456	}
	457
bf5a5309	458	grp->npins = size / pin_size;
8f903f8a	459	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin),
ae75ff81	460	GFP_KERNEL);
8f903f8a	461	grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
ae75ff81	462	GFP_KERNEL);
8f903f8a SH	463	if (!grp->pins \|\| ! grp->pin_ids)
	464	return -ENOMEM;
	465
e1641531 SG	466	for (i = 0; i < grp->npins; i++) {
e1641531 SG	467	u32 mux_reg = be32_to_cpu(*list++);
bf5a5309 JL	468	u32 conf_reg;
	469	unsigned int pin_id;
	470	struct imx_pin_reg *pin_reg;
8f903f8a	471	struct imx_pin *pin = &grp->pins[i];
e1641531	472
bf5a5309 JL	473	if (info->flags & SHARE_MUX_CONF_REG)
	474	conf_reg = mux_reg;
	475	else
	476	conf_reg = be32_to_cpu(*list++);
	477
	478	pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
	479	pin_reg = &info->pin_regs[pin_id];
8f903f8a SH	480	pin->pin = pin_id;
8f903f8a SH	481	grp->pin_ids[i] = pin_id;
e1641531 SG	482	pin_reg->mux_reg = mux_reg;
e1641531 SG	483	pin_reg->conf_reg = conf_reg;
8f903f8a SH	484	pin->input_reg = be32_to_cpu(*list++);
	485	pin->mux_mode = be32_to_cpu(*list++);
	486	pin->input_val = be32_to_cpu(*list++);
e1641531	487
ae75ff81 DA	488	/* SION bit is in mux register */
	489	config = be32_to_cpu(*list++);
	490	if (config & IMX_PAD_SION)
8f903f8a SH	491	pin->mux_mode \|= IOMUXC_CONFIG_SION;
8f903f8a SH	492	pin->config = config & ~IMX_PAD_SION;
ae75ff81	493
7c001e55	494	dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[pin_id].name,
40604469 SH	495	pin->mux_mode, pin->config);
40604469 SH	496	}
3a86a5f8	497
ae75ff81 DA	498	return 0;
	499	}
	500
150632b0 GKH	501	static int imx_pinctrl_parse_functions(struct device_node *np,
	502	struct imx_pinctrl_soc_info *info,
	503	u32 index)
ae75ff81 DA	504	{
	505	struct device_node *child;
	506	struct imx_pmx_func *func;
	507	struct imx_pin_group *grp;
ae75ff81 DA	508	static u32 grp_index;
	509	u32 i = 0;
	510
	511	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
	512
	513	func = &info->functions[index];
	514
	515	/* Initialise function */
	516	func->name = np->name;
	517	func->num_groups = of_get_child_count(np);
	518	if (func->num_groups <= 0) {
01312513	519	dev_err(info->dev, "no groups defined in %s\n", np->full_name);
ae75ff81 DA	520	return -EINVAL;
	521	}
	522	func->groups = devm_kzalloc(info->dev,
	523	func->num_groups * sizeof(char *), GFP_KERNEL);
	524
	525	for_each_child_of_node(np, child) {
	526	func->groups[i] = child->name;
	527	grp = &info->groups[grp_index++];
5e13762c	528	imx_pinctrl_parse_groups(child, grp, info, i++);
ae75ff81 DA	529	}
	530
	531	return 0;
	532	}
	533
150632b0	534	static int imx_pinctrl_probe_dt(struct platform_device *pdev,
ae75ff81 DA	535	struct imx_pinctrl_soc_info *info)
	536	{
	537	struct device_node *np = pdev->dev.of_node;
	538	struct device_node *child;
ae75ff81 DA	539	u32 nfuncs = 0;
	540	u32 i = 0;
	541
	542	if (!np)
	543	return -ENODEV;
	544
	545	nfuncs = of_get_child_count(np);
	546	if (nfuncs <= 0) {
	547	dev_err(&pdev->dev, "no functions defined\n");
	548	return -EINVAL;
	549	}
	550
	551	info->nfunctions = nfuncs;
	552	info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
	553	GFP_KERNEL);
	554	if (!info->functions)
	555	return -ENOMEM;
	556
	557	info->ngroups = 0;
	558	for_each_child_of_node(np, child)
	559	info->ngroups += of_get_child_count(child);
	560	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
	561	GFP_KERNEL);
	562	if (!info->groups)
	563	return -ENOMEM;
	564
7ea46e0f SH	565	for_each_child_of_node(np, child)
7ea46e0f SH	566	imx_pinctrl_parse_functions(child, info, i++);
ae75ff81 DA	567
	568	return 0;
	569	}
	570
150632b0 GKH	571	int imx_pinctrl_probe(struct platform_device *pdev,
150632b0 GKH	572	struct imx_pinctrl_soc_info *info)
ae75ff81 DA	573	{
	574	struct imx_pinctrl *ipctl;
	575	struct resource *res;
	576	int ret;
	577
e1641531	578	if (!info \|\| !info->pins \|\| !info->npins) {
ae75ff81 DA	579	dev_err(&pdev->dev, "wrong pinctrl info\n");
	580	return -EINVAL;
	581	}
	582	info->dev = &pdev->dev;
	583
	584	/* Create state holders etc for this driver */
	585	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
	586	if (!ipctl)
	587	return -ENOMEM;
	588
e1641531 SG	589	info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(info->pin_regs)
	590	info->npins, GFP_KERNEL);
	591	if (!info->pin_regs)
	592	return -ENOMEM;
	593
ae75ff81	594	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9e0c1fb2 TR	595	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
	596	if (IS_ERR(ipctl->base))
	597	return PTR_ERR(ipctl->base);
ae75ff81 DA	598
	599	imx_pinctrl_desc.name = dev_name(&pdev->dev);
	600	imx_pinctrl_desc.pins = info->pins;
	601	imx_pinctrl_desc.npins = info->npins;
	602
	603	ret = imx_pinctrl_probe_dt(pdev, info);
	604	if (ret) {
	605	dev_err(&pdev->dev, "fail to probe dt properties\n");
	606	return ret;
	607	}
	608
	609	ipctl->info = info;
	610	ipctl->dev = info->dev;
	611	platform_set_drvdata(pdev, ipctl);
	612	ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
	613	if (!ipctl->pctl) {
	614	dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
	615	return -EINVAL;
	616	}
	617
	618	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
	619
	620	return 0;
	621	}
	622
f90f54b3	623	int imx_pinctrl_remove(struct platform_device *pdev)
ae75ff81 DA	624	{
	625	struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
	626
	627	pinctrl_unregister(ipctl->pctl);
	628
	629	return 0;
	630	}