Commit | Line | Data |
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06351d13 LW |
1 | /* |
2 | * Driver for the Gemini pin controller | |
3 | * | |
4 | * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> | |
5 | * | |
6 | * This is a group-only pin controller. | |
7 | */ | |
8 | #include <linux/err.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/mfd/syscon.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/pinctrl/machine.h> | |
14 | #include <linux/pinctrl/pinctrl.h> | |
15 | #include <linux/pinctrl/pinmux.h> | |
1c5b7f3c LW |
16 | #include <linux/pinctrl/pinconf.h> |
17 | #include <linux/pinctrl/pinconf-generic.h> | |
06351d13 LW |
18 | #include <linux/platform_device.h> |
19 | #include <linux/slab.h> | |
20 | #include <linux/regmap.h> | |
21 | ||
22 | #include "pinctrl-utils.h" | |
23 | ||
24 | #define DRIVER_NAME "pinctrl-gemini" | |
25 | ||
26 | /** | |
60ad481f LW |
27 | * struct gemini_pin_conf - information about configuring a pin |
28 | * @pin: the pin number | |
29 | * @reg: config register | |
30 | * @mask: the bits affecting the configuration of the pin | |
31 | */ | |
32 | struct gemini_pin_conf { | |
33 | unsigned int pin; | |
34 | u32 reg; | |
35 | u32 mask; | |
36 | }; | |
37 | ||
38 | /** | |
39 | * struct gemini_pmx - state holder for the gemini pin controller | |
06351d13 LW |
40 | * @dev: a pointer back to containing device |
41 | * @virtbase: the offset to the controller in virtual memory | |
42 | * @map: regmap to access registers | |
43 | * @is_3512: whether the SoC/package is the 3512 variant | |
44 | * @is_3516: whether the SoC/package is the 3516 variant | |
45 | * @flash_pin: whether the flash pin (extended pins for parallel | |
46 | * flash) is set | |
60ad481f LW |
47 | * @confs: pin config information |
48 | * @nconfs: number of pin config information items | |
06351d13 LW |
49 | */ |
50 | struct gemini_pmx { | |
51 | struct device *dev; | |
52 | struct pinctrl_dev *pctl; | |
53 | struct regmap *map; | |
54 | bool is_3512; | |
55 | bool is_3516; | |
56 | bool flash_pin; | |
60ad481f LW |
57 | const struct gemini_pin_conf *confs; |
58 | unsigned int nconfs; | |
06351d13 LW |
59 | }; |
60 | ||
61 | /** | |
62 | * struct gemini_pin_group - describes a Gemini pin group | |
63 | * @name: the name of this specific pin group | |
64 | * @pins: an array of discrete physical pins used in this group, taken | |
65 | * from the driver-local pin enumeration space | |
66 | * @num_pins: the number of pins in this group array, i.e. the number of | |
67 | * elements in .pins so we can iterate over that array | |
68 | * @mask: bits to clear to enable this when doing pin muxing | |
69 | * @value: bits to set to enable this when doing pin muxing | |
70 | */ | |
71 | struct gemini_pin_group { | |
72 | const char *name; | |
73 | const unsigned int *pins; | |
74 | const unsigned int num_pins; | |
75 | u32 mask; | |
76 | u32 value; | |
77 | }; | |
78 | ||
60ad481f LW |
79 | /* Some straight-forward control registers */ |
80 | #define GLOBAL_WORD_ID 0x00 | |
81 | #define GLOBAL_STATUS 0x04 | |
82 | #define GLOBAL_STATUS_FLPIN BIT(20) | |
83 | #define GLOBAL_GMAC_CTRL_SKEW 0x1c | |
84 | #define GLOBAL_GMAC0_DATA_SKEW 0x20 | |
85 | #define GLOBAL_GMAC1_DATA_SKEW 0x24 | |
06351d13 LW |
86 | /* |
87 | * Global Miscellaneous Control Register | |
88 | * This register controls all Gemini pad/pin multiplexing | |
89 | * | |
90 | * It is a tricky register though: | |
91 | * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot | |
92 | * be brought back online, so it means permanent disablement of the | |
93 | * corresponding pads. | |
94 | * - For the bits named *_DISABLE, once you enable something, it cannot be | |
95 | * DISABLED again. So you select a flash configuration once, and then | |
96 | * you are stuck with it. | |
97 | */ | |
06351d13 | 98 | #define GLOBAL_MISC_CTRL 0x30 |
756a024f LW |
99 | #define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27) |
100 | /* Not really used */ | |
101 | #define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28) | |
102 | /* Activated with GMAC1 */ | |
103 | #define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27) | |
104 | /* This will be the default */ | |
105 | #define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0 | |
06351d13 LW |
106 | #define TVC_CLK_PAD_ENABLE BIT(20) |
107 | #define PCI_CLK_PAD_ENABLE BIT(17) | |
108 | #define LPC_CLK_PAD_ENABLE BIT(16) | |
109 | #define TVC_PADS_ENABLE BIT(9) | |
110 | #define SSP_PADS_ENABLE BIT(8) | |
111 | #define LCD_PADS_ENABLE BIT(7) | |
112 | #define LPC_PADS_ENABLE BIT(6) | |
113 | #define PCI_PADS_ENABLE BIT(5) | |
114 | #define IDE_PADS_ENABLE BIT(4) | |
115 | #define DRAM_PADS_POWERDOWN BIT(3) | |
116 | #define NAND_PADS_DISABLE BIT(2) | |
117 | #define PFLASH_PADS_DISABLE BIT(1) | |
118 | #define SFLASH_PADS_DISABLE BIT(0) | |
756a024f LW |
119 | #define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27)) |
120 | #define PADS_MAXBIT 27 | |
06351d13 LW |
121 | |
122 | /* Ordered by bit index */ | |
123 | static const char * const gemini_padgroups[] = { | |
124 | "serial flash", | |
125 | "parallel flash", | |
126 | "NAND flash", | |
127 | "DRAM", | |
128 | "IDE", | |
129 | "PCI", | |
130 | "LPC", | |
131 | "LCD", | |
132 | "SSP", | |
133 | "TVC", | |
134 | NULL, NULL, NULL, NULL, NULL, NULL, | |
135 | "LPC CLK", | |
136 | "PCI CLK", | |
137 | NULL, NULL, | |
138 | "TVC CLK", | |
eeb690bc LW |
139 | NULL, NULL, NULL, NULL, NULL, |
140 | "GMAC1", | |
06351d13 LW |
141 | }; |
142 | ||
143 | static const struct pinctrl_pin_desc gemini_3512_pins[] = { | |
144 | /* Row A */ | |
145 | PINCTRL_PIN(0, "A1 VREF CTRL"), | |
146 | PINCTRL_PIN(1, "A2 VCC2IO CTRL"), | |
147 | PINCTRL_PIN(2, "A3 DRAM CK"), | |
148 | PINCTRL_PIN(3, "A4 DRAM CK N"), | |
149 | PINCTRL_PIN(4, "A5 DRAM A5"), | |
150 | PINCTRL_PIN(5, "A6 DRAM CKE"), | |
151 | PINCTRL_PIN(6, "A7 DRAM DQ11"), | |
152 | PINCTRL_PIN(7, "A8 DRAM DQ0"), | |
153 | PINCTRL_PIN(8, "A9 DRAM DQ5"), | |
154 | PINCTRL_PIN(9, "A10 DRAM DQ6"), | |
155 | PINCTRL_PIN(10, "A11 DRAM DRAM VREF"), | |
156 | PINCTRL_PIN(11, "A12 DRAM BA1"), | |
157 | PINCTRL_PIN(12, "A13 DRAM A2"), | |
158 | PINCTRL_PIN(13, "A14 PCI GNT1 N"), | |
159 | PINCTRL_PIN(14, "A15 PCI REQ9 N"), | |
160 | PINCTRL_PIN(15, "A16 PCI REQ2 N"), | |
161 | PINCTRL_PIN(16, "A17 PCI REQ3 N"), | |
162 | PINCTRL_PIN(17, "A18 PCI AD31"), | |
163 | /* Row B */ | |
164 | PINCTRL_PIN(18, "B1 VCCK CTRL"), | |
165 | PINCTRL_PIN(19, "B2 PWR EN"), | |
166 | PINCTRL_PIN(20, "B3 RTC CLKI"), | |
167 | PINCTRL_PIN(21, "B4 DRAM A4"), | |
168 | PINCTRL_PIN(22, "B5 DRAM A6"), | |
169 | PINCTRL_PIN(23, "B6 DRAM A12"), | |
170 | PINCTRL_PIN(24, "B7 DRAM DQS1"), | |
171 | PINCTRL_PIN(25, "B8 DRAM DQ15"), | |
172 | PINCTRL_PIN(26, "B9 DRAM DQ4"), | |
173 | PINCTRL_PIN(27, "B10 DRAM DQS0"), | |
174 | PINCTRL_PIN(28, "B11 DRAM WE N"), | |
175 | PINCTRL_PIN(29, "B12 DRAM A10"), | |
176 | PINCTRL_PIN(30, "B13 DRAM A3"), | |
177 | PINCTRL_PIN(31, "B14 PCI GNT0 N"), | |
178 | PINCTRL_PIN(32, "B15 PCI GNT3 N"), | |
179 | PINCTRL_PIN(33, "B16 PCI REQ1 N"), | |
180 | PINCTRL_PIN(34, "B17 PCI AD30"), | |
181 | PINCTRL_PIN(35, "B18 PCI AD29"), | |
182 | /* Row C */ | |
183 | PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */ | |
184 | PINCTRL_PIN(37, "C2 XTALI"), | |
185 | PINCTRL_PIN(38, "C3 PWR BTN"), | |
186 | PINCTRL_PIN(39, "C4 RTC CLKO"), | |
187 | PINCTRL_PIN(40, "C5 DRAM A7"), | |
188 | PINCTRL_PIN(41, "C6 DRAM A11"), | |
189 | PINCTRL_PIN(42, "C7 DRAM DQ10"), | |
190 | PINCTRL_PIN(43, "C8 DRAM DQ14"), | |
191 | PINCTRL_PIN(44, "C9 DRAM DQ3"), | |
192 | PINCTRL_PIN(45, "C10 DRAM DQ7"), | |
193 | PINCTRL_PIN(46, "C11 DRAM CAS N"), | |
194 | PINCTRL_PIN(47, "C12 DRAM A0"), | |
195 | PINCTRL_PIN(48, "C13 PCI INT0 N"), | |
196 | PINCTRL_PIN(49, "C14 EXT RESET N"), | |
197 | PINCTRL_PIN(50, "C15 PCI GNT2 N"), | |
198 | PINCTRL_PIN(51, "C16 PCI AD28"), | |
199 | PINCTRL_PIN(52, "C17 PCI AD27"), | |
200 | PINCTRL_PIN(53, "C18 PCI AD26"), | |
201 | /* Row D */ | |
202 | PINCTRL_PIN(54, "D1 AVCCKHA"), | |
203 | PINCTRL_PIN(55, "D2 AGNDIOHA"), | |
204 | PINCTRL_PIN(56, "D3 XTALO"), | |
205 | PINCTRL_PIN(57, "D4 AVCC3IOHA"), | |
206 | PINCTRL_PIN(58, "D5 DRAM A8"), | |
207 | PINCTRL_PIN(59, "D6 DRAM A9"), | |
208 | PINCTRL_PIN(60, "D7 DRAM DQ9"), | |
209 | PINCTRL_PIN(61, "D8 DRAM DQ13"), | |
210 | PINCTRL_PIN(62, "D9 DRAM DQ2"), | |
211 | PINCTRL_PIN(63, "D10 DRAM A13"), | |
212 | PINCTRL_PIN(64, "D11 DRAM RAS N"), | |
213 | PINCTRL_PIN(65, "D12 DRAM A1"), | |
214 | PINCTRL_PIN(66, "D13 PCI INTC N"), | |
215 | PINCTRL_PIN(67, "D14 PCI CLK"), | |
216 | PINCTRL_PIN(68, "D15 PCI AD25"), | |
217 | PINCTRL_PIN(69, "D16 PCI AD24"), | |
218 | PINCTRL_PIN(70, "D17 PCI CBE3 N"), | |
219 | PINCTRL_PIN(71, "D18 PCI AD23"), | |
220 | /* Row E */ | |
221 | PINCTRL_PIN(72, "E1 AVCC3IOHA"), | |
222 | PINCTRL_PIN(73, "E2 EBG"), | |
223 | PINCTRL_PIN(74, "E3 AVCC3IOHB"), | |
224 | PINCTRL_PIN(75, "E4 REXT"), | |
225 | PINCTRL_PIN(76, "E5 GND"), | |
226 | PINCTRL_PIN(77, "E6 DRAM DQM1"), | |
227 | PINCTRL_PIN(78, "E7 DRAM DQ8"), | |
228 | PINCTRL_PIN(79, "E8 DRAM DQ12"), | |
229 | PINCTRL_PIN(80, "E9 DRAM DQ1"), | |
230 | PINCTRL_PIN(81, "E10 DRAM DQM0"), | |
231 | PINCTRL_PIN(82, "E11 DRAM BA0"), | |
232 | PINCTRL_PIN(83, "E12 PCI INTA N"), | |
233 | PINCTRL_PIN(84, "E13 PCI INTB N"), | |
234 | PINCTRL_PIN(85, "E14 GND"), | |
235 | PINCTRL_PIN(86, "E15 PCI AD22"), | |
236 | PINCTRL_PIN(87, "E16 PCI AD21"), | |
237 | PINCTRL_PIN(88, "E17 PCI AD20"), | |
238 | PINCTRL_PIN(89, "E18 PCI AD19"), | |
239 | /* Row F */ | |
240 | PINCTRL_PIN(90, "F1 SATA0 RXDP"), | |
241 | PINCTRL_PIN(91, "F2 SATA0 RXDN"), | |
242 | PINCTRL_PIN(92, "F3 AGNDK 0"), | |
243 | PINCTRL_PIN(93, "F4 AVCC3 S"), | |
244 | PINCTRL_PIN(94, "F5 AVCCK P"), | |
245 | PINCTRL_PIN(95, "F6 GND"), | |
246 | PINCTRL_PIN(96, "F7 VCC2IOHA 2"), | |
247 | PINCTRL_PIN(97, "F8 VCC2IOHA 2"), | |
248 | PINCTRL_PIN(98, "F9 V1"), | |
249 | PINCTRL_PIN(99, "F10 V1"), | |
250 | PINCTRL_PIN(100, "F11 VCC2IOHA 2"), | |
251 | PINCTRL_PIN(101, "F12 VCC2IOHA 2"), | |
252 | PINCTRL_PIN(102, "F13 GND"), | |
253 | PINCTRL_PIN(103, "F14 PCI AD18"), | |
254 | PINCTRL_PIN(104, "F15 PCI AD17"), | |
255 | PINCTRL_PIN(105, "F16 PCI AD16"), | |
256 | PINCTRL_PIN(106, "F17 PCI CBE2 N"), | |
257 | PINCTRL_PIN(107, "F18 PCI FRAME N"), | |
258 | /* Row G */ | |
259 | PINCTRL_PIN(108, "G1 SATA0 TXDP"), | |
260 | PINCTRL_PIN(109, "G2 SATA0 TXDN"), | |
261 | PINCTRL_PIN(110, "G3 AGNDK 1"), | |
262 | PINCTRL_PIN(111, "G4 AVCCK 0"), | |
263 | PINCTRL_PIN(112, "G5 TEST CLKOUT"), | |
264 | PINCTRL_PIN(113, "G6 AGND"), | |
265 | PINCTRL_PIN(114, "G7 GND"), | |
266 | PINCTRL_PIN(115, "G8 VCC2IOHA 2"), | |
267 | PINCTRL_PIN(116, "G9 V1"), | |
268 | PINCTRL_PIN(117, "G10 V1"), | |
269 | PINCTRL_PIN(118, "G11 VCC2IOHA 2"), | |
270 | PINCTRL_PIN(119, "G12 GND"), | |
271 | PINCTRL_PIN(120, "G13 VCC3IOHA"), | |
272 | PINCTRL_PIN(121, "G14 PCI IRDY N"), | |
273 | PINCTRL_PIN(122, "G15 PCI TRDY N"), | |
274 | PINCTRL_PIN(123, "G16 PCI DEVSEL N"), | |
275 | PINCTRL_PIN(124, "G17 PCI STOP N"), | |
276 | PINCTRL_PIN(125, "G18 PCI PAR"), | |
277 | /* Row H */ | |
278 | PINCTRL_PIN(126, "H1 SATA1 TXDP"), | |
279 | PINCTRL_PIN(127, "H2 SATA1 TXDN"), | |
280 | PINCTRL_PIN(128, "H3 AGNDK 2"), | |
281 | PINCTRL_PIN(129, "H4 AVCCK 1"), | |
282 | PINCTRL_PIN(130, "H5 AVCCK S"), | |
283 | PINCTRL_PIN(131, "H6 AVCCKHB"), | |
284 | PINCTRL_PIN(132, "H7 AGND"), | |
285 | PINCTRL_PIN(133, "H8 GND"), | |
286 | PINCTRL_PIN(134, "H9 GND"), | |
287 | PINCTRL_PIN(135, "H10 GND"), | |
288 | PINCTRL_PIN(136, "H11 GND"), | |
289 | PINCTRL_PIN(137, "H12 VCC3IOHA"), | |
290 | PINCTRL_PIN(138, "H13 VCC3IOHA"), | |
291 | PINCTRL_PIN(139, "H14 PCI CBE1 N"), | |
292 | PINCTRL_PIN(140, "H15 PCI AD15"), | |
293 | PINCTRL_PIN(141, "H16 PCI AD14"), | |
294 | PINCTRL_PIN(142, "H17 PCI AD13"), | |
295 | PINCTRL_PIN(143, "H18 PCI AD12"), | |
296 | /* Row J (for some reason I is skipped) */ | |
297 | PINCTRL_PIN(144, "J1 SATA1 RXDP"), | |
298 | PINCTRL_PIN(145, "J2 SATA1 RXDN"), | |
299 | PINCTRL_PIN(146, "J3 AGNDK 3"), | |
300 | PINCTRL_PIN(147, "J4 AVCCK 2"), | |
301 | PINCTRL_PIN(148, "J5 IDE DA1"), | |
302 | PINCTRL_PIN(149, "J6 V1"), | |
303 | PINCTRL_PIN(150, "J7 V1"), | |
304 | PINCTRL_PIN(151, "J8 GND"), | |
305 | PINCTRL_PIN(152, "J9 GND"), | |
306 | PINCTRL_PIN(153, "J10 GND"), | |
307 | PINCTRL_PIN(154, "J11 GND"), | |
308 | PINCTRL_PIN(155, "J12 V1"), | |
309 | PINCTRL_PIN(156, "J13 V1"), | |
310 | PINCTRL_PIN(157, "J14 PCI AD11"), | |
311 | PINCTRL_PIN(158, "J15 PCI AD10"), | |
312 | PINCTRL_PIN(159, "J16 PCI AD9"), | |
313 | PINCTRL_PIN(160, "J17 PCI AD8"), | |
314 | PINCTRL_PIN(161, "J18 PCI CBE0 N"), | |
315 | /* Row K */ | |
316 | PINCTRL_PIN(162, "K1 IDE CS1 N"), | |
317 | PINCTRL_PIN(163, "K2 IDE CS0 N"), | |
318 | PINCTRL_PIN(164, "K3 AVCCK 3"), | |
319 | PINCTRL_PIN(165, "K4 IDE DA2"), | |
320 | PINCTRL_PIN(166, "K5 IDE DA0"), | |
321 | PINCTRL_PIN(167, "K6 V1"), | |
322 | PINCTRL_PIN(168, "K7 V1"), | |
323 | PINCTRL_PIN(169, "K8 GND"), | |
324 | PINCTRL_PIN(170, "K9 GND"), | |
325 | PINCTRL_PIN(171, "K10 GND"), | |
326 | PINCTRL_PIN(172, "K11 GND"), | |
327 | PINCTRL_PIN(173, "K12 V1"), | |
328 | PINCTRL_PIN(174, "K13 V1"), | |
329 | PINCTRL_PIN(175, "K14 PCI AD3"), | |
330 | PINCTRL_PIN(176, "K15 PCI AD4"), | |
331 | PINCTRL_PIN(177, "K16 PCI AD5"), | |
332 | PINCTRL_PIN(178, "K17 PCI AD6"), | |
333 | PINCTRL_PIN(179, "K18 PCI AD7"), | |
334 | /* Row L */ | |
335 | PINCTRL_PIN(180, "L1 IDE INTRQ"), | |
336 | PINCTRL_PIN(181, "L2 IDE DMACK N"), | |
337 | PINCTRL_PIN(182, "L3 IDE IORDY"), | |
338 | PINCTRL_PIN(183, "L4 IDE DIOR N"), | |
339 | PINCTRL_PIN(184, "L5 IDE DIOW N"), | |
340 | PINCTRL_PIN(185, "L6 VCC3IOHA"), | |
341 | PINCTRL_PIN(186, "L7 VCC3IOHA"), | |
342 | PINCTRL_PIN(187, "L8 GND"), | |
343 | PINCTRL_PIN(188, "L9 GND"), | |
344 | PINCTRL_PIN(189, "L10 GND"), | |
345 | PINCTRL_PIN(190, "L11 GND"), | |
346 | PINCTRL_PIN(191, "L12 VCC3IOHA"), | |
347 | PINCTRL_PIN(192, "L13 VCC3IOHA"), | |
348 | PINCTRL_PIN(193, "L14 GPIO0 30"), | |
349 | PINCTRL_PIN(194, "L15 GPIO0 31"), | |
350 | PINCTRL_PIN(195, "L16 PCI AD0"), | |
351 | PINCTRL_PIN(196, "L17 PCI AD1"), | |
352 | PINCTRL_PIN(197, "L18 PCI AD2"), | |
353 | /* Row M */ | |
354 | PINCTRL_PIN(198, "M1 IDE DMARQ"), | |
355 | PINCTRL_PIN(199, "M2 IDE DD15"), | |
356 | PINCTRL_PIN(200, "M3 IDE DD0"), | |
357 | PINCTRL_PIN(201, "M4 IDE DD14"), | |
358 | PINCTRL_PIN(202, "M5 IDE DD1"), | |
359 | PINCTRL_PIN(203, "M6 VCC3IOHA"), | |
360 | PINCTRL_PIN(204, "M7 GND"), | |
361 | PINCTRL_PIN(205, "M8 VCC2IOHA 1"), | |
362 | PINCTRL_PIN(206, "M9 V1"), | |
363 | PINCTRL_PIN(207, "M10 V1"), | |
364 | PINCTRL_PIN(208, "M11 VCC3IOHA"), | |
365 | PINCTRL_PIN(209, "M12 GND"), | |
366 | PINCTRL_PIN(210, "M13 VCC3IOHA"), | |
367 | PINCTRL_PIN(211, "M14 GPIO0 25"), | |
368 | PINCTRL_PIN(212, "M15 GPIO0 26"), | |
369 | PINCTRL_PIN(213, "M16 GPIO0 27"), | |
370 | PINCTRL_PIN(214, "M17 GPIO0 28"), | |
371 | PINCTRL_PIN(215, "M18 GPIO0 29"), | |
372 | /* Row N */ | |
373 | PINCTRL_PIN(216, "N1 IDE DD13"), | |
374 | PINCTRL_PIN(217, "N2 IDE DD2"), | |
375 | PINCTRL_PIN(218, "N3 IDE DD12"), | |
376 | PINCTRL_PIN(219, "N4 IDE DD3"), | |
377 | PINCTRL_PIN(220, "N5 IDE DD11"), | |
378 | PINCTRL_PIN(221, "N6 GND"), | |
379 | PINCTRL_PIN(222, "N7 VCC2IOHA 1"), | |
380 | PINCTRL_PIN(223, "N8 VCC2IOHA 1"), | |
381 | PINCTRL_PIN(224, "N9 V1"), | |
382 | PINCTRL_PIN(225, "N10 V1"), | |
383 | PINCTRL_PIN(226, "N11 VCC3IOHA"), | |
384 | PINCTRL_PIN(227, "N12 VCC3IOHA"), | |
385 | PINCTRL_PIN(228, "N13 GND"), | |
386 | PINCTRL_PIN(229, "N14 GPIO0 20"), | |
387 | PINCTRL_PIN(230, "N15 GPIO0 21"), | |
388 | PINCTRL_PIN(231, "N16 GPIO0 22"), | |
389 | PINCTRL_PIN(232, "N17 GPIO0 23"), | |
390 | PINCTRL_PIN(233, "N18 GPIO0 24"), | |
391 | /* Row P (for some reason O is skipped) */ | |
392 | PINCTRL_PIN(234, "P1 IDE DD4"), | |
393 | PINCTRL_PIN(235, "P2 IDE DD10"), | |
394 | PINCTRL_PIN(236, "P3 IDE DD5"), | |
395 | PINCTRL_PIN(237, "P4 IDE DD9"), | |
396 | PINCTRL_PIN(238, "P5 GND"), | |
397 | PINCTRL_PIN(239, "P6 USB XSCO"), | |
398 | PINCTRL_PIN(240, "P7 GMAC0 TXD3"), | |
399 | PINCTRL_PIN(241, "P8 GMAC0 TXEN"), | |
400 | PINCTRL_PIN(242, "P9 GMAC0 RXD2"), | |
401 | PINCTRL_PIN(243, "P10 GMAC1 TXC"), | |
402 | PINCTRL_PIN(244, "P11 GMAC1 RXD1"), | |
403 | PINCTRL_PIN(245, "P12 MODE SEL 1"), | |
404 | PINCTRL_PIN(246, "P13 GPIO1 28"), | |
405 | PINCTRL_PIN(247, "P14 GND"), | |
406 | PINCTRL_PIN(248, "P15 GPIO0 5"), | |
407 | PINCTRL_PIN(249, "P16 GPIO0 17"), | |
408 | PINCTRL_PIN(250, "P17 GPIO0 18"), | |
409 | PINCTRL_PIN(251, "P18 GPIO0 19"), | |
410 | /* Row R (for some reason Q us skipped) */ | |
411 | PINCTRL_PIN(252, "R1 IDE DD6"), | |
412 | PINCTRL_PIN(253, "R2 IDE DD8"), | |
413 | PINCTRL_PIN(254, "R3 IDE DD7"), | |
414 | PINCTRL_PIN(255, "R4 IDE RESET N"), | |
415 | PINCTRL_PIN(256, "R5 ICE0 DBGACK"), | |
416 | PINCTRL_PIN(257, "R6 USB XSCI"), | |
417 | PINCTRL_PIN(258, "R7 GMAC0 TXD2"), | |
418 | PINCTRL_PIN(259, "R8 GMAC0 RXDV"), | |
419 | PINCTRL_PIN(260, "R9 GMAC0 RXD3"), | |
420 | PINCTRL_PIN(261, "R10 GMAC1 TXD0"), | |
421 | PINCTRL_PIN(262, "R11 GMAC1 RXD0"), | |
422 | PINCTRL_PIN(263, "R12 MODE SEL 0"), | |
423 | PINCTRL_PIN(264, "R13 MODE SEL 3"), | |
424 | PINCTRL_PIN(265, "R14 GPIO0 0"), | |
425 | PINCTRL_PIN(266, "R15 GPIO0 4"), | |
426 | PINCTRL_PIN(267, "R16 GPIO0 9"), | |
427 | PINCTRL_PIN(268, "R17 GPIO0 15"), | |
428 | PINCTRL_PIN(269, "R18 GPIO0 16"), | |
429 | /* Row T (for some reason S is skipped) */ | |
430 | PINCTRL_PIN(270, "T1 ICE0 DBGRQ"), | |
431 | PINCTRL_PIN(271, "T2 ICE0 IDO"), | |
432 | PINCTRL_PIN(272, "T3 ICE0 ICK"), | |
433 | PINCTRL_PIN(273, "T4 ICE0 IMS"), | |
434 | PINCTRL_PIN(274, "T5 ICE0 IDI"), | |
435 | PINCTRL_PIN(275, "T6 USB RREF"), | |
436 | PINCTRL_PIN(276, "T7 GMAC0 TXD1"), | |
437 | PINCTRL_PIN(277, "T8 GMAC0 RXC"), | |
438 | PINCTRL_PIN(278, "T9 GMAC0 CRS"), | |
439 | PINCTRL_PIN(279, "T10 GMAC1 TXD1"), | |
440 | PINCTRL_PIN(280, "T11 GMAC1 RXC"), | |
441 | PINCTRL_PIN(281, "T12 GMAC1 CRS"), | |
442 | PINCTRL_PIN(282, "T13 EXT CLK"), | |
443 | PINCTRL_PIN(283, "T14 GPIO1 31"), | |
444 | PINCTRL_PIN(284, "T15 GPIO0 3"), | |
445 | PINCTRL_PIN(285, "T16 GPIO0 8"), | |
446 | PINCTRL_PIN(286, "T17 GPIO0 12"), | |
447 | PINCTRL_PIN(287, "T18 GPIO0 14"), | |
448 | /* Row U */ | |
449 | PINCTRL_PIN(288, "U1 ICE0 IRST N"), | |
450 | PINCTRL_PIN(289, "U2 USB0 VCCHSRT"), | |
451 | PINCTRL_PIN(290, "U3 USB0 DP"), | |
452 | PINCTRL_PIN(291, "U4 USB VCCA U20"), | |
453 | PINCTRL_PIN(292, "U5 USB1 DP"), | |
454 | PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"), | |
455 | PINCTRL_PIN(294, "U7 GMAC0 TXD0"), | |
456 | PINCTRL_PIN(295, "U8 GMAC0 RXD0"), | |
457 | PINCTRL_PIN(296, "U9 GMAC1 COL"), | |
458 | PINCTRL_PIN(297, "U10 GMAC1 TXD2"), | |
459 | PINCTRL_PIN(298, "U11 GMAC1 RXDV"), | |
460 | PINCTRL_PIN(299, "U12 GMAC1 RXD3"), | |
461 | PINCTRL_PIN(300, "U13 MODE SEL 2"), | |
462 | PINCTRL_PIN(301, "U14 GPIO1 30"), | |
463 | PINCTRL_PIN(302, "U15 GPIO0 2"), | |
464 | PINCTRL_PIN(303, "U16 GPIO0 7"), | |
465 | PINCTRL_PIN(304, "U17 GPIO0 11"), | |
466 | PINCTRL_PIN(305, "U18 GPIO0 13"), | |
467 | /* Row V */ | |
468 | PINCTRL_PIN(306, "V1 USB0 GNDHSRT"), | |
469 | PINCTRL_PIN(307, "V2 USB0 DM"), | |
470 | PINCTRL_PIN(308, "V3 USB GNDA U20"), | |
471 | PINCTRL_PIN(309, "V4 USB1 DM"), | |
472 | PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"), | |
473 | PINCTRL_PIN(311, "V6 GMAC0 COL"), | |
474 | PINCTRL_PIN(312, "V7 GMAC0 TXC"), | |
475 | PINCTRL_PIN(313, "V8 GMAC0 RXD1"), | |
476 | PINCTRL_PIN(314, "V9 REF CLK"), | |
477 | PINCTRL_PIN(315, "V10 GMAC1 TXD3"), | |
478 | PINCTRL_PIN(316, "V11 GMAC1 TXEN"), | |
479 | PINCTRL_PIN(317, "V12 GMAC1 RXD2"), | |
480 | PINCTRL_PIN(318, "V13 M30 CLK"), | |
481 | PINCTRL_PIN(319, "V14 GPIO1 29"), | |
482 | PINCTRL_PIN(320, "V15 GPIO0 1"), | |
483 | PINCTRL_PIN(321, "V16 GPIO0 6"), | |
484 | PINCTRL_PIN(322, "V17 GPIO0 10"), | |
485 | PINCTRL_PIN(323, "V18 SYS RESET N"), | |
486 | }; | |
487 | ||
488 | ||
489 | /* Digital ground */ | |
490 | static const unsigned int gnd_3512_pins[] = { | |
491 | 76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169, | |
492 | 170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247 | |
493 | }; | |
494 | ||
495 | static const unsigned int dram_3512_pins[] = { | |
496 | 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29, | |
497 | 30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77, | |
498 | 78, 79, 80, 81, 82 | |
499 | }; | |
500 | ||
501 | static const unsigned int rtc_3512_pins[] = { 57, 20, 39 }; | |
502 | ||
503 | static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 }; | |
504 | ||
505 | static const unsigned int system_3512_pins[] = { | |
506 | 318, 264, 300, 245, 263, 282, 314, 323, 49, | |
507 | }; | |
508 | ||
509 | static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 }; | |
510 | ||
511 | static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 }; | |
512 | ||
513 | static const unsigned int ide_3512_pins[] = { | |
514 | 162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202, | |
515 | 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255 | |
516 | }; | |
517 | ||
518 | static const unsigned int sata_3512_pins[] = { | |
519 | 75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129, | |
520 | 128, 127, 126, 147, 146, 145, 144, 164 | |
521 | }; | |
522 | ||
523 | static const unsigned int usb_3512_pins[] = { | |
524 | 306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293 | |
525 | }; | |
526 | ||
527 | /* GMII, ethernet pins */ | |
756a024f LW |
528 | static const unsigned int gmii_gmac0_3512_pins[] = { |
529 | 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313 | |
530 | }; | |
531 | ||
532 | static const unsigned int gmii_gmac1_3512_pins[] = { | |
533 | 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317 | |
06351d13 LW |
534 | }; |
535 | ||
536 | static const unsigned int pci_3512_pins[] = { | |
537 | 13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69, | |
538 | 70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123, | |
539 | 124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177, | |
540 | 178, 179, 195, 196, 197 | |
541 | }; | |
542 | ||
543 | /* | |
544 | * Apparently the LPC interface is using the PCICLK for the clocking so | |
545 | * PCI needs to be active at the same time. | |
546 | */ | |
547 | static const unsigned int lpc_3512_pins[] = { | |
548 | 285, /* LPC_LAD[0] */ | |
549 | 304, /* LPC_SERIRQ */ | |
550 | 286, /* LPC_LAD[2] */ | |
551 | 305, /* LPC_LFRAME# */ | |
552 | 287, /* LPC_LAD[3] */ | |
553 | 268, /* LPC_LAD[1] */ | |
554 | }; | |
555 | ||
556 | /* Character LCD */ | |
557 | static const unsigned int lcd_3512_pins[] = { | |
558 | 262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211 | |
559 | }; | |
560 | ||
561 | static const unsigned int ssp_3512_pins[] = { | |
562 | 285, /* SSP_97RST# SSP AC97 Reset, active low */ | |
563 | 304, /* SSP_FSC */ | |
564 | 286, /* SSP_ECLK */ | |
565 | 305, /* SSP_TXD */ | |
566 | 287, /* SSP_RXD */ | |
567 | 268, /* SSP_SCLK */ | |
568 | }; | |
569 | ||
570 | static const unsigned int uart_rxtx_3512_pins[] = { | |
571 | 267, /* UART_SIN serial input, RX */ | |
572 | 322, /* UART_SOUT serial output, TX */ | |
573 | }; | |
574 | ||
575 | static const unsigned int uart_modem_3512_pins[] = { | |
576 | 285, /* UART_NDCD DCD carrier detect */ | |
577 | 304, /* UART_NDTR DTR data terminal ready */ | |
578 | 286, /* UART_NDSR DSR data set ready */ | |
579 | 305, /* UART_NRTS RTS request to send */ | |
580 | 287, /* UART_NCTS CTS clear to send */ | |
581 | 268, /* UART_NRI RI ring indicator */ | |
582 | }; | |
583 | ||
584 | static const unsigned int tvc_3512_pins[] = { | |
585 | 246, /* TVC_DATA[0] */ | |
586 | 319, /* TVC_DATA[1] */ | |
587 | 301, /* TVC_DATA[2] */ | |
588 | 283, /* TVC_DATA[3] */ | |
589 | 265, /* TVC_CLK */ | |
590 | 320, /* TVC_DATA[4] */ | |
591 | 302, /* TVC_DATA[5] */ | |
592 | 284, /* TVC_DATA[6] */ | |
593 | 266, /* TVC_DATA[7] */ | |
594 | }; | |
595 | ||
596 | /* NAND flash pins */ | |
597 | static const unsigned int nflash_3512_pins[] = { | |
598 | 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, | |
599 | 253, 254, 249, 250, 232, 233, 211, 193, 194 | |
600 | }; | |
601 | ||
602 | /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ | |
603 | static const unsigned int pflash_3512_pins[] = { | |
604 | 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, | |
605 | 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, | |
606 | 214, 215, 193, 194 | |
607 | }; | |
608 | ||
609 | /* | |
610 | * The parallel flash can be set up in a 26-bit address bus mode exposing | |
611 | * A[0-15] (A[15] takes the place of ALE), but it has the | |
612 | * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be | |
613 | * used at the same time. | |
614 | */ | |
615 | static const unsigned int pflash_3512_pins_extended[] = { | |
616 | 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, | |
617 | 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, | |
618 | 214, 215, 193, 194, | |
619 | /* The extra pins */ | |
620 | 296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281, | |
621 | 265, | |
622 | }; | |
623 | ||
624 | /* Serial flash pins CE0, CE1, DI, DO, CK */ | |
625 | static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 }; | |
626 | ||
627 | /* The GPIO0A (0) pin overlap with TVC and extended parallel flash */ | |
628 | static const unsigned int gpio0a_3512_pins[] = { 265 }; | |
629 | ||
630 | /* The GPIO0B (1-4) pins overlap with TVC and ICE */ | |
631 | static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 }; | |
632 | ||
633 | /* The GPIO0C (5-7) pins overlap with ICE */ | |
634 | static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 }; | |
635 | ||
636 | /* The GPIO0D (9,10) pins overlap with UART RX/TX */ | |
637 | static const unsigned int gpio0d_3512_pins[] = { 267, 322 }; | |
638 | ||
639 | /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */ | |
640 | static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 }; | |
641 | ||
642 | /* The GPIO0F (16) pins overlap with LCD */ | |
643 | static const unsigned int gpio0f_3512_pins[] = { 269 }; | |
644 | ||
645 | /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */ | |
646 | static const unsigned int gpio0g_3512_pins[] = { 249, 250 }; | |
647 | ||
648 | /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */ | |
649 | static const unsigned int gpio0h_3512_pins[] = { 251, 229 }; | |
650 | ||
651 | /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */ | |
652 | static const unsigned int gpio0i_3512_pins[] = { 230, 231 }; | |
653 | ||
654 | /* The GPIO0J (23) pins overlap with all flash */ | |
655 | static const unsigned int gpio0j_3512_pins[] = { 232 }; | |
656 | ||
657 | /* The GPIO0K (24,25) pins overlap with all flash and LCD */ | |
658 | static const unsigned int gpio0k_3512_pins[] = { 233, 211 }; | |
659 | ||
660 | /* The GPIO0L (26-29) pins overlap with parallel flash */ | |
661 | static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 }; | |
662 | ||
663 | /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */ | |
664 | static const unsigned int gpio0m_3512_pins[] = { 193, 194 }; | |
665 | ||
666 | /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ | |
667 | static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 }; | |
668 | ||
669 | /* The GPIO1B (5-10, 27) pins overlap with just IDE */ | |
670 | static const unsigned int gpio1b_3512_pins[] = { | |
671 | 180, 181, 182, 183, 184, 198, 255 | |
672 | }; | |
673 | ||
674 | /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ | |
675 | static const unsigned int gpio1c_3512_pins[] = { | |
676 | 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, | |
677 | 252, 253, 254 | |
678 | }; | |
679 | ||
680 | /* The GPIO1D (28-31) pins overlap with LCD and TVC */ | |
681 | static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; | |
682 | ||
756a024f | 683 | /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ |
06351d13 LW |
684 | static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; |
685 | ||
756a024f | 686 | /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ |
06351d13 LW |
687 | static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; |
688 | ||
689 | /* The GPIO2C (8-31) pins overlap with PCI */ | |
690 | static const unsigned int gpio2c_3512_pins[] = { | |
691 | 17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105, | |
692 | 140, 141, 142, 143, 157, 158, 159, 160 | |
693 | }; | |
694 | ||
695 | /* Groups for the 3512 SoC/package */ | |
696 | static const struct gemini_pin_group gemini_3512_pin_groups[] = { | |
697 | { | |
698 | .name = "gndgrp", | |
699 | .pins = gnd_3512_pins, | |
700 | .num_pins = ARRAY_SIZE(gnd_3512_pins), | |
701 | }, | |
702 | { | |
703 | .name = "dramgrp", | |
704 | .pins = dram_3512_pins, | |
705 | .num_pins = ARRAY_SIZE(dram_3512_pins), | |
706 | .mask = DRAM_PADS_POWERDOWN, | |
707 | }, | |
708 | { | |
709 | .name = "rtcgrp", | |
710 | .pins = rtc_3512_pins, | |
711 | .num_pins = ARRAY_SIZE(rtc_3512_pins), | |
712 | }, | |
713 | { | |
714 | .name = "powergrp", | |
715 | .pins = power_3512_pins, | |
716 | .num_pins = ARRAY_SIZE(power_3512_pins), | |
717 | }, | |
718 | { | |
719 | .name = "systemgrp", | |
720 | .pins = system_3512_pins, | |
721 | .num_pins = ARRAY_SIZE(system_3512_pins), | |
722 | }, | |
723 | { | |
724 | .name = "vcontrolgrp", | |
725 | .pins = vcontrol_3512_pins, | |
726 | .num_pins = ARRAY_SIZE(vcontrol_3512_pins), | |
727 | }, | |
728 | { | |
729 | .name = "icegrp", | |
730 | .pins = ice_3512_pins, | |
731 | .num_pins = ARRAY_SIZE(ice_3512_pins), | |
732 | /* Conflict with some GPIO groups */ | |
733 | }, | |
734 | { | |
735 | .name = "idegrp", | |
736 | .pins = ide_3512_pins, | |
737 | .num_pins = ARRAY_SIZE(ide_3512_pins), | |
738 | /* Conflict with all flash usage */ | |
739 | .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | | |
740 | PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, | |
741 | }, | |
742 | { | |
743 | .name = "satagrp", | |
744 | .pins = sata_3512_pins, | |
745 | .num_pins = ARRAY_SIZE(sata_3512_pins), | |
746 | }, | |
747 | { | |
748 | .name = "usbgrp", | |
749 | .pins = usb_3512_pins, | |
750 | .num_pins = ARRAY_SIZE(usb_3512_pins), | |
751 | }, | |
752 | { | |
756a024f LW |
753 | .name = "gmii_gmac0_grp", |
754 | .pins = gmii_gmac0_3512_pins, | |
755 | .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins), | |
756 | }, | |
757 | { | |
758 | .name = "gmii_gmac1_grp", | |
759 | .pins = gmii_gmac1_3512_pins, | |
760 | .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins), | |
761 | /* Bring out RGMII on the GMAC1 pins */ | |
762 | .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, | |
06351d13 LW |
763 | }, |
764 | { | |
765 | .name = "pcigrp", | |
766 | .pins = pci_3512_pins, | |
767 | .num_pins = ARRAY_SIZE(pci_3512_pins), | |
768 | /* Conflict only with GPIO2 */ | |
769 | .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, | |
770 | }, | |
771 | { | |
772 | .name = "lpcgrp", | |
773 | .pins = lpc_3512_pins, | |
774 | .num_pins = ARRAY_SIZE(lpc_3512_pins), | |
775 | /* Conflict with SSP and UART modem pins */ | |
776 | .mask = SSP_PADS_ENABLE, | |
777 | .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, | |
778 | }, | |
779 | { | |
780 | .name = "lcdgrp", | |
781 | .pins = lcd_3512_pins, | |
782 | .num_pins = ARRAY_SIZE(lcd_3512_pins), | |
783 | /* Conflict with TVC and ICE */ | |
784 | .mask = TVC_PADS_ENABLE, | |
785 | .value = LCD_PADS_ENABLE, | |
786 | }, | |
787 | { | |
788 | .name = "sspgrp", | |
789 | .pins = ssp_3512_pins, | |
790 | .num_pins = ARRAY_SIZE(ssp_3512_pins), | |
791 | /* Conflict with LPC and UART modem pins */ | |
792 | .mask = LPC_PADS_ENABLE, | |
793 | .value = SSP_PADS_ENABLE, | |
794 | }, | |
795 | { | |
796 | .name = "uartrxtxgrp", | |
797 | .pins = uart_rxtx_3512_pins, | |
798 | .num_pins = ARRAY_SIZE(uart_rxtx_3512_pins), | |
799 | /* No conflicts except GPIO */ | |
800 | }, | |
801 | { | |
802 | .name = "uartmodemgrp", | |
803 | .pins = uart_modem_3512_pins, | |
804 | .num_pins = ARRAY_SIZE(uart_modem_3512_pins), | |
805 | /* | |
806 | * Conflict with LPC and SSP, | |
807 | * so when those are both disabled, modem UART can thrive. | |
808 | */ | |
809 | .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, | |
810 | }, | |
811 | { | |
812 | .name = "tvcgrp", | |
813 | .pins = tvc_3512_pins, | |
814 | .num_pins = ARRAY_SIZE(tvc_3512_pins), | |
815 | /* Conflict with character LCD and ICE */ | |
816 | .mask = LCD_PADS_ENABLE, | |
817 | .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE, | |
818 | }, | |
819 | /* | |
820 | * The construction is done such that it is possible to use a serial | |
821 | * flash together with a NAND or parallel (NOR) flash, but it is not | |
822 | * possible to use NAND and parallel flash together. To use serial | |
823 | * flash with one of the two others, the muxbits need to be flipped | |
824 | * around before any access. | |
825 | */ | |
826 | { | |
827 | .name = "nflashgrp", | |
828 | .pins = nflash_3512_pins, | |
829 | .num_pins = ARRAY_SIZE(nflash_3512_pins), | |
830 | /* Conflict with IDE, parallel and serial flash */ | |
831 | .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, | |
832 | .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, | |
833 | }, | |
834 | { | |
835 | .name = "pflashgrp", | |
836 | .pins = pflash_3512_pins, | |
837 | .num_pins = ARRAY_SIZE(pflash_3512_pins), | |
838 | /* Conflict with IDE, NAND and serial flash */ | |
839 | .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, | |
840 | .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, | |
841 | }, | |
842 | { | |
843 | .name = "sflashgrp", | |
844 | .pins = sflash_3512_pins, | |
845 | .num_pins = ARRAY_SIZE(sflash_3512_pins), | |
846 | /* Conflict with IDE, NAND and parallel flash */ | |
847 | .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, | |
848 | .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, | |
849 | }, | |
850 | { | |
851 | .name = "gpio0agrp", | |
852 | .pins = gpio0a_3512_pins, | |
853 | .num_pins = ARRAY_SIZE(gpio0a_3512_pins), | |
854 | /* Conflict with TVC */ | |
855 | .mask = TVC_PADS_ENABLE, | |
856 | }, | |
857 | { | |
858 | .name = "gpio0bgrp", | |
859 | .pins = gpio0b_3512_pins, | |
860 | .num_pins = ARRAY_SIZE(gpio0b_3512_pins), | |
861 | /* Conflict with TVC and ICE */ | |
862 | .mask = TVC_PADS_ENABLE, | |
863 | }, | |
864 | { | |
865 | .name = "gpio0cgrp", | |
866 | .pins = gpio0c_3512_pins, | |
867 | .num_pins = ARRAY_SIZE(gpio0c_3512_pins), | |
868 | /* Conflict with ICE */ | |
869 | }, | |
870 | { | |
871 | .name = "gpio0dgrp", | |
872 | .pins = gpio0d_3512_pins, | |
873 | .num_pins = ARRAY_SIZE(gpio0d_3512_pins), | |
874 | /* Conflict with UART RX/TX */ | |
875 | }, | |
876 | { | |
877 | .name = "gpio0egrp", | |
878 | .pins = gpio0e_3512_pins, | |
879 | .num_pins = ARRAY_SIZE(gpio0e_3512_pins), | |
880 | /* Conflict with LPC, UART modem pins, SSP */ | |
881 | .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, | |
882 | }, | |
883 | { | |
884 | .name = "gpio0fgrp", | |
885 | .pins = gpio0f_3512_pins, | |
886 | .num_pins = ARRAY_SIZE(gpio0f_3512_pins), | |
887 | /* Conflict with LCD */ | |
888 | .mask = LCD_PADS_ENABLE, | |
889 | }, | |
890 | { | |
891 | .name = "gpio0ggrp", | |
892 | .pins = gpio0g_3512_pins, | |
893 | .num_pins = ARRAY_SIZE(gpio0g_3512_pins), | |
894 | /* Conflict with NAND flash */ | |
895 | .value = NAND_PADS_DISABLE, | |
896 | }, | |
897 | { | |
898 | .name = "gpio0hgrp", | |
899 | .pins = gpio0h_3512_pins, | |
900 | .num_pins = ARRAY_SIZE(gpio0h_3512_pins), | |
901 | /* Conflict with parallel flash */ | |
902 | .value = PFLASH_PADS_DISABLE, | |
903 | }, | |
904 | { | |
905 | .name = "gpio0igrp", | |
906 | .pins = gpio0i_3512_pins, | |
907 | .num_pins = ARRAY_SIZE(gpio0i_3512_pins), | |
908 | /* Conflict with serial flash */ | |
909 | .value = SFLASH_PADS_DISABLE, | |
910 | }, | |
911 | { | |
912 | .name = "gpio0jgrp", | |
913 | .pins = gpio0j_3512_pins, | |
914 | .num_pins = ARRAY_SIZE(gpio0j_3512_pins), | |
915 | /* Conflict with all flash */ | |
916 | .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | | |
917 | SFLASH_PADS_DISABLE, | |
918 | }, | |
919 | { | |
920 | .name = "gpio0kgrp", | |
921 | .pins = gpio0k_3512_pins, | |
922 | .num_pins = ARRAY_SIZE(gpio0k_3512_pins), | |
923 | /* Conflict with all flash and LCD */ | |
924 | .mask = LCD_PADS_ENABLE, | |
925 | .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | | |
926 | SFLASH_PADS_DISABLE, | |
927 | }, | |
928 | { | |
929 | .name = "gpio0lgrp", | |
930 | .pins = gpio0l_3512_pins, | |
931 | .num_pins = ARRAY_SIZE(gpio0l_3512_pins), | |
932 | /* Conflict with parallel flash */ | |
933 | .value = PFLASH_PADS_DISABLE, | |
934 | }, | |
935 | { | |
936 | .name = "gpio0mgrp", | |
937 | .pins = gpio0m_3512_pins, | |
938 | .num_pins = ARRAY_SIZE(gpio0m_3512_pins), | |
939 | /* Conflict with parallel and NAND flash */ | |
940 | .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, | |
941 | }, | |
942 | { | |
943 | .name = "gpio1agrp", | |
944 | .pins = gpio1a_3512_pins, | |
945 | .num_pins = ARRAY_SIZE(gpio1a_3512_pins), | |
946 | /* Conflict with IDE and parallel flash */ | |
947 | .mask = IDE_PADS_ENABLE, | |
948 | .value = PFLASH_PADS_DISABLE, | |
949 | }, | |
950 | { | |
951 | .name = "gpio1bgrp", | |
952 | .pins = gpio1b_3512_pins, | |
953 | .num_pins = ARRAY_SIZE(gpio1b_3512_pins), | |
954 | /* Conflict with IDE only */ | |
955 | .mask = IDE_PADS_ENABLE, | |
956 | }, | |
957 | { | |
958 | .name = "gpio1cgrp", | |
959 | .pins = gpio1c_3512_pins, | |
960 | .num_pins = ARRAY_SIZE(gpio1c_3512_pins), | |
961 | /* Conflict with IDE, parallel and NAND flash */ | |
962 | .mask = IDE_PADS_ENABLE, | |
963 | .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, | |
964 | }, | |
965 | { | |
966 | .name = "gpio1dgrp", | |
967 | .pins = gpio1d_3512_pins, | |
968 | .num_pins = ARRAY_SIZE(gpio1d_3512_pins), | |
969 | /* Conflict with LCD and TVC */ | |
970 | .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE, | |
971 | }, | |
972 | { | |
973 | .name = "gpio2agrp", | |
974 | .pins = gpio2a_3512_pins, | |
975 | .num_pins = ARRAY_SIZE(gpio2a_3512_pins), | |
756a024f LW |
976 | .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, |
977 | /* Conflict with GMII GMAC1 and extended parallel flash */ | |
06351d13 LW |
978 | }, |
979 | { | |
980 | .name = "gpio2bgrp", | |
981 | .pins = gpio2b_3512_pins, | |
982 | .num_pins = ARRAY_SIZE(gpio2b_3512_pins), | |
756a024f LW |
983 | /* Conflict with GMII GMAC1, extended parallel flash and LCD */ |
984 | .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, | |
06351d13 LW |
985 | }, |
986 | { | |
987 | .name = "gpio2cgrp", | |
988 | .pins = gpio2c_3512_pins, | |
989 | .num_pins = ARRAY_SIZE(gpio2c_3512_pins), | |
990 | /* Conflict with PCI */ | |
991 | .mask = PCI_PADS_ENABLE, | |
992 | }, | |
993 | }; | |
994 | ||
995 | /* Pin names for the pinmux subsystem, 3516 variant */ | |
996 | static const struct pinctrl_pin_desc gemini_3516_pins[] = { | |
997 | /* Row A */ | |
998 | PINCTRL_PIN(0, "A1 AVCC3IOHA"), | |
999 | PINCTRL_PIN(1, "A2 DRAM CK N"), | |
1000 | PINCTRL_PIN(2, "A3 DRAM CK"), | |
1001 | PINCTRL_PIN(3, "A4 DRAM DQM1"), | |
1002 | PINCTRL_PIN(4, "A5 DRAM DQ9"), | |
1003 | PINCTRL_PIN(5, "A6 DRAM DQ13"), | |
1004 | PINCTRL_PIN(6, "A7 DRAM DQ1"), | |
1005 | PINCTRL_PIN(7, "A8 DRAM DQ2"), | |
1006 | PINCTRL_PIN(8, "A9 DRAM DQ4"), | |
1007 | PINCTRL_PIN(9, "A10 DRAM VREF"), | |
1008 | PINCTRL_PIN(10, "A11 DRAM DQ24"), | |
1009 | PINCTRL_PIN(11, "A12 DRAM DQ28"), | |
1010 | PINCTRL_PIN(12, "A13 DRAM DQ30"), | |
1011 | PINCTRL_PIN(13, "A14 DRAM DQ18"), | |
1012 | PINCTRL_PIN(14, "A15 DRAM DQ21"), | |
1013 | PINCTRL_PIN(15, "A16 DRAM CAS_N"), | |
1014 | PINCTRL_PIN(16, "A17 DRAM BA1"), | |
1015 | PINCTRL_PIN(17, "A18 PCI INTA N"), | |
1016 | PINCTRL_PIN(18, "A19 PCI INTB N"), | |
1017 | PINCTRL_PIN(19, "A20 PCI INTC N"), | |
1018 | /* Row B */ | |
1019 | PINCTRL_PIN(20, "B1 PWR EN"), | |
1020 | PINCTRL_PIN(21, "B2 GND"), | |
1021 | PINCTRL_PIN(22, "B3 RTC CLKO"), | |
1022 | PINCTRL_PIN(23, "B4 DRAM A5"), | |
1023 | PINCTRL_PIN(24, "B5 DRAM A6"), | |
1024 | PINCTRL_PIN(25, "B6 DRAM DQS1"), | |
1025 | PINCTRL_PIN(26, "B7 DRAM DQ11"), | |
1026 | PINCTRL_PIN(27, "B8 DRAM DQ0"), | |
1027 | PINCTRL_PIN(28, "B9 DRAM DQS0"), | |
1028 | PINCTRL_PIN(29, "B10 DRAM DQ7"), | |
1029 | PINCTRL_PIN(30, "B11 DRAM DQS3"), | |
1030 | PINCTRL_PIN(31, "B12 DRAM DQ27"), | |
1031 | PINCTRL_PIN(32, "B13 DRAM DQ31"), | |
1032 | PINCTRL_PIN(33, "B14 DRAM DQ20"), | |
1033 | PINCTRL_PIN(34, "B15 DRAM DQS2"), | |
1034 | PINCTRL_PIN(35, "B16 DRAM WE N"), | |
1035 | PINCTRL_PIN(36, "B17 DRAM A10"), | |
1036 | PINCTRL_PIN(37, "B18 DRAM A2"), | |
1037 | PINCTRL_PIN(38, "B19 GND"), | |
1038 | PINCTRL_PIN(39, "B20 PCI GNT0 N"), | |
1039 | /* Row C */ | |
1040 | PINCTRL_PIN(40, "C1 AGNDIOHA"), | |
1041 | PINCTRL_PIN(41, "C2 XTALI"), | |
1042 | PINCTRL_PIN(42, "C3 GND"), | |
1043 | PINCTRL_PIN(43, "C4 RTC CLKI"), | |
1044 | PINCTRL_PIN(44, "C5 DRAM A12"), | |
1045 | PINCTRL_PIN(45, "C6 DRAM A11"), | |
1046 | PINCTRL_PIN(46, "C7 DRAM DQ8"), | |
1047 | PINCTRL_PIN(47, "C8 DRAM DQ10"), | |
1048 | PINCTRL_PIN(48, "C9 DRAM DQ3"), | |
1049 | PINCTRL_PIN(49, "C10 DRAM DQ6"), | |
1050 | PINCTRL_PIN(50, "C11 DRAM DQM0"), | |
1051 | PINCTRL_PIN(51, "C12 DRAM DQ26"), | |
1052 | PINCTRL_PIN(52, "C13 DRAM DQ16"), | |
1053 | PINCTRL_PIN(53, "C14 DRAM DQ22"), | |
1054 | PINCTRL_PIN(54, "C15 DRAM DQM2"), | |
1055 | PINCTRL_PIN(55, "C16 DRAM BA0"), | |
1056 | PINCTRL_PIN(56, "C17 DRAM A3"), | |
1057 | PINCTRL_PIN(57, "C18 GND"), | |
1058 | PINCTRL_PIN(58, "C19 PCI GNT1 N"), | |
1059 | PINCTRL_PIN(59, "C20 PCI REQ2 N"), | |
1060 | /* Row D */ | |
1061 | PINCTRL_PIN(60, "D1 AVCC3IOAHA"), | |
1062 | PINCTRL_PIN(61, "D2 AVCCKHA"), | |
1063 | PINCTRL_PIN(62, "D3 XTALO"), | |
1064 | PINCTRL_PIN(63, "D4 GND"), | |
1065 | PINCTRL_PIN(64, "D5 CIR RXD"), | |
1066 | PINCTRL_PIN(65, "D6 DRAM A7"), | |
1067 | PINCTRL_PIN(66, "D7 DRAM A4"), | |
1068 | PINCTRL_PIN(67, "D8 DRAM A8"), | |
1069 | PINCTRL_PIN(68, "D9 DRAM CKE"), | |
1070 | PINCTRL_PIN(69, "D10 DRAM DQ14"), | |
1071 | PINCTRL_PIN(70, "D11 DRAM DQ5"), | |
1072 | PINCTRL_PIN(71, "D12 DRAM DQ25"), | |
1073 | PINCTRL_PIN(72, "D13 DRAM DQ17"), | |
1074 | PINCTRL_PIN(73, "D14 DRAM DQ23"), | |
1075 | PINCTRL_PIN(74, "D15 DRAM RAS N"), | |
1076 | PINCTRL_PIN(75, "D16 DRAM A1"), | |
1077 | PINCTRL_PIN(76, "D17 GND"), | |
1078 | PINCTRL_PIN(77, "D18 EXT RESET N"), | |
1079 | PINCTRL_PIN(78, "D19 PCI REQ1 N"), | |
1080 | PINCTRL_PIN(79, "D20 PCI REQ3 N"), | |
1081 | /* Row E */ | |
1082 | PINCTRL_PIN(80, "E1 VCC2IO CTRL"), | |
1083 | PINCTRL_PIN(81, "E2 VREF CTRL"), | |
1084 | PINCTRL_PIN(82, "E3 CIR RST N"), | |
1085 | PINCTRL_PIN(83, "E4 PWR BTN"), | |
1086 | PINCTRL_PIN(84, "E5 GND"), | |
1087 | PINCTRL_PIN(85, "E6 CIR TXD"), | |
1088 | PINCTRL_PIN(86, "E7 VCCK CTRL"), | |
1089 | PINCTRL_PIN(87, "E8 DRAM A9"), | |
1090 | PINCTRL_PIN(88, "E9 DRAM DQ12"), | |
1091 | PINCTRL_PIN(89, "E10 DRAM DQ15"), | |
1092 | PINCTRL_PIN(90, "E11 DRAM DQM3"), | |
1093 | PINCTRL_PIN(91, "E12 DRAM DQ29"), | |
1094 | PINCTRL_PIN(92, "E13 DRAM DQ19"), | |
1095 | PINCTRL_PIN(93, "E14 DRAM A13"), | |
1096 | PINCTRL_PIN(94, "E15 DRAM A0"), | |
1097 | PINCTRL_PIN(95, "E16 GND"), | |
1098 | PINCTRL_PIN(96, "E17 PCI INTD N"), | |
1099 | PINCTRL_PIN(97, "E18 PCI GNT3 N"), | |
1100 | PINCTRL_PIN(98, "E19 PCI AD29"), | |
1101 | PINCTRL_PIN(99, "E20 PCI AD28"), | |
1102 | /* Row F */ | |
1103 | PINCTRL_PIN(100, "F1 AVCCKHB"), | |
1104 | PINCTRL_PIN(101, "F2 AVCCK P"), | |
1105 | PINCTRL_PIN(102, "F3 EBG"), | |
1106 | PINCTRL_PIN(103, "F4 REXT"), | |
1107 | PINCTRL_PIN(104, "F5 AVCC3IOHB"), | |
1108 | PINCTRL_PIN(105, "F6 GND"), | |
1109 | PINCTRL_PIN(106, "F7 VCC2IOHA 2"), | |
1110 | PINCTRL_PIN(107, "F8 VCC2IOHA 2"), | |
1111 | PINCTRL_PIN(108, "F9 VCC2IOHA 2"), | |
1112 | PINCTRL_PIN(109, "F10 V1"), | |
1113 | PINCTRL_PIN(110, "F11 V1"), | |
1114 | PINCTRL_PIN(111, "F12 VCC2IOHA 2"), | |
1115 | PINCTRL_PIN(112, "F13 VCC2IOHA 2"), | |
1116 | PINCTRL_PIN(113, "F14 VCC2IOHA 2"), | |
1117 | PINCTRL_PIN(114, "F15 GND"), | |
1118 | PINCTRL_PIN(115, "F16 PCI CLK"), | |
1119 | PINCTRL_PIN(116, "F17 PCI GNT2 N"), | |
1120 | PINCTRL_PIN(117, "F18 PCI AD31"), | |
1121 | PINCTRL_PIN(118, "F19 PCI AD26"), | |
1122 | PINCTRL_PIN(119, "F20 PCI CBE3 N"), | |
1123 | /* Row G */ | |
1124 | PINCTRL_PIN(120, "G1 SATA0 RXDP"), | |
1125 | PINCTRL_PIN(121, "G2 SATA0 RXDN"), | |
1126 | PINCTRL_PIN(122, "G3 AGNDK 0"), | |
1127 | PINCTRL_PIN(123, "G4 AVCCK S"), | |
1128 | PINCTRL_PIN(124, "G5 AVCC3 S"), | |
1129 | PINCTRL_PIN(125, "G6 VCC2IOHA 2"), | |
1130 | PINCTRL_PIN(126, "G7 GND"), | |
1131 | PINCTRL_PIN(127, "G8 VCC2IOHA 2"), | |
1132 | PINCTRL_PIN(128, "G9 V1"), | |
1133 | PINCTRL_PIN(129, "G10 V1"), | |
1134 | PINCTRL_PIN(130, "G11 V1"), | |
1135 | PINCTRL_PIN(131, "G12 V1"), | |
1136 | PINCTRL_PIN(132, "G13 VCC2IOHA 2"), | |
1137 | PINCTRL_PIN(133, "G14 GND"), | |
1138 | PINCTRL_PIN(134, "G15 VCC3IOHA"), | |
1139 | PINCTRL_PIN(135, "G16 PCI REQ0 N"), | |
1140 | PINCTRL_PIN(136, "G17 PCI AD30"), | |
1141 | PINCTRL_PIN(137, "G18 PCI AD24"), | |
1142 | PINCTRL_PIN(138, "G19 PCI AD23"), | |
1143 | PINCTRL_PIN(139, "G20 PCI AD21"), | |
1144 | /* Row H */ | |
1145 | PINCTRL_PIN(140, "H1 SATA0 TXDP"), | |
1146 | PINCTRL_PIN(141, "H2 SATA0 TXDN"), | |
1147 | PINCTRL_PIN(142, "H3 AGNDK 1"), | |
1148 | PINCTRL_PIN(143, "H4 AVCCK 0"), | |
1149 | PINCTRL_PIN(144, "H5 TEST CLKOUT"), | |
1150 | PINCTRL_PIN(145, "H6 AGND"), | |
1151 | PINCTRL_PIN(146, "H7 VCC2IOHA 2"), | |
1152 | PINCTRL_PIN(147, "H8 GND"), | |
1153 | PINCTRL_PIN(148, "H9 GND"), | |
1154 | PINCTRL_PIN(149, "H10 GDN"), | |
1155 | PINCTRL_PIN(150, "H11 GND"), | |
1156 | PINCTRL_PIN(151, "H12 GND"), | |
1157 | PINCTRL_PIN(152, "H13 GND"), | |
1158 | PINCTRL_PIN(153, "H14 VCC3IOHA"), | |
1159 | PINCTRL_PIN(154, "H15 VCC3IOHA"), | |
1160 | PINCTRL_PIN(155, "H16 PCI AD27"), | |
1161 | PINCTRL_PIN(156, "H17 PCI AD25"), | |
1162 | PINCTRL_PIN(157, "H18 PCI AD22"), | |
1163 | PINCTRL_PIN(158, "H19 PCI AD18"), | |
1164 | PINCTRL_PIN(159, "H20 PCI AD17"), | |
1165 | /* Row J (for some reason I is skipped) */ | |
1166 | PINCTRL_PIN(160, "J1 SATA1 TXDP"), | |
1167 | PINCTRL_PIN(161, "J2 SATA1 TXDN"), | |
1168 | PINCTRL_PIN(162, "J3 AGNDK 2"), | |
1169 | PINCTRL_PIN(163, "J4 AVCCK 1"), | |
1170 | PINCTRL_PIN(164, "J5 AGND"), | |
1171 | PINCTRL_PIN(165, "J6 AGND"), | |
1172 | PINCTRL_PIN(166, "J7 V1"), | |
1173 | PINCTRL_PIN(167, "J8 GND"), | |
1174 | PINCTRL_PIN(168, "J9 GND"), | |
1175 | PINCTRL_PIN(169, "J10 GND"), | |
1176 | PINCTRL_PIN(170, "J11 GND"), | |
1177 | PINCTRL_PIN(171, "J12 GND"), | |
1178 | PINCTRL_PIN(172, "J13 GND"), | |
1179 | PINCTRL_PIN(173, "J14 V1"), | |
1180 | PINCTRL_PIN(174, "J15 VCC3IOHA"), | |
1181 | PINCTRL_PIN(175, "J16 PCI AD19"), | |
1182 | PINCTRL_PIN(176, "J17 PCI AD20"), | |
1183 | PINCTRL_PIN(177, "J18 PCI AD16"), | |
1184 | PINCTRL_PIN(178, "J19 PCI CBE2 N"), | |
1185 | PINCTRL_PIN(179, "J20 PCI FRAME N"), | |
1186 | /* Row K */ | |
1187 | PINCTRL_PIN(180, "K1 SATA1 RXDP"), | |
1188 | PINCTRL_PIN(181, "K2 SATA1 RXDN"), | |
1189 | PINCTRL_PIN(182, "K3 AGNDK 3"), | |
1190 | PINCTRL_PIN(183, "K4 AVCCK 2"), | |
1191 | PINCTRL_PIN(184, "K5 AGND"), | |
1192 | PINCTRL_PIN(185, "K6 V1"), | |
1193 | PINCTRL_PIN(186, "K7 V1"), | |
1194 | PINCTRL_PIN(187, "K8 GND"), | |
1195 | PINCTRL_PIN(188, "K9 GND"), | |
1196 | PINCTRL_PIN(189, "K10 GND"), | |
1197 | PINCTRL_PIN(190, "K11 GND"), | |
1198 | PINCTRL_PIN(191, "K12 GND"), | |
1199 | PINCTRL_PIN(192, "K13 GND"), | |
1200 | PINCTRL_PIN(193, "K14 V1"), | |
1201 | PINCTRL_PIN(194, "K15 V1"), | |
1202 | PINCTRL_PIN(195, "K16 PCI TRDY N"), | |
1203 | PINCTRL_PIN(196, "K17 PCI IRDY N"), | |
1204 | PINCTRL_PIN(197, "K18 PCI DEVSEL N"), | |
1205 | PINCTRL_PIN(198, "K19 PCI STOP N"), | |
1206 | PINCTRL_PIN(199, "K20 PCI PAR"), | |
1207 | /* Row L */ | |
1208 | PINCTRL_PIN(200, "L1 IDE CS0 N"), | |
1209 | PINCTRL_PIN(201, "L2 IDE DA0"), | |
1210 | PINCTRL_PIN(202, "L3 AVCCK 3"), | |
1211 | PINCTRL_PIN(203, "L4 AGND"), | |
1212 | PINCTRL_PIN(204, "L5 IDE DIOR N"), | |
1213 | PINCTRL_PIN(205, "L6 V1"), | |
1214 | PINCTRL_PIN(206, "L7 V1"), | |
1215 | PINCTRL_PIN(207, "L8 GND"), | |
1216 | PINCTRL_PIN(208, "L9 GND"), | |
1217 | PINCTRL_PIN(209, "L10 GND"), | |
1218 | PINCTRL_PIN(210, "L11 GND"), | |
1219 | PINCTRL_PIN(211, "L12 GND"), | |
1220 | PINCTRL_PIN(212, "L13 GND"), | |
1221 | PINCTRL_PIN(213, "L14 V1"), | |
1222 | PINCTRL_PIN(214, "L15 V1"), | |
1223 | PINCTRL_PIN(215, "L16 PCI AD12"), | |
1224 | PINCTRL_PIN(216, "L17 PCI AD13"), | |
1225 | PINCTRL_PIN(217, "L18 PCI AD14"), | |
1226 | PINCTRL_PIN(218, "L19 PCI AD15"), | |
1227 | PINCTRL_PIN(219, "L20 PCI CBE1 N"), | |
1228 | /* Row M */ | |
1229 | PINCTRL_PIN(220, "M1 IDE DA1"), | |
1230 | PINCTRL_PIN(221, "M2 IDE CS1 N"), | |
1231 | PINCTRL_PIN(222, "M3 IDE DA2"), | |
1232 | PINCTRL_PIN(223, "M4 IDE DMACK N"), | |
1233 | PINCTRL_PIN(224, "M5 IDE DD1"), | |
1234 | PINCTRL_PIN(225, "M6 VCC3IOHA"), | |
1235 | PINCTRL_PIN(226, "M7 V1"), | |
1236 | PINCTRL_PIN(227, "M8 GND"), | |
1237 | PINCTRL_PIN(228, "M9 GND"), | |
1238 | PINCTRL_PIN(229, "M10 GND"), | |
1239 | PINCTRL_PIN(230, "M11 GND"), | |
1240 | PINCTRL_PIN(231, "M12 GND"), | |
1241 | PINCTRL_PIN(232, "M13 GND"), | |
1242 | PINCTRL_PIN(233, "M14 V1"), | |
1243 | PINCTRL_PIN(234, "M15 VCC3IOHA"), | |
1244 | PINCTRL_PIN(235, "M16 PCI AD7"), | |
1245 | PINCTRL_PIN(236, "M17 PCI AD6"), | |
1246 | PINCTRL_PIN(237, "M18 PCI AD9"), | |
1247 | PINCTRL_PIN(238, "M19 PCI AD10"), | |
1248 | PINCTRL_PIN(239, "M20 PCI AD11"), | |
1249 | /* Row N */ | |
1250 | PINCTRL_PIN(240, "N1 IDE IORDY"), | |
1251 | PINCTRL_PIN(241, "N2 IDE INTRQ"), | |
1252 | PINCTRL_PIN(242, "N3 IDE DIOW N"), | |
1253 | PINCTRL_PIN(243, "N4 IDE DD15"), | |
1254 | PINCTRL_PIN(244, "N5 IDE DMARQ"), | |
1255 | PINCTRL_PIN(245, "N6 VCC3IOHA"), | |
1256 | PINCTRL_PIN(246, "N7 VCC3IOHA"), | |
1257 | PINCTRL_PIN(247, "N8 GND"), | |
1258 | PINCTRL_PIN(248, "N9 GND"), | |
1259 | PINCTRL_PIN(249, "N10 GND"), | |
1260 | PINCTRL_PIN(250, "N11 GND"), | |
1261 | PINCTRL_PIN(251, "N12 GND"), | |
1262 | PINCTRL_PIN(252, "N13 GND"), | |
1263 | PINCTRL_PIN(253, "N14 VCC3IOHA"), | |
1264 | PINCTRL_PIN(254, "N15 VCC3IOHA"), | |
1265 | PINCTRL_PIN(255, "N16 PCI CLKRUN N"), | |
1266 | PINCTRL_PIN(256, "N17 PCI AD0"), | |
1267 | PINCTRL_PIN(257, "N18 PCI AD4"), | |
1268 | PINCTRL_PIN(258, "N19 PCI CBE0 N"), | |
1269 | PINCTRL_PIN(259, "N20 PCI AD8"), | |
1270 | /* Row P (for some reason O is skipped) */ | |
1271 | PINCTRL_PIN(260, "P1 IDE DD0"), | |
1272 | PINCTRL_PIN(261, "P2 IDE DD14"), | |
1273 | PINCTRL_PIN(262, "P3 IDE DD2"), | |
1274 | PINCTRL_PIN(263, "P4 IDE DD4"), | |
1275 | PINCTRL_PIN(264, "P5 IDE DD3"), | |
1276 | PINCTRL_PIN(265, "P6 VCC3IOHA"), | |
1277 | PINCTRL_PIN(266, "P7 GND"), | |
1278 | PINCTRL_PIN(267, "P8 VCC2IOHA 1"), | |
1279 | PINCTRL_PIN(268, "P9 V1"), | |
1280 | PINCTRL_PIN(269, "P10 V1"), | |
1281 | PINCTRL_PIN(270, "P11 V1"), | |
1282 | PINCTRL_PIN(271, "P12 V1"), | |
1283 | PINCTRL_PIN(272, "P13 VCC3IOHA"), | |
1284 | PINCTRL_PIN(273, "P14 GND"), | |
1285 | PINCTRL_PIN(274, "P15 VCC3IOHA"), | |
1286 | PINCTRL_PIN(275, "P16 GPIO0 30"), | |
1287 | PINCTRL_PIN(276, "P17 GPIO0 28"), | |
1288 | PINCTRL_PIN(277, "P18 PCI AD1"), | |
1289 | PINCTRL_PIN(278, "P19 PCI AD3"), | |
1290 | PINCTRL_PIN(279, "P20 PCI AD5"), | |
1291 | /* Row R (for some reason Q us skipped) */ | |
1292 | PINCTRL_PIN(280, "R1 IDE DD13"), | |
1293 | PINCTRL_PIN(281, "R2 IDE DD12"), | |
1294 | PINCTRL_PIN(282, "R3 IDE DD10"), | |
1295 | PINCTRL_PIN(283, "R4 IDE DD6"), | |
1296 | PINCTRL_PIN(284, "R5 ICE0 IDI"), | |
1297 | PINCTRL_PIN(285, "R6 GND"), | |
1298 | PINCTRL_PIN(286, "R7 VCC2IOHA 1"), | |
1299 | PINCTRL_PIN(287, "R8 VCC2IOHA 1"), | |
1300 | PINCTRL_PIN(288, "R9 VCC2IOHA 1"), | |
1301 | PINCTRL_PIN(289, "R10 V1"), | |
1302 | PINCTRL_PIN(290, "R11 V1"), | |
1303 | PINCTRL_PIN(291, "R12 VCC3IOHA"), | |
1304 | PINCTRL_PIN(292, "R13 VCC3IOHA"), | |
1305 | PINCTRL_PIN(293, "R14 VCC3IOHA"), | |
1306 | PINCTRL_PIN(294, "R15 GND"), | |
1307 | PINCTRL_PIN(295, "R16 GPIO0 23"), | |
1308 | PINCTRL_PIN(296, "R17 GPIO0 21"), | |
1309 | PINCTRL_PIN(297, "R18 GPIO0 26"), | |
1310 | PINCTRL_PIN(298, "R19 GPIO0 31"), | |
1311 | PINCTRL_PIN(299, "R20 PCI AD2"), | |
1312 | /* Row T (for some reason S is skipped) */ | |
1313 | PINCTRL_PIN(300, "T1 IDE DD11"), | |
1314 | PINCTRL_PIN(301, "T2 IDE DD5"), | |
1315 | PINCTRL_PIN(302, "T3 IDE DD8"), | |
1316 | PINCTRL_PIN(303, "T4 ICE0 IDO"), | |
1317 | PINCTRL_PIN(304, "T5 GND"), | |
1318 | PINCTRL_PIN(305, "T6 USB GNDA U20"), | |
1319 | PINCTRL_PIN(306, "T7 GMAC0 TXD0"), | |
1320 | PINCTRL_PIN(307, "T8 GMAC0 TXEN"), | |
1321 | PINCTRL_PIN(308, "T9 GMAC1 TXD3"), | |
1322 | PINCTRL_PIN(309, "T10 GMAC1 RXDV"), | |
1323 | PINCTRL_PIN(310, "T11 GMAC1 RXD2"), | |
1324 | PINCTRL_PIN(311, "T12 GPIO1 29"), | |
1325 | PINCTRL_PIN(312, "T13 GPIO0 3"), | |
1326 | PINCTRL_PIN(313, "T14 GPIO0 9"), | |
1327 | PINCTRL_PIN(314, "T15 GPIO0 16"), | |
1328 | PINCTRL_PIN(315, "T16 GND"), | |
1329 | PINCTRL_PIN(316, "T17 GPIO0 14"), | |
1330 | PINCTRL_PIN(317, "T18 GPIO0 19"), | |
1331 | PINCTRL_PIN(318, "T19 GPIO0 27"), | |
1332 | PINCTRL_PIN(319, "T20 GPIO0 29"), | |
1333 | /* Row U */ | |
1334 | PINCTRL_PIN(320, "U1 IDE DD9"), | |
1335 | PINCTRL_PIN(321, "U2 IDE DD7"), | |
1336 | PINCTRL_PIN(322, "U3 ICE0 ICK"), | |
1337 | PINCTRL_PIN(323, "U4 GND"), | |
1338 | PINCTRL_PIN(324, "U5 USB XSCO"), | |
1339 | PINCTRL_PIN(325, "U6 GMAC0 TXD1"), | |
1340 | PINCTRL_PIN(326, "U7 GMAC0 TXD3"), | |
1341 | PINCTRL_PIN(327, "U8 GMAC0 TXC"), | |
1342 | PINCTRL_PIN(328, "U9 GMAC0 RXD3"), | |
1343 | PINCTRL_PIN(329, "U10 GMAC1 TXD0"), | |
1344 | PINCTRL_PIN(330, "U11 GMAC1 CRS"), | |
1345 | PINCTRL_PIN(331, "U12 EXT CLK"), | |
1346 | PINCTRL_PIN(332, "U13 DEV DEF"), | |
1347 | PINCTRL_PIN(333, "U14 GPIO0 0"), | |
1348 | PINCTRL_PIN(334, "U15 GPIO0 4"), | |
1349 | PINCTRL_PIN(335, "U16 GPIO0 10"), | |
1350 | PINCTRL_PIN(336, "U17 GND"), | |
1351 | PINCTRL_PIN(337, "U18 GPIO0 17"), | |
1352 | PINCTRL_PIN(338, "U19 GPIO0 22"), | |
1353 | PINCTRL_PIN(339, "U20 GPIO0 25"), | |
1354 | /* Row V */ | |
1355 | PINCTRL_PIN(340, "V1 ICE0 DBGACK"), | |
1356 | PINCTRL_PIN(341, "V2 ICE0 DBGRQ"), | |
1357 | PINCTRL_PIN(342, "V3 GND"), | |
1358 | PINCTRL_PIN(343, "V4 ICE0 IRST N"), | |
1359 | PINCTRL_PIN(344, "V5 USB XSCI"), | |
1360 | PINCTRL_PIN(345, "V6 GMAC0 COL"), | |
1361 | PINCTRL_PIN(346, "V7 GMAC0 TXD2"), | |
1362 | PINCTRL_PIN(347, "V8 GMAC0 RXDV"), | |
1363 | PINCTRL_PIN(348, "V9 GMAC0 RXD1"), | |
1364 | PINCTRL_PIN(349, "V10 GMAC1 COL"), | |
1365 | PINCTRL_PIN(350, "V11 GMAC1 TXC"), | |
1366 | PINCTRL_PIN(351, "V12 GMAC1 RXD1"), | |
1367 | PINCTRL_PIN(352, "V13 MODE SEL1"), | |
1368 | PINCTRL_PIN(353, "V14 GPIO1 28"), | |
1369 | PINCTRL_PIN(354, "V15 GPIO0 1"), | |
1370 | PINCTRL_PIN(355, "V16 GPIO0 8"), | |
1371 | PINCTRL_PIN(356, "V17 GPIO0 11"), | |
1372 | PINCTRL_PIN(357, "V18 GND"), | |
1373 | PINCTRL_PIN(358, "V19 GPIO0 18"), | |
1374 | PINCTRL_PIN(359, "V20 GPIO0 24"), | |
1375 | /* Row W */ | |
1376 | PINCTRL_PIN(360, "W1 IDE RESET N"), | |
1377 | PINCTRL_PIN(361, "W2 GND"), | |
1378 | PINCTRL_PIN(362, "W3 USB0 VCCHSRT"), | |
1379 | PINCTRL_PIN(363, "W4 USB0 DP"), | |
1380 | PINCTRL_PIN(364, "W5 USB VCCA U20"), | |
1381 | PINCTRL_PIN(365, "W6 USB1 DP"), | |
1382 | PINCTRL_PIN(366, "W7 USB1 GNDHSRT"), | |
1383 | PINCTRL_PIN(367, "W8 GMAC0 RXD0"), | |
1384 | PINCTRL_PIN(368, "W9 GMAC0 CRS"), | |
1385 | PINCTRL_PIN(369, "W10 GMAC1 TXD2"), | |
1386 | PINCTRL_PIN(370, "W11 GMAC1 TXEN"), | |
1387 | PINCTRL_PIN(371, "W12 GMAC1 RXD3"), | |
1388 | PINCTRL_PIN(372, "W13 MODE SEL0"), | |
1389 | PINCTRL_PIN(373, "W14 MODE SEL3"), | |
1390 | PINCTRL_PIN(374, "W15 GPIO1 31"), | |
1391 | PINCTRL_PIN(375, "W16 GPIO0 5"), | |
1392 | PINCTRL_PIN(376, "W17 GPIO0 7"), | |
1393 | PINCTRL_PIN(377, "W18 GPIO0 12"), | |
1394 | PINCTRL_PIN(378, "W19 GND"), | |
1395 | PINCTRL_PIN(379, "W20 GPIO0 20"), | |
1396 | /* Row Y */ | |
1397 | PINCTRL_PIN(380, "Y1 ICE0 IMS"), | |
1398 | PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"), | |
1399 | PINCTRL_PIN(382, "Y3 USB0 DM"), | |
1400 | PINCTRL_PIN(383, "Y4 USB RREF"), | |
1401 | PINCTRL_PIN(384, "Y5 USB1 DM"), | |
1402 | PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"), | |
1403 | PINCTRL_PIN(386, "Y7 GMAC0 RXC"), | |
1404 | PINCTRL_PIN(387, "Y8 GMAC0 RXD2"), | |
1405 | PINCTRL_PIN(388, "Y9 REF CLK"), | |
1406 | PINCTRL_PIN(389, "Y10 GMAC1 TXD1"), | |
1407 | PINCTRL_PIN(390, "Y11 GMAC1 RXC"), | |
1408 | PINCTRL_PIN(391, "Y12 GMAC1 RXD0"), | |
1409 | PINCTRL_PIN(392, "Y13 M30 CLK"), | |
1410 | PINCTRL_PIN(393, "Y14 MODE SEL2"), | |
1411 | PINCTRL_PIN(394, "Y15 GPIO1 30"), | |
1412 | PINCTRL_PIN(395, "Y16 GPIO0 2"), | |
1413 | PINCTRL_PIN(396, "Y17 GPIO0 6"), | |
1414 | PINCTRL_PIN(397, "Y18 SYS RESET N"), | |
1415 | PINCTRL_PIN(398, "Y19 GPIO0 13"), | |
1416 | PINCTRL_PIN(399, "Y20 GPIO0 15"), | |
1417 | }; | |
1418 | ||
1419 | /* Digital ground */ | |
1420 | static const unsigned int gnd_3516_pins[] = { | |
1421 | 21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150, | |
1422 | 151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192, | |
1423 | 207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248, | |
1424 | 249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357, | |
1425 | 361, 378 | |
1426 | }; | |
1427 | ||
1428 | static const unsigned int dram_3516_pins[] = { | |
1429 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26, | |
1430 | 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50, | |
1431 | 51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, | |
1432 | 87, 88, 89, 90, 91, 92, 93, 94 | |
1433 | }; | |
1434 | ||
1435 | static const unsigned int rtc_3516_pins[] = { 0, 43, 22 }; | |
1436 | ||
1437 | static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 }; | |
1438 | ||
1439 | static const unsigned int cir_3516_pins[] = { 85, 64, 82 }; | |
1440 | ||
1441 | static const unsigned int system_3516_pins[] = { | |
1442 | 332, 392, 372, 373, 393, 352, 331, 388, 397, 77 | |
1443 | }; | |
1444 | ||
1445 | static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 }; | |
1446 | ||
1447 | static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 }; | |
1448 | ||
1449 | static const unsigned int ide_3516_pins[] = { | |
1450 | 200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260, | |
1451 | 261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360 | |
1452 | }; | |
1453 | ||
1454 | static const unsigned int sata_3516_pins[] = { | |
1455 | 100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143, | |
1456 | 144, 160, 161, 162, 163, 180, 181, 182, 183, 202 | |
1457 | }; | |
1458 | ||
1459 | static const unsigned int usb_3516_pins[] = { | |
1460 | 305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385 | |
1461 | }; | |
1462 | ||
1463 | /* GMII, ethernet pins */ | |
756a024f LW |
1464 | static const unsigned int gmii_gmac0_3516_pins[] = { |
1465 | 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387 | |
1466 | }; | |
1467 | ||
1468 | static const unsigned int gmii_gmac1_3516_pins[] = { | |
1469 | 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391 | |
06351d13 LW |
1470 | }; |
1471 | ||
1472 | static const unsigned int pci_3516_pins[] = { | |
1473 | 17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118, | |
1474 | 119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177, | |
1475 | 178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236, | |
1476 | 237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299 | |
1477 | }; | |
1478 | ||
1479 | /* | |
1480 | * Apparently the LPC interface is using the PCICLK for the clocking so | |
1481 | * PCI needs to be active at the same time. | |
1482 | */ | |
1483 | static const unsigned int lpc_3516_pins[] = { | |
1484 | 355, /* LPC_LAD[0] */ | |
1485 | 356, /* LPC_SERIRQ */ | |
1486 | 377, /* LPC_LAD[2] */ | |
1487 | 398, /* LPC_LFRAME# */ | |
1488 | 316, /* LPC_LAD[3] */ | |
1489 | 399, /* LPC_LAD[1] */ | |
1490 | }; | |
1491 | ||
1492 | /* Character LCD */ | |
1493 | static const unsigned int lcd_3516_pins[] = { | |
1494 | 391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339 | |
1495 | }; | |
1496 | ||
1497 | static const unsigned int ssp_3516_pins[] = { | |
1498 | 355, /* SSP_97RST# SSP AC97 Reset, active low */ | |
1499 | 356, /* SSP_FSC */ | |
1500 | 377, /* SSP_ECLK */ | |
1501 | 398, /* SSP_TXD */ | |
1502 | 316, /* SSP_RXD */ | |
1503 | 399, /* SSP_SCLK */ | |
1504 | }; | |
1505 | ||
1506 | static const unsigned int uart_rxtx_3516_pins[] = { | |
1507 | 313, /* UART_SIN serial input, RX */ | |
1508 | 335, /* UART_SOUT serial output, TX */ | |
1509 | }; | |
1510 | ||
1511 | static const unsigned int uart_modem_3516_pins[] = { | |
1512 | 355, /* UART_NDCD DCD carrier detect */ | |
1513 | 356, /* UART_NDTR DTR data terminal ready */ | |
1514 | 377, /* UART_NDSR DSR data set ready */ | |
1515 | 398, /* UART_NRTS RTS request to send */ | |
1516 | 316, /* UART_NCTS CTS clear to send */ | |
1517 | 399, /* UART_NRI RI ring indicator */ | |
1518 | }; | |
1519 | ||
1520 | static const unsigned int tvc_3516_pins[] = { | |
1521 | 353, /* TVC_DATA[0] */ | |
1522 | 311, /* TVC_DATA[1] */ | |
1523 | 394, /* TVC_DATA[2] */ | |
1524 | 374, /* TVC_DATA[3] */ | |
1525 | 333, /* TVC_CLK */ | |
1526 | 354, /* TVC_DATA[4] */ | |
1527 | 395, /* TVC_DATA[5] */ | |
1528 | 312, /* TVC_DATA[6] */ | |
1529 | 334, /* TVC_DATA[7] */ | |
1530 | }; | |
1531 | ||
1532 | /* NAND flash pins */ | |
1533 | static const unsigned int nflash_3516_pins[] = { | |
1534 | 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, | |
1535 | 302, 321, 337, 358, 295, 359, 339, 275, 298 | |
1536 | }; | |
1537 | ||
1538 | /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ | |
1539 | static const unsigned int pflash_3516_pins[] = { | |
1540 | 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, | |
1541 | 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, | |
1542 | 276, 319, 275, 298 | |
1543 | }; | |
1544 | ||
1545 | /* | |
1546 | * The parallel flash can be set up in a 26-bit address bus mode exposing | |
1547 | * A[0-15] (A[15] takes the place of ALE), but it has the | |
1548 | * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be | |
1549 | * used at the same time. | |
1550 | */ | |
1551 | static const unsigned int pflash_3516_pins_extended[] = { | |
1552 | 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, | |
1553 | 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, | |
1554 | 276, 319, 275, 298, | |
1555 | /* The extra pins */ | |
1556 | 349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330, | |
1557 | 333 | |
1558 | }; | |
1559 | ||
1560 | /* Serial flash pins CE0, CE1, DI, DO, CK */ | |
1561 | static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 }; | |
1562 | ||
1563 | /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */ | |
1564 | static const unsigned int gpio0a_3516_pins[] = { 333, 354, 395, 312, 334 }; | |
1565 | ||
1566 | /* The GPIO0B (5-7) pins overlap with ICE */ | |
1567 | static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 }; | |
1568 | ||
1569 | /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */ | |
1570 | static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 }; | |
1571 | ||
1572 | /* The GPIO0D (9,10) pins overlap with UART RX/TX */ | |
1573 | static const unsigned int gpio0d_3516_pins[] = { 313, 335 }; | |
1574 | ||
1575 | /* The GPIO0E (16) pins overlap with LCD */ | |
1576 | static const unsigned int gpio0e_3516_pins[] = { 314 }; | |
1577 | ||
1578 | /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */ | |
1579 | static const unsigned int gpio0f_3516_pins[] = { 337, 358 }; | |
1580 | ||
1581 | /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */ | |
1582 | static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 }; | |
1583 | ||
1584 | /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */ | |
1585 | static const unsigned int gpio0h_3516_pins[] = { 296, 338 }; | |
1586 | ||
1587 | /* The GPIO0I (23) pins overlap with all flash */ | |
1588 | static const unsigned int gpio0i_3516_pins[] = { 295 }; | |
1589 | ||
1590 | /* The GPIO0J (24,25) pins overlap with all flash and LCD */ | |
1591 | static const unsigned int gpio0j_3516_pins[] = { 359, 339 }; | |
1592 | ||
1593 | /* The GPIO0K (30,31) pins overlap with NAND flash */ | |
1594 | static const unsigned int gpio0k_3516_pins[] = { 275, 298 }; | |
1595 | ||
1596 | /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ | |
1597 | static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 }; | |
1598 | ||
1599 | /* The GPIO1B (5-10,27) pins overlap with just IDE */ | |
1600 | static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 }; | |
1601 | ||
1602 | /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ | |
1603 | static const unsigned int gpio1c_3516_pins[] = { | |
1604 | 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, | |
1605 | 302, 321 | |
1606 | }; | |
1607 | ||
1608 | /* The GPIO1D (28-31) pins overlap with TVC */ | |
1609 | static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; | |
1610 | ||
756a024f | 1611 | /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ |
06351d13 LW |
1612 | static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; |
1613 | ||
756a024f | 1614 | /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ |
06351d13 LW |
1615 | static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; |
1616 | ||
1617 | /* The GPIO2C (8-31) pins overlap with PCI */ | |
1618 | static const unsigned int gpio2c_3516_pins[] = { | |
1619 | 259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139, | |
1620 | 157, 138, 137, 156, 118, 155, 99, 98, 136, 117 | |
1621 | }; | |
1622 | ||
1623 | /* Groups for the 3516 SoC/package */ | |
1624 | static const struct gemini_pin_group gemini_3516_pin_groups[] = { | |
1625 | { | |
1626 | .name = "gndgrp", | |
1627 | .pins = gnd_3516_pins, | |
1628 | .num_pins = ARRAY_SIZE(gnd_3516_pins), | |
1629 | }, | |
1630 | { | |
1631 | .name = "dramgrp", | |
1632 | .pins = dram_3516_pins, | |
1633 | .num_pins = ARRAY_SIZE(dram_3516_pins), | |
1634 | .mask = DRAM_PADS_POWERDOWN, | |
1635 | }, | |
1636 | { | |
1637 | .name = "rtcgrp", | |
1638 | .pins = rtc_3516_pins, | |
1639 | .num_pins = ARRAY_SIZE(rtc_3516_pins), | |
1640 | }, | |
1641 | { | |
1642 | .name = "powergrp", | |
1643 | .pins = power_3516_pins, | |
1644 | .num_pins = ARRAY_SIZE(power_3516_pins), | |
1645 | }, | |
1646 | { | |
1647 | .name = "cirgrp", | |
1648 | .pins = cir_3516_pins, | |
1649 | .num_pins = ARRAY_SIZE(cir_3516_pins), | |
1650 | }, | |
1651 | { | |
1652 | .name = "systemgrp", | |
1653 | .pins = system_3516_pins, | |
1654 | .num_pins = ARRAY_SIZE(system_3516_pins), | |
1655 | }, | |
1656 | { | |
1657 | .name = "vcontrolgrp", | |
1658 | .pins = vcontrol_3516_pins, | |
1659 | .num_pins = ARRAY_SIZE(vcontrol_3516_pins), | |
1660 | }, | |
1661 | { | |
1662 | .name = "icegrp", | |
1663 | .pins = ice_3516_pins, | |
1664 | .num_pins = ARRAY_SIZE(ice_3516_pins), | |
1665 | /* Conflict with some GPIO groups */ | |
1666 | }, | |
1667 | { | |
1668 | .name = "idegrp", | |
1669 | .pins = ide_3516_pins, | |
1670 | .num_pins = ARRAY_SIZE(ide_3516_pins), | |
1671 | /* Conflict with all flash usage */ | |
1672 | .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | | |
1673 | PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, | |
1674 | }, | |
1675 | { | |
1676 | .name = "satagrp", | |
1677 | .pins = sata_3516_pins, | |
1678 | .num_pins = ARRAY_SIZE(sata_3516_pins), | |
1679 | }, | |
1680 | { | |
1681 | .name = "usbgrp", | |
1682 | .pins = usb_3516_pins, | |
1683 | .num_pins = ARRAY_SIZE(usb_3516_pins), | |
1684 | }, | |
1685 | { | |
756a024f LW |
1686 | .name = "gmii_gmac0_grp", |
1687 | .pins = gmii_gmac0_3516_pins, | |
1688 | .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins), | |
1689 | }, | |
1690 | { | |
1691 | .name = "gmii_gmac1_grp", | |
1692 | .pins = gmii_gmac1_3516_pins, | |
1693 | .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins), | |
1694 | /* Bring out RGMII on the GMAC1 pins */ | |
1695 | .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, | |
06351d13 LW |
1696 | }, |
1697 | { | |
1698 | .name = "pcigrp", | |
1699 | .pins = pci_3516_pins, | |
1700 | .num_pins = ARRAY_SIZE(pci_3516_pins), | |
1701 | /* Conflict only with GPIO2 */ | |
1702 | .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, | |
1703 | }, | |
1704 | { | |
1705 | .name = "lpcgrp", | |
1706 | .pins = lpc_3516_pins, | |
1707 | .num_pins = ARRAY_SIZE(lpc_3516_pins), | |
1708 | /* Conflict with SSP */ | |
1709 | .mask = SSP_PADS_ENABLE, | |
1710 | .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, | |
1711 | }, | |
1712 | { | |
1713 | .name = "lcdgrp", | |
1714 | .pins = lcd_3516_pins, | |
1715 | .num_pins = ARRAY_SIZE(lcd_3516_pins), | |
1716 | .mask = TVC_PADS_ENABLE, | |
1717 | .value = LCD_PADS_ENABLE, | |
1718 | }, | |
1719 | { | |
1720 | .name = "sspgrp", | |
1721 | .pins = ssp_3516_pins, | |
1722 | .num_pins = ARRAY_SIZE(ssp_3516_pins), | |
1723 | /* Conflict with LPC */ | |
1724 | .mask = LPC_PADS_ENABLE, | |
1725 | .value = SSP_PADS_ENABLE, | |
1726 | }, | |
1727 | { | |
1728 | .name = "uartrxtxgrp", | |
1729 | .pins = uart_rxtx_3516_pins, | |
1730 | .num_pins = ARRAY_SIZE(uart_rxtx_3516_pins), | |
1731 | /* No conflicts except GPIO */ | |
1732 | }, | |
1733 | { | |
1734 | .name = "uartmodemgrp", | |
1735 | .pins = uart_modem_3516_pins, | |
1736 | .num_pins = ARRAY_SIZE(uart_modem_3516_pins), | |
1737 | /* | |
1738 | * Conflict with LPC and SSP, | |
1739 | * so when those are both disabled, modem UART can thrive. | |
1740 | */ | |
1741 | .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, | |
1742 | }, | |
1743 | { | |
1744 | .name = "tvcgrp", | |
1745 | .pins = tvc_3516_pins, | |
1746 | .num_pins = ARRAY_SIZE(tvc_3516_pins), | |
1747 | /* Conflict with character LCD */ | |
1748 | .mask = LCD_PADS_ENABLE, | |
1749 | .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE, | |
1750 | }, | |
1751 | /* | |
1752 | * The construction is done such that it is possible to use a serial | |
1753 | * flash together with a NAND or parallel (NOR) flash, but it is not | |
1754 | * possible to use NAND and parallel flash together. To use serial | |
1755 | * flash with one of the two others, the muxbits need to be flipped | |
1756 | * around before any access. | |
1757 | */ | |
1758 | { | |
1759 | .name = "nflashgrp", | |
1760 | .pins = nflash_3516_pins, | |
1761 | .num_pins = ARRAY_SIZE(nflash_3516_pins), | |
1762 | /* Conflict with IDE, parallel and serial flash */ | |
1763 | .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, | |
1764 | .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, | |
1765 | }, | |
1766 | { | |
1767 | .name = "pflashgrp", | |
1768 | .pins = pflash_3516_pins, | |
1769 | .num_pins = ARRAY_SIZE(pflash_3516_pins), | |
1770 | /* Conflict with IDE, NAND and serial flash */ | |
1771 | .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, | |
1772 | .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, | |
1773 | }, | |
1774 | { | |
1775 | .name = "sflashgrp", | |
1776 | .pins = sflash_3516_pins, | |
1777 | .num_pins = ARRAY_SIZE(sflash_3516_pins), | |
1778 | /* Conflict with IDE, NAND and parallel flash */ | |
1779 | .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, | |
1780 | .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, | |
1781 | }, | |
1782 | { | |
1783 | .name = "gpio0agrp", | |
1784 | .pins = gpio0a_3516_pins, | |
1785 | .num_pins = ARRAY_SIZE(gpio0a_3516_pins), | |
1786 | /* Conflict with TVC and ICE */ | |
1787 | .mask = TVC_PADS_ENABLE, | |
1788 | }, | |
1789 | { | |
1790 | .name = "gpio0bgrp", | |
1791 | .pins = gpio0b_3516_pins, | |
1792 | .num_pins = ARRAY_SIZE(gpio0b_3516_pins), | |
1793 | /* Conflict with ICE */ | |
1794 | }, | |
1795 | { | |
1796 | .name = "gpio0cgrp", | |
1797 | .pins = gpio0c_3516_pins, | |
1798 | .num_pins = ARRAY_SIZE(gpio0c_3516_pins), | |
1799 | /* Conflict with LPC, UART and SSP */ | |
1800 | .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, | |
1801 | }, | |
1802 | { | |
1803 | .name = "gpio0dgrp", | |
1804 | .pins = gpio0d_3516_pins, | |
1805 | .num_pins = ARRAY_SIZE(gpio0d_3516_pins), | |
1806 | /* Conflict with UART */ | |
1807 | }, | |
1808 | { | |
1809 | .name = "gpio0egrp", | |
1810 | .pins = gpio0e_3516_pins, | |
1811 | .num_pins = ARRAY_SIZE(gpio0e_3516_pins), | |
1812 | /* Conflict with LCD */ | |
1813 | .mask = LCD_PADS_ENABLE, | |
1814 | }, | |
1815 | { | |
1816 | .name = "gpio0fgrp", | |
1817 | .pins = gpio0f_3516_pins, | |
1818 | .num_pins = ARRAY_SIZE(gpio0f_3516_pins), | |
1819 | /* Conflict with NAND flash */ | |
1820 | .value = NAND_PADS_DISABLE, | |
1821 | }, | |
1822 | { | |
1823 | .name = "gpio0ggrp", | |
1824 | .pins = gpio0g_3516_pins, | |
1825 | .num_pins = ARRAY_SIZE(gpio0g_3516_pins), | |
1826 | /* Conflict with parallel flash */ | |
1827 | .value = PFLASH_PADS_DISABLE, | |
1828 | }, | |
1829 | { | |
1830 | .name = "gpio0hgrp", | |
1831 | .pins = gpio0h_3516_pins, | |
1832 | .num_pins = ARRAY_SIZE(gpio0h_3516_pins), | |
1833 | /* Conflict with serial flash */ | |
1834 | .value = SFLASH_PADS_DISABLE, | |
1835 | }, | |
1836 | { | |
1837 | .name = "gpio0igrp", | |
1838 | .pins = gpio0i_3516_pins, | |
1839 | .num_pins = ARRAY_SIZE(gpio0i_3516_pins), | |
1840 | /* Conflict with all flash */ | |
1841 | .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | | |
1842 | SFLASH_PADS_DISABLE, | |
1843 | }, | |
1844 | { | |
1845 | .name = "gpio0jgrp", | |
1846 | .pins = gpio0j_3516_pins, | |
1847 | .num_pins = ARRAY_SIZE(gpio0j_3516_pins), | |
1848 | /* Conflict with all flash and LCD */ | |
1849 | .mask = LCD_PADS_ENABLE, | |
1850 | .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | | |
1851 | SFLASH_PADS_DISABLE, | |
1852 | }, | |
1853 | { | |
1854 | .name = "gpio0kgrp", | |
1855 | .pins = gpio0k_3516_pins, | |
1856 | .num_pins = ARRAY_SIZE(gpio0k_3516_pins), | |
1857 | /* Conflict with parallel and NAND flash */ | |
1858 | .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, | |
1859 | }, | |
1860 | { | |
1861 | .name = "gpio1agrp", | |
1862 | .pins = gpio1a_3516_pins, | |
1863 | .num_pins = ARRAY_SIZE(gpio1a_3516_pins), | |
1864 | /* Conflict with IDE and parallel flash */ | |
1865 | .mask = IDE_PADS_ENABLE, | |
1866 | .value = PFLASH_PADS_DISABLE, | |
1867 | }, | |
1868 | { | |
1869 | .name = "gpio1bgrp", | |
1870 | .pins = gpio1b_3516_pins, | |
1871 | .num_pins = ARRAY_SIZE(gpio1b_3516_pins), | |
1872 | /* Conflict with IDE only */ | |
1873 | .mask = IDE_PADS_ENABLE, | |
1874 | }, | |
1875 | { | |
1876 | .name = "gpio1cgrp", | |
1877 | .pins = gpio1c_3516_pins, | |
1878 | .num_pins = ARRAY_SIZE(gpio1c_3516_pins), | |
1879 | /* Conflict with IDE, parallel and NAND flash */ | |
1880 | .mask = IDE_PADS_ENABLE, | |
1881 | .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, | |
1882 | }, | |
1883 | { | |
1884 | .name = "gpio1dgrp", | |
1885 | .pins = gpio1d_3516_pins, | |
1886 | .num_pins = ARRAY_SIZE(gpio1d_3516_pins), | |
1887 | /* Conflict with TVC */ | |
1888 | .mask = TVC_PADS_ENABLE, | |
1889 | }, | |
1890 | { | |
1891 | .name = "gpio2agrp", | |
1892 | .pins = gpio2a_3516_pins, | |
1893 | .num_pins = ARRAY_SIZE(gpio2a_3516_pins), | |
756a024f LW |
1894 | .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, |
1895 | /* Conflict with GMII GMAC1 and extended parallel flash */ | |
06351d13 LW |
1896 | }, |
1897 | { | |
1898 | .name = "gpio2bgrp", | |
1899 | .pins = gpio2b_3516_pins, | |
1900 | .num_pins = ARRAY_SIZE(gpio2b_3516_pins), | |
756a024f LW |
1901 | /* Conflict with GMII GMAC1, extended parallel flash and LCD */ |
1902 | .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, | |
06351d13 LW |
1903 | }, |
1904 | { | |
1905 | .name = "gpio2cgrp", | |
1906 | .pins = gpio2c_3516_pins, | |
1907 | .num_pins = ARRAY_SIZE(gpio2c_3516_pins), | |
1908 | /* Conflict with PCI */ | |
1909 | .mask = PCI_PADS_ENABLE, | |
1910 | }, | |
1911 | }; | |
1912 | ||
1913 | static int gemini_get_groups_count(struct pinctrl_dev *pctldev) | |
1914 | { | |
1915 | struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
1916 | ||
1917 | if (pmx->is_3512) | |
1918 | return ARRAY_SIZE(gemini_3512_pin_groups); | |
1919 | if (pmx->is_3516) | |
1920 | return ARRAY_SIZE(gemini_3516_pin_groups); | |
1921 | return 0; | |
1922 | } | |
1923 | ||
1924 | static const char *gemini_get_group_name(struct pinctrl_dev *pctldev, | |
1925 | unsigned int selector) | |
1926 | { | |
1927 | struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
1928 | ||
1929 | if (pmx->is_3512) | |
1930 | return gemini_3512_pin_groups[selector].name; | |
1931 | if (pmx->is_3516) | |
1932 | return gemini_3516_pin_groups[selector].name; | |
1933 | return NULL; | |
1934 | } | |
1935 | ||
1936 | static int gemini_get_group_pins(struct pinctrl_dev *pctldev, | |
1937 | unsigned int selector, | |
1938 | const unsigned int **pins, | |
1939 | unsigned int *num_pins) | |
1940 | { | |
1941 | struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
1942 | ||
1943 | /* The special case with the 3516 flash pin */ | |
1944 | if (pmx->flash_pin && | |
1945 | pmx->is_3512 && | |
1946 | !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) { | |
1947 | *pins = pflash_3512_pins_extended; | |
1948 | *num_pins = ARRAY_SIZE(pflash_3512_pins_extended); | |
1949 | return 0; | |
1950 | } | |
1951 | if (pmx->flash_pin && | |
1952 | pmx->is_3516 && | |
1953 | !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) { | |
1954 | *pins = pflash_3516_pins_extended; | |
1955 | *num_pins = ARRAY_SIZE(pflash_3516_pins_extended); | |
1956 | return 0; | |
1957 | } | |
1958 | if (pmx->is_3512) { | |
1959 | *pins = gemini_3512_pin_groups[selector].pins; | |
1960 | *num_pins = gemini_3512_pin_groups[selector].num_pins; | |
1961 | } | |
1962 | if (pmx->is_3516) { | |
1963 | *pins = gemini_3516_pin_groups[selector].pins; | |
1964 | *num_pins = gemini_3516_pin_groups[selector].num_pins; | |
1965 | } | |
1966 | return 0; | |
1967 | } | |
1968 | ||
1969 | static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
1970 | unsigned int offset) | |
1971 | { | |
1972 | seq_printf(s, " " DRIVER_NAME); | |
1973 | } | |
1974 | ||
06351d13 LW |
1975 | static const struct pinctrl_ops gemini_pctrl_ops = { |
1976 | .get_groups_count = gemini_get_groups_count, | |
1977 | .get_group_name = gemini_get_group_name, | |
1978 | .get_group_pins = gemini_get_group_pins, | |
1979 | .pin_dbg_show = gemini_pin_dbg_show, | |
60ad481f | 1980 | .dt_node_to_map = pinconf_generic_dt_node_to_map_all, |
1c5b7f3c | 1981 | .dt_free_map = pinconf_generic_dt_free_map, |
06351d13 LW |
1982 | }; |
1983 | ||
1984 | /** | |
1985 | * struct gemini_pmx_func - describes Gemini pinmux functions | |
1986 | * @name: the name of this specific function | |
1987 | * @groups: corresponding pin groups | |
1988 | */ | |
1989 | struct gemini_pmx_func { | |
1990 | const char *name; | |
1991 | const char * const *groups; | |
1992 | const unsigned int num_groups; | |
1993 | }; | |
1994 | ||
1995 | static const char * const dramgrps[] = { "dramgrp" }; | |
1996 | static const char * const rtcgrps[] = { "rtcgrp" }; | |
1997 | static const char * const powergrps[] = { "powergrp" }; | |
1998 | static const char * const cirgrps[] = { "cirgrp" }; | |
1999 | static const char * const systemgrps[] = { "systemgrp" }; | |
2000 | static const char * const vcontrolgrps[] = { "vcontrolgrp" }; | |
2001 | static const char * const icegrps[] = { "icegrp" }; | |
2002 | static const char * const idegrps[] = { "idegrp" }; | |
2003 | static const char * const satagrps[] = { "satagrp" }; | |
2004 | static const char * const usbgrps[] = { "usbgrp" }; | |
756a024f | 2005 | static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" }; |
06351d13 LW |
2006 | static const char * const pcigrps[] = { "pcigrp" }; |
2007 | static const char * const lpcgrps[] = { "lpcgrp" }; | |
2008 | static const char * const lcdgrps[] = { "lcdgrp" }; | |
2009 | static const char * const sspgrps[] = { "sspgrp" }; | |
2010 | static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" }; | |
2011 | static const char * const tvcgrps[] = { "tvcgrp" }; | |
2012 | static const char * const nflashgrps[] = { "nflashgrp" }; | |
2013 | static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" }; | |
2014 | static const char * const sflashgrps[] = { "sflashgrp" }; | |
2015 | static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp", | |
2016 | "gpio0dgrp", "gpio0egrp", "gpio0fgrp", | |
2017 | "gpio0ggrp", "gpio0hgrp", "gpio0igrp", | |
2018 | "gpio0jgrp", "gpio0kgrp" }; | |
2019 | static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp", | |
2020 | "gpio1dgrp" }; | |
2021 | static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" }; | |
2022 | ||
2023 | static const struct gemini_pmx_func gemini_pmx_functions[] = { | |
2024 | { | |
2025 | .name = "dram", | |
2026 | .groups = dramgrps, | |
2027 | .num_groups = ARRAY_SIZE(idegrps), | |
2028 | }, | |
2029 | { | |
2030 | .name = "rtc", | |
2031 | .groups = rtcgrps, | |
2032 | .num_groups = ARRAY_SIZE(rtcgrps), | |
2033 | }, | |
2034 | { | |
2035 | .name = "power", | |
2036 | .groups = powergrps, | |
2037 | .num_groups = ARRAY_SIZE(powergrps), | |
2038 | }, | |
2039 | { | |
2040 | /* This function is strictly unavailable on 3512 */ | |
2041 | .name = "cir", | |
2042 | .groups = cirgrps, | |
2043 | .num_groups = ARRAY_SIZE(cirgrps), | |
2044 | }, | |
2045 | { | |
2046 | .name = "system", | |
2047 | .groups = systemgrps, | |
2048 | .num_groups = ARRAY_SIZE(systemgrps), | |
2049 | }, | |
2050 | { | |
2051 | .name = "vcontrol", | |
2052 | .groups = vcontrolgrps, | |
2053 | .num_groups = ARRAY_SIZE(vcontrolgrps), | |
2054 | }, | |
2055 | { | |
2056 | .name = "ice", | |
2057 | .groups = icegrps, | |
2058 | .num_groups = ARRAY_SIZE(icegrps), | |
2059 | }, | |
2060 | { | |
2061 | .name = "ide", | |
2062 | .groups = idegrps, | |
2063 | .num_groups = ARRAY_SIZE(idegrps), | |
2064 | }, | |
2065 | { | |
2066 | .name = "sata", | |
2067 | .groups = satagrps, | |
2068 | .num_groups = ARRAY_SIZE(satagrps), | |
2069 | }, | |
89aab2d6 LW |
2070 | { |
2071 | .name = "usb", | |
2072 | .groups = usbgrps, | |
2073 | .num_groups = ARRAY_SIZE(usbgrps), | |
2074 | }, | |
2075 | { | |
2076 | .name = "gmii", | |
2077 | .groups = gmiigrps, | |
2078 | .num_groups = ARRAY_SIZE(gmiigrps), | |
2079 | }, | |
06351d13 LW |
2080 | { |
2081 | .name = "pci", | |
2082 | .groups = pcigrps, | |
2083 | .num_groups = ARRAY_SIZE(pcigrps), | |
2084 | }, | |
2085 | { | |
2086 | .name = "lpc", | |
2087 | .groups = lpcgrps, | |
2088 | .num_groups = ARRAY_SIZE(lpcgrps), | |
2089 | }, | |
2090 | { | |
2091 | .name = "lcd", | |
2092 | .groups = lcdgrps, | |
2093 | .num_groups = ARRAY_SIZE(lcdgrps), | |
2094 | }, | |
2095 | { | |
2096 | .name = "ssp", | |
2097 | .groups = sspgrps, | |
2098 | .num_groups = ARRAY_SIZE(sspgrps), | |
2099 | }, | |
2100 | { | |
2101 | .name = "uart", | |
2102 | .groups = uartgrps, | |
2103 | .num_groups = ARRAY_SIZE(uartgrps), | |
2104 | }, | |
2105 | { | |
2106 | .name = "tvc", | |
2107 | .groups = tvcgrps, | |
2108 | .num_groups = ARRAY_SIZE(tvcgrps), | |
2109 | }, | |
2110 | { | |
2111 | .name = "nflash", | |
2112 | .groups = nflashgrps, | |
2113 | .num_groups = ARRAY_SIZE(nflashgrps), | |
2114 | }, | |
2115 | { | |
2116 | .name = "pflash", | |
2117 | .groups = pflashgrps, | |
2118 | .num_groups = ARRAY_SIZE(pflashgrps), | |
2119 | }, | |
2120 | { | |
2121 | .name = "sflash", | |
2122 | .groups = sflashgrps, | |
2123 | .num_groups = ARRAY_SIZE(sflashgrps), | |
2124 | }, | |
2125 | { | |
2126 | .name = "gpio0", | |
2127 | .groups = gpio0grps, | |
2128 | .num_groups = ARRAY_SIZE(gpio0grps), | |
2129 | }, | |
2130 | { | |
2131 | .name = "gpio1", | |
2132 | .groups = gpio1grps, | |
2133 | .num_groups = ARRAY_SIZE(gpio1grps), | |
2134 | }, | |
2135 | { | |
2136 | .name = "gpio2", | |
2137 | .groups = gpio2grps, | |
2138 | .num_groups = ARRAY_SIZE(gpio2grps), | |
2139 | }, | |
2140 | }; | |
2141 | ||
2142 | ||
2143 | static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev, | |
2144 | unsigned int selector, | |
2145 | unsigned int group) | |
2146 | { | |
2147 | struct gemini_pmx *pmx; | |
2148 | const struct gemini_pmx_func *func; | |
2149 | const struct gemini_pin_group *grp; | |
2150 | u32 before, after, expected; | |
2151 | unsigned long tmp; | |
2152 | int i; | |
2153 | ||
2154 | pmx = pinctrl_dev_get_drvdata(pctldev); | |
2155 | ||
2156 | func = &gemini_pmx_functions[selector]; | |
2157 | if (pmx->is_3512) | |
2158 | grp = &gemini_3512_pin_groups[group]; | |
2159 | else if (pmx->is_3516) | |
2160 | grp = &gemini_3516_pin_groups[group]; | |
2161 | else { | |
2162 | dev_err(pmx->dev, "invalid SoC type\n"); | |
2163 | return -ENODEV; | |
2164 | } | |
2165 | ||
2166 | dev_info(pmx->dev, | |
2167 | "ACTIVATE function \"%s\" with group \"%s\"\n", | |
2168 | func->name, grp->name); | |
2169 | ||
2170 | regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); | |
2171 | regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, grp->mask, | |
2172 | grp->value); | |
2173 | regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); | |
2174 | ||
2175 | /* Which bits changed */ | |
2176 | before &= PADS_MASK; | |
2177 | after &= PADS_MASK; | |
2178 | expected = before &= ~grp->mask; | |
2179 | expected |= grp->value; | |
2180 | expected &= PADS_MASK; | |
2181 | ||
2182 | /* Print changed states */ | |
2183 | tmp = grp->mask; | |
2184 | for_each_set_bit(i, &tmp, PADS_MAXBIT) { | |
2185 | bool enabled = !(i > 3); | |
2186 | ||
2187 | /* Did not go low though it should */ | |
2188 | if (after & BIT(i)) { | |
2189 | dev_err(pmx->dev, | |
2190 | "pin group %s could not be %s: " | |
2191 | "probably a hardware limitation\n", | |
2192 | gemini_padgroups[i], | |
2193 | enabled ? "enabled" : "disabled"); | |
2194 | dev_err(pmx->dev, | |
2195 | "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", | |
2196 | before, after, expected); | |
2197 | } else { | |
2198 | dev_info(pmx->dev, | |
2199 | "padgroup %s %s\n", | |
2200 | gemini_padgroups[i], | |
2201 | enabled ? "enabled" : "disabled"); | |
2202 | } | |
2203 | } | |
2204 | ||
2205 | tmp = grp->value; | |
2206 | for_each_set_bit(i, &tmp, PADS_MAXBIT) { | |
2207 | bool enabled = (i > 3); | |
2208 | ||
2209 | /* Did not go high though it should */ | |
2210 | if (!(after & BIT(i))) { | |
2211 | dev_err(pmx->dev, | |
2212 | "pin group %s could not be %s: " | |
2213 | "probably a hardware limitation\n", | |
2214 | gemini_padgroups[i], | |
2215 | enabled ? "enabled" : "disabled"); | |
2216 | dev_err(pmx->dev, | |
2217 | "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", | |
2218 | before, after, expected); | |
2219 | } else { | |
2220 | dev_info(pmx->dev, | |
2221 | "padgroup %s %s\n", | |
2222 | gemini_padgroups[i], | |
2223 | enabled ? "enabled" : "disabled"); | |
2224 | } | |
2225 | } | |
2226 | ||
2227 | return 0; | |
2228 | } | |
2229 | ||
2230 | static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
2231 | { | |
2232 | return ARRAY_SIZE(gemini_pmx_functions); | |
2233 | } | |
2234 | ||
2235 | static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
2236 | unsigned int selector) | |
2237 | { | |
2238 | return gemini_pmx_functions[selector].name; | |
2239 | } | |
2240 | ||
2241 | static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev, | |
2242 | unsigned int selector, | |
2243 | const char * const **groups, | |
2244 | unsigned int * const num_groups) | |
2245 | { | |
2246 | *groups = gemini_pmx_functions[selector].groups; | |
2247 | *num_groups = gemini_pmx_functions[selector].num_groups; | |
2248 | return 0; | |
2249 | } | |
2250 | ||
2251 | static const struct pinmux_ops gemini_pmx_ops = { | |
2252 | .get_functions_count = gemini_pmx_get_funcs_count, | |
2253 | .get_function_name = gemini_pmx_get_func_name, | |
2254 | .get_function_groups = gemini_pmx_get_groups, | |
2255 | .set_mux = gemini_pmx_set_mux, | |
2256 | }; | |
2257 | ||
60ad481f LW |
2258 | #define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \ |
2259 | .pin = _n, \ | |
2260 | .reg = _r, \ | |
2261 | .mask = GENMASK(_hb, _lb) \ | |
2262 | } | |
2263 | ||
2264 | static const struct gemini_pin_conf gemini_confs_3512[] = { | |
2265 | GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ | |
2266 | GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ | |
2267 | GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ | |
2268 | GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ | |
2269 | GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ | |
2270 | GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ | |
2271 | GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ | |
2272 | GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ | |
2273 | GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ | |
2274 | GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ | |
2275 | GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ | |
2276 | GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ | |
2277 | GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ | |
2278 | GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ | |
2279 | GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ | |
2280 | GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ | |
2281 | GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ | |
2282 | GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ | |
2283 | GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ | |
2284 | GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ | |
2285 | GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ | |
2286 | GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ | |
2287 | GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ | |
2288 | GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ | |
2289 | }; | |
2290 | ||
2291 | static const struct gemini_pin_conf gemini_confs_3516[] = { | |
2292 | GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ | |
2293 | GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ | |
2294 | GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ | |
2295 | GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ | |
2296 | GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ | |
2297 | GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ | |
2298 | GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ | |
2299 | GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ | |
2300 | GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ | |
2301 | GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ | |
2302 | GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ | |
2303 | GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ | |
2304 | GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ | |
2305 | GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ | |
2306 | GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ | |
2307 | GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ | |
2308 | GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ | |
2309 | GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ | |
2310 | GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ | |
2311 | GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ | |
2312 | GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ | |
2313 | GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ | |
2314 | GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ | |
2315 | GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ | |
2316 | }; | |
2317 | ||
2318 | static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx, | |
2319 | unsigned int pin) | |
2320 | { | |
2321 | const struct gemini_pin_conf *retconf; | |
2322 | int i; | |
2323 | ||
2324 | for (i = 0; i < pmx->nconfs; i++) { | |
793b9184 | 2325 | retconf = &pmx->confs[i]; |
60ad481f LW |
2326 | if (retconf->pin == pin) |
2327 | return retconf; | |
2328 | } | |
2329 | return NULL; | |
2330 | } | |
2331 | ||
2332 | static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
2333 | unsigned long *config) | |
2334 | { | |
2335 | struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
2336 | enum pin_config_param param = pinconf_to_config_param(*config); | |
2337 | const struct gemini_pin_conf *conf; | |
2338 | u32 val; | |
2339 | ||
2340 | switch (param) { | |
2341 | case PIN_CONFIG_SKEW_DELAY: | |
2342 | conf = gemini_get_pin_conf(pmx, pin); | |
2343 | if (!conf) | |
2344 | return -ENOTSUPP; | |
2345 | regmap_read(pmx->map, conf->reg, &val); | |
2346 | val &= conf->mask; | |
2347 | val >>= (ffs(conf->mask) - 1); | |
2348 | *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val); | |
2349 | break; | |
2350 | default: | |
2351 | return -ENOTSUPP; | |
2352 | } | |
2353 | ||
2354 | return 0; | |
2355 | } | |
2356 | ||
2357 | static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
2358 | unsigned long *configs, unsigned int num_configs) | |
2359 | { | |
2360 | struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
2361 | const struct gemini_pin_conf *conf; | |
2362 | enum pin_config_param param; | |
2363 | u32 arg; | |
2364 | int ret = 0; | |
2365 | int i; | |
2366 | ||
2367 | for (i = 0; i < num_configs; i++) { | |
2368 | param = pinconf_to_config_param(configs[i]); | |
2369 | arg = pinconf_to_config_argument(configs[i]); | |
2370 | ||
2371 | switch (param) { | |
2372 | case PIN_CONFIG_SKEW_DELAY: | |
2373 | if (arg > 0xf) | |
2374 | return -EINVAL; | |
2375 | conf = gemini_get_pin_conf(pmx, pin); | |
2376 | if (!conf) { | |
2377 | dev_err(pmx->dev, | |
2378 | "invalid pin for skew delay %d\n", pin); | |
2379 | return -ENOTSUPP; | |
2380 | } | |
2381 | arg <<= (ffs(conf->mask) - 1); | |
2382 | dev_dbg(pmx->dev, | |
2383 | "set pin %d to skew delay mask %08x, val %08x\n", | |
2384 | pin, conf->mask, arg); | |
2385 | regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); | |
2386 | break; | |
2387 | default: | |
2388 | dev_err(pmx->dev, "Invalid config param %04x\n", param); | |
2389 | return -ENOTSUPP; | |
2390 | } | |
2391 | } | |
2392 | ||
2393 | return ret; | |
2394 | } | |
2395 | ||
2396 | static const struct pinconf_ops gemini_pinconf_ops = { | |
2397 | .pin_config_get = gemini_pinconf_get, | |
2398 | .pin_config_set = gemini_pinconf_set, | |
2399 | .is_generic = true, | |
2400 | }; | |
2401 | ||
06351d13 LW |
2402 | static struct pinctrl_desc gemini_pmx_desc = { |
2403 | .name = DRIVER_NAME, | |
2404 | .pctlops = &gemini_pctrl_ops, | |
2405 | .pmxops = &gemini_pmx_ops, | |
60ad481f | 2406 | .confops = &gemini_pinconf_ops, |
06351d13 LW |
2407 | .owner = THIS_MODULE, |
2408 | }; | |
2409 | ||
2410 | static int gemini_pmx_probe(struct platform_device *pdev) | |
2411 | { | |
2412 | struct gemini_pmx *pmx; | |
2413 | struct regmap *map; | |
2414 | struct device *dev = &pdev->dev; | |
2415 | struct device *parent; | |
2416 | unsigned long tmp; | |
2417 | u32 val; | |
2418 | int ret; | |
2419 | int i; | |
2420 | ||
2421 | /* Create state holders etc for this driver */ | |
2422 | pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); | |
2423 | if (!pmx) | |
2424 | return -ENOMEM; | |
2425 | ||
2426 | pmx->dev = &pdev->dev; | |
2427 | parent = dev->parent; | |
2428 | if (!parent) { | |
2429 | dev_err(dev, "no parent to pin controller\n"); | |
2430 | return -ENODEV; | |
2431 | } | |
2432 | map = syscon_node_to_regmap(parent->of_node); | |
2433 | if (IS_ERR(map)) { | |
2434 | dev_err(dev, "no syscon regmap\n"); | |
2435 | return PTR_ERR(map); | |
2436 | } | |
2437 | pmx->map = map; | |
2438 | ||
2439 | /* Check that regmap works at first call, then no more */ | |
2440 | ret = regmap_read(map, GLOBAL_WORD_ID, &val); | |
2441 | if (ret) { | |
2442 | dev_err(dev, "cannot access regmap\n"); | |
2443 | return ret; | |
2444 | } | |
2445 | val >>= 8; | |
2446 | val &= 0xffff; | |
2447 | if (val == 0x3512) { | |
2448 | pmx->is_3512 = true; | |
60ad481f LW |
2449 | pmx->confs = gemini_confs_3512; |
2450 | pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); | |
06351d13 LW |
2451 | gemini_pmx_desc.pins = gemini_3512_pins; |
2452 | gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); | |
2453 | dev_info(dev, "detected 3512 chip variant\n"); | |
2454 | } else if (val == 0x3516) { | |
2455 | pmx->is_3516 = true; | |
60ad481f LW |
2456 | pmx->confs = gemini_confs_3516; |
2457 | pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); | |
06351d13 LW |
2458 | gemini_pmx_desc.pins = gemini_3516_pins; |
2459 | gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); | |
2460 | dev_info(dev, "detected 3516 chip variant\n"); | |
2461 | } else { | |
2462 | dev_err(dev, "unknown chip ID: %04x\n", val); | |
2463 | return -ENODEV; | |
2464 | } | |
2465 | ||
2466 | ret = regmap_read(map, GLOBAL_MISC_CTRL, &val); | |
2467 | dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val); | |
2468 | /* Mask off relevant pads */ | |
2469 | val &= PADS_MASK; | |
2470 | /* Invert the meaning of the DRAM+flash pads */ | |
2471 | val ^= 0x0f; | |
2472 | /* Print initial state */ | |
2473 | tmp = val; | |
2474 | for_each_set_bit(i, &tmp, PADS_MAXBIT) { | |
2475 | dev_info(dev, "pad group %s %s\n", gemini_padgroups[i], | |
2476 | (val & BIT(i)) ? "enabled" : "disabled"); | |
2477 | } | |
2478 | ||
2479 | /* Check if flash pin is set */ | |
2480 | regmap_read(map, GLOBAL_STATUS, &val); | |
2481 | pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); | |
2482 | dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); | |
2483 | ||
2484 | pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); | |
2485 | if (IS_ERR(pmx->pctl)) { | |
2486 | dev_err(dev, "could not register pinmux driver\n"); | |
2487 | return PTR_ERR(pmx->pctl); | |
2488 | } | |
2489 | ||
2490 | dev_info(dev, "initialized Gemini pin control driver\n"); | |
2491 | ||
2492 | return 0; | |
2493 | } | |
2494 | ||
2495 | static const struct of_device_id gemini_pinctrl_match[] = { | |
2496 | { .compatible = "cortina,gemini-pinctrl" }, | |
2497 | {}, | |
2498 | }; | |
2499 | ||
2500 | static struct platform_driver gemini_pmx_driver = { | |
2501 | .driver = { | |
2502 | .name = DRIVER_NAME, | |
2503 | .of_match_table = gemini_pinctrl_match, | |
2504 | }, | |
2505 | .probe = gemini_pmx_probe, | |
2506 | }; | |
2507 | ||
2508 | static int __init gemini_pmx_init(void) | |
2509 | { | |
2510 | return platform_driver_register(&gemini_pmx_driver); | |
2511 | } | |
2512 | arch_initcall(gemini_pmx_init); |