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43b169db TA |
1 | /* |
2 | * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * Copyright (c) 2012 Linaro Ltd | |
7 | * http://www.linaro.org | |
8 | * | |
9 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This file contains the Samsung Exynos specific information required by the | |
17 | * the Samsung pinctrl/gpiolib driver. It also includes the implementation of | |
18 | * external gpio and wakeup interrupt support. | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irqdomain.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/err.h> | |
30 | ||
31 | #include <asm/mach/irq.h> | |
32 | ||
33 | #include "pinctrl-samsung.h" | |
34 | #include "pinctrl-exynos.h" | |
35 | ||
36 | /* list of external wakeup controllers supported */ | |
37 | static const struct of_device_id exynos_wkup_irq_ids[] = { | |
38 | { .compatible = "samsung,exynos4210-wakeup-eint", }, | |
39 | }; | |
40 | ||
41 | static void exynos_gpio_irq_unmask(struct irq_data *irqd) | |
42 | { | |
595be726 TF |
43 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
44 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
45 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; | |
43b169db TA |
46 | unsigned long mask; |
47 | ||
48 | mask = readl(d->virt_base + reg_mask); | |
595be726 | 49 | mask &= ~(1 << irqd->hwirq); |
43b169db TA |
50 | writel(mask, d->virt_base + reg_mask); |
51 | } | |
52 | ||
53 | static void exynos_gpio_irq_mask(struct irq_data *irqd) | |
54 | { | |
595be726 TF |
55 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
56 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
57 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; | |
43b169db TA |
58 | unsigned long mask; |
59 | ||
60 | mask = readl(d->virt_base + reg_mask); | |
595be726 | 61 | mask |= 1 << irqd->hwirq; |
43b169db TA |
62 | writel(mask, d->virt_base + reg_mask); |
63 | } | |
64 | ||
65 | static void exynos_gpio_irq_ack(struct irq_data *irqd) | |
66 | { | |
595be726 TF |
67 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
68 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
69 | unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; | |
43b169db | 70 | |
595be726 | 71 | writel(1 << irqd->hwirq, d->virt_base + reg_pend); |
43b169db TA |
72 | } |
73 | ||
74 | static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) | |
75 | { | |
595be726 TF |
76 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
77 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
43b169db | 78 | struct samsung_pin_ctrl *ctrl = d->ctrl; |
595be726 TF |
79 | unsigned int pin = irqd->hwirq; |
80 | unsigned int shift = EXYNOS_EINT_CON_LEN * pin; | |
43b169db | 81 | unsigned int con, trig_type; |
595be726 | 82 | unsigned long reg_con = ctrl->geint_con + bank->eint_offset; |
ee2f573c | 83 | unsigned int mask; |
43b169db TA |
84 | |
85 | switch (type) { | |
86 | case IRQ_TYPE_EDGE_RISING: | |
87 | trig_type = EXYNOS_EINT_EDGE_RISING; | |
88 | break; | |
89 | case IRQ_TYPE_EDGE_FALLING: | |
90 | trig_type = EXYNOS_EINT_EDGE_FALLING; | |
91 | break; | |
92 | case IRQ_TYPE_EDGE_BOTH: | |
93 | trig_type = EXYNOS_EINT_EDGE_BOTH; | |
94 | break; | |
95 | case IRQ_TYPE_LEVEL_HIGH: | |
96 | trig_type = EXYNOS_EINT_LEVEL_HIGH; | |
97 | break; | |
98 | case IRQ_TYPE_LEVEL_LOW: | |
99 | trig_type = EXYNOS_EINT_LEVEL_LOW; | |
100 | break; | |
101 | default: | |
102 | pr_err("unsupported external interrupt type\n"); | |
103 | return -EINVAL; | |
104 | } | |
105 | ||
106 | if (type & IRQ_TYPE_EDGE_BOTH) | |
107 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); | |
108 | else | |
109 | __irq_set_handler_locked(irqd->irq, handle_level_irq); | |
110 | ||
111 | con = readl(d->virt_base + reg_con); | |
112 | con &= ~(EXYNOS_EINT_CON_MASK << shift); | |
113 | con |= trig_type << shift; | |
114 | writel(con, d->virt_base + reg_con); | |
ee2f573c TF |
115 | |
116 | reg_con = bank->pctl_offset; | |
595be726 | 117 | shift = pin * bank->func_width; |
ee2f573c TF |
118 | mask = (1 << bank->func_width) - 1; |
119 | ||
120 | con = readl(d->virt_base + reg_con); | |
121 | con &= ~(mask << shift); | |
122 | con |= EXYNOS_EINT_FUNC << shift; | |
123 | writel(con, d->virt_base + reg_con); | |
124 | ||
43b169db TA |
125 | return 0; |
126 | } | |
127 | ||
128 | /* | |
129 | * irq_chip for gpio interrupts. | |
130 | */ | |
131 | static struct irq_chip exynos_gpio_irq_chip = { | |
132 | .name = "exynos_gpio_irq_chip", | |
133 | .irq_unmask = exynos_gpio_irq_unmask, | |
134 | .irq_mask = exynos_gpio_irq_mask, | |
135 | .irq_ack = exynos_gpio_irq_ack, | |
136 | .irq_set_type = exynos_gpio_irq_set_type, | |
137 | }; | |
138 | ||
43b169db TA |
139 | static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, |
140 | irq_hw_number_t hw) | |
141 | { | |
595be726 | 142 | struct samsung_pin_bank *b = h->host_data; |
43b169db | 143 | |
595be726 | 144 | irq_set_chip_data(virq, b); |
43b169db TA |
145 | irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, |
146 | handle_level_irq); | |
147 | set_irq_flags(virq, IRQF_VALID); | |
148 | return 0; | |
149 | } | |
150 | ||
43b169db TA |
151 | /* |
152 | * irq domain callbacks for external gpio interrupt controller. | |
153 | */ | |
154 | static const struct irq_domain_ops exynos_gpio_irqd_ops = { | |
155 | .map = exynos_gpio_irq_map, | |
43b169db TA |
156 | .xlate = irq_domain_xlate_twocell, |
157 | }; | |
158 | ||
159 | static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) | |
160 | { | |
161 | struct samsung_pinctrl_drv_data *d = data; | |
162 | struct samsung_pin_ctrl *ctrl = d->ctrl; | |
163 | struct samsung_pin_bank *bank = ctrl->pin_banks; | |
164 | unsigned int svc, group, pin, virq; | |
165 | ||
166 | svc = readl(d->virt_base + ctrl->svc); | |
167 | group = EXYNOS_SVC_GROUP(svc); | |
168 | pin = svc & EXYNOS_SVC_NUM_MASK; | |
169 | ||
170 | if (!group) | |
171 | return IRQ_HANDLED; | |
172 | bank += (group - 1); | |
173 | ||
595be726 | 174 | virq = irq_linear_revmap(bank->irq_domain, pin); |
43b169db TA |
175 | if (!virq) |
176 | return IRQ_NONE; | |
177 | generic_handle_irq(virq); | |
178 | return IRQ_HANDLED; | |
179 | } | |
180 | ||
181 | /* | |
182 | * exynos_eint_gpio_init() - setup handling of external gpio interrupts. | |
183 | * @d: driver data of samsung pinctrl driver. | |
184 | */ | |
185 | static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) | |
186 | { | |
595be726 | 187 | struct samsung_pin_bank *bank; |
43b169db TA |
188 | struct device *dev = d->dev; |
189 | unsigned int ret; | |
595be726 | 190 | unsigned int i; |
43b169db TA |
191 | |
192 | if (!d->irq) { | |
193 | dev_err(dev, "irq number not available\n"); | |
194 | return -EINVAL; | |
195 | } | |
196 | ||
197 | ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, | |
198 | 0, dev_name(dev), d); | |
199 | if (ret) { | |
200 | dev_err(dev, "irq request failed\n"); | |
201 | return -ENXIO; | |
202 | } | |
203 | ||
595be726 TF |
204 | bank = d->ctrl->pin_banks; |
205 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
206 | if (bank->eint_type != EINT_TYPE_GPIO) | |
207 | continue; | |
208 | bank->irq_domain = irq_domain_add_linear(bank->of_node, | |
209 | bank->nr_pins, &exynos_gpio_irqd_ops, bank); | |
210 | if (!bank->irq_domain) { | |
211 | dev_err(dev, "gpio irq domain add failed\n"); | |
212 | return -ENXIO; | |
213 | } | |
43b169db TA |
214 | } |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static void exynos_wkup_irq_unmask(struct irq_data *irqd) | |
220 | { | |
a04b07c0 TF |
221 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
222 | struct samsung_pinctrl_drv_data *d = b->drvdata; | |
223 | unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; | |
43b169db TA |
224 | unsigned long mask; |
225 | ||
226 | mask = readl(d->virt_base + reg_mask); | |
a04b07c0 | 227 | mask &= ~(1 << irqd->hwirq); |
43b169db TA |
228 | writel(mask, d->virt_base + reg_mask); |
229 | } | |
230 | ||
231 | static void exynos_wkup_irq_mask(struct irq_data *irqd) | |
232 | { | |
a04b07c0 TF |
233 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
234 | struct samsung_pinctrl_drv_data *d = b->drvdata; | |
235 | unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; | |
43b169db TA |
236 | unsigned long mask; |
237 | ||
238 | mask = readl(d->virt_base + reg_mask); | |
a04b07c0 | 239 | mask |= 1 << irqd->hwirq; |
43b169db TA |
240 | writel(mask, d->virt_base + reg_mask); |
241 | } | |
242 | ||
243 | static void exynos_wkup_irq_ack(struct irq_data *irqd) | |
244 | { | |
a04b07c0 TF |
245 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
246 | struct samsung_pinctrl_drv_data *d = b->drvdata; | |
247 | unsigned long pend = d->ctrl->weint_pend + b->eint_offset; | |
43b169db | 248 | |
a04b07c0 | 249 | writel(1 << irqd->hwirq, d->virt_base + pend); |
43b169db TA |
250 | } |
251 | ||
252 | static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) | |
253 | { | |
a04b07c0 TF |
254 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
255 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
256 | unsigned int pin = irqd->hwirq; | |
257 | unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset; | |
43b169db TA |
258 | unsigned long shift = EXYNOS_EINT_CON_LEN * pin; |
259 | unsigned long con, trig_type; | |
260 | ||
261 | switch (type) { | |
262 | case IRQ_TYPE_EDGE_RISING: | |
263 | trig_type = EXYNOS_EINT_EDGE_RISING; | |
264 | break; | |
265 | case IRQ_TYPE_EDGE_FALLING: | |
266 | trig_type = EXYNOS_EINT_EDGE_FALLING; | |
267 | break; | |
268 | case IRQ_TYPE_EDGE_BOTH: | |
269 | trig_type = EXYNOS_EINT_EDGE_BOTH; | |
270 | break; | |
271 | case IRQ_TYPE_LEVEL_HIGH: | |
272 | trig_type = EXYNOS_EINT_LEVEL_HIGH; | |
273 | break; | |
274 | case IRQ_TYPE_LEVEL_LOW: | |
275 | trig_type = EXYNOS_EINT_LEVEL_LOW; | |
276 | break; | |
277 | default: | |
278 | pr_err("unsupported external interrupt type\n"); | |
279 | return -EINVAL; | |
280 | } | |
281 | ||
282 | if (type & IRQ_TYPE_EDGE_BOTH) | |
283 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); | |
284 | else | |
285 | __irq_set_handler_locked(irqd->irq, handle_level_irq); | |
286 | ||
287 | con = readl(d->virt_base + reg_con); | |
288 | con &= ~(EXYNOS_EINT_CON_MASK << shift); | |
289 | con |= trig_type << shift; | |
290 | writel(con, d->virt_base + reg_con); | |
291 | return 0; | |
292 | } | |
293 | ||
294 | /* | |
295 | * irq_chip for wakeup interrupts | |
296 | */ | |
297 | static struct irq_chip exynos_wkup_irq_chip = { | |
298 | .name = "exynos_wkup_irq_chip", | |
299 | .irq_unmask = exynos_wkup_irq_unmask, | |
300 | .irq_mask = exynos_wkup_irq_mask, | |
301 | .irq_ack = exynos_wkup_irq_ack, | |
302 | .irq_set_type = exynos_wkup_irq_set_type, | |
303 | }; | |
304 | ||
305 | /* interrupt handler for wakeup interrupts 0..15 */ | |
306 | static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) | |
307 | { | |
308 | struct exynos_weint_data *eintd = irq_get_handler_data(irq); | |
a04b07c0 | 309 | struct samsung_pin_bank *bank = eintd->bank; |
43b169db TA |
310 | struct irq_chip *chip = irq_get_chip(irq); |
311 | int eint_irq; | |
312 | ||
313 | chained_irq_enter(chip, desc); | |
314 | chip->irq_mask(&desc->irq_data); | |
315 | ||
316 | if (chip->irq_ack) | |
317 | chip->irq_ack(&desc->irq_data); | |
318 | ||
a04b07c0 | 319 | eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); |
43b169db TA |
320 | generic_handle_irq(eint_irq); |
321 | chip->irq_unmask(&desc->irq_data); | |
322 | chained_irq_exit(chip, desc); | |
323 | } | |
324 | ||
a04b07c0 TF |
325 | static inline void exynos_irq_demux_eint(unsigned long pend, |
326 | struct irq_domain *domain) | |
43b169db TA |
327 | { |
328 | unsigned int irq; | |
329 | ||
330 | while (pend) { | |
331 | irq = fls(pend) - 1; | |
a04b07c0 | 332 | generic_handle_irq(irq_find_mapping(domain, irq)); |
43b169db TA |
333 | pend &= ~(1 << irq); |
334 | } | |
335 | } | |
336 | ||
337 | /* interrupt handler for wakeup interrupt 16 */ | |
338 | static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | |
339 | { | |
340 | struct irq_chip *chip = irq_get_chip(irq); | |
a04b07c0 TF |
341 | struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); |
342 | struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; | |
343 | struct samsung_pin_ctrl *ctrl = d->ctrl; | |
43b169db | 344 | unsigned long pend; |
de59049b | 345 | unsigned long mask; |
a04b07c0 | 346 | int i; |
43b169db TA |
347 | |
348 | chained_irq_enter(chip, desc); | |
a04b07c0 TF |
349 | |
350 | for (i = 0; i < eintd->nr_banks; ++i) { | |
351 | struct samsung_pin_bank *b = eintd->banks[i]; | |
352 | pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset); | |
353 | mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset); | |
354 | exynos_irq_demux_eint(pend & ~mask, b->irq_domain); | |
355 | } | |
356 | ||
43b169db TA |
357 | chained_irq_exit(chip, desc); |
358 | } | |
359 | ||
360 | static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, | |
361 | irq_hw_number_t hw) | |
362 | { | |
363 | irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq); | |
364 | irq_set_chip_data(virq, h->host_data); | |
365 | set_irq_flags(virq, IRQF_VALID); | |
366 | return 0; | |
367 | } | |
368 | ||
369 | /* | |
370 | * irq domain callbacks for external wakeup interrupt controller. | |
371 | */ | |
372 | static const struct irq_domain_ops exynos_wkup_irqd_ops = { | |
373 | .map = exynos_wkup_irq_map, | |
374 | .xlate = irq_domain_xlate_twocell, | |
375 | }; | |
376 | ||
377 | /* | |
378 | * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. | |
379 | * @d: driver data of samsung pinctrl driver. | |
380 | */ | |
381 | static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) | |
382 | { | |
383 | struct device *dev = d->dev; | |
c3ad056b TF |
384 | struct device_node *wkup_np = NULL; |
385 | struct device_node *np; | |
a04b07c0 | 386 | struct samsung_pin_bank *bank; |
43b169db | 387 | struct exynos_weint_data *weint_data; |
a04b07c0 TF |
388 | struct exynos_muxed_weint_data *muxed_data; |
389 | unsigned int muxed_banks = 0; | |
390 | unsigned int i; | |
43b169db TA |
391 | int idx, irq; |
392 | ||
c3ad056b TF |
393 | for_each_child_of_node(dev->of_node, np) { |
394 | if (of_match_node(exynos_wkup_irq_ids, np)) { | |
395 | wkup_np = np; | |
396 | break; | |
397 | } | |
43b169db | 398 | } |
c3ad056b TF |
399 | if (!wkup_np) |
400 | return -ENODEV; | |
43b169db | 401 | |
a04b07c0 TF |
402 | bank = d->ctrl->pin_banks; |
403 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
404 | if (bank->eint_type != EINT_TYPE_WKUP) | |
405 | continue; | |
43b169db | 406 | |
a04b07c0 TF |
407 | bank->irq_domain = irq_domain_add_linear(bank->of_node, |
408 | bank->nr_pins, &exynos_wkup_irqd_ops, bank); | |
409 | if (!bank->irq_domain) { | |
410 | dev_err(dev, "wkup irq domain add failed\n"); | |
411 | return -ENXIO; | |
412 | } | |
43b169db | 413 | |
a04b07c0 TF |
414 | if (!of_find_property(bank->of_node, "interrupts", NULL)) { |
415 | bank->eint_type = EINT_TYPE_WKUP_MUX; | |
416 | ++muxed_banks; | |
417 | continue; | |
418 | } | |
43b169db | 419 | |
a04b07c0 TF |
420 | weint_data = devm_kzalloc(dev, bank->nr_pins |
421 | * sizeof(*weint_data), GFP_KERNEL); | |
422 | if (!weint_data) { | |
423 | dev_err(dev, "could not allocate memory for weint_data\n"); | |
424 | return -ENOMEM; | |
425 | } | |
43b169db | 426 | |
a04b07c0 TF |
427 | for (idx = 0; idx < bank->nr_pins; ++idx) { |
428 | irq = irq_of_parse_and_map(bank->of_node, idx); | |
429 | if (!irq) { | |
430 | dev_err(dev, "irq number for eint-%s-%d not found\n", | |
431 | bank->name, idx); | |
432 | continue; | |
433 | } | |
434 | weint_data[idx].irq = idx; | |
435 | weint_data[idx].bank = bank; | |
43b169db TA |
436 | irq_set_handler_data(irq, &weint_data[idx]); |
437 | irq_set_chained_handler(irq, exynos_irq_eint0_15); | |
43b169db TA |
438 | } |
439 | } | |
a04b07c0 TF |
440 | |
441 | if (!muxed_banks) | |
442 | return 0; | |
443 | ||
444 | irq = irq_of_parse_and_map(wkup_np, 0); | |
445 | if (!irq) { | |
446 | dev_err(dev, "irq number for muxed EINTs not found\n"); | |
447 | return 0; | |
448 | } | |
449 | ||
450 | muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) | |
451 | + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); | |
452 | if (!muxed_data) { | |
453 | dev_err(dev, "could not allocate memory for muxed_data\n"); | |
454 | return -ENOMEM; | |
455 | } | |
456 | ||
457 | irq_set_chained_handler(irq, exynos_irq_demux_eint16_31); | |
458 | irq_set_handler_data(irq, muxed_data); | |
459 | ||
460 | bank = d->ctrl->pin_banks; | |
461 | idx = 0; | |
462 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
463 | if (bank->eint_type != EINT_TYPE_WKUP_MUX) | |
464 | continue; | |
465 | ||
466 | muxed_data->banks[idx++] = bank; | |
467 | } | |
468 | muxed_data->nr_banks = muxed_banks; | |
469 | ||
43b169db TA |
470 | return 0; |
471 | } | |
472 | ||
473 | /* pin banks of exynos4210 pin-controller 0 */ | |
474 | static struct samsung_pin_bank exynos4210_pin_banks0[] = { | |
1b6056d6 TF |
475 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
476 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), | |
477 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), | |
478 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), | |
479 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), | |
480 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), | |
481 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), | |
482 | EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), | |
483 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), | |
484 | EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), | |
485 | EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), | |
486 | EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), | |
487 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), | |
488 | EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), | |
489 | EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), | |
490 | EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), | |
43b169db TA |
491 | }; |
492 | ||
493 | /* pin banks of exynos4210 pin-controller 1 */ | |
494 | static struct samsung_pin_bank exynos4210_pin_banks1[] = { | |
1b6056d6 TF |
495 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), |
496 | EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), | |
497 | EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), | |
498 | EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), | |
499 | EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), | |
500 | EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), | |
501 | EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), | |
502 | EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), | |
503 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), | |
40ba6227 TF |
504 | EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), |
505 | EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), | |
506 | EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), | |
507 | EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), | |
508 | EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), | |
509 | EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), | |
510 | EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), | |
a04b07c0 TF |
511 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), |
512 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), | |
513 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), | |
514 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), | |
43b169db TA |
515 | }; |
516 | ||
517 | /* pin banks of exynos4210 pin-controller 2 */ | |
518 | static struct samsung_pin_bank exynos4210_pin_banks2[] = { | |
40ba6227 | 519 | EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), |
43b169db TA |
520 | }; |
521 | ||
522 | /* | |
523 | * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes | |
524 | * three gpio/pin-mux/pinconfig controllers. | |
525 | */ | |
526 | struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { | |
527 | { | |
528 | /* pin-controller instance 0 data */ | |
529 | .pin_banks = exynos4210_pin_banks0, | |
530 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), | |
43b169db TA |
531 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
532 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
533 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
534 | .svc = EXYNOS_SVC_OFFSET, | |
535 | .eint_gpio_init = exynos_eint_gpio_init, | |
536 | .label = "exynos4210-gpio-ctrl0", | |
537 | }, { | |
538 | /* pin-controller instance 1 data */ | |
539 | .pin_banks = exynos4210_pin_banks1, | |
540 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), | |
43b169db TA |
541 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
542 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
543 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
544 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, | |
545 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
546 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
547 | .svc = EXYNOS_SVC_OFFSET, | |
548 | .eint_gpio_init = exynos_eint_gpio_init, | |
549 | .eint_wkup_init = exynos_eint_wkup_init, | |
550 | .label = "exynos4210-gpio-ctrl1", | |
551 | }, { | |
552 | /* pin-controller instance 2 data */ | |
553 | .pin_banks = exynos4210_pin_banks2, | |
554 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), | |
43b169db TA |
555 | .label = "exynos4210-gpio-ctrl2", |
556 | }, | |
557 | }; |