Commit | Line | Data |
---|---|---|
bd41b99d | 1 | /* |
c103de24 | 2 | * U300 GPIO module. |
bd41b99d | 3 | * |
cc890cd7 | 4 | * Copyright (C) 2007-2011 ST-Ericsson AB |
bd41b99d | 5 | * License terms: GNU General Public License (GPL) version 2 |
bd41b99d LW |
6 | * This can driver either of the two basic GPIO cores |
7 | * available in the U300 platforms: | |
8 | * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0) | |
9 | * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) | |
cc890cd7 | 10 | * Author: Linus Walleij <linus.walleij@linaro.org> |
bd41b99d | 11 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> |
bd41b99d LW |
12 | */ |
13 | #include <linux/module.h> | |
cc890cd7 | 14 | #include <linux/irq.h> |
bd41b99d LW |
15 | #include <linux/interrupt.h> |
16 | #include <linux/delay.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/gpio.h> | |
cc890cd7 LW |
23 | #include <linux/list.h> |
24 | #include <linux/slab.h> | |
28a8d14c | 25 | #include <linux/pinctrl/consumer.h> |
eb3cf18c | 26 | #include <mach/gpio-u300.h> |
bd41b99d | 27 | |
cc890cd7 LW |
28 | /* |
29 | * Register definitions for COH 901 335 variant | |
30 | */ | |
31 | #define U300_335_PORT_STRIDE (0x1C) | |
32 | /* Port X Pin Data Register 32bit, this is both input and output (R/W) */ | |
33 | #define U300_335_PXPDIR (0x00) | |
34 | #define U300_335_PXPDOR (0x00) | |
35 | /* Port X Pin Config Register 32bit (R/W) */ | |
36 | #define U300_335_PXPCR (0x04) | |
37 | /* This register layout is the same in both blocks */ | |
38 | #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) | |
39 | #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) | |
40 | #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) | |
41 | #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) | |
42 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) | |
43 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) | |
44 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) | |
45 | /* Port X Interrupt Event Register 32bit (R/W) */ | |
46 | #define U300_335_PXIEV (0x08) | |
47 | /* Port X Interrupt Enable Register 32bit (R/W) */ | |
48 | #define U300_335_PXIEN (0x0C) | |
49 | /* Port X Interrupt Force Register 32bit (R/W) */ | |
50 | #define U300_335_PXIFR (0x10) | |
51 | /* Port X Interrupt Config Register 32bit (R/W) */ | |
52 | #define U300_335_PXICR (0x14) | |
53 | /* This register layout is the same in both blocks */ | |
54 | #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) | |
55 | #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) | |
56 | #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) | |
57 | #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) | |
58 | /* Port X Pull-up Enable Register 32bit (R/W) */ | |
59 | #define U300_335_PXPER (0x18) | |
60 | /* This register layout is the same in both blocks */ | |
61 | #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) | |
62 | #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) | |
63 | /* Control Register 32bit (R/W) */ | |
64 | #define U300_335_CR (0x54) | |
65 | #define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL) | |
66 | ||
67 | /* | |
68 | * Register definitions for COH 901 571 / 3 variant | |
69 | */ | |
70 | #define U300_571_PORT_STRIDE (0x30) | |
71 | /* | |
72 | * Control Register 32bit (R/W) | |
73 | * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores | |
74 | * gives the number of GPIO pins. | |
75 | * bit 8-2 (mask 0x000001FC) contains the core version ID. | |
76 | */ | |
77 | #define U300_571_CR (0x00) | |
78 | #define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL) | |
79 | #define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) | |
80 | /* | |
81 | * These registers have the same layout and function as the corresponding | |
82 | * COH 901 335 registers, just at different offset. | |
83 | */ | |
84 | #define U300_571_PXPDIR (0x04) | |
85 | #define U300_571_PXPDOR (0x08) | |
86 | #define U300_571_PXPCR (0x0C) | |
87 | #define U300_571_PXPER (0x10) | |
88 | #define U300_571_PXIEV (0x14) | |
89 | #define U300_571_PXIEN (0x18) | |
90 | #define U300_571_PXIFR (0x1C) | |
91 | #define U300_571_PXICR (0x20) | |
92 | ||
93 | /* 8 bits per port, no version has more than 7 ports */ | |
94 | #define U300_GPIO_PINS_PER_PORT 8 | |
95 | #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7) | |
96 | ||
97 | struct u300_gpio { | |
98 | struct gpio_chip chip; | |
99 | struct list_head port_list; | |
100 | struct clk *clk; | |
101 | struct resource *memres; | |
102 | void __iomem *base; | |
103 | struct device *dev; | |
104 | int irq_base; | |
105 | u32 stride; | |
106 | /* Register offsets */ | |
107 | u32 pcr; | |
108 | u32 dor; | |
109 | u32 dir; | |
110 | u32 per; | |
111 | u32 icr; | |
112 | u32 ien; | |
113 | u32 iev; | |
114 | }; | |
bd41b99d LW |
115 | |
116 | struct u300_gpio_port { | |
cc890cd7 LW |
117 | struct list_head node; |
118 | struct u300_gpio *gpio; | |
119 | char name[8]; | |
bd41b99d LW |
120 | int irq; |
121 | int number; | |
cc890cd7 | 122 | u8 toggle_edge_mode; |
bd41b99d LW |
123 | }; |
124 | ||
cc890cd7 LW |
125 | /* |
126 | * Macro to expand to read a specific register found in the "gpio" | |
127 | * struct. It requires the struct u300_gpio *gpio variable to exist in | |
128 | * its context. It calculates the port offset from the given pin | |
129 | * offset, muliplies by the port stride and adds the register offset | |
130 | * so it provides a pointer to the desired register. | |
131 | */ | |
132 | #define U300_PIN_REG(pin, reg) \ | |
133 | (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) | |
bd41b99d | 134 | |
cc890cd7 LW |
135 | /* |
136 | * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO | |
137 | * register. | |
138 | */ | |
139 | #define U300_PIN_BIT(pin) \ | |
140 | (1 << (pin & 0x07)) | |
bd41b99d | 141 | |
cc890cd7 LW |
142 | struct u300_gpio_confdata { |
143 | u16 bias_mode; | |
144 | bool output; | |
145 | int outval; | |
bd41b99d LW |
146 | }; |
147 | ||
cc890cd7 LW |
148 | /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */ |
149 | #define BS335_GPIO_NUM_PORTS 7 | |
150 | /* BS365 has five ports of 8 bits each = GPIO pins 0..39 */ | |
151 | #define BS365_GPIO_NUM_PORTS 5 | |
bd41b99d | 152 | |
cc890cd7 | 153 | #define U300_FLOATING_INPUT { \ |
a050b3ee | 154 | .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ |
cc890cd7 LW |
155 | .output = false, \ |
156 | } | |
bd41b99d | 157 | |
cc890cd7 | 158 | #define U300_PULL_UP_INPUT { \ |
a050b3ee | 159 | .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ |
cc890cd7 LW |
160 | .output = false, \ |
161 | } | |
bd41b99d | 162 | |
cc890cd7 LW |
163 | #define U300_OUTPUT_LOW { \ |
164 | .output = true, \ | |
165 | .outval = 0, \ | |
166 | } | |
bd41b99d | 167 | |
cc890cd7 LW |
168 | #define U300_OUTPUT_HIGH { \ |
169 | .output = true, \ | |
170 | .outval = 1, \ | |
171 | } | |
bd41b99d | 172 | |
bd41b99d LW |
173 | |
174 | /* Initial configuration */ | |
cc890cd7 LW |
175 | static const struct __initdata u300_gpio_confdata |
176 | bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { | |
bd41b99d LW |
177 | /* Port 0, pins 0-7 */ |
178 | { | |
cc890cd7 LW |
179 | U300_FLOATING_INPUT, |
180 | U300_OUTPUT_HIGH, | |
181 | U300_FLOATING_INPUT, | |
182 | U300_OUTPUT_LOW, | |
183 | U300_OUTPUT_LOW, | |
184 | U300_OUTPUT_LOW, | |
185 | U300_OUTPUT_LOW, | |
186 | U300_OUTPUT_LOW, | |
bd41b99d LW |
187 | }, |
188 | /* Port 1, pins 0-7 */ | |
189 | { | |
cc890cd7 LW |
190 | U300_OUTPUT_LOW, |
191 | U300_OUTPUT_LOW, | |
192 | U300_OUTPUT_LOW, | |
193 | U300_PULL_UP_INPUT, | |
194 | U300_FLOATING_INPUT, | |
195 | U300_OUTPUT_HIGH, | |
196 | U300_OUTPUT_LOW, | |
197 | U300_OUTPUT_LOW, | |
bd41b99d LW |
198 | }, |
199 | /* Port 2, pins 0-7 */ | |
200 | { | |
cc890cd7 LW |
201 | U300_FLOATING_INPUT, |
202 | U300_FLOATING_INPUT, | |
203 | U300_FLOATING_INPUT, | |
204 | U300_FLOATING_INPUT, | |
205 | U300_OUTPUT_LOW, | |
206 | U300_PULL_UP_INPUT, | |
207 | U300_OUTPUT_LOW, | |
208 | U300_PULL_UP_INPUT, | |
bd41b99d LW |
209 | }, |
210 | /* Port 3, pins 0-7 */ | |
211 | { | |
cc890cd7 LW |
212 | U300_PULL_UP_INPUT, |
213 | U300_OUTPUT_LOW, | |
214 | U300_FLOATING_INPUT, | |
215 | U300_FLOATING_INPUT, | |
216 | U300_FLOATING_INPUT, | |
217 | U300_FLOATING_INPUT, | |
218 | U300_FLOATING_INPUT, | |
219 | U300_FLOATING_INPUT, | |
bd41b99d LW |
220 | }, |
221 | /* Port 4, pins 0-7 */ | |
222 | { | |
cc890cd7 LW |
223 | U300_FLOATING_INPUT, |
224 | U300_FLOATING_INPUT, | |
225 | U300_FLOATING_INPUT, | |
226 | U300_FLOATING_INPUT, | |
227 | U300_FLOATING_INPUT, | |
228 | U300_FLOATING_INPUT, | |
229 | U300_FLOATING_INPUT, | |
230 | U300_FLOATING_INPUT, | |
bd41b99d LW |
231 | }, |
232 | /* Port 5, pins 0-7 */ | |
233 | { | |
cc890cd7 LW |
234 | U300_FLOATING_INPUT, |
235 | U300_FLOATING_INPUT, | |
236 | U300_FLOATING_INPUT, | |
237 | U300_FLOATING_INPUT, | |
238 | U300_FLOATING_INPUT, | |
239 | U300_FLOATING_INPUT, | |
240 | U300_FLOATING_INPUT, | |
241 | U300_FLOATING_INPUT, | |
bd41b99d LW |
242 | }, |
243 | /* Port 6, pind 0-7 */ | |
244 | { | |
cc890cd7 LW |
245 | U300_FLOATING_INPUT, |
246 | U300_FLOATING_INPUT, | |
247 | U300_FLOATING_INPUT, | |
248 | U300_FLOATING_INPUT, | |
249 | U300_FLOATING_INPUT, | |
250 | U300_FLOATING_INPUT, | |
251 | U300_FLOATING_INPUT, | |
252 | U300_FLOATING_INPUT, | |
bd41b99d | 253 | } |
cc890cd7 | 254 | }; |
bd41b99d | 255 | |
cc890cd7 LW |
256 | static const struct __initdata u300_gpio_confdata |
257 | bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { | |
bd41b99d LW |
258 | /* Port 0, pins 0-7 */ |
259 | { | |
cc890cd7 LW |
260 | U300_FLOATING_INPUT, |
261 | U300_OUTPUT_LOW, | |
262 | U300_FLOATING_INPUT, | |
263 | U300_OUTPUT_LOW, | |
264 | U300_OUTPUT_LOW, | |
265 | U300_OUTPUT_LOW, | |
266 | U300_PULL_UP_INPUT, | |
267 | U300_FLOATING_INPUT, | |
bd41b99d LW |
268 | }, |
269 | /* Port 1, pins 0-7 */ | |
270 | { | |
cc890cd7 LW |
271 | U300_OUTPUT_LOW, |
272 | U300_FLOATING_INPUT, | |
273 | U300_OUTPUT_LOW, | |
274 | U300_FLOATING_INPUT, | |
275 | U300_FLOATING_INPUT, | |
276 | U300_OUTPUT_HIGH, | |
277 | U300_OUTPUT_LOW, | |
278 | U300_OUTPUT_LOW, | |
bd41b99d LW |
279 | }, |
280 | /* Port 2, pins 0-7 */ | |
281 | { | |
cc890cd7 LW |
282 | U300_FLOATING_INPUT, |
283 | U300_PULL_UP_INPUT, | |
284 | U300_OUTPUT_LOW, | |
285 | U300_OUTPUT_LOW, | |
286 | U300_PULL_UP_INPUT, | |
287 | U300_PULL_UP_INPUT, | |
288 | U300_PULL_UP_INPUT, | |
289 | U300_PULL_UP_INPUT, | |
bd41b99d LW |
290 | }, |
291 | /* Port 3, pins 0-7 */ | |
292 | { | |
cc890cd7 LW |
293 | U300_PULL_UP_INPUT, |
294 | U300_PULL_UP_INPUT, | |
295 | U300_PULL_UP_INPUT, | |
296 | U300_PULL_UP_INPUT, | |
297 | U300_PULL_UP_INPUT, | |
298 | U300_PULL_UP_INPUT, | |
299 | U300_PULL_UP_INPUT, | |
300 | U300_PULL_UP_INPUT, | |
bd41b99d LW |
301 | }, |
302 | /* Port 4, pins 0-7 */ | |
303 | { | |
cc890cd7 LW |
304 | U300_PULL_UP_INPUT, |
305 | U300_PULL_UP_INPUT, | |
306 | U300_PULL_UP_INPUT, | |
307 | U300_PULL_UP_INPUT, | |
bd41b99d | 308 | /* These 4 pins doesn't exist on DB3210 */ |
cc890cd7 LW |
309 | U300_OUTPUT_LOW, |
310 | U300_OUTPUT_LOW, | |
311 | U300_OUTPUT_LOW, | |
312 | U300_OUTPUT_LOW, | |
bd41b99d | 313 | } |
bd41b99d | 314 | }; |
bd41b99d | 315 | |
cc890cd7 LW |
316 | /** |
317 | * to_u300_gpio() - get the pointer to u300_gpio | |
318 | * @chip: the gpio chip member of the structure u300_gpio | |
bd41b99d | 319 | */ |
cc890cd7 | 320 | static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip) |
bd41b99d | 321 | { |
cc890cd7 | 322 | return container_of(chip, struct u300_gpio, chip); |
bd41b99d | 323 | } |
bd41b99d | 324 | |
b4e3ac74 LW |
325 | static int u300_gpio_request(struct gpio_chip *chip, unsigned offset) |
326 | { | |
327 | /* | |
328 | * Map back to global GPIO space and request muxing, the direction | |
329 | * parameter does not matter for this controller. | |
330 | */ | |
331 | int gpio = chip->base + offset; | |
332 | ||
e93bcee0 | 333 | return pinctrl_request_gpio(gpio); |
b4e3ac74 LW |
334 | } |
335 | ||
336 | static void u300_gpio_free(struct gpio_chip *chip, unsigned offset) | |
337 | { | |
338 | int gpio = chip->base + offset; | |
339 | ||
e93bcee0 | 340 | pinctrl_free_gpio(gpio); |
b4e3ac74 LW |
341 | } |
342 | ||
cc890cd7 | 343 | static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 344 | { |
cc890cd7 | 345 | struct u300_gpio *gpio = to_u300_gpio(chip); |
bd41b99d | 346 | |
cc890cd7 | 347 | return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset); |
bd41b99d | 348 | } |
bd41b99d | 349 | |
cc890cd7 | 350 | static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
ee17962e | 351 | { |
cc890cd7 LW |
352 | struct u300_gpio *gpio = to_u300_gpio(chip); |
353 | unsigned long flags; | |
354 | u32 val; | |
ee17962e | 355 | |
cc890cd7 | 356 | local_irq_save(flags); |
bd41b99d | 357 | |
cc890cd7 LW |
358 | val = readl(U300_PIN_REG(offset, dor)); |
359 | if (value) | |
360 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); | |
361 | else | |
362 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); | |
bd41b99d | 363 | |
cc890cd7 | 364 | local_irq_restore(flags); |
bd41b99d | 365 | } |
bd41b99d | 366 | |
cc890cd7 | 367 | static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 368 | { |
cc890cd7 LW |
369 | struct u300_gpio *gpio = to_u300_gpio(chip); |
370 | unsigned long flags; | |
371 | u32 val; | |
bd41b99d | 372 | |
cc890cd7 LW |
373 | local_irq_save(flags); |
374 | val = readl(U300_PIN_REG(offset, pcr)); | |
375 | /* Mask out this pin, note 2 bits per setting */ | |
376 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); | |
377 | writel(val, U300_PIN_REG(offset, pcr)); | |
378 | local_irq_restore(flags); | |
379 | return 0; | |
bd41b99d | 380 | } |
bd41b99d | 381 | |
cc890cd7 LW |
382 | static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
383 | int value) | |
bd41b99d | 384 | { |
cc890cd7 | 385 | struct u300_gpio *gpio = to_u300_gpio(chip); |
bd41b99d | 386 | unsigned long flags; |
cc890cd7 LW |
387 | u32 oldmode; |
388 | u32 val; | |
bd41b99d LW |
389 | |
390 | local_irq_save(flags); | |
cc890cd7 LW |
391 | val = readl(U300_PIN_REG(offset, pcr)); |
392 | /* | |
393 | * Drive mode must be set by the special mode set function, set | |
394 | * push/pull mode by default if no mode has been selected. | |
395 | */ | |
396 | oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << | |
397 | ((offset & 0x07) << 1)); | |
398 | /* mode = 0 means input, else some mode is already set */ | |
399 | if (oldmode == 0) { | |
400 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << | |
401 | ((offset & 0x07) << 1)); | |
402 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL | |
403 | << ((offset & 0x07) << 1)); | |
404 | writel(val, U300_PIN_REG(offset, pcr)); | |
bd41b99d | 405 | } |
cc890cd7 | 406 | u300_gpio_set(chip, offset, value); |
bd41b99d | 407 | local_irq_restore(flags); |
cc890cd7 | 408 | return 0; |
bd41b99d | 409 | } |
bd41b99d | 410 | |
cc890cd7 | 411 | static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 412 | { |
cc890cd7 LW |
413 | struct u300_gpio *gpio = to_u300_gpio(chip); |
414 | int retirq = gpio->irq_base + offset; | |
415 | ||
416 | dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset, | |
417 | retirq); | |
418 | return retirq; | |
419 | } | |
420 | ||
421 | static int u300_gpio_config(struct gpio_chip *chip, unsigned offset, | |
a050b3ee | 422 | enum pin_config_param param, unsigned long data) |
cc890cd7 LW |
423 | { |
424 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
bd41b99d LW |
425 | unsigned long flags; |
426 | u32 val; | |
427 | ||
bd41b99d | 428 | local_irq_save(flags); |
cc890cd7 | 429 | switch (param) { |
a050b3ee LW |
430 | case PIN_CONFIG_BIAS_DISABLE: |
431 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
cc890cd7 LW |
432 | val = readl(U300_PIN_REG(offset, per)); |
433 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); | |
434 | break; | |
a050b3ee | 435 | case PIN_CONFIG_BIAS_PULL_UP: |
cc890cd7 LW |
436 | val = readl(U300_PIN_REG(offset, per)); |
437 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); | |
438 | break; | |
a050b3ee | 439 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
cc890cd7 LW |
440 | val = readl(U300_PIN_REG(offset, pcr)); |
441 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
442 | << ((offset & 0x07) << 1)); | |
443 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL | |
444 | << ((offset & 0x07) << 1)); | |
445 | writel(val, U300_PIN_REG(offset, pcr)); | |
446 | break; | |
a050b3ee | 447 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
cc890cd7 LW |
448 | val = readl(U300_PIN_REG(offset, pcr)); |
449 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
450 | << ((offset & 0x07) << 1)); | |
451 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN | |
452 | << ((offset & 0x07) << 1)); | |
453 | writel(val, U300_PIN_REG(offset, pcr)); | |
454 | break; | |
a050b3ee | 455 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
cc890cd7 LW |
456 | val = readl(U300_PIN_REG(offset, pcr)); |
457 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
458 | << ((offset & 0x07) << 1)); | |
459 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE | |
460 | << ((offset & 0x07) << 1)); | |
461 | writel(val, U300_PIN_REG(offset, pcr)); | |
462 | break; | |
463 | default: | |
464 | local_irq_restore(flags); | |
465 | dev_err(gpio->dev, "illegal configuration requested\n"); | |
466 | return -EINVAL; | |
467 | } | |
bd41b99d LW |
468 | local_irq_restore(flags); |
469 | return 0; | |
470 | } | |
bd41b99d | 471 | |
cc890cd7 LW |
472 | static struct gpio_chip u300_gpio_chip = { |
473 | .label = "u300-gpio-chip", | |
474 | .owner = THIS_MODULE, | |
b4e3ac74 LW |
475 | .request = u300_gpio_request, |
476 | .free = u300_gpio_free, | |
cc890cd7 LW |
477 | .get = u300_gpio_get, |
478 | .set = u300_gpio_set, | |
479 | .direction_input = u300_gpio_direction_input, | |
480 | .direction_output = u300_gpio_direction_output, | |
481 | .to_irq = u300_gpio_to_irq, | |
482 | }; | |
483 | ||
484 | static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) | |
bd41b99d | 485 | { |
bd41b99d LW |
486 | u32 val; |
487 | ||
cc890cd7 LW |
488 | val = readl(U300_PIN_REG(offset, icr)); |
489 | /* Set mode depending on state */ | |
490 | if (u300_gpio_get(&gpio->chip, offset)) { | |
491 | /* High now, let's trigger on falling edge next then */ | |
492 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
493 | dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", | |
494 | offset); | |
495 | } else { | |
496 | /* Low now, let's trigger on rising edge next then */ | |
497 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
498 | dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", | |
499 | offset); | |
500 | } | |
bd41b99d | 501 | } |
bd41b99d | 502 | |
cc890cd7 | 503 | static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) |
bd41b99d | 504 | { |
cc890cd7 LW |
505 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
506 | struct u300_gpio *gpio = port->gpio; | |
507 | int offset = d->irq - gpio->irq_base; | |
bd41b99d | 508 | u32 val; |
bd41b99d | 509 | |
cc890cd7 LW |
510 | if ((trigger & IRQF_TRIGGER_RISING) && |
511 | (trigger & IRQF_TRIGGER_FALLING)) { | |
512 | /* | |
513 | * The GPIO block can only trigger on falling OR rising edges, | |
514 | * not both. So we need to toggle the mode whenever the pin | |
515 | * goes from one state to the other with a special state flag | |
516 | */ | |
517 | dev_dbg(gpio->dev, | |
518 | "trigger on both rising and falling edge on pin %d\n", | |
519 | offset); | |
520 | port->toggle_edge_mode |= U300_PIN_BIT(offset); | |
521 | u300_toggle_trigger(gpio, offset); | |
522 | } else if (trigger & IRQF_TRIGGER_RISING) { | |
523 | dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n", | |
524 | offset); | |
525 | val = readl(U300_PIN_REG(offset, icr)); | |
526 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
527 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); | |
528 | } else if (trigger & IRQF_TRIGGER_FALLING) { | |
529 | dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n", | |
530 | offset); | |
531 | val = readl(U300_PIN_REG(offset, icr)); | |
532 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
533 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); | |
534 | } | |
535 | ||
536 | return 0; | |
bd41b99d | 537 | } |
bd41b99d | 538 | |
cc890cd7 | 539 | static void u300_gpio_irq_enable(struct irq_data *d) |
bd41b99d | 540 | { |
cc890cd7 LW |
541 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
542 | struct u300_gpio *gpio = port->gpio; | |
543 | int offset = d->irq - gpio->irq_base; | |
bd41b99d LW |
544 | u32 val; |
545 | unsigned long flags; | |
546 | ||
547 | local_irq_save(flags); | |
cc890cd7 LW |
548 | val = readl(U300_PIN_REG(offset, ien)); |
549 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | |
bd41b99d LW |
550 | local_irq_restore(flags); |
551 | } | |
bd41b99d | 552 | |
cc890cd7 | 553 | static void u300_gpio_irq_disable(struct irq_data *d) |
bd41b99d | 554 | { |
cc890cd7 LW |
555 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
556 | struct u300_gpio *gpio = port->gpio; | |
557 | int offset = d->irq - gpio->irq_base; | |
bd41b99d LW |
558 | u32 val; |
559 | unsigned long flags; | |
560 | ||
561 | local_irq_save(flags); | |
cc890cd7 LW |
562 | val = readl(U300_PIN_REG(offset, ien)); |
563 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | |
bd41b99d LW |
564 | local_irq_restore(flags); |
565 | } | |
bd41b99d | 566 | |
cc890cd7 LW |
567 | static struct irq_chip u300_gpio_irqchip = { |
568 | .name = "u300-gpio-irqchip", | |
569 | .irq_enable = u300_gpio_irq_enable, | |
570 | .irq_disable = u300_gpio_irq_disable, | |
571 | .irq_set_type = u300_gpio_irq_type, | |
572 | ||
573 | }; | |
574 | ||
575 | static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
bd41b99d | 576 | { |
cc890cd7 LW |
577 | struct u300_gpio_port *port = irq_get_handler_data(irq); |
578 | struct u300_gpio *gpio = port->gpio; | |
579 | int pinoffset = port->number << 3; /* get the right stride */ | |
580 | unsigned long val; | |
bd41b99d | 581 | |
cc890cd7 | 582 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
bd41b99d | 583 | /* Read event register */ |
cc890cd7 | 584 | val = readl(U300_PIN_REG(pinoffset, iev)); |
bd41b99d | 585 | /* Mask relevant bits */ |
cc890cd7 | 586 | val &= 0xFFU; /* 8 bits per port */ |
bd41b99d | 587 | /* ACK IRQ (clear event) */ |
cc890cd7 LW |
588 | writel(val, U300_PIN_REG(pinoffset, iev)); |
589 | ||
590 | /* Call IRQ handler */ | |
591 | if (val != 0) { | |
592 | int irqoffset; | |
593 | ||
594 | for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { | |
595 | int pin_irq = gpio->irq_base + (port->number << 3) | |
596 | + irqoffset; | |
597 | int offset = pinoffset + irqoffset; | |
598 | ||
599 | dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", | |
600 | pin_irq, offset); | |
601 | generic_handle_irq(pin_irq); | |
602 | /* | |
603 | * Triggering IRQ on both rising and falling edge | |
604 | * needs mockery | |
605 | */ | |
606 | if (port->toggle_edge_mode & U300_PIN_BIT(offset)) | |
607 | u300_toggle_trigger(gpio, offset); | |
608 | } | |
bd41b99d | 609 | } |
cc890cd7 LW |
610 | |
611 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
bd41b99d LW |
612 | } |
613 | ||
cc890cd7 LW |
614 | static void __init u300_gpio_init_pin(struct u300_gpio *gpio, |
615 | int offset, | |
616 | const struct u300_gpio_confdata *conf) | |
bd41b99d | 617 | { |
cc890cd7 LW |
618 | /* Set mode: input or output */ |
619 | if (conf->output) { | |
620 | u300_gpio_direction_output(&gpio->chip, offset, conf->outval); | |
bd41b99d | 621 | |
cc890cd7 LW |
622 | /* Deactivate bias mode for output */ |
623 | u300_gpio_config(&gpio->chip, offset, | |
a050b3ee LW |
624 | PIN_CONFIG_BIAS_HIGH_IMPEDANCE, |
625 | 0); | |
cc890cd7 LW |
626 | |
627 | /* Set drive mode for output */ | |
628 | u300_gpio_config(&gpio->chip, offset, | |
a050b3ee | 629 | PIN_CONFIG_DRIVE_PUSH_PULL, 0); |
cc890cd7 LW |
630 | |
631 | dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", | |
632 | offset, conf->outval); | |
633 | } else { | |
634 | u300_gpio_direction_input(&gpio->chip, offset); | |
635 | ||
636 | /* Always set output low on input pins */ | |
637 | u300_gpio_set(&gpio->chip, offset, 0); | |
638 | ||
639 | /* Set bias mode for input */ | |
a050b3ee | 640 | u300_gpio_config(&gpio->chip, offset, conf->bias_mode, 0); |
cc890cd7 LW |
641 | |
642 | dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", | |
643 | offset, conf->bias_mode); | |
bd41b99d | 644 | } |
cc890cd7 | 645 | } |
bd41b99d | 646 | |
cc890cd7 LW |
647 | static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, |
648 | struct u300_gpio_platform *plat) | |
649 | { | |
650 | int i, j; | |
651 | ||
652 | /* Write default config and values to all pins */ | |
653 | for (i = 0; i < plat->ports; i++) { | |
654 | for (j = 0; j < 8; j++) { | |
655 | const struct u300_gpio_confdata *conf; | |
656 | int offset = (i*8) + j; | |
657 | ||
658 | if (plat->variant == U300_GPIO_COH901571_3_BS335) | |
659 | conf = &bs335_gpio_config[i][j]; | |
660 | else if (plat->variant == U300_GPIO_COH901571_3_BS365) | |
661 | conf = &bs365_gpio_config[i][j]; | |
662 | else | |
663 | break; | |
664 | ||
665 | u300_gpio_init_pin(gpio, offset, conf); | |
bd41b99d LW |
666 | } |
667 | } | |
cc890cd7 | 668 | } |
bd41b99d | 669 | |
cc890cd7 LW |
670 | static inline void u300_gpio_free_ports(struct u300_gpio *gpio) |
671 | { | |
672 | struct u300_gpio_port *port; | |
673 | struct list_head *p, *n; | |
674 | ||
675 | list_for_each_safe(p, n, &gpio->port_list) { | |
676 | port = list_entry(p, struct u300_gpio_port, node); | |
677 | list_del(&port->node); | |
cc890cd7 | 678 | kfree(port); |
bd41b99d | 679 | } |
bd41b99d LW |
680 | } |
681 | ||
cc890cd7 | 682 | static int __init u300_gpio_probe(struct platform_device *pdev) |
bd41b99d | 683 | { |
cc890cd7 LW |
684 | struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); |
685 | struct u300_gpio *gpio; | |
bd41b99d | 686 | int err = 0; |
cc890cd7 LW |
687 | int portno; |
688 | u32 val; | |
689 | u32 ifr; | |
bd41b99d | 690 | int i; |
bd41b99d | 691 | |
cc890cd7 LW |
692 | gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL); |
693 | if (gpio == NULL) { | |
694 | dev_err(&pdev->dev, "failed to allocate memory\n"); | |
695 | return -ENOMEM; | |
696 | } | |
697 | ||
698 | gpio->chip = u300_gpio_chip; | |
699 | gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT; | |
700 | gpio->irq_base = plat->gpio_irq_base; | |
701 | gpio->chip.dev = &pdev->dev; | |
702 | gpio->chip.base = plat->gpio_base; | |
703 | gpio->dev = &pdev->dev; | |
bd41b99d LW |
704 | |
705 | /* Get GPIO clock */ | |
cc890cd7 LW |
706 | gpio->clk = clk_get(gpio->dev, NULL); |
707 | if (IS_ERR(gpio->clk)) { | |
708 | err = PTR_ERR(gpio->clk); | |
709 | dev_err(gpio->dev, "could not get GPIO clock\n"); | |
bd41b99d LW |
710 | goto err_no_clk; |
711 | } | |
cc890cd7 | 712 | err = clk_enable(gpio->clk); |
bd41b99d | 713 | if (err) { |
cc890cd7 | 714 | dev_err(gpio->dev, "could not enable GPIO clock\n"); |
bd41b99d LW |
715 | goto err_no_clk_enable; |
716 | } | |
717 | ||
cc890cd7 LW |
718 | gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
719 | if (!gpio->memres) { | |
720 | dev_err(gpio->dev, "could not get GPIO memory resource\n"); | |
721 | err = -ENODEV; | |
bd41b99d | 722 | goto err_no_resource; |
cc890cd7 | 723 | } |
bd41b99d | 724 | |
cc890cd7 LW |
725 | if (!request_mem_region(gpio->memres->start, |
726 | resource_size(gpio->memres), | |
28f65c11 | 727 | "GPIO Controller")) { |
bd41b99d LW |
728 | err = -ENODEV; |
729 | goto err_no_ioregion; | |
730 | } | |
731 | ||
cc890cd7 LW |
732 | gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres)); |
733 | if (!gpio->base) { | |
bd41b99d LW |
734 | err = -ENOMEM; |
735 | goto err_no_ioremap; | |
736 | } | |
cc890cd7 LW |
737 | |
738 | if (plat->variant == U300_GPIO_COH901335) { | |
739 | dev_info(gpio->dev, | |
740 | "initializing GPIO Controller COH 901 335\n"); | |
741 | gpio->stride = U300_335_PORT_STRIDE; | |
742 | gpio->pcr = U300_335_PXPCR; | |
743 | gpio->dor = U300_335_PXPDOR; | |
744 | gpio->dir = U300_335_PXPDIR; | |
745 | gpio->per = U300_335_PXPER; | |
746 | gpio->icr = U300_335_PXICR; | |
747 | gpio->ien = U300_335_PXIEN; | |
748 | gpio->iev = U300_335_PXIEV; | |
749 | ifr = U300_335_PXIFR; | |
750 | ||
751 | /* Turn on the GPIO block */ | |
752 | writel(U300_335_CR_BLOCK_CLOCK_ENABLE, | |
753 | gpio->base + U300_335_CR); | |
754 | } else if (plat->variant == U300_GPIO_COH901571_3_BS335 || | |
755 | plat->variant == U300_GPIO_COH901571_3_BS365) { | |
756 | dev_info(gpio->dev, | |
757 | "initializing GPIO Controller COH 901 571/3\n"); | |
758 | gpio->stride = U300_571_PORT_STRIDE; | |
759 | gpio->pcr = U300_571_PXPCR; | |
760 | gpio->dor = U300_571_PXPDOR; | |
761 | gpio->dir = U300_571_PXPDIR; | |
762 | gpio->per = U300_571_PXPER; | |
763 | gpio->icr = U300_571_PXICR; | |
764 | gpio->ien = U300_571_PXIEN; | |
765 | gpio->iev = U300_571_PXIEV; | |
766 | ifr = U300_571_PXIFR; | |
767 | ||
768 | val = readl(gpio->base + U300_571_CR); | |
769 | dev_info(gpio->dev, "COH901571/3 block version: %d, " \ | |
770 | "number of cores: %d totalling %d pins\n", | |
771 | ((val & 0x000001FC) >> 2), | |
772 | ((val & 0x0000FE00) >> 9), | |
773 | ((val & 0x0000FE00) >> 9) * 8); | |
774 | writel(U300_571_CR_BLOCK_CLKRQ_ENABLE, | |
775 | gpio->base + U300_571_CR); | |
776 | u300_gpio_init_coh901571(gpio, plat); | |
777 | } else { | |
778 | dev_err(gpio->dev, "unknown block variant\n"); | |
779 | err = -ENODEV; | |
780 | goto err_unknown_variant; | |
781 | } | |
782 | ||
783 | /* Add each port with its IRQ separately */ | |
784 | INIT_LIST_HEAD(&gpio->port_list); | |
785 | for (portno = 0 ; portno < plat->ports; portno++) { | |
786 | struct u300_gpio_port *port = | |
787 | kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); | |
788 | ||
789 | if (!port) { | |
790 | dev_err(gpio->dev, "out of memory\n"); | |
791 | err = -ENOMEM; | |
792 | goto err_no_port; | |
bd41b99d | 793 | } |
cc890cd7 LW |
794 | |
795 | snprintf(port->name, 8, "gpio%d", portno); | |
796 | port->number = portno; | |
797 | port->gpio = gpio; | |
798 | ||
799 | port->irq = platform_get_irq_byname(pdev, | |
800 | port->name); | |
801 | ||
802 | dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq, | |
803 | port->name); | |
804 | ||
805 | irq_set_chained_handler(port->irq, u300_gpio_irq_handler); | |
806 | irq_set_handler_data(port->irq, port); | |
807 | ||
808 | /* For each GPIO pin set the unique IRQ handler */ | |
809 | for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) { | |
810 | int irqno = gpio->irq_base + (portno << 3) + i; | |
811 | ||
812 | dev_dbg(gpio->dev, "handler for IRQ %d on %s\n", | |
813 | irqno, port->name); | |
814 | irq_set_chip_and_handler(irqno, &u300_gpio_irqchip, | |
815 | handle_simple_irq); | |
816 | set_irq_flags(irqno, IRQF_VALID); | |
817 | irq_set_chip_data(irqno, port); | |
818 | } | |
819 | ||
820 | /* Turns off irq force (test register) for this port */ | |
821 | writel(0x0, gpio->base + portno * gpio->stride + ifr); | |
822 | ||
823 | list_add_tail(&port->node, &gpio->port_list); | |
bd41b99d | 824 | } |
cc890cd7 LW |
825 | dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); |
826 | ||
827 | err = gpiochip_add(&gpio->chip); | |
828 | if (err) { | |
829 | dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); | |
830 | goto err_no_chip; | |
831 | } | |
832 | ||
128a06d4 LW |
833 | /* Spawn pin controller device as child of the GPIO, pass gpio chip */ |
834 | plat->pinctrl_device->dev.platform_data = &gpio->chip; | |
835 | err = platform_device_register(plat->pinctrl_device); | |
836 | if (err) | |
837 | goto err_no_pinctrl; | |
838 | ||
cc890cd7 | 839 | platform_set_drvdata(pdev, gpio); |
bd41b99d LW |
840 | |
841 | return 0; | |
842 | ||
128a06d4 LW |
843 | err_no_pinctrl: |
844 | err = gpiochip_remove(&gpio->chip); | |
cc890cd7 LW |
845 | err_no_chip: |
846 | err_no_port: | |
847 | u300_gpio_free_ports(gpio); | |
848 | err_unknown_variant: | |
849 | iounmap(gpio->base); | |
850 | err_no_ioremap: | |
851 | release_mem_region(gpio->memres->start, resource_size(gpio->memres)); | |
852 | err_no_ioregion: | |
853 | err_no_resource: | |
854 | clk_disable(gpio->clk); | |
855 | err_no_clk_enable: | |
856 | clk_put(gpio->clk); | |
857 | err_no_clk: | |
858 | kfree(gpio); | |
859 | dev_info(&pdev->dev, "module ERROR:%d\n", err); | |
bd41b99d LW |
860 | return err; |
861 | } | |
862 | ||
cc890cd7 | 863 | static int __exit u300_gpio_remove(struct platform_device *pdev) |
bd41b99d | 864 | { |
cc890cd7 LW |
865 | struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); |
866 | struct u300_gpio *gpio = platform_get_drvdata(pdev); | |
867 | int err; | |
bd41b99d LW |
868 | |
869 | /* Turn off the GPIO block */ | |
cc890cd7 LW |
870 | if (plat->variant == U300_GPIO_COH901335) |
871 | writel(0x00000000U, gpio->base + U300_335_CR); | |
872 | if (plat->variant == U300_GPIO_COH901571_3_BS335 || | |
873 | plat->variant == U300_GPIO_COH901571_3_BS365) | |
874 | writel(0x00000000U, gpio->base + U300_571_CR); | |
875 | ||
876 | err = gpiochip_remove(&gpio->chip); | |
877 | if (err < 0) { | |
878 | dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err); | |
879 | return err; | |
880 | } | |
881 | u300_gpio_free_ports(gpio); | |
882 | iounmap(gpio->base); | |
883 | release_mem_region(gpio->memres->start, | |
884 | resource_size(gpio->memres)); | |
885 | clk_disable(gpio->clk); | |
886 | clk_put(gpio->clk); | |
887 | platform_set_drvdata(pdev, NULL); | |
888 | kfree(gpio); | |
bd41b99d LW |
889 | return 0; |
890 | } | |
891 | ||
cc890cd7 | 892 | static struct platform_driver u300_gpio_driver = { |
bd41b99d LW |
893 | .driver = { |
894 | .name = "u300-gpio", | |
895 | }, | |
cc890cd7 | 896 | .remove = __exit_p(u300_gpio_remove), |
bd41b99d LW |
897 | }; |
898 | ||
bd41b99d LW |
899 | static int __init u300_gpio_init(void) |
900 | { | |
cc890cd7 | 901 | return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); |
bd41b99d LW |
902 | } |
903 | ||
904 | static void __exit u300_gpio_exit(void) | |
905 | { | |
cc890cd7 | 906 | platform_driver_unregister(&u300_gpio_driver); |
bd41b99d LW |
907 | } |
908 | ||
909 | arch_initcall(u300_gpio_init); | |
910 | module_exit(u300_gpio_exit); | |
911 | ||
912 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | |
cc890cd7 | 913 | MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver"); |
bd41b99d | 914 | MODULE_LICENSE("GPL"); |