[linux-2.6-block.git] / drivers / pinctrl / pinctrl-axp209.c

/*
 * AXP20x pinctrl and GPIO driver
 *
 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under  the terms of the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/axp20x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#define AXP20X_GPIO_FUNCTIONS		0x7
#define AXP20X_GPIO_FUNCTION_OUT_LOW	0
#define AXP20X_GPIO_FUNCTION_OUT_HIGH	1
#define AXP20X_GPIO_FUNCTION_INPUT	2

#define AXP20X_FUNC_GPIO_OUT		0
#define AXP20X_FUNC_GPIO_IN		1
#define AXP20X_FUNC_LDO			2
#define AXP20X_FUNC_ADC			3
#define AXP20X_FUNCS_NB			4

#define AXP20X_MUX_GPIO_OUT		0
#define AXP20X_MUX_GPIO_IN		BIT(1)
#define AXP20X_MUX_ADC			BIT(2)

struct axp20x_pctrl_desc {
	const struct pinctrl_pin_desc	*pins;
	unsigned int			npins;
	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	u8				ldo_mask;
	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	u8				adc_mask;
	u8				gpio_status_offset;
};

struct axp20x_pinctrl_function {
	const char	*name;
	unsigned int	muxval;
	const char	**groups;
	unsigned int	ngroups;
};

struct axp20x_pctl {
	struct gpio_chip	chip;
	struct regmap		*regmap;
	struct pinctrl_dev			*pctl_dev;
	struct device				*dev;
	const struct axp20x_pctrl_desc		*desc;
	struct axp20x_pinctrl_function		funcs[AXP20X_FUNCS_NB];
};

static const struct pinctrl_pin_desc axp209_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
	PINCTRL_PIN(2, "GPIO2"),
};

static const struct axp20x_pctrl_desc axp20x_data = {
	.pins	= axp209_pins,
	.npins	= ARRAY_SIZE(axp209_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0) | BIT(1),
	.gpio_status_offset = 4,
};

static int axp20x_gpio_get_reg(unsigned int offset)
{
	switch (offset) {
	case 0:
		return AXP20X_GPIO0_CTRL;
	case 1:
		return AXP20X_GPIO1_CTRL;
	case 2:
		return AXP20X_GPIO2_CTRL;
	}

	return -EINVAL;
}

static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
{
	return pinctrl_gpio_direction_input(chip->base + offset);
}

static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int ret;

	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
	if (ret)
		return ret;

	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
}

static int axp20x_gpio_get_direction(struct gpio_chip *chip,
				     unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int reg, ret;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	ret = regmap_read(pctl->regmap, reg, &val);
	if (ret)
		return ret;

	/*
	 * This shouldn't really happen if the pin is in use already,
	 * or if it's not in use yet, it doesn't matter since we're
	 * going to change the value soon anyway. Default to output.
	 */
	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
		return 0;

	/*
	 * The GPIO directions are the three lowest values.
	 * 2 is input, 0 and 1 are output
	 */
	return val & 2;
}

static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
			      int value)
{
	chip->set(chip, offset, value);

	return 0;
}

static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
			    int value)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return;

	regmap_update_bits(pctl->regmap, reg,
			   AXP20X_GPIO_FUNCTIONS,
			   value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
			   AXP20X_GPIO_FUNCTION_OUT_LOW);
}

static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
			  u8 config)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
				  config);
}

static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return ARRAY_SIZE(pctl->funcs);
}

static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
					unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->funcs[selector].name;
}

static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
				  unsigned int selector,
				  const char * const **groups,
				  unsigned int *num_groups)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*groups = pctl->funcs[selector].groups;
	*num_groups = pctl->funcs[selector].ngroups;

	return 0;
}

static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
			      unsigned int function, unsigned int group)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	unsigned int mask;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	if (function <= AXP20X_FUNC_GPIO_IN)
		return axp20x_pmx_set(pctldev, group,
				      pctl->funcs[function].muxval);

	if (function == AXP20X_FUNC_LDO)
		mask = pctl->desc->ldo_mask;
	else
		mask = pctl->desc->adc_mask;

	if (!(BIT(group) & mask))
		return -EINVAL;

	/*
	 * We let the regulator framework handle the LDO muxing as muxing bits
	 * are basically also regulators on/off bits. It's better not to enforce
	 * any state of the regulator when selecting LDO mux so that we don't
	 * interfere with the regulator driver.
	 */
	if (function == AXP20X_FUNC_LDO)
		return 0;

	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
}

static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
					 struct pinctrl_gpio_range *range,
					 unsigned int offset, bool input)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	if (input)
		return axp20x_pmx_set(pctldev, offset,
				      pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);

	return axp20x_pmx_set(pctldev, offset,
			      pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
}

static const struct pinmux_ops axp20x_pmx_ops = {
	.get_functions_count	= axp20x_pmx_func_cnt,
	.get_function_name	= axp20x_pmx_func_name,
	.get_function_groups	= axp20x_pmx_func_groups,
	.set_mux		= axp20x_pmx_set_mux,
	.gpio_set_direction	= axp20x_pmx_gpio_set_direction,
	.strict			= true,
};

static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->npins;
}

static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
			     const unsigned int **pins, unsigned int *num_pins)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*pins = (unsigned int *)&pctl->desc->pins[selector];
	*num_pins = 1;

	return 0;
}

static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
				     unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->pins[selector].name;
}

static const struct pinctrl_ops axp20x_pctrl_ops = {
	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
	.dt_free_map		= pinconf_generic_dt_free_map,
	.get_groups_count	= axp20x_groups_cnt,
	.get_group_name		= axp20x_group_name,
	.get_group_pins		= axp20x_group_pins,
};

static void axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
					  unsigned int mask_len,
					  struct axp20x_pinctrl_function *func,
					  const struct pinctrl_pin_desc *pins)
{
	unsigned long int mask_cpy = mask;
	const char **group;
	unsigned int ngroups = hweight8(mask);
	int bit;

	func->ngroups = ngroups;
	if (func->ngroups > 0) {
		func->groups = devm_kzalloc(dev, ngroups * sizeof(const char *),
					    GFP_KERNEL);
		group = func->groups;
		for_each_set_bit(bit, &mask_cpy, mask_len) {
			*group = pins[bit].name;
			group++;
		}
	}
}

static void axp20x_build_funcs_groups(struct platform_device *pdev)
{
	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
	int i, pin, npins = pctl->desc->npins;

	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
	/*
	 * Muxval for LDO is useless as we won't use it.
	 * See comment in axp20x_pmx_set_mux.
	 */
	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
	pctl->funcs[AXP20X_FUNC_ADC].muxval = AXP20X_MUX_ADC;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
		pctl->funcs[i].ngroups = npins;
		pctl->funcs[i].groups = devm_kzalloc(&pdev->dev,
						     npins * sizeof(char *),
						     GFP_KERNEL);
		for (pin = 0; pin < npins; pin++)
			pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
	}

	axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_LDO],
				      pctl->desc->pins);

	axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_ADC],
				      pctl->desc->pins);
}

static int axp20x_pctl_probe(struct platform_device *pdev)
{
	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
	struct axp20x_pctl *pctl;
	struct pinctrl_desc *pctrl_desc;
	int ret;

	if (!of_device_is_available(pdev->dev.of_node))
		return -ENODEV;

	if (!axp20x) {
		dev_err(&pdev->dev, "Parent drvdata not set\n");
		return -EINVAL;
	}

	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
	if (!pctl)
		return -ENOMEM;

	pctl->chip.base			= -1;
	pctl->chip.can_sleep		= true;
	pctl->chip.request		= gpiochip_generic_request;
	pctl->chip.free			= gpiochip_generic_free;
	pctl->chip.parent		= &pdev->dev;
	pctl->chip.label		= dev_name(&pdev->dev);
	pctl->chip.owner		= THIS_MODULE;
	pctl->chip.get			= axp20x_gpio_get;
	pctl->chip.get_direction	= axp20x_gpio_get_direction;
	pctl->chip.set			= axp20x_gpio_set;
	pctl->chip.direction_input	= axp20x_gpio_input;
	pctl->chip.direction_output	= axp20x_gpio_output;
	pctl->chip.ngpio		= 3;

	pctl->desc = &axp20x_data;
	pctl->regmap = axp20x->regmap;
	pctl->dev = &pdev->dev;

	platform_set_drvdata(pdev, pctl);

	axp20x_build_funcs_groups(pdev);

	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	if (!pctrl_desc)
		return -ENOMEM;

	pctrl_desc->name = dev_name(&pdev->dev);
	pctrl_desc->owner = THIS_MODULE;
	pctrl_desc->pins = pctl->desc->pins;
	pctrl_desc->npins = pctl->desc->npins;
	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	pctrl_desc->pmxops = &axp20x_pmx_ops;

	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
	if (IS_ERR(pctl->pctl_dev)) {
		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
		return PTR_ERR(pctl->pctl_dev);
	}

	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register GPIO chip\n");
		return ret;
	}

	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
				     pctl->desc->pins->number,
				     pctl->desc->pins->number,
				     pctl->desc->npins);
	if (ret) {
		dev_err(&pdev->dev, "failed to add pin range\n");
		return ret;
	}

	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");

	return 0;
}

static const struct of_device_id axp20x_pctl_match[] = {
	{ .compatible = "x-powers,axp209-gpio" },
	{ }
};
MODULE_DEVICE_TABLE(of, axp20x_pctl_match);

static struct platform_driver axp20x_pctl_driver = {
	.probe		= axp20x_pctl_probe,
	.driver = {
		.name		= "axp20x-gpio",
		.of_match_table	= axp20x_pctl_match,
	},
};

module_platform_driver(axp20x_pctl_driver);

MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
f72f4b44	1	/*
23f75d7d	2	* AXP20x pinctrl and GPIO driver
f72f4b44 MR	3	*
f72f4b44 MR	4	* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
23f75d7d	5	* Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
f72f4b44 MR	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
	13	#include <linux/bitops.h>
	14	#include <linux/device.h>
	15	#include <linux/gpio/driver.h>
	16	#include <linux/init.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/kernel.h>
	19	#include <linux/mfd/axp20x.h>
	20	#include <linux/module.h>
	21	#include <linux/of.h>
23f75d7d QS	22	#include <linux/pinctrl/pinconf-generic.h>
	23	#include <linux/pinctrl/pinctrl.h>
	24	#include <linux/pinctrl/pinmux.h>
f72f4b44 MR	25	#include <linux/platform_device.h>
	26	#include <linux/regmap.h>
	27	#include <linux/slab.h>
	28
	29	#define AXP20X_GPIO_FUNCTIONS 0x7
	30	#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
	31	#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
	32	#define AXP20X_GPIO_FUNCTION_INPUT 2
	33
23f75d7d QS	34	#define AXP20X_FUNC_GPIO_OUT 0
	35	#define AXP20X_FUNC_GPIO_IN 1
	36	#define AXP20X_FUNC_LDO 2
	37	#define AXP20X_FUNC_ADC 3
	38	#define AXP20X_FUNCS_NB 4
	39
	40	#define AXP20X_MUX_GPIO_OUT 0
	41	#define AXP20X_MUX_GPIO_IN BIT(1)
	42	#define AXP20X_MUX_ADC BIT(2)
	43
	44	struct axp20x_pctrl_desc {
	45	const struct pinctrl_pin_desc *pins;
	46	unsigned int npins;
	47	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	48	u8 ldo_mask;
	49	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	50	u8 adc_mask;
48e706fb	51	u8 gpio_status_offset;
23f75d7d QS	52	};
	53
	54	struct axp20x_pinctrl_function {
	55	const char *name;
	56	unsigned int muxval;
	57	const char **groups;
	58	unsigned int ngroups;
	59	};
	60
d242e60c	61	struct axp20x_pctl {
f72f4b44 MR	62	struct gpio_chip chip;
f72f4b44 MR	63	struct regmap *regmap;
23f75d7d QS	64	struct pinctrl_dev *pctl_dev;
	65	struct device *dev;
	66	const struct axp20x_pctrl_desc *desc;
	67	struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
	68	};
	69
	70	static const struct pinctrl_pin_desc axp209_pins[] = {
	71	PINCTRL_PIN(0, "GPIO0"),
	72	PINCTRL_PIN(1, "GPIO1"),
	73	PINCTRL_PIN(2, "GPIO2"),
	74	};
	75
	76	static const struct axp20x_pctrl_desc axp20x_data = {
	77	.pins = axp209_pins,
	78	.npins = ARRAY_SIZE(axp209_pins),
	79	.ldo_mask = BIT(0) \| BIT(1),
	80	.adc_mask = BIT(0) \| BIT(1),
48e706fb	81	.gpio_status_offset = 4,
f72f4b44 MR	82	};
f72f4b44 MR	83
3cac991e	84	static int axp20x_gpio_get_reg(unsigned int offset)
f72f4b44 MR	85	{
	86	switch (offset) {
	87	case 0:
	88	return AXP20X_GPIO0_CTRL;
	89	case 1:
	90	return AXP20X_GPIO1_CTRL;
	91	case 2:
	92	return AXP20X_GPIO2_CTRL;
	93	}
	94
	95	return -EINVAL;
	96	}
	97
3cac991e	98	static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
f72f4b44	99	{
23f75d7d	100	return pinctrl_gpio_direction_input(chip->base + offset);
f72f4b44 MR	101	}
f72f4b44 MR	102
3cac991e	103	static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
f72f4b44	104	{
d242e60c	105	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44	106	unsigned int val;
1d2b2ac0	107	int ret;
f72f4b44	108
d242e60c	109	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
f72f4b44 MR	110	if (ret)
	111	return ret;
	112
48e706fb	113	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
f72f4b44 MR	114	}
f72f4b44 MR	115
3cac991e QS	116	static int axp20x_gpio_get_direction(struct gpio_chip *chip,
3cac991e QS	117	unsigned int offset)
81d3753d	118	{
d242e60c	119	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
81d3753d MR	120	unsigned int val;
	121	int reg, ret;
	122
	123	reg = axp20x_gpio_get_reg(offset);
	124	if (reg < 0)
	125	return reg;
	126
d242e60c	127	ret = regmap_read(pctl->regmap, reg, &val);
81d3753d MR	128	if (ret)
	129	return ret;
	130
	131	/*
	132	* This shouldn't really happen if the pin is in use already,
	133	* or if it's not in use yet, it doesn't matter since we're
	134	* going to change the value soon anyway. Default to output.
	135	*/
	136	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
	137	return 0;
	138
	139	/*
	140	* The GPIO directions are the three lowest values.
	141	* 2 is input, 0 and 1 are output
	142	*/
	143	return val & 2;
	144	}
	145
3cac991e	146	static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
f72f4b44	147	int value)
23f75d7d QS	148	{
	149	chip->set(chip, offset, value);
	150
	151	return 0;
	152	}
	153
	154	static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
	155	int value)
f72f4b44	156	{
d242e60c	157	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44 MR	158	int reg;
f72f4b44 MR	159
23f75d7d QS	160	reg = axp20x_gpio_get_reg(offset);
	161	if (reg < 0)
	162	return;
	163
d242e60c	164	regmap_update_bits(pctl->regmap, reg,
23f75d7d QS	165	AXP20X_GPIO_FUNCTIONS,
	166	value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
	167	AXP20X_GPIO_FUNCTION_OUT_LOW);
	168	}
	169
	170	static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
	171	u8 config)
	172	{
d242e60c	173	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	174	int reg;
23f75d7d QS	175
f72f4b44 MR	176	reg = axp20x_gpio_get_reg(offset);
	177	if (reg < 0)
	178	return reg;
	179
d242e60c	180	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
23f75d7d	181	config);
f72f4b44 MR	182	}
f72f4b44 MR	183
23f75d7d QS	184	static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
23f75d7d QS	185	{
d242e60c	186	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	187
d242e60c	188	return ARRAY_SIZE(pctl->funcs);
23f75d7d QS	189	}
	190
	191	static const char axp20x_pmx_func_name(struct pinctrl_dev pctldev,
	192	unsigned int selector)
	193	{
d242e60c	194	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	195
d242e60c	196	return pctl->funcs[selector].name;
23f75d7d QS	197	}
	198
	199	static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
	200	unsigned int selector,
	201	const char * const **groups,
	202	unsigned int *num_groups)
	203	{
d242e60c	204	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	205
d242e60c QS	206	*groups = pctl->funcs[selector].groups;
d242e60c QS	207	*num_groups = pctl->funcs[selector].ngroups;
23f75d7d QS	208
	209	return 0;
	210	}
	211
	212	static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
	213	unsigned int function, unsigned int group)
	214	{
d242e60c	215	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	216	unsigned int mask;
	217
	218	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	219	if (function <= AXP20X_FUNC_GPIO_IN)
	220	return axp20x_pmx_set(pctldev, group,
d242e60c	221	pctl->funcs[function].muxval);
23f75d7d QS	222
23f75d7d QS	223	if (function == AXP20X_FUNC_LDO)
d242e60c	224	mask = pctl->desc->ldo_mask;
23f75d7d	225	else
d242e60c	226	mask = pctl->desc->adc_mask;
23f75d7d QS	227
	228	if (!(BIT(group) & mask))
	229	return -EINVAL;
	230
	231	/*
	232	* We let the regulator framework handle the LDO muxing as muxing bits
	233	* are basically also regulators on/off bits. It's better not to enforce
	234	* any state of the regulator when selecting LDO mux so that we don't
	235	* interfere with the regulator driver.
	236	*/
	237	if (function == AXP20X_FUNC_LDO)
	238	return 0;
	239
d242e60c	240	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
23f75d7d QS	241	}
	242
	243	static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
	244	struct pinctrl_gpio_range *range,
	245	unsigned int offset, bool input)
	246	{
d242e60c	247	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	248
	249	if (input)
	250	return axp20x_pmx_set(pctldev, offset,
d242e60c	251	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
23f75d7d QS	252
23f75d7d QS	253	return axp20x_pmx_set(pctldev, offset,
d242e60c	254	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
23f75d7d QS	255	}
	256
	257	static const struct pinmux_ops axp20x_pmx_ops = {
	258	.get_functions_count = axp20x_pmx_func_cnt,
	259	.get_function_name = axp20x_pmx_func_name,
	260	.get_function_groups = axp20x_pmx_func_groups,
	261	.set_mux = axp20x_pmx_set_mux,
	262	.gpio_set_direction = axp20x_pmx_gpio_set_direction,
	263	.strict = true,
	264	};
	265
	266	static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
	267	{
d242e60c	268	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	269
d242e60c	270	return pctl->desc->npins;
23f75d7d QS	271	}
	272
	273	static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
	274	const unsigned int *pins, unsigned int num_pins)
	275	{
d242e60c	276	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	277
d242e60c	278	pins = (unsigned int )&pctl->desc->pins[selector];
23f75d7d QS	279	*num_pins = 1;
	280
	281	return 0;
	282	}
	283
	284	static const char axp20x_group_name(struct pinctrl_dev pctldev,
	285	unsigned int selector)
f72f4b44	286	{
d242e60c	287	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	288
d242e60c	289	return pctl->desc->pins[selector].name;
23f75d7d QS	290	}
	291
	292	static const struct pinctrl_ops axp20x_pctrl_ops = {
	293	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
	294	.dt_free_map = pinconf_generic_dt_free_map,
	295	.get_groups_count = axp20x_groups_cnt,
	296	.get_group_name = axp20x_group_name,
	297	.get_group_pins = axp20x_group_pins,
	298	};
	299
	300	static void axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
	301	unsigned int mask_len,
	302	struct axp20x_pinctrl_function *func,
	303	const struct pinctrl_pin_desc *pins)
	304	{
	305	unsigned long int mask_cpy = mask;
	306	const char **group;
	307	unsigned int ngroups = hweight8(mask);
	308	int bit;
	309
	310	func->ngroups = ngroups;
	311	if (func->ngroups > 0) {
	312	func->groups = devm_kzalloc(dev, ngroups * sizeof(const char *),
	313	GFP_KERNEL);
	314	group = func->groups;
	315	for_each_set_bit(bit, &mask_cpy, mask_len) {
	316	*group = pins[bit].name;
	317	group++;
	318	}
	319	}
	320	}
	321
	322	static void axp20x_build_funcs_groups(struct platform_device *pdev)
	323	{
d242e60c QS	324	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
	325	int i, pin, npins = pctl->desc->npins;
	326
	327	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	328	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	329	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	330	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	331	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
23f75d7d QS	332	/*
	333	* Muxval for LDO is useless as we won't use it.
	334	* See comment in axp20x_pmx_set_mux.
	335	*/
d242e60c QS	336	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
d242e60c QS	337	pctl->funcs[AXP20X_FUNC_ADC].muxval = AXP20X_MUX_ADC;
23f75d7d QS	338
	339	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	340	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
d242e60c QS	341	pctl->funcs[i].ngroups = npins;
d242e60c QS	342	pctl->funcs[i].groups = devm_kzalloc(&pdev->dev,
23f75d7d QS	343	npins * sizeof(char *),
	344	GFP_KERNEL);
	345	for (pin = 0; pin < npins; pin++)
d242e60c	346	pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
23f75d7d QS	347	}
23f75d7d QS	348
d242e60c QS	349	axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
	350	npins, &pctl->funcs[AXP20X_FUNC_LDO],
	351	pctl->desc->pins);
23f75d7d	352
d242e60c QS	353	axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
	354	npins, &pctl->funcs[AXP20X_FUNC_ADC],
	355	pctl->desc->pins);
f72f4b44 MR	356	}
f72f4b44 MR	357
d242e60c	358	static int axp20x_pctl_probe(struct platform_device *pdev)
f72f4b44 MR	359	{
f72f4b44 MR	360	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
d242e60c	361	struct axp20x_pctl *pctl;
23f75d7d	362	struct pinctrl_desc *pctrl_desc;
f72f4b44 MR	363	int ret;
	364
	365	if (!of_device_is_available(pdev->dev.of_node))
	366	return -ENODEV;
	367
	368	if (!axp20x) {
	369	dev_err(&pdev->dev, "Parent drvdata not set\n");
	370	return -EINVAL;
	371	}
	372
d242e60c QS	373	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
d242e60c QS	374	if (!pctl)
f72f4b44 MR	375	return -ENOMEM;
f72f4b44 MR	376
d242e60c QS	377	pctl->chip.base = -1;
	378	pctl->chip.can_sleep = true;
	379	pctl->chip.request = gpiochip_generic_request;
	380	pctl->chip.free = gpiochip_generic_free;
	381	pctl->chip.parent = &pdev->dev;
	382	pctl->chip.label = dev_name(&pdev->dev);
	383	pctl->chip.owner = THIS_MODULE;
	384	pctl->chip.get = axp20x_gpio_get;
	385	pctl->chip.get_direction = axp20x_gpio_get_direction;
	386	pctl->chip.set = axp20x_gpio_set;
	387	pctl->chip.direction_input = axp20x_gpio_input;
	388	pctl->chip.direction_output = axp20x_gpio_output;
	389	pctl->chip.ngpio = 3;
	390
	391	pctl->desc = &axp20x_data;
	392	pctl->regmap = axp20x->regmap;
	393	pctl->dev = &pdev->dev;
	394
	395	platform_set_drvdata(pdev, pctl);
23f75d7d QS	396
	397	axp20x_build_funcs_groups(pdev);
	398
	399	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	400	if (!pctrl_desc)
	401	return -ENOMEM;
	402
	403	pctrl_desc->name = dev_name(&pdev->dev);
	404	pctrl_desc->owner = THIS_MODULE;
d242e60c QS	405	pctrl_desc->pins = pctl->desc->pins;
d242e60c QS	406	pctrl_desc->npins = pctl->desc->npins;
23f75d7d QS	407	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	408	pctrl_desc->pmxops = &axp20x_pmx_ops;
	409
d242e60c QS	410	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
d242e60c QS	411	if (IS_ERR(pctl->pctl_dev)) {
23f75d7d	412	dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
d242e60c	413	return PTR_ERR(pctl->pctl_dev);
23f75d7d	414	}
f72f4b44	415
d242e60c	416	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
f72f4b44 MR	417	if (ret) {
	418	dev_err(&pdev->dev, "Failed to register GPIO chip\n");
	419	return ret;
	420	}
	421
d242e60c QS	422	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
	423	pctl->desc->pins->number,
	424	pctl->desc->pins->number,
	425	pctl->desc->npins);
23f75d7d QS	426	if (ret) {
	427	dev_err(&pdev->dev, "failed to add pin range\n");
	428	return ret;
	429	}
	430
	431	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
f72f4b44 MR	432
	433	return 0;
	434	}
	435
d242e60c	436	static const struct of_device_id axp20x_pctl_match[] = {
f72f4b44 MR	437	{ .compatible = "x-powers,axp209-gpio" },
	438	{ }
	439	};
d242e60c	440	MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
f72f4b44	441
d242e60c QS	442	static struct platform_driver axp20x_pctl_driver = {
d242e60c QS	443	.probe = axp20x_pctl_probe,
f72f4b44 MR	444	.driver = {
f72f4b44 MR	445	.name = "axp20x-gpio",
d242e60c	446	.of_match_table = axp20x_pctl_match,
f72f4b44 MR	447	},
	448	};
	449
d242e60c	450	module_platform_driver(axp20x_pctl_driver);
f72f4b44 MR	451
f72f4b44 MR	452	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
23f75d7d QS	453	MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
23f75d7d QS	454	MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
f72f4b44	455	MODULE_LICENSE("GPL");