[linux-2.6-block.git] / drivers / pinctrl / pinctrl-axp209.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * AXP20x pinctrl and GPIO driver
 *
 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
 */

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/axp20x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

#define AXP20X_GPIO_FUNCTIONS		0x7
#define AXP20X_GPIO_FUNCTION_OUT_LOW	0
#define AXP20X_GPIO_FUNCTION_OUT_HIGH	1
#define AXP20X_GPIO_FUNCTION_INPUT	2

#define AXP20X_GPIO3_FUNCTIONS		GENMASK(2, 1)
#define AXP20X_GPIO3_FUNCTION_OUT_LOW	0
#define AXP20X_GPIO3_FUNCTION_OUT_HIGH	2
#define AXP20X_GPIO3_FUNCTION_INPUT	4

#define AXP20X_FUNC_GPIO_OUT		0
#define AXP20X_FUNC_GPIO_IN		1
#define AXP20X_FUNC_LDO			2
#define AXP20X_FUNC_ADC			3
#define AXP20X_FUNCS_NB			4

#define AXP20X_MUX_GPIO_OUT		0
#define AXP20X_MUX_GPIO_IN		BIT(1)
#define AXP20X_MUX_ADC			BIT(2)

#define AXP813_MUX_ADC			(BIT(2) | BIT(0))

struct axp20x_pctrl_desc {
	const struct pinctrl_pin_desc	*pins;
	unsigned int			npins;
	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	u8				ldo_mask;
	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	u8				adc_mask;
	u8				gpio_status_offset;
	u8				adc_mux;
};

struct axp20x_pinctrl_function {
	const char	*name;
	unsigned int	muxval;
	const char	**groups;
	unsigned int	ngroups;
};

struct axp20x_pctl {
	struct gpio_chip	chip;
	struct regmap		*regmap;
	struct pinctrl_dev			*pctl_dev;
	struct device				*dev;
	const struct axp20x_pctrl_desc		*desc;
	struct axp20x_pinctrl_function		funcs[AXP20X_FUNCS_NB];
};

static const struct pinctrl_pin_desc axp209_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
	PINCTRL_PIN(2, "GPIO2"),
	PINCTRL_PIN(3, "GPIO3"),
};

static const struct pinctrl_pin_desc axp22x_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
};

static const struct axp20x_pctrl_desc axp20x_data = {
	.pins	= axp209_pins,
	.npins	= ARRAY_SIZE(axp209_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0) | BIT(1),
	.gpio_status_offset = 4,
	.adc_mux = AXP20X_MUX_ADC,
};

static const struct axp20x_pctrl_desc axp22x_data = {
	.pins	= axp22x_pins,
	.npins	= ARRAY_SIZE(axp22x_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.gpio_status_offset = 0,
};

static const struct axp20x_pctrl_desc axp813_data = {
	.pins	= axp22x_pins,
	.npins	= ARRAY_SIZE(axp22x_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0),
	.gpio_status_offset = 0,
	.adc_mux = AXP813_MUX_ADC,
};

static int axp20x_gpio_get_reg(unsigned int offset)
{
	switch (offset) {
	case 0:
		return AXP20X_GPIO0_CTRL;
	case 1:
		return AXP20X_GPIO1_CTRL;
	case 2:
		return AXP20X_GPIO2_CTRL;
	}

	return -EINVAL;
}

static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
{
	return pinctrl_gpio_direction_input(chip->base + offset);
}

static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int ret;

	/* AXP209 has GPIO3 status sharing the settings register */
	if (offset == 3) {
		ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
		if (ret)
			return ret;
		return !!(val & BIT(0));
	}

	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
	if (ret)
		return ret;

	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
}

static int axp20x_gpio_get_direction(struct gpio_chip *chip,
				     unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int reg, ret;

	/* AXP209 GPIO3 settings have a different layout */
	if (offset == 3) {
		ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
		if (ret)
			return ret;
		if (val & AXP20X_GPIO3_FUNCTION_INPUT)
			return GPIO_LINE_DIRECTION_IN;

		return GPIO_LINE_DIRECTION_OUT;
	}

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	ret = regmap_read(pctl->regmap, reg, &val);
	if (ret)
		return ret;

	/*
	 * This shouldn't really happen if the pin is in use already,
	 * or if it's not in use yet, it doesn't matter since we're
	 * going to change the value soon anyway. Default to output.
	 */
	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
		return GPIO_LINE_DIRECTION_OUT;

	/*
	 * The GPIO directions are the three lowest values.
	 * 2 is input, 0 and 1 are output
	 */
	if (val & 2)
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
			      int value)
{
	chip->set(chip, offset, value);

	return 0;
}

static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
			    int value)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	int reg;

	/* AXP209 has GPIO3 status sharing the settings register */
	if (offset == 3) {
		regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
				   AXP20X_GPIO3_FUNCTIONS,
				   value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
				   AXP20X_GPIO3_FUNCTION_OUT_LOW);
		return;
	}

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return;

	regmap_update_bits(pctl->regmap, reg,
			   AXP20X_GPIO_FUNCTIONS,
			   value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
			   AXP20X_GPIO_FUNCTION_OUT_LOW);
}

static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
			  u8 config)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	int reg;

	/* AXP209 GPIO3 settings have a different layout */
	if (offset == 3) {
		return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
				   AXP20X_GPIO3_FUNCTIONS,
				   config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
				   AXP20X_GPIO3_FUNCTION_INPUT);
	}

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
				  config);
}

static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return ARRAY_SIZE(pctl->funcs);
}

static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
					unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->funcs[selector].name;
}

static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
				  unsigned int selector,
				  const char * const **groups,
				  unsigned int *num_groups)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*groups = pctl->funcs[selector].groups;
	*num_groups = pctl->funcs[selector].ngroups;

	return 0;
}

static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
			      unsigned int function, unsigned int group)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	unsigned int mask;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	if (function <= AXP20X_FUNC_GPIO_IN)
		return axp20x_pmx_set(pctldev, group,
				      pctl->funcs[function].muxval);

	if (function == AXP20X_FUNC_LDO)
		mask = pctl->desc->ldo_mask;
	else
		mask = pctl->desc->adc_mask;

	if (!(BIT(group) & mask))
		return -EINVAL;

	/*
	 * We let the regulator framework handle the LDO muxing as muxing bits
	 * are basically also regulators on/off bits. It's better not to enforce
	 * any state of the regulator when selecting LDO mux so that we don't
	 * interfere with the regulator driver.
	 */
	if (function == AXP20X_FUNC_LDO)
		return 0;

	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
}

static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
					 struct pinctrl_gpio_range *range,
					 unsigned int offset, bool input)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	if (input)
		return axp20x_pmx_set(pctldev, offset,
				      pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);

	return axp20x_pmx_set(pctldev, offset,
			      pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
}

static const struct pinmux_ops axp20x_pmx_ops = {
	.get_functions_count	= axp20x_pmx_func_cnt,
	.get_function_name	= axp20x_pmx_func_name,
	.get_function_groups	= axp20x_pmx_func_groups,
	.set_mux		= axp20x_pmx_set_mux,
	.gpio_set_direction	= axp20x_pmx_gpio_set_direction,
	.strict			= true,
};

static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->npins;
}

static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
			     const unsigned int **pins, unsigned int *num_pins)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*pins = (unsigned int *)&pctl->desc->pins[selector];
	*num_pins = 1;

	return 0;
}

static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
				     unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->pins[selector].name;
}

static const struct pinctrl_ops axp20x_pctrl_ops = {
	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
	.dt_free_map		= pinconf_generic_dt_free_map,
	.get_groups_count	= axp20x_groups_cnt,
	.get_group_name		= axp20x_group_name,
	.get_group_pins		= axp20x_group_pins,
};

static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
					  unsigned int mask_len,
					  struct axp20x_pinctrl_function *func,
					  const struct pinctrl_pin_desc *pins)
{
	unsigned long int mask_cpy = mask;
	const char **group;
	unsigned int ngroups = hweight8(mask);
	int bit;

	func->ngroups = ngroups;
	if (func->ngroups > 0) {
		func->groups = devm_kcalloc(dev,
					    ngroups, sizeof(const char *),
					    GFP_KERNEL);
		if (!func->groups)
			return -ENOMEM;
		group = func->groups;
		for_each_set_bit(bit, &mask_cpy, mask_len) {
			*group = pins[bit].name;
			group++;
		}
	}

	return 0;
}

static int axp20x_build_funcs_groups(struct platform_device *pdev)
{
	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
	int i, ret, pin, npins = pctl->desc->npins;

	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
	/*
	 * Muxval for LDO is useless as we won't use it.
	 * See comment in axp20x_pmx_set_mux.
	 */
	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
		pctl->funcs[i].ngroups = npins;
		pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
						     npins, sizeof(char *),
						     GFP_KERNEL);
		if (!pctl->funcs[i].groups)
			return -ENOMEM;
		for (pin = 0; pin < npins; pin++)
			pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
	}

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_LDO],
				      pctl->desc->pins);
	if (ret)
		return ret;

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_ADC],
				      pctl->desc->pins);
	if (ret)
		return ret;

	return 0;
}

static const struct of_device_id axp20x_pctl_match[] = {
	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
	{ .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	{ }
};
MODULE_DEVICE_TABLE(of, axp20x_pctl_match);

static int axp20x_pctl_probe(struct platform_device *pdev)
{
	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
	struct axp20x_pctl *pctl;
	struct device *dev = &pdev->dev;
	struct pinctrl_desc *pctrl_desc;
	int ret;

	if (!of_device_is_available(pdev->dev.of_node))
		return -ENODEV;

	if (!axp20x) {
		dev_err(&pdev->dev, "Parent drvdata not set\n");
		return -EINVAL;
	}

	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
	if (!pctl)
		return -ENOMEM;

	pctl->chip.base			= -1;
	pctl->chip.can_sleep		= true;
	pctl->chip.request		= gpiochip_generic_request;
	pctl->chip.free			= gpiochip_generic_free;
	pctl->chip.parent		= &pdev->dev;
	pctl->chip.label		= dev_name(&pdev->dev);
	pctl->chip.owner		= THIS_MODULE;
	pctl->chip.get			= axp20x_gpio_get;
	pctl->chip.get_direction	= axp20x_gpio_get_direction;
	pctl->chip.set			= axp20x_gpio_set;
	pctl->chip.direction_input	= axp20x_gpio_input;
	pctl->chip.direction_output	= axp20x_gpio_output;

	pctl->desc = of_device_get_match_data(dev);

	pctl->chip.ngpio		= pctl->desc->npins;

	pctl->regmap = axp20x->regmap;
	pctl->dev = &pdev->dev;

	platform_set_drvdata(pdev, pctl);

	ret = axp20x_build_funcs_groups(pdev);
	if (ret) {
		dev_err(&pdev->dev, "failed to build groups\n");
		return ret;
	}

	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	if (!pctrl_desc)
		return -ENOMEM;

	pctrl_desc->name = dev_name(&pdev->dev);
	pctrl_desc->owner = THIS_MODULE;
	pctrl_desc->pins = pctl->desc->pins;
	pctrl_desc->npins = pctl->desc->npins;
	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	pctrl_desc->pmxops = &axp20x_pmx_ops;

	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
	if (IS_ERR(pctl->pctl_dev)) {
		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
		return PTR_ERR(pctl->pctl_dev);
	}

	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register GPIO chip\n");
		return ret;
	}

	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
				     pctl->desc->pins->number,
				     pctl->desc->pins->number,
				     pctl->desc->npins);
	if (ret) {
		dev_err(&pdev->dev, "failed to add pin range\n");
		return ret;
	}

	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");

	return 0;
}

static struct platform_driver axp20x_pctl_driver = {
	.probe		= axp20x_pctl_probe,
	.driver = {
		.name		= "axp20x-gpio",
		.of_match_table	= axp20x_pctl_match,
	},
};

module_platform_driver(axp20x_pctl_driver);

MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
f72f4b44	2	/*
23f75d7d	3	* AXP20x pinctrl and GPIO driver
f72f4b44 MR	4	*
f72f4b44 MR	5	* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
23f75d7d	6	* Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
f72f4b44 MR	7	*/
	8
	9	#include <linux/bitops.h>
	10	#include <linux/device.h>
	11	#include <linux/gpio/driver.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel.h>
	15	#include <linux/mfd/axp20x.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/regmap.h>
	20	#include <linux/slab.h>
	21
20ce9552 AS	22	#include <linux/pinctrl/consumer.h>
	23	#include <linux/pinctrl/pinconf-generic.h>
	24	#include <linux/pinctrl/pinctrl.h>
	25	#include <linux/pinctrl/pinmux.h>
	26
f72f4b44 MR	27	#define AXP20X_GPIO_FUNCTIONS 0x7
	28	#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
	29	#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
	30	#define AXP20X_GPIO_FUNCTION_INPUT 2
	31
44825e5e JM	32	#define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)
	33	#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
	34	#define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2
	35	#define AXP20X_GPIO3_FUNCTION_INPUT 4
	36
23f75d7d QS	37	#define AXP20X_FUNC_GPIO_OUT 0
	38	#define AXP20X_FUNC_GPIO_IN 1
	39	#define AXP20X_FUNC_LDO 2
	40	#define AXP20X_FUNC_ADC 3
	41	#define AXP20X_FUNCS_NB 4
	42
	43	#define AXP20X_MUX_GPIO_OUT 0
	44	#define AXP20X_MUX_GPIO_IN BIT(1)
	45	#define AXP20X_MUX_ADC BIT(2)
	46
e1190083 QS	47	#define AXP813_MUX_ADC (BIT(2) \| BIT(0))
e1190083 QS	48
23f75d7d QS	49	struct axp20x_pctrl_desc {
	50	const struct pinctrl_pin_desc *pins;
	51	unsigned int npins;
	52	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	53	u8 ldo_mask;
	54	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	55	u8 adc_mask;
48e706fb	56	u8 gpio_status_offset;
a0a4b4c2	57	u8 adc_mux;
23f75d7d QS	58	};
	59
	60	struct axp20x_pinctrl_function {
	61	const char *name;
	62	unsigned int muxval;
	63	const char **groups;
	64	unsigned int ngroups;
	65	};
	66
d242e60c	67	struct axp20x_pctl {
f72f4b44 MR	68	struct gpio_chip chip;
f72f4b44 MR	69	struct regmap *regmap;
23f75d7d QS	70	struct pinctrl_dev *pctl_dev;
	71	struct device *dev;
	72	const struct axp20x_pctrl_desc *desc;
	73	struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
	74	};
	75
	76	static const struct pinctrl_pin_desc axp209_pins[] = {
	77	PINCTRL_PIN(0, "GPIO0"),
	78	PINCTRL_PIN(1, "GPIO1"),
	79	PINCTRL_PIN(2, "GPIO2"),
44825e5e	80	PINCTRL_PIN(3, "GPIO3"),
23f75d7d QS	81	};
23f75d7d QS	82
d4c0b614	83	static const struct pinctrl_pin_desc axp22x_pins[] = {
e1190083 QS	84	PINCTRL_PIN(0, "GPIO0"),
	85	PINCTRL_PIN(1, "GPIO1"),
	86	};
	87
23f75d7d QS	88	static const struct axp20x_pctrl_desc axp20x_data = {
	89	.pins = axp209_pins,
	90	.npins = ARRAY_SIZE(axp209_pins),
	91	.ldo_mask = BIT(0) \| BIT(1),
	92	.adc_mask = BIT(0) \| BIT(1),
48e706fb	93	.gpio_status_offset = 4,
a0a4b4c2	94	.adc_mux = AXP20X_MUX_ADC,
f72f4b44 MR	95	};
f72f4b44 MR	96
d4c0b614 SH	97	static const struct axp20x_pctrl_desc axp22x_data = {
	98	.pins = axp22x_pins,
	99	.npins = ARRAY_SIZE(axp22x_pins),
	100	.ldo_mask = BIT(0) \| BIT(1),
	101	.gpio_status_offset = 0,
	102	};
	103
e1190083	104	static const struct axp20x_pctrl_desc axp813_data = {
d4c0b614 SH	105	.pins = axp22x_pins,
d4c0b614 SH	106	.npins = ARRAY_SIZE(axp22x_pins),
e1190083 QS	107	.ldo_mask = BIT(0) \| BIT(1),
	108	.adc_mask = BIT(0),
	109	.gpio_status_offset = 0,
	110	.adc_mux = AXP813_MUX_ADC,
	111	};
	112
3cac991e	113	static int axp20x_gpio_get_reg(unsigned int offset)
f72f4b44 MR	114	{
	115	switch (offset) {
	116	case 0:
	117	return AXP20X_GPIO0_CTRL;
	118	case 1:
	119	return AXP20X_GPIO1_CTRL;
	120	case 2:
	121	return AXP20X_GPIO2_CTRL;
	122	}
	123
	124	return -EINVAL;
	125	}
	126
3cac991e	127	static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
f72f4b44	128	{
23f75d7d	129	return pinctrl_gpio_direction_input(chip->base + offset);
f72f4b44 MR	130	}
f72f4b44 MR	131
3cac991e	132	static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
f72f4b44	133	{
d242e60c	134	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44	135	unsigned int val;
1d2b2ac0	136	int ret;
f72f4b44	137
44825e5e JM	138	/* AXP209 has GPIO3 status sharing the settings register */
	139	if (offset == 3) {
	140	ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
	141	if (ret)
	142	return ret;
	143	return !!(val & BIT(0));
	144	}
	145
d242e60c	146	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
f72f4b44 MR	147	if (ret)
	148	return ret;
	149
48e706fb	150	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
f72f4b44 MR	151	}
f72f4b44 MR	152
3cac991e QS	153	static int axp20x_gpio_get_direction(struct gpio_chip *chip,
3cac991e QS	154	unsigned int offset)
81d3753d	155	{
d242e60c	156	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
81d3753d MR	157	unsigned int val;
	158	int reg, ret;
	159
44825e5e JM	160	/* AXP209 GPIO3 settings have a different layout */
	161	if (offset == 3) {
	162	ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
	163	if (ret)
	164	return ret;
	165	if (val & AXP20X_GPIO3_FUNCTION_INPUT)
	166	return GPIO_LINE_DIRECTION_IN;
	167
	168	return GPIO_LINE_DIRECTION_OUT;
	169	}
	170
81d3753d MR	171	reg = axp20x_gpio_get_reg(offset);
	172	if (reg < 0)
	173	return reg;
	174
d242e60c	175	ret = regmap_read(pctl->regmap, reg, &val);
81d3753d MR	176	if (ret)
	177	return ret;
	178
	179	/*
	180	* This shouldn't really happen if the pin is in use already,
	181	* or if it's not in use yet, it doesn't matter since we're
	182	* going to change the value soon anyway. Default to output.
	183	*/
	184	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
3c827873	185	return GPIO_LINE_DIRECTION_OUT;
81d3753d MR	186
	187	/*
	188	* The GPIO directions are the three lowest values.
	189	* 2 is input, 0 and 1 are output
	190	*/
3c827873 MV	191	if (val & 2)
	192	return GPIO_LINE_DIRECTION_IN;
	193
	194	return GPIO_LINE_DIRECTION_OUT;
81d3753d MR	195	}
81d3753d MR	196
3cac991e	197	static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
f72f4b44	198	int value)
23f75d7d QS	199	{
	200	chip->set(chip, offset, value);
	201
	202	return 0;
	203	}
	204
	205	static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
	206	int value)
f72f4b44	207	{
d242e60c	208	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44 MR	209	int reg;
f72f4b44 MR	210
44825e5e JM	211	/* AXP209 has GPIO3 status sharing the settings register */
	212	if (offset == 3) {
	213	regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
	214	AXP20X_GPIO3_FUNCTIONS,
	215	value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
	216	AXP20X_GPIO3_FUNCTION_OUT_LOW);
	217	return;
	218	}
	219
23f75d7d QS	220	reg = axp20x_gpio_get_reg(offset);
	221	if (reg < 0)
	222	return;
	223
d242e60c	224	regmap_update_bits(pctl->regmap, reg,
23f75d7d QS	225	AXP20X_GPIO_FUNCTIONS,
	226	value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
	227	AXP20X_GPIO_FUNCTION_OUT_LOW);
	228	}
	229
	230	static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
	231	u8 config)
	232	{
d242e60c	233	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	234	int reg;
23f75d7d QS	235
44825e5e JM	236	/* AXP209 GPIO3 settings have a different layout */
	237	if (offset == 3) {
	238	return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
	239	AXP20X_GPIO3_FUNCTIONS,
	240	config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
	241	AXP20X_GPIO3_FUNCTION_INPUT);
	242	}
	243
f72f4b44 MR	244	reg = axp20x_gpio_get_reg(offset);
	245	if (reg < 0)
	246	return reg;
	247
d242e60c	248	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
23f75d7d	249	config);
f72f4b44 MR	250	}
f72f4b44 MR	251
23f75d7d QS	252	static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
23f75d7d QS	253	{
d242e60c	254	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	255
d242e60c	256	return ARRAY_SIZE(pctl->funcs);
23f75d7d QS	257	}
	258
	259	static const char axp20x_pmx_func_name(struct pinctrl_dev pctldev,
	260	unsigned int selector)
	261	{
d242e60c	262	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	263
d242e60c	264	return pctl->funcs[selector].name;
23f75d7d QS	265	}
	266
	267	static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
	268	unsigned int selector,
	269	const char * const **groups,
	270	unsigned int *num_groups)
	271	{
d242e60c	272	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	273
d242e60c QS	274	*groups = pctl->funcs[selector].groups;
d242e60c QS	275	*num_groups = pctl->funcs[selector].ngroups;
23f75d7d QS	276
	277	return 0;
	278	}
	279
	280	static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
	281	unsigned int function, unsigned int group)
	282	{
d242e60c	283	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	284	unsigned int mask;
	285
	286	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	287	if (function <= AXP20X_FUNC_GPIO_IN)
	288	return axp20x_pmx_set(pctldev, group,
d242e60c	289	pctl->funcs[function].muxval);
23f75d7d QS	290
23f75d7d QS	291	if (function == AXP20X_FUNC_LDO)
d242e60c	292	mask = pctl->desc->ldo_mask;
23f75d7d	293	else
d242e60c	294	mask = pctl->desc->adc_mask;
23f75d7d QS	295
	296	if (!(BIT(group) & mask))
	297	return -EINVAL;
	298
	299	/*
	300	* We let the regulator framework handle the LDO muxing as muxing bits
	301	* are basically also regulators on/off bits. It's better not to enforce
	302	* any state of the regulator when selecting LDO mux so that we don't
	303	* interfere with the regulator driver.
	304	*/
	305	if (function == AXP20X_FUNC_LDO)
	306	return 0;
	307
d242e60c	308	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
23f75d7d QS	309	}
	310
	311	static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
	312	struct pinctrl_gpio_range *range,
	313	unsigned int offset, bool input)
	314	{
d242e60c	315	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	316
	317	if (input)
	318	return axp20x_pmx_set(pctldev, offset,
d242e60c	319	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
23f75d7d QS	320
23f75d7d QS	321	return axp20x_pmx_set(pctldev, offset,
d242e60c	322	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
23f75d7d QS	323	}
	324
	325	static const struct pinmux_ops axp20x_pmx_ops = {
	326	.get_functions_count = axp20x_pmx_func_cnt,
	327	.get_function_name = axp20x_pmx_func_name,
	328	.get_function_groups = axp20x_pmx_func_groups,
	329	.set_mux = axp20x_pmx_set_mux,
	330	.gpio_set_direction = axp20x_pmx_gpio_set_direction,
	331	.strict = true,
	332	};
	333
	334	static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
	335	{
d242e60c	336	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	337
d242e60c	338	return pctl->desc->npins;
23f75d7d QS	339	}
	340
	341	static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
	342	const unsigned int *pins, unsigned int num_pins)
	343	{
d242e60c	344	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	345
d242e60c	346	pins = (unsigned int )&pctl->desc->pins[selector];
23f75d7d QS	347	*num_pins = 1;
	348
	349	return 0;
	350	}
	351
	352	static const char axp20x_group_name(struct pinctrl_dev pctldev,
	353	unsigned int selector)
f72f4b44	354	{
d242e60c	355	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	356
d242e60c	357	return pctl->desc->pins[selector].name;
23f75d7d QS	358	}
	359
	360	static const struct pinctrl_ops axp20x_pctrl_ops = {
	361	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
	362	.dt_free_map = pinconf_generic_dt_free_map,
	363	.get_groups_count = axp20x_groups_cnt,
	364	.get_group_name = axp20x_group_name,
	365	.get_group_pins = axp20x_group_pins,
	366	};
	367
504c7697	368	static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
23f75d7d QS	369	unsigned int mask_len,
	370	struct axp20x_pinctrl_function *func,
	371	const struct pinctrl_pin_desc *pins)
	372	{
	373	unsigned long int mask_cpy = mask;
	374	const char **group;
	375	unsigned int ngroups = hweight8(mask);
	376	int bit;
	377
	378	func->ngroups = ngroups;
	379	if (func->ngroups > 0) {
a86854d0 KC	380	func->groups = devm_kcalloc(dev,
a86854d0 KC	381	ngroups, sizeof(const char *),
23f75d7d	382	GFP_KERNEL);
504c7697 AV	383	if (!func->groups)
504c7697 AV	384	return -ENOMEM;
23f75d7d QS	385	group = func->groups;
	386	for_each_set_bit(bit, &mask_cpy, mask_len) {
	387	*group = pins[bit].name;
	388	group++;
	389	}
	390	}
504c7697 AV	391
504c7697 AV	392	return 0;
23f75d7d QS	393	}
23f75d7d QS	394
504c7697	395	static int axp20x_build_funcs_groups(struct platform_device *pdev)
23f75d7d	396	{
d242e60c	397	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
504c7697	398	int i, ret, pin, npins = pctl->desc->npins;
d242e60c QS	399
	400	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	401	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	402	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	403	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	404	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
23f75d7d QS	405	/*
	406	* Muxval for LDO is useless as we won't use it.
	407	* See comment in axp20x_pmx_set_mux.
	408	*/
d242e60c	409	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
a0a4b4c2	410	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
23f75d7d QS	411
	412	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	413	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
d242e60c	414	pctl->funcs[i].ngroups = npins;
a86854d0 KC	415	pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
a86854d0 KC	416	npins, sizeof(char *),
23f75d7d	417	GFP_KERNEL);
1adc90c7 AP	418	if (!pctl->funcs[i].groups)
1adc90c7 AP	419	return -ENOMEM;
23f75d7d	420	for (pin = 0; pin < npins; pin++)
d242e60c	421	pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
23f75d7d QS	422	}
23f75d7d QS	423
504c7697	424	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
d242e60c QS	425	npins, &pctl->funcs[AXP20X_FUNC_LDO],
d242e60c QS	426	pctl->desc->pins);
504c7697 AV	427	if (ret)
504c7697 AV	428	return ret;
23f75d7d	429
504c7697	430	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
d242e60c QS	431	npins, &pctl->funcs[AXP20X_FUNC_ADC],
d242e60c QS	432	pctl->desc->pins);
504c7697 AV	433	if (ret)
	434	return ret;
	435
	436	return 0;
f72f4b44 MR	437	}
f72f4b44 MR	438
e1190083 QS	439	static const struct of_device_id axp20x_pctl_match[] = {
e1190083 QS	440	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
d4c0b614	441	{ .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
e1190083 QS	442	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	443	{ }
	444	};
	445	MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
	446
d242e60c	447	static int axp20x_pctl_probe(struct platform_device *pdev)
f72f4b44 MR	448	{
f72f4b44 MR	449	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
d242e60c	450	struct axp20x_pctl *pctl;
e1190083	451	struct device *dev = &pdev->dev;
23f75d7d	452	struct pinctrl_desc *pctrl_desc;
f72f4b44 MR	453	int ret;
	454
	455	if (!of_device_is_available(pdev->dev.of_node))
	456	return -ENODEV;
	457
	458	if (!axp20x) {
	459	dev_err(&pdev->dev, "Parent drvdata not set\n");
	460	return -EINVAL;
	461	}
	462
d242e60c QS	463	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
d242e60c QS	464	if (!pctl)
f72f4b44 MR	465	return -ENOMEM;
f72f4b44 MR	466
d242e60c QS	467	pctl->chip.base = -1;
	468	pctl->chip.can_sleep = true;
	469	pctl->chip.request = gpiochip_generic_request;
	470	pctl->chip.free = gpiochip_generic_free;
	471	pctl->chip.parent = &pdev->dev;
	472	pctl->chip.label = dev_name(&pdev->dev);
	473	pctl->chip.owner = THIS_MODULE;
	474	pctl->chip.get = axp20x_gpio_get;
	475	pctl->chip.get_direction = axp20x_gpio_get_direction;
	476	pctl->chip.set = axp20x_gpio_set;
	477	pctl->chip.direction_input = axp20x_gpio_input;
	478	pctl->chip.direction_output = axp20x_gpio_output;
d242e60c	479
9b8ee3c0	480	pctl->desc = of_device_get_match_data(dev);
a0498152 QS	481
	482	pctl->chip.ngpio = pctl->desc->npins;
	483
d242e60c QS	484	pctl->regmap = axp20x->regmap;
	485	pctl->dev = &pdev->dev;
	486
	487	platform_set_drvdata(pdev, pctl);
23f75d7d	488
504c7697 AV	489	ret = axp20x_build_funcs_groups(pdev);
	490	if (ret) {
	491	dev_err(&pdev->dev, "failed to build groups\n");
	492	return ret;
	493	}
23f75d7d QS	494
	495	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	496	if (!pctrl_desc)
	497	return -ENOMEM;
	498
	499	pctrl_desc->name = dev_name(&pdev->dev);
	500	pctrl_desc->owner = THIS_MODULE;
d242e60c QS	501	pctrl_desc->pins = pctl->desc->pins;
d242e60c QS	502	pctrl_desc->npins = pctl->desc->npins;
23f75d7d QS	503	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	504	pctrl_desc->pmxops = &axp20x_pmx_ops;
	505
d242e60c QS	506	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
d242e60c QS	507	if (IS_ERR(pctl->pctl_dev)) {
23f75d7d	508	dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
d242e60c	509	return PTR_ERR(pctl->pctl_dev);
23f75d7d	510	}
f72f4b44	511
d242e60c	512	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
f72f4b44 MR	513	if (ret) {
	514	dev_err(&pdev->dev, "Failed to register GPIO chip\n");
	515	return ret;
	516	}
	517
d242e60c QS	518	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
	519	pctl->desc->pins->number,
	520	pctl->desc->pins->number,
	521	pctl->desc->npins);
23f75d7d QS	522	if (ret) {
	523	dev_err(&pdev->dev, "failed to add pin range\n");
	524	return ret;
	525	}
	526
	527	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
f72f4b44 MR	528
	529	return 0;
	530	}
	531
d242e60c QS	532	static struct platform_driver axp20x_pctl_driver = {
d242e60c QS	533	.probe = axp20x_pctl_probe,
f72f4b44 MR	534	.driver = {
f72f4b44 MR	535	.name = "axp20x-gpio",
d242e60c	536	.of_match_table = axp20x_pctl_match,
f72f4b44 MR	537	},
	538	};
	539
d242e60c	540	module_platform_driver(axp20x_pctl_driver);
f72f4b44 MR	541
f72f4b44 MR	542	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
23f75d7d QS	543	MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
23f75d7d QS	544	MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
f72f4b44	545	MODULE_LICENSE("GPL");