[linux-2.6-block.git] / drivers / pinctrl / pinctrl-axp209.c

/*
 * AXP20x pinctrl and GPIO driver
 *
 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under  the terms of the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/axp20x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#define AXP20X_GPIO_FUNCTIONS		0x7
#define AXP20X_GPIO_FUNCTION_OUT_LOW	0
#define AXP20X_GPIO_FUNCTION_OUT_HIGH	1
#define AXP20X_GPIO_FUNCTION_INPUT	2

#define AXP20X_FUNC_GPIO_OUT		0
#define AXP20X_FUNC_GPIO_IN		1
#define AXP20X_FUNC_LDO			2
#define AXP20X_FUNC_ADC			3
#define AXP20X_FUNCS_NB			4

#define AXP20X_MUX_GPIO_OUT		0
#define AXP20X_MUX_GPIO_IN		BIT(1)
#define AXP20X_MUX_ADC			BIT(2)

#define AXP813_MUX_ADC			(BIT(2) | BIT(0))

struct axp20x_pctrl_desc {
	const struct pinctrl_pin_desc	*pins;
	unsigned int			npins;
	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	u8				ldo_mask;
	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	u8				adc_mask;
	u8				gpio_status_offset;
	u8				adc_mux;
};

struct axp20x_pinctrl_function {
	const char	*name;
	unsigned int	muxval;
	const char	**groups;
	unsigned int	ngroups;
};

struct axp20x_pctl {
	struct gpio_chip	chip;
	struct regmap		*regmap;
	struct pinctrl_dev			*pctl_dev;
	struct device				*dev;
	const struct axp20x_pctrl_desc		*desc;
	struct axp20x_pinctrl_function		funcs[AXP20X_FUNCS_NB];
};

static const struct pinctrl_pin_desc axp209_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
	PINCTRL_PIN(2, "GPIO2"),
};

static const struct pinctrl_pin_desc axp813_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
};

static const struct axp20x_pctrl_desc axp20x_data = {
	.pins	= axp209_pins,
	.npins	= ARRAY_SIZE(axp209_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0) | BIT(1),
	.gpio_status_offset = 4,
	.adc_mux = AXP20X_MUX_ADC,
};

static const struct axp20x_pctrl_desc axp813_data = {
	.pins	= axp813_pins,
	.npins	= ARRAY_SIZE(axp813_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0),
	.gpio_status_offset = 0,
	.adc_mux = AXP813_MUX_ADC,
};

static int axp20x_gpio_get_reg(unsigned int offset)
{
	switch (offset) {
	case 0:
		return AXP20X_GPIO0_CTRL;
	case 1:
		return AXP20X_GPIO1_CTRL;
	case 2:
		return AXP20X_GPIO2_CTRL;
	}

	return -EINVAL;
}

static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
{
	return pinctrl_gpio_direction_input(chip->base + offset);
}

static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int ret;

	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
	if (ret)
		return ret;

	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
}

static int axp20x_gpio_get_direction(struct gpio_chip *chip,
				     unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int reg, ret;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	ret = regmap_read(pctl->regmap, reg, &val);
	if (ret)
		return ret;

	/*
	 * This shouldn't really happen if the pin is in use already,
	 * or if it's not in use yet, it doesn't matter since we're
	 * going to change the value soon anyway. Default to output.
	 */
	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
		return 0;

	/*
	 * The GPIO directions are the three lowest values.
	 * 2 is input, 0 and 1 are output
	 */
	return val & 2;
}

static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
			      int value)
{
	chip->set(chip, offset, value);

	return 0;
}

static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
			    int value)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return;

	regmap_update_bits(pctl->regmap, reg,
			   AXP20X_GPIO_FUNCTIONS,
			   value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
			   AXP20X_GPIO_FUNCTION_OUT_LOW);
}

static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
			  u8 config)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
				  config);
}

static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return ARRAY_SIZE(pctl->funcs);
}

static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
					unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->funcs[selector].name;
}

static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
				  unsigned int selector,
				  const char * const **groups,
				  unsigned int *num_groups)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*groups = pctl->funcs[selector].groups;
	*num_groups = pctl->funcs[selector].ngroups;

	return 0;
}

static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
			      unsigned int function, unsigned int group)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	unsigned int mask;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	if (function <= AXP20X_FUNC_GPIO_IN)
		return axp20x_pmx_set(pctldev, group,
				      pctl->funcs[function].muxval);

	if (function == AXP20X_FUNC_LDO)
		mask = pctl->desc->ldo_mask;
	else
		mask = pctl->desc->adc_mask;

	if (!(BIT(group) & mask))
		return -EINVAL;

	/*
	 * We let the regulator framework handle the LDO muxing as muxing bits
	 * are basically also regulators on/off bits. It's better not to enforce
	 * any state of the regulator when selecting LDO mux so that we don't
	 * interfere with the regulator driver.
	 */
	if (function == AXP20X_FUNC_LDO)
		return 0;

	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
}

static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
					 struct pinctrl_gpio_range *range,
					 unsigned int offset, bool input)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	if (input)
		return axp20x_pmx_set(pctldev, offset,
				      pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);

	return axp20x_pmx_set(pctldev, offset,
			      pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
}

static const struct pinmux_ops axp20x_pmx_ops = {
	.get_functions_count	= axp20x_pmx_func_cnt,
	.get_function_name	= axp20x_pmx_func_name,
	.get_function_groups	= axp20x_pmx_func_groups,
	.set_mux		= axp20x_pmx_set_mux,
	.gpio_set_direction	= axp20x_pmx_gpio_set_direction,
	.strict			= true,
};

static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->npins;
}

static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
			     const unsigned int **pins, unsigned int *num_pins)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*pins = (unsigned int *)&pctl->desc->pins[selector];
	*num_pins = 1;

	return 0;
}

static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
				     unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->pins[selector].name;
}

static const struct pinctrl_ops axp20x_pctrl_ops = {
	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
	.dt_free_map		= pinconf_generic_dt_free_map,
	.get_groups_count	= axp20x_groups_cnt,
	.get_group_name		= axp20x_group_name,
	.get_group_pins		= axp20x_group_pins,
};

static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
					  unsigned int mask_len,
					  struct axp20x_pinctrl_function *func,
					  const struct pinctrl_pin_desc *pins)
{
	unsigned long int mask_cpy = mask;
	const char **group;
	unsigned int ngroups = hweight8(mask);
	int bit;

	func->ngroups = ngroups;
	if (func->ngroups > 0) {
		func->groups = devm_kcalloc(dev,
					    ngroups, sizeof(const char *),
					    GFP_KERNEL);
		if (!func->groups)
			return -ENOMEM;
		group = func->groups;
		for_each_set_bit(bit, &mask_cpy, mask_len) {
			*group = pins[bit].name;
			group++;
		}
	}

	return 0;
}

static int axp20x_build_funcs_groups(struct platform_device *pdev)
{
	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
	int i, ret, pin, npins = pctl->desc->npins;

	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
	/*
	 * Muxval for LDO is useless as we won't use it.
	 * See comment in axp20x_pmx_set_mux.
	 */
	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
		pctl->funcs[i].ngroups = npins;
		pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
						     npins, sizeof(char *),
						     GFP_KERNEL);
		for (pin = 0; pin < npins; pin++)
			pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
	}

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_LDO],
				      pctl->desc->pins);
	if (ret)
		return ret;

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_ADC],
				      pctl->desc->pins);
	if (ret)
		return ret;

	return 0;
}

static const struct of_device_id axp20x_pctl_match[] = {
	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	{ }
};
MODULE_DEVICE_TABLE(of, axp20x_pctl_match);

static int axp20x_pctl_probe(struct platform_device *pdev)
{
	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
	struct axp20x_pctl *pctl;
	struct device *dev = &pdev->dev;
	struct pinctrl_desc *pctrl_desc;
	int ret;

	if (!of_device_is_available(pdev->dev.of_node))
		return -ENODEV;

	if (!axp20x) {
		dev_err(&pdev->dev, "Parent drvdata not set\n");
		return -EINVAL;
	}

	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
	if (!pctl)
		return -ENOMEM;

	pctl->chip.base			= -1;
	pctl->chip.can_sleep		= true;
	pctl->chip.request		= gpiochip_generic_request;
	pctl->chip.free			= gpiochip_generic_free;
	pctl->chip.parent		= &pdev->dev;
	pctl->chip.label		= dev_name(&pdev->dev);
	pctl->chip.owner		= THIS_MODULE;
	pctl->chip.get			= axp20x_gpio_get;
	pctl->chip.get_direction	= axp20x_gpio_get_direction;
	pctl->chip.set			= axp20x_gpio_set;
	pctl->chip.direction_input	= axp20x_gpio_input;
	pctl->chip.direction_output	= axp20x_gpio_output;

	pctl->desc = of_device_get_match_data(dev);

	pctl->chip.ngpio		= pctl->desc->npins;

	pctl->regmap = axp20x->regmap;
	pctl->dev = &pdev->dev;

	platform_set_drvdata(pdev, pctl);

	ret = axp20x_build_funcs_groups(pdev);
	if (ret) {
		dev_err(&pdev->dev, "failed to build groups\n");
		return ret;
	}

	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	if (!pctrl_desc)
		return -ENOMEM;

	pctrl_desc->name = dev_name(&pdev->dev);
	pctrl_desc->owner = THIS_MODULE;
	pctrl_desc->pins = pctl->desc->pins;
	pctrl_desc->npins = pctl->desc->npins;
	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	pctrl_desc->pmxops = &axp20x_pmx_ops;

	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
	if (IS_ERR(pctl->pctl_dev)) {
		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
		return PTR_ERR(pctl->pctl_dev);
	}

	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register GPIO chip\n");
		return ret;
	}

	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
				     pctl->desc->pins->number,
				     pctl->desc->pins->number,
				     pctl->desc->npins);
	if (ret) {
		dev_err(&pdev->dev, "failed to add pin range\n");
		return ret;
	}

	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");

	return 0;
}

static struct platform_driver axp20x_pctl_driver = {
	.probe		= axp20x_pctl_probe,
	.driver = {
		.name		= "axp20x-gpio",
		.of_match_table	= axp20x_pctl_match,
	},
};

module_platform_driver(axp20x_pctl_driver);

MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
f72f4b44	1	/*
23f75d7d	2	* AXP20x pinctrl and GPIO driver
f72f4b44 MR	3	*
f72f4b44 MR	4	* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
23f75d7d	5	* Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
f72f4b44 MR	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
	13	#include <linux/bitops.h>
	14	#include <linux/device.h>
	15	#include <linux/gpio/driver.h>
	16	#include <linux/init.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/kernel.h>
	19	#include <linux/mfd/axp20x.h>
	20	#include <linux/module.h>
	21	#include <linux/of.h>
e1190083	22	#include <linux/of_device.h>
23f75d7d QS	23	#include <linux/pinctrl/pinconf-generic.h>
	24	#include <linux/pinctrl/pinctrl.h>
	25	#include <linux/pinctrl/pinmux.h>
f72f4b44 MR	26	#include <linux/platform_device.h>
	27	#include <linux/regmap.h>
	28	#include <linux/slab.h>
	29
	30	#define AXP20X_GPIO_FUNCTIONS 0x7
	31	#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
	32	#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
	33	#define AXP20X_GPIO_FUNCTION_INPUT 2
	34
23f75d7d QS	35	#define AXP20X_FUNC_GPIO_OUT 0
	36	#define AXP20X_FUNC_GPIO_IN 1
	37	#define AXP20X_FUNC_LDO 2
	38	#define AXP20X_FUNC_ADC 3
	39	#define AXP20X_FUNCS_NB 4
	40
	41	#define AXP20X_MUX_GPIO_OUT 0
	42	#define AXP20X_MUX_GPIO_IN BIT(1)
	43	#define AXP20X_MUX_ADC BIT(2)
	44
e1190083 QS	45	#define AXP813_MUX_ADC (BIT(2) \| BIT(0))
e1190083 QS	46
23f75d7d QS	47	struct axp20x_pctrl_desc {
	48	const struct pinctrl_pin_desc *pins;
	49	unsigned int npins;
	50	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	51	u8 ldo_mask;
	52	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	53	u8 adc_mask;
48e706fb	54	u8 gpio_status_offset;
a0a4b4c2	55	u8 adc_mux;
23f75d7d QS	56	};
	57
	58	struct axp20x_pinctrl_function {
	59	const char *name;
	60	unsigned int muxval;
	61	const char **groups;
	62	unsigned int ngroups;
	63	};
	64
d242e60c	65	struct axp20x_pctl {
f72f4b44 MR	66	struct gpio_chip chip;
f72f4b44 MR	67	struct regmap *regmap;
23f75d7d QS	68	struct pinctrl_dev *pctl_dev;
	69	struct device *dev;
	70	const struct axp20x_pctrl_desc *desc;
	71	struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
	72	};
	73
	74	static const struct pinctrl_pin_desc axp209_pins[] = {
	75	PINCTRL_PIN(0, "GPIO0"),
	76	PINCTRL_PIN(1, "GPIO1"),
	77	PINCTRL_PIN(2, "GPIO2"),
	78	};
	79
e1190083 QS	80	static const struct pinctrl_pin_desc axp813_pins[] = {
	81	PINCTRL_PIN(0, "GPIO0"),
	82	PINCTRL_PIN(1, "GPIO1"),
	83	};
	84
23f75d7d QS	85	static const struct axp20x_pctrl_desc axp20x_data = {
	86	.pins = axp209_pins,
	87	.npins = ARRAY_SIZE(axp209_pins),
	88	.ldo_mask = BIT(0) \| BIT(1),
	89	.adc_mask = BIT(0) \| BIT(1),
48e706fb	90	.gpio_status_offset = 4,
a0a4b4c2	91	.adc_mux = AXP20X_MUX_ADC,
f72f4b44 MR	92	};
f72f4b44 MR	93
e1190083 QS	94	static const struct axp20x_pctrl_desc axp813_data = {
	95	.pins = axp813_pins,
	96	.npins = ARRAY_SIZE(axp813_pins),
	97	.ldo_mask = BIT(0) \| BIT(1),
	98	.adc_mask = BIT(0),
	99	.gpio_status_offset = 0,
	100	.adc_mux = AXP813_MUX_ADC,
	101	};
	102
3cac991e	103	static int axp20x_gpio_get_reg(unsigned int offset)
f72f4b44 MR	104	{
	105	switch (offset) {
	106	case 0:
	107	return AXP20X_GPIO0_CTRL;
	108	case 1:
	109	return AXP20X_GPIO1_CTRL;
	110	case 2:
	111	return AXP20X_GPIO2_CTRL;
	112	}
	113
	114	return -EINVAL;
	115	}
	116
3cac991e	117	static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
f72f4b44	118	{
23f75d7d	119	return pinctrl_gpio_direction_input(chip->base + offset);
f72f4b44 MR	120	}
f72f4b44 MR	121
3cac991e	122	static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
f72f4b44	123	{
d242e60c	124	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44	125	unsigned int val;
1d2b2ac0	126	int ret;
f72f4b44	127
d242e60c	128	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
f72f4b44 MR	129	if (ret)
	130	return ret;
	131
48e706fb	132	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
f72f4b44 MR	133	}
f72f4b44 MR	134
3cac991e QS	135	static int axp20x_gpio_get_direction(struct gpio_chip *chip,
3cac991e QS	136	unsigned int offset)
81d3753d	137	{
d242e60c	138	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
81d3753d MR	139	unsigned int val;
	140	int reg, ret;
	141
	142	reg = axp20x_gpio_get_reg(offset);
	143	if (reg < 0)
	144	return reg;
	145
d242e60c	146	ret = regmap_read(pctl->regmap, reg, &val);
81d3753d MR	147	if (ret)
	148	return ret;
	149
	150	/*
	151	* This shouldn't really happen if the pin is in use already,
	152	* or if it's not in use yet, it doesn't matter since we're
	153	* going to change the value soon anyway. Default to output.
	154	*/
	155	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
	156	return 0;
	157
	158	/*
	159	* The GPIO directions are the three lowest values.
	160	* 2 is input, 0 and 1 are output
	161	*/
	162	return val & 2;
	163	}
	164
3cac991e	165	static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
f72f4b44	166	int value)
23f75d7d QS	167	{
	168	chip->set(chip, offset, value);
	169
	170	return 0;
	171	}
	172
	173	static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
	174	int value)
f72f4b44	175	{
d242e60c	176	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44 MR	177	int reg;
f72f4b44 MR	178
23f75d7d QS	179	reg = axp20x_gpio_get_reg(offset);
	180	if (reg < 0)
	181	return;
	182
d242e60c	183	regmap_update_bits(pctl->regmap, reg,
23f75d7d QS	184	AXP20X_GPIO_FUNCTIONS,
	185	value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
	186	AXP20X_GPIO_FUNCTION_OUT_LOW);
	187	}
	188
	189	static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
	190	u8 config)
	191	{
d242e60c	192	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	193	int reg;
23f75d7d QS	194
f72f4b44 MR	195	reg = axp20x_gpio_get_reg(offset);
	196	if (reg < 0)
	197	return reg;
	198
d242e60c	199	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
23f75d7d	200	config);
f72f4b44 MR	201	}
f72f4b44 MR	202
23f75d7d QS	203	static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
23f75d7d QS	204	{
d242e60c	205	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	206
d242e60c	207	return ARRAY_SIZE(pctl->funcs);
23f75d7d QS	208	}
	209
	210	static const char axp20x_pmx_func_name(struct pinctrl_dev pctldev,
	211	unsigned int selector)
	212	{
d242e60c	213	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	214
d242e60c	215	return pctl->funcs[selector].name;
23f75d7d QS	216	}
	217
	218	static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
	219	unsigned int selector,
	220	const char * const **groups,
	221	unsigned int *num_groups)
	222	{
d242e60c	223	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	224
d242e60c QS	225	*groups = pctl->funcs[selector].groups;
d242e60c QS	226	*num_groups = pctl->funcs[selector].ngroups;
23f75d7d QS	227
	228	return 0;
	229	}
	230
	231	static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
	232	unsigned int function, unsigned int group)
	233	{
d242e60c	234	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	235	unsigned int mask;
	236
	237	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	238	if (function <= AXP20X_FUNC_GPIO_IN)
	239	return axp20x_pmx_set(pctldev, group,
d242e60c	240	pctl->funcs[function].muxval);
23f75d7d QS	241
23f75d7d QS	242	if (function == AXP20X_FUNC_LDO)
d242e60c	243	mask = pctl->desc->ldo_mask;
23f75d7d	244	else
d242e60c	245	mask = pctl->desc->adc_mask;
23f75d7d QS	246
	247	if (!(BIT(group) & mask))
	248	return -EINVAL;
	249
	250	/*
	251	* We let the regulator framework handle the LDO muxing as muxing bits
	252	* are basically also regulators on/off bits. It's better not to enforce
	253	* any state of the regulator when selecting LDO mux so that we don't
	254	* interfere with the regulator driver.
	255	*/
	256	if (function == AXP20X_FUNC_LDO)
	257	return 0;
	258
d242e60c	259	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
23f75d7d QS	260	}
	261
	262	static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
	263	struct pinctrl_gpio_range *range,
	264	unsigned int offset, bool input)
	265	{
d242e60c	266	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	267
	268	if (input)
	269	return axp20x_pmx_set(pctldev, offset,
d242e60c	270	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
23f75d7d QS	271
23f75d7d QS	272	return axp20x_pmx_set(pctldev, offset,
d242e60c	273	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
23f75d7d QS	274	}
	275
	276	static const struct pinmux_ops axp20x_pmx_ops = {
	277	.get_functions_count = axp20x_pmx_func_cnt,
	278	.get_function_name = axp20x_pmx_func_name,
	279	.get_function_groups = axp20x_pmx_func_groups,
	280	.set_mux = axp20x_pmx_set_mux,
	281	.gpio_set_direction = axp20x_pmx_gpio_set_direction,
	282	.strict = true,
	283	};
	284
	285	static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
	286	{
d242e60c	287	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	288
d242e60c	289	return pctl->desc->npins;
23f75d7d QS	290	}
	291
	292	static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
	293	const unsigned int *pins, unsigned int num_pins)
	294	{
d242e60c	295	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	296
d242e60c	297	pins = (unsigned int )&pctl->desc->pins[selector];
23f75d7d QS	298	*num_pins = 1;
	299
	300	return 0;
	301	}
	302
	303	static const char axp20x_group_name(struct pinctrl_dev pctldev,
	304	unsigned int selector)
f72f4b44	305	{
d242e60c	306	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	307
d242e60c	308	return pctl->desc->pins[selector].name;
23f75d7d QS	309	}
	310
	311	static const struct pinctrl_ops axp20x_pctrl_ops = {
	312	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
	313	.dt_free_map = pinconf_generic_dt_free_map,
	314	.get_groups_count = axp20x_groups_cnt,
	315	.get_group_name = axp20x_group_name,
	316	.get_group_pins = axp20x_group_pins,
	317	};
	318
504c7697	319	static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
23f75d7d QS	320	unsigned int mask_len,
	321	struct axp20x_pinctrl_function *func,
	322	const struct pinctrl_pin_desc *pins)
	323	{
	324	unsigned long int mask_cpy = mask;
	325	const char **group;
	326	unsigned int ngroups = hweight8(mask);
	327	int bit;
	328
	329	func->ngroups = ngroups;
	330	if (func->ngroups > 0) {
a86854d0 KC	331	func->groups = devm_kcalloc(dev,
a86854d0 KC	332	ngroups, sizeof(const char *),
23f75d7d	333	GFP_KERNEL);
504c7697 AV	334	if (!func->groups)
504c7697 AV	335	return -ENOMEM;
23f75d7d QS	336	group = func->groups;
	337	for_each_set_bit(bit, &mask_cpy, mask_len) {
	338	*group = pins[bit].name;
	339	group++;
	340	}
	341	}
504c7697 AV	342
504c7697 AV	343	return 0;
23f75d7d QS	344	}
23f75d7d QS	345
504c7697	346	static int axp20x_build_funcs_groups(struct platform_device *pdev)
23f75d7d	347	{
d242e60c	348	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
504c7697	349	int i, ret, pin, npins = pctl->desc->npins;
d242e60c QS	350
	351	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	352	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	353	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	354	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	355	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
23f75d7d QS	356	/*
	357	* Muxval for LDO is useless as we won't use it.
	358	* See comment in axp20x_pmx_set_mux.
	359	*/
d242e60c	360	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
a0a4b4c2	361	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
23f75d7d QS	362
	363	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	364	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
d242e60c	365	pctl->funcs[i].ngroups = npins;
a86854d0 KC	366	pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
a86854d0 KC	367	npins, sizeof(char *),
23f75d7d QS	368	GFP_KERNEL);
23f75d7d QS	369	for (pin = 0; pin < npins; pin++)
d242e60c	370	pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
23f75d7d QS	371	}
23f75d7d QS	372
504c7697	373	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
d242e60c QS	374	npins, &pctl->funcs[AXP20X_FUNC_LDO],
d242e60c QS	375	pctl->desc->pins);
504c7697 AV	376	if (ret)
504c7697 AV	377	return ret;
23f75d7d	378
504c7697	379	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
d242e60c QS	380	npins, &pctl->funcs[AXP20X_FUNC_ADC],
d242e60c QS	381	pctl->desc->pins);
504c7697 AV	382	if (ret)
	383	return ret;
	384
	385	return 0;
f72f4b44 MR	386	}
f72f4b44 MR	387
e1190083 QS	388	static const struct of_device_id axp20x_pctl_match[] = {
	389	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
	390	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	391	{ }
	392	};
	393	MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
	394
d242e60c	395	static int axp20x_pctl_probe(struct platform_device *pdev)
f72f4b44 MR	396	{
f72f4b44 MR	397	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
d242e60c	398	struct axp20x_pctl *pctl;
e1190083	399	struct device *dev = &pdev->dev;
23f75d7d	400	struct pinctrl_desc *pctrl_desc;
f72f4b44 MR	401	int ret;
	402
	403	if (!of_device_is_available(pdev->dev.of_node))
	404	return -ENODEV;
	405
	406	if (!axp20x) {
	407	dev_err(&pdev->dev, "Parent drvdata not set\n");
	408	return -EINVAL;
	409	}
	410
d242e60c QS	411	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
d242e60c QS	412	if (!pctl)
f72f4b44 MR	413	return -ENOMEM;
f72f4b44 MR	414
d242e60c QS	415	pctl->chip.base = -1;
	416	pctl->chip.can_sleep = true;
	417	pctl->chip.request = gpiochip_generic_request;
	418	pctl->chip.free = gpiochip_generic_free;
	419	pctl->chip.parent = &pdev->dev;
	420	pctl->chip.label = dev_name(&pdev->dev);
	421	pctl->chip.owner = THIS_MODULE;
	422	pctl->chip.get = axp20x_gpio_get;
	423	pctl->chip.get_direction = axp20x_gpio_get_direction;
	424	pctl->chip.set = axp20x_gpio_set;
	425	pctl->chip.direction_input = axp20x_gpio_input;
	426	pctl->chip.direction_output = axp20x_gpio_output;
d242e60c	427
9b8ee3c0	428	pctl->desc = of_device_get_match_data(dev);
a0498152 QS	429
	430	pctl->chip.ngpio = pctl->desc->npins;
	431
d242e60c QS	432	pctl->regmap = axp20x->regmap;
	433	pctl->dev = &pdev->dev;
	434
	435	platform_set_drvdata(pdev, pctl);
23f75d7d	436
504c7697 AV	437	ret = axp20x_build_funcs_groups(pdev);
	438	if (ret) {
	439	dev_err(&pdev->dev, "failed to build groups\n");
	440	return ret;
	441	}
23f75d7d QS	442
	443	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	444	if (!pctrl_desc)
	445	return -ENOMEM;
	446
	447	pctrl_desc->name = dev_name(&pdev->dev);
	448	pctrl_desc->owner = THIS_MODULE;
d242e60c QS	449	pctrl_desc->pins = pctl->desc->pins;
d242e60c QS	450	pctrl_desc->npins = pctl->desc->npins;
23f75d7d QS	451	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	452	pctrl_desc->pmxops = &axp20x_pmx_ops;
	453
d242e60c QS	454	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
d242e60c QS	455	if (IS_ERR(pctl->pctl_dev)) {
23f75d7d	456	dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
d242e60c	457	return PTR_ERR(pctl->pctl_dev);
23f75d7d	458	}
f72f4b44	459
d242e60c	460	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
f72f4b44 MR	461	if (ret) {
	462	dev_err(&pdev->dev, "Failed to register GPIO chip\n");
	463	return ret;
	464	}
	465
d242e60c QS	466	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
	467	pctl->desc->pins->number,
	468	pctl->desc->pins->number,
	469	pctl->desc->npins);
23f75d7d QS	470	if (ret) {
	471	dev_err(&pdev->dev, "failed to add pin range\n");
	472	return ret;
	473	}
	474
	475	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
f72f4b44 MR	476
	477	return 0;
	478	}
	479
d242e60c QS	480	static struct platform_driver axp20x_pctl_driver = {
d242e60c QS	481	.probe = axp20x_pctl_probe,
f72f4b44 MR	482	.driver = {
f72f4b44 MR	483	.name = "axp20x-gpio",
d242e60c	484	.of_match_table = axp20x_pctl_match,
f72f4b44 MR	485	},
	486	};
	487
d242e60c	488	module_platform_driver(axp20x_pctl_driver);
f72f4b44 MR	489
f72f4b44 MR	490	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
23f75d7d QS	491	MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
23f75d7d QS	492	MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
f72f4b44	493	MODULE_LICENSE("GPL");