[linux-2.6-block.git] / drivers / pinctrl / pinctrl-axp209.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * AXP20x pinctrl and GPIO driver
 *
 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
 */

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/axp20x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#define AXP20X_GPIO_FUNCTIONS		0x7
#define AXP20X_GPIO_FUNCTION_OUT_LOW	0
#define AXP20X_GPIO_FUNCTION_OUT_HIGH	1
#define AXP20X_GPIO_FUNCTION_INPUT	2

#define AXP20X_FUNC_GPIO_OUT		0
#define AXP20X_FUNC_GPIO_IN		1
#define AXP20X_FUNC_LDO			2
#define AXP20X_FUNC_ADC			3
#define AXP20X_FUNCS_NB			4

#define AXP20X_MUX_GPIO_OUT		0
#define AXP20X_MUX_GPIO_IN		BIT(1)
#define AXP20X_MUX_ADC			BIT(2)

#define AXP813_MUX_ADC			(BIT(2) | BIT(0))

struct axp20x_pctrl_desc {
	const struct pinctrl_pin_desc	*pins;
	unsigned int			npins;
	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	u8				ldo_mask;
	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	u8				adc_mask;
	u8				gpio_status_offset;
	u8				adc_mux;
};

struct axp20x_pinctrl_function {
	const char	*name;
	unsigned int	muxval;
	const char	**groups;
	unsigned int	ngroups;
};

struct axp20x_pctl {
	struct gpio_chip	chip;
	struct regmap		*regmap;
	struct pinctrl_dev			*pctl_dev;
	struct device				*dev;
	const struct axp20x_pctrl_desc		*desc;
	struct axp20x_pinctrl_function		funcs[AXP20X_FUNCS_NB];
};

static const struct pinctrl_pin_desc axp209_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
	PINCTRL_PIN(2, "GPIO2"),
};

static const struct pinctrl_pin_desc axp22x_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
};

static const struct axp20x_pctrl_desc axp20x_data = {
	.pins	= axp209_pins,
	.npins	= ARRAY_SIZE(axp209_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0) | BIT(1),
	.gpio_status_offset = 4,
	.adc_mux = AXP20X_MUX_ADC,
};

static const struct axp20x_pctrl_desc axp22x_data = {
	.pins	= axp22x_pins,
	.npins	= ARRAY_SIZE(axp22x_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.gpio_status_offset = 0,
};

static const struct axp20x_pctrl_desc axp813_data = {
	.pins	= axp22x_pins,
	.npins	= ARRAY_SIZE(axp22x_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0),
	.gpio_status_offset = 0,
	.adc_mux = AXP813_MUX_ADC,
};

static int axp20x_gpio_get_reg(unsigned int offset)
{
	switch (offset) {
	case 0:
		return AXP20X_GPIO0_CTRL;
	case 1:
		return AXP20X_GPIO1_CTRL;
	case 2:
		return AXP20X_GPIO2_CTRL;
	}

	return -EINVAL;
}

static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
{
	return pinctrl_gpio_direction_input(chip->base + offset);
}

static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int ret;

	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
	if (ret)
		return ret;

	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
}

static int axp20x_gpio_get_direction(struct gpio_chip *chip,
				     unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int reg, ret;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	ret = regmap_read(pctl->regmap, reg, &val);
	if (ret)
		return ret;

	/*
	 * This shouldn't really happen if the pin is in use already,
	 * or if it's not in use yet, it doesn't matter since we're
	 * going to change the value soon anyway. Default to output.
	 */
	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
		return GPIO_LINE_DIRECTION_OUT;

	/*
	 * The GPIO directions are the three lowest values.
	 * 2 is input, 0 and 1 are output
	 */
	if (val & 2)
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
			      int value)
{
	chip->set(chip, offset, value);

	return 0;
}

static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
			    int value)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return;

	regmap_update_bits(pctl->regmap, reg,
			   AXP20X_GPIO_FUNCTIONS,
			   value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
			   AXP20X_GPIO_FUNCTION_OUT_LOW);
}

static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
			  u8 config)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
				  config);
}

static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return ARRAY_SIZE(pctl->funcs);
}

static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
					unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->funcs[selector].name;
}

static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
				  unsigned int selector,
				  const char * const **groups,
				  unsigned int *num_groups)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*groups = pctl->funcs[selector].groups;
	*num_groups = pctl->funcs[selector].ngroups;

	return 0;
}

static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
			      unsigned int function, unsigned int group)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	unsigned int mask;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	if (function <= AXP20X_FUNC_GPIO_IN)
		return axp20x_pmx_set(pctldev, group,
				      pctl->funcs[function].muxval);

	if (function == AXP20X_FUNC_LDO)
		mask = pctl->desc->ldo_mask;
	else
		mask = pctl->desc->adc_mask;

	if (!(BIT(group) & mask))
		return -EINVAL;

	/*
	 * We let the regulator framework handle the LDO muxing as muxing bits
	 * are basically also regulators on/off bits. It's better not to enforce
	 * any state of the regulator when selecting LDO mux so that we don't
	 * interfere with the regulator driver.
	 */
	if (function == AXP20X_FUNC_LDO)
		return 0;

	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
}

static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
					 struct pinctrl_gpio_range *range,
					 unsigned int offset, bool input)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	if (input)
		return axp20x_pmx_set(pctldev, offset,
				      pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);

	return axp20x_pmx_set(pctldev, offset,
			      pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
}

static const struct pinmux_ops axp20x_pmx_ops = {
	.get_functions_count	= axp20x_pmx_func_cnt,
	.get_function_name	= axp20x_pmx_func_name,
	.get_function_groups	= axp20x_pmx_func_groups,
	.set_mux		= axp20x_pmx_set_mux,
	.gpio_set_direction	= axp20x_pmx_gpio_set_direction,
	.strict			= true,
};

static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->npins;
}

static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
			     const unsigned int **pins, unsigned int *num_pins)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*pins = (unsigned int *)&pctl->desc->pins[selector];
	*num_pins = 1;

	return 0;
}

static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
				     unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->pins[selector].name;
}

static const struct pinctrl_ops axp20x_pctrl_ops = {
	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
	.dt_free_map		= pinconf_generic_dt_free_map,
	.get_groups_count	= axp20x_groups_cnt,
	.get_group_name		= axp20x_group_name,
	.get_group_pins		= axp20x_group_pins,
};

static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
					  unsigned int mask_len,
					  struct axp20x_pinctrl_function *func,
					  const struct pinctrl_pin_desc *pins)
{
	unsigned long int mask_cpy = mask;
	const char **group;
	unsigned int ngroups = hweight8(mask);
	int bit;

	func->ngroups = ngroups;
	if (func->ngroups > 0) {
		func->groups = devm_kcalloc(dev,
					    ngroups, sizeof(const char *),
					    GFP_KERNEL);
		if (!func->groups)
			return -ENOMEM;
		group = func->groups;
		for_each_set_bit(bit, &mask_cpy, mask_len) {
			*group = pins[bit].name;
			group++;
		}
	}

	return 0;
}

static int axp20x_build_funcs_groups(struct platform_device *pdev)
{
	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
	int i, ret, pin, npins = pctl->desc->npins;

	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
	/*
	 * Muxval for LDO is useless as we won't use it.
	 * See comment in axp20x_pmx_set_mux.
	 */
	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
		pctl->funcs[i].ngroups = npins;
		pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
						     npins, sizeof(char *),
						     GFP_KERNEL);
		if (!pctl->funcs[i].groups)
			return -ENOMEM;
		for (pin = 0; pin < npins; pin++)
			pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
	}

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_LDO],
				      pctl->desc->pins);
	if (ret)
		return ret;

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_ADC],
				      pctl->desc->pins);
	if (ret)
		return ret;

	return 0;
}

static const struct of_device_id axp20x_pctl_match[] = {
	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
	{ .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	{ }
};
MODULE_DEVICE_TABLE(of, axp20x_pctl_match);

static int axp20x_pctl_probe(struct platform_device *pdev)
{
	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
	struct axp20x_pctl *pctl;
	struct device *dev = &pdev->dev;
	struct pinctrl_desc *pctrl_desc;
	int ret;

	if (!of_device_is_available(pdev->dev.of_node))
		return -ENODEV;

	if (!axp20x) {
		dev_err(&pdev->dev, "Parent drvdata not set\n");
		return -EINVAL;
	}

	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
	if (!pctl)
		return -ENOMEM;

	pctl->chip.base			= -1;
	pctl->chip.can_sleep		= true;
	pctl->chip.request		= gpiochip_generic_request;
	pctl->chip.free			= gpiochip_generic_free;
	pctl->chip.parent		= &pdev->dev;
	pctl->chip.label		= dev_name(&pdev->dev);
	pctl->chip.owner		= THIS_MODULE;
	pctl->chip.get			= axp20x_gpio_get;
	pctl->chip.get_direction	= axp20x_gpio_get_direction;
	pctl->chip.set			= axp20x_gpio_set;
	pctl->chip.direction_input	= axp20x_gpio_input;
	pctl->chip.direction_output	= axp20x_gpio_output;

	pctl->desc = of_device_get_match_data(dev);

	pctl->chip.ngpio		= pctl->desc->npins;

	pctl->regmap = axp20x->regmap;
	pctl->dev = &pdev->dev;

	platform_set_drvdata(pdev, pctl);

	ret = axp20x_build_funcs_groups(pdev);
	if (ret) {
		dev_err(&pdev->dev, "failed to build groups\n");
		return ret;
	}

	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	if (!pctrl_desc)
		return -ENOMEM;

	pctrl_desc->name = dev_name(&pdev->dev);
	pctrl_desc->owner = THIS_MODULE;
	pctrl_desc->pins = pctl->desc->pins;
	pctrl_desc->npins = pctl->desc->npins;
	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	pctrl_desc->pmxops = &axp20x_pmx_ops;

	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
	if (IS_ERR(pctl->pctl_dev)) {
		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
		return PTR_ERR(pctl->pctl_dev);
	}

	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register GPIO chip\n");
		return ret;
	}

	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
				     pctl->desc->pins->number,
				     pctl->desc->pins->number,
				     pctl->desc->npins);
	if (ret) {
		dev_err(&pdev->dev, "failed to add pin range\n");
		return ret;
	}

	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");

	return 0;
}

static struct platform_driver axp20x_pctl_driver = {
	.probe		= axp20x_pctl_probe,
	.driver = {
		.name		= "axp20x-gpio",
		.of_match_table	= axp20x_pctl_match,
	},
};

module_platform_driver(axp20x_pctl_driver);

MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
f72f4b44	2	/*
23f75d7d	3	* AXP20x pinctrl and GPIO driver
f72f4b44 MR	4	*
f72f4b44 MR	5	* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
23f75d7d	6	* Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
f72f4b44 MR	7	*/
	8
	9	#include <linux/bitops.h>
	10	#include <linux/device.h>
	11	#include <linux/gpio/driver.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel.h>
	15	#include <linux/mfd/axp20x.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
e1190083	18	#include <linux/of_device.h>
23f75d7d QS	19	#include <linux/pinctrl/pinconf-generic.h>
	20	#include <linux/pinctrl/pinctrl.h>
	21	#include <linux/pinctrl/pinmux.h>
f72f4b44 MR	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/slab.h>
	25
	26	#define AXP20X_GPIO_FUNCTIONS 0x7
	27	#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
	28	#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
	29	#define AXP20X_GPIO_FUNCTION_INPUT 2
	30
23f75d7d QS	31	#define AXP20X_FUNC_GPIO_OUT 0
	32	#define AXP20X_FUNC_GPIO_IN 1
	33	#define AXP20X_FUNC_LDO 2
	34	#define AXP20X_FUNC_ADC 3
	35	#define AXP20X_FUNCS_NB 4
	36
	37	#define AXP20X_MUX_GPIO_OUT 0
	38	#define AXP20X_MUX_GPIO_IN BIT(1)
	39	#define AXP20X_MUX_ADC BIT(2)
	40
e1190083 QS	41	#define AXP813_MUX_ADC (BIT(2) \| BIT(0))
e1190083 QS	42
23f75d7d QS	43	struct axp20x_pctrl_desc {
	44	const struct pinctrl_pin_desc *pins;
	45	unsigned int npins;
	46	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	47	u8 ldo_mask;
	48	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	49	u8 adc_mask;
48e706fb	50	u8 gpio_status_offset;
a0a4b4c2	51	u8 adc_mux;
23f75d7d QS	52	};
	53
	54	struct axp20x_pinctrl_function {
	55	const char *name;
	56	unsigned int muxval;
	57	const char **groups;
	58	unsigned int ngroups;
	59	};
	60
d242e60c	61	struct axp20x_pctl {
f72f4b44 MR	62	struct gpio_chip chip;
f72f4b44 MR	63	struct regmap *regmap;
23f75d7d QS	64	struct pinctrl_dev *pctl_dev;
	65	struct device *dev;
	66	const struct axp20x_pctrl_desc *desc;
	67	struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
	68	};
	69
	70	static const struct pinctrl_pin_desc axp209_pins[] = {
	71	PINCTRL_PIN(0, "GPIO0"),
	72	PINCTRL_PIN(1, "GPIO1"),
	73	PINCTRL_PIN(2, "GPIO2"),
	74	};
	75
d4c0b614	76	static const struct pinctrl_pin_desc axp22x_pins[] = {
e1190083 QS	77	PINCTRL_PIN(0, "GPIO0"),
	78	PINCTRL_PIN(1, "GPIO1"),
	79	};
	80
23f75d7d QS	81	static const struct axp20x_pctrl_desc axp20x_data = {
	82	.pins = axp209_pins,
	83	.npins = ARRAY_SIZE(axp209_pins),
	84	.ldo_mask = BIT(0) \| BIT(1),
	85	.adc_mask = BIT(0) \| BIT(1),
48e706fb	86	.gpio_status_offset = 4,
a0a4b4c2	87	.adc_mux = AXP20X_MUX_ADC,
f72f4b44 MR	88	};
f72f4b44 MR	89
d4c0b614 SH	90	static const struct axp20x_pctrl_desc axp22x_data = {
	91	.pins = axp22x_pins,
	92	.npins = ARRAY_SIZE(axp22x_pins),
	93	.ldo_mask = BIT(0) \| BIT(1),
	94	.gpio_status_offset = 0,
	95	};
	96
e1190083	97	static const struct axp20x_pctrl_desc axp813_data = {
d4c0b614 SH	98	.pins = axp22x_pins,
d4c0b614 SH	99	.npins = ARRAY_SIZE(axp22x_pins),
e1190083 QS	100	.ldo_mask = BIT(0) \| BIT(1),
	101	.adc_mask = BIT(0),
	102	.gpio_status_offset = 0,
	103	.adc_mux = AXP813_MUX_ADC,
	104	};
	105
3cac991e	106	static int axp20x_gpio_get_reg(unsigned int offset)
f72f4b44 MR	107	{
	108	switch (offset) {
	109	case 0:
	110	return AXP20X_GPIO0_CTRL;
	111	case 1:
	112	return AXP20X_GPIO1_CTRL;
	113	case 2:
	114	return AXP20X_GPIO2_CTRL;
	115	}
	116
	117	return -EINVAL;
	118	}
	119
3cac991e	120	static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
f72f4b44	121	{
23f75d7d	122	return pinctrl_gpio_direction_input(chip->base + offset);
f72f4b44 MR	123	}
f72f4b44 MR	124
3cac991e	125	static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
f72f4b44	126	{
d242e60c	127	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44	128	unsigned int val;
1d2b2ac0	129	int ret;
f72f4b44	130
d242e60c	131	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
f72f4b44 MR	132	if (ret)
	133	return ret;
	134
48e706fb	135	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
f72f4b44 MR	136	}
f72f4b44 MR	137
3cac991e QS	138	static int axp20x_gpio_get_direction(struct gpio_chip *chip,
3cac991e QS	139	unsigned int offset)
81d3753d	140	{
d242e60c	141	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
81d3753d MR	142	unsigned int val;
	143	int reg, ret;
	144
	145	reg = axp20x_gpio_get_reg(offset);
	146	if (reg < 0)
	147	return reg;
	148
d242e60c	149	ret = regmap_read(pctl->regmap, reg, &val);
81d3753d MR	150	if (ret)
	151	return ret;
	152
	153	/*
	154	* This shouldn't really happen if the pin is in use already,
	155	* or if it's not in use yet, it doesn't matter since we're
	156	* going to change the value soon anyway. Default to output.
	157	*/
	158	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
3c827873	159	return GPIO_LINE_DIRECTION_OUT;
81d3753d MR	160
	161	/*
	162	* The GPIO directions are the three lowest values.
	163	* 2 is input, 0 and 1 are output
	164	*/
3c827873 MV	165	if (val & 2)
	166	return GPIO_LINE_DIRECTION_IN;
	167
	168	return GPIO_LINE_DIRECTION_OUT;
81d3753d MR	169	}
81d3753d MR	170
3cac991e	171	static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
f72f4b44	172	int value)
23f75d7d QS	173	{
	174	chip->set(chip, offset, value);
	175
	176	return 0;
	177	}
	178
	179	static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
	180	int value)
f72f4b44	181	{
d242e60c	182	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44 MR	183	int reg;
f72f4b44 MR	184
23f75d7d QS	185	reg = axp20x_gpio_get_reg(offset);
	186	if (reg < 0)
	187	return;
	188
d242e60c	189	regmap_update_bits(pctl->regmap, reg,
23f75d7d QS	190	AXP20X_GPIO_FUNCTIONS,
	191	value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
	192	AXP20X_GPIO_FUNCTION_OUT_LOW);
	193	}
	194
	195	static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
	196	u8 config)
	197	{
d242e60c	198	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	199	int reg;
23f75d7d QS	200
f72f4b44 MR	201	reg = axp20x_gpio_get_reg(offset);
	202	if (reg < 0)
	203	return reg;
	204
d242e60c	205	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
23f75d7d	206	config);
f72f4b44 MR	207	}
f72f4b44 MR	208
23f75d7d QS	209	static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
23f75d7d QS	210	{
d242e60c	211	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	212
d242e60c	213	return ARRAY_SIZE(pctl->funcs);
23f75d7d QS	214	}
	215
	216	static const char axp20x_pmx_func_name(struct pinctrl_dev pctldev,
	217	unsigned int selector)
	218	{
d242e60c	219	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	220
d242e60c	221	return pctl->funcs[selector].name;
23f75d7d QS	222	}
	223
	224	static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
	225	unsigned int selector,
	226	const char * const **groups,
	227	unsigned int *num_groups)
	228	{
d242e60c	229	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	230
d242e60c QS	231	*groups = pctl->funcs[selector].groups;
d242e60c QS	232	*num_groups = pctl->funcs[selector].ngroups;
23f75d7d QS	233
	234	return 0;
	235	}
	236
	237	static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
	238	unsigned int function, unsigned int group)
	239	{
d242e60c	240	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	241	unsigned int mask;
	242
	243	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	244	if (function <= AXP20X_FUNC_GPIO_IN)
	245	return axp20x_pmx_set(pctldev, group,
d242e60c	246	pctl->funcs[function].muxval);
23f75d7d QS	247
23f75d7d QS	248	if (function == AXP20X_FUNC_LDO)
d242e60c	249	mask = pctl->desc->ldo_mask;
23f75d7d	250	else
d242e60c	251	mask = pctl->desc->adc_mask;
23f75d7d QS	252
	253	if (!(BIT(group) & mask))
	254	return -EINVAL;
	255
	256	/*
	257	* We let the regulator framework handle the LDO muxing as muxing bits
	258	* are basically also regulators on/off bits. It's better not to enforce
	259	* any state of the regulator when selecting LDO mux so that we don't
	260	* interfere with the regulator driver.
	261	*/
	262	if (function == AXP20X_FUNC_LDO)
	263	return 0;
	264
d242e60c	265	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
23f75d7d QS	266	}
	267
	268	static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
	269	struct pinctrl_gpio_range *range,
	270	unsigned int offset, bool input)
	271	{
d242e60c	272	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	273
	274	if (input)
	275	return axp20x_pmx_set(pctldev, offset,
d242e60c	276	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
23f75d7d QS	277
23f75d7d QS	278	return axp20x_pmx_set(pctldev, offset,
d242e60c	279	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
23f75d7d QS	280	}
	281
	282	static const struct pinmux_ops axp20x_pmx_ops = {
	283	.get_functions_count = axp20x_pmx_func_cnt,
	284	.get_function_name = axp20x_pmx_func_name,
	285	.get_function_groups = axp20x_pmx_func_groups,
	286	.set_mux = axp20x_pmx_set_mux,
	287	.gpio_set_direction = axp20x_pmx_gpio_set_direction,
	288	.strict = true,
	289	};
	290
	291	static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
	292	{
d242e60c	293	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	294
d242e60c	295	return pctl->desc->npins;
23f75d7d QS	296	}
	297
	298	static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
	299	const unsigned int *pins, unsigned int num_pins)
	300	{
d242e60c	301	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	302
d242e60c	303	pins = (unsigned int )&pctl->desc->pins[selector];
23f75d7d QS	304	*num_pins = 1;
	305
	306	return 0;
	307	}
	308
	309	static const char axp20x_group_name(struct pinctrl_dev pctldev,
	310	unsigned int selector)
f72f4b44	311	{
d242e60c	312	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	313
d242e60c	314	return pctl->desc->pins[selector].name;
23f75d7d QS	315	}
	316
	317	static const struct pinctrl_ops axp20x_pctrl_ops = {
	318	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
	319	.dt_free_map = pinconf_generic_dt_free_map,
	320	.get_groups_count = axp20x_groups_cnt,
	321	.get_group_name = axp20x_group_name,
	322	.get_group_pins = axp20x_group_pins,
	323	};
	324
504c7697	325	static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
23f75d7d QS	326	unsigned int mask_len,
	327	struct axp20x_pinctrl_function *func,
	328	const struct pinctrl_pin_desc *pins)
	329	{
	330	unsigned long int mask_cpy = mask;
	331	const char **group;
	332	unsigned int ngroups = hweight8(mask);
	333	int bit;
	334
	335	func->ngroups = ngroups;
	336	if (func->ngroups > 0) {
a86854d0 KC	337	func->groups = devm_kcalloc(dev,
a86854d0 KC	338	ngroups, sizeof(const char *),
23f75d7d	339	GFP_KERNEL);
504c7697 AV	340	if (!func->groups)
504c7697 AV	341	return -ENOMEM;
23f75d7d QS	342	group = func->groups;
	343	for_each_set_bit(bit, &mask_cpy, mask_len) {
	344	*group = pins[bit].name;
	345	group++;
	346	}
	347	}
504c7697 AV	348
504c7697 AV	349	return 0;
23f75d7d QS	350	}
23f75d7d QS	351
504c7697	352	static int axp20x_build_funcs_groups(struct platform_device *pdev)
23f75d7d	353	{
d242e60c	354	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
504c7697	355	int i, ret, pin, npins = pctl->desc->npins;
d242e60c QS	356
	357	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	358	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	359	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	360	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	361	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
23f75d7d QS	362	/*
	363	* Muxval for LDO is useless as we won't use it.
	364	* See comment in axp20x_pmx_set_mux.
	365	*/
d242e60c	366	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
a0a4b4c2	367	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
23f75d7d QS	368
	369	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	370	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
d242e60c	371	pctl->funcs[i].ngroups = npins;
a86854d0 KC	372	pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
a86854d0 KC	373	npins, sizeof(char *),
23f75d7d	374	GFP_KERNEL);
1adc90c7 AP	375	if (!pctl->funcs[i].groups)
1adc90c7 AP	376	return -ENOMEM;
23f75d7d	377	for (pin = 0; pin < npins; pin++)
d242e60c	378	pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
23f75d7d QS	379	}
23f75d7d QS	380
504c7697	381	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
d242e60c QS	382	npins, &pctl->funcs[AXP20X_FUNC_LDO],
d242e60c QS	383	pctl->desc->pins);
504c7697 AV	384	if (ret)
504c7697 AV	385	return ret;
23f75d7d	386
504c7697	387	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
d242e60c QS	388	npins, &pctl->funcs[AXP20X_FUNC_ADC],
d242e60c QS	389	pctl->desc->pins);
504c7697 AV	390	if (ret)
	391	return ret;
	392
	393	return 0;
f72f4b44 MR	394	}
f72f4b44 MR	395
e1190083 QS	396	static const struct of_device_id axp20x_pctl_match[] = {
e1190083 QS	397	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
d4c0b614	398	{ .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
e1190083 QS	399	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	400	{ }
	401	};
	402	MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
	403
d242e60c	404	static int axp20x_pctl_probe(struct platform_device *pdev)
f72f4b44 MR	405	{
f72f4b44 MR	406	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
d242e60c	407	struct axp20x_pctl *pctl;
e1190083	408	struct device *dev = &pdev->dev;
23f75d7d	409	struct pinctrl_desc *pctrl_desc;
f72f4b44 MR	410	int ret;
	411
	412	if (!of_device_is_available(pdev->dev.of_node))
	413	return -ENODEV;
	414
	415	if (!axp20x) {
	416	dev_err(&pdev->dev, "Parent drvdata not set\n");
	417	return -EINVAL;
	418	}
	419
d242e60c QS	420	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
d242e60c QS	421	if (!pctl)
f72f4b44 MR	422	return -ENOMEM;
f72f4b44 MR	423
d242e60c QS	424	pctl->chip.base = -1;
	425	pctl->chip.can_sleep = true;
	426	pctl->chip.request = gpiochip_generic_request;
	427	pctl->chip.free = gpiochip_generic_free;
	428	pctl->chip.parent = &pdev->dev;
	429	pctl->chip.label = dev_name(&pdev->dev);
	430	pctl->chip.owner = THIS_MODULE;
	431	pctl->chip.get = axp20x_gpio_get;
	432	pctl->chip.get_direction = axp20x_gpio_get_direction;
	433	pctl->chip.set = axp20x_gpio_set;
	434	pctl->chip.direction_input = axp20x_gpio_input;
	435	pctl->chip.direction_output = axp20x_gpio_output;
d242e60c	436
9b8ee3c0	437	pctl->desc = of_device_get_match_data(dev);
a0498152 QS	438
	439	pctl->chip.ngpio = pctl->desc->npins;
	440
d242e60c QS	441	pctl->regmap = axp20x->regmap;
	442	pctl->dev = &pdev->dev;
	443
	444	platform_set_drvdata(pdev, pctl);
23f75d7d	445
504c7697 AV	446	ret = axp20x_build_funcs_groups(pdev);
	447	if (ret) {
	448	dev_err(&pdev->dev, "failed to build groups\n");
	449	return ret;
	450	}
23f75d7d QS	451
	452	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	453	if (!pctrl_desc)
	454	return -ENOMEM;
	455
	456	pctrl_desc->name = dev_name(&pdev->dev);
	457	pctrl_desc->owner = THIS_MODULE;
d242e60c QS	458	pctrl_desc->pins = pctl->desc->pins;
d242e60c QS	459	pctrl_desc->npins = pctl->desc->npins;
23f75d7d QS	460	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	461	pctrl_desc->pmxops = &axp20x_pmx_ops;
	462
d242e60c QS	463	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
d242e60c QS	464	if (IS_ERR(pctl->pctl_dev)) {
23f75d7d	465	dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
d242e60c	466	return PTR_ERR(pctl->pctl_dev);
23f75d7d	467	}
f72f4b44	468
d242e60c	469	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
f72f4b44 MR	470	if (ret) {
	471	dev_err(&pdev->dev, "Failed to register GPIO chip\n");
	472	return ret;
	473	}
	474
d242e60c QS	475	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
	476	pctl->desc->pins->number,
	477	pctl->desc->pins->number,
	478	pctl->desc->npins);
23f75d7d QS	479	if (ret) {
	480	dev_err(&pdev->dev, "failed to add pin range\n");
	481	return ret;
	482	}
	483
	484	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
f72f4b44 MR	485
	486	return 0;
	487	}
	488
d242e60c QS	489	static struct platform_driver axp20x_pctl_driver = {
d242e60c QS	490	.probe = axp20x_pctl_probe,
f72f4b44 MR	491	.driver = {
f72f4b44 MR	492	.name = "axp20x-gpio",
d242e60c	493	.of_match_table = axp20x_pctl_match,
f72f4b44 MR	494	},
	495	};
	496
d242e60c	497	module_platform_driver(axp20x_pctl_driver);
f72f4b44 MR	498
f72f4b44 MR	499	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
23f75d7d QS	500	MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
23f75d7d QS	501	MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
f72f4b44	502	MODULE_LICENSE("GPL");