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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
f72f4b44 | 2 | /* |
23f75d7d | 3 | * AXP20x pinctrl and GPIO driver |
f72f4b44 MR |
4 | * |
5 | * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> | |
23f75d7d | 6 | * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com> |
f72f4b44 MR |
7 | */ |
8 | ||
9 | #include <linux/bitops.h> | |
10 | #include <linux/device.h> | |
11 | #include <linux/gpio/driver.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/mfd/axp20x.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/regmap.h> | |
20 | #include <linux/slab.h> | |
21 | ||
20ce9552 AS |
22 | #include <linux/pinctrl/consumer.h> |
23 | #include <linux/pinctrl/pinconf-generic.h> | |
24 | #include <linux/pinctrl/pinctrl.h> | |
25 | #include <linux/pinctrl/pinmux.h> | |
26 | ||
f72f4b44 MR |
27 | #define AXP20X_GPIO_FUNCTIONS 0x7 |
28 | #define AXP20X_GPIO_FUNCTION_OUT_LOW 0 | |
29 | #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1 | |
30 | #define AXP20X_GPIO_FUNCTION_INPUT 2 | |
31 | ||
44825e5e JM |
32 | #define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1) |
33 | #define AXP20X_GPIO3_FUNCTION_OUT_LOW 0 | |
34 | #define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2 | |
35 | #define AXP20X_GPIO3_FUNCTION_INPUT 4 | |
36 | ||
23f75d7d QS |
37 | #define AXP20X_FUNC_GPIO_OUT 0 |
38 | #define AXP20X_FUNC_GPIO_IN 1 | |
39 | #define AXP20X_FUNC_LDO 2 | |
40 | #define AXP20X_FUNC_ADC 3 | |
41 | #define AXP20X_FUNCS_NB 4 | |
42 | ||
43 | #define AXP20X_MUX_GPIO_OUT 0 | |
44 | #define AXP20X_MUX_GPIO_IN BIT(1) | |
45 | #define AXP20X_MUX_ADC BIT(2) | |
46 | ||
e1190083 QS |
47 | #define AXP813_MUX_ADC (BIT(2) | BIT(0)) |
48 | ||
23f75d7d QS |
49 | struct axp20x_pctrl_desc { |
50 | const struct pinctrl_pin_desc *pins; | |
51 | unsigned int npins; | |
52 | /* Stores the pins supporting LDO function. Bit offset is pin number. */ | |
53 | u8 ldo_mask; | |
54 | /* Stores the pins supporting ADC function. Bit offset is pin number. */ | |
55 | u8 adc_mask; | |
48e706fb | 56 | u8 gpio_status_offset; |
a0a4b4c2 | 57 | u8 adc_mux; |
23f75d7d QS |
58 | }; |
59 | ||
60 | struct axp20x_pinctrl_function { | |
61 | const char *name; | |
62 | unsigned int muxval; | |
63 | const char **groups; | |
64 | unsigned int ngroups; | |
65 | }; | |
66 | ||
d242e60c | 67 | struct axp20x_pctl { |
f72f4b44 MR |
68 | struct gpio_chip chip; |
69 | struct regmap *regmap; | |
23f75d7d QS |
70 | struct pinctrl_dev *pctl_dev; |
71 | struct device *dev; | |
72 | const struct axp20x_pctrl_desc *desc; | |
73 | struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB]; | |
74 | }; | |
75 | ||
76 | static const struct pinctrl_pin_desc axp209_pins[] = { | |
77 | PINCTRL_PIN(0, "GPIO0"), | |
78 | PINCTRL_PIN(1, "GPIO1"), | |
79 | PINCTRL_PIN(2, "GPIO2"), | |
44825e5e | 80 | PINCTRL_PIN(3, "GPIO3"), |
23f75d7d QS |
81 | }; |
82 | ||
d4c0b614 | 83 | static const struct pinctrl_pin_desc axp22x_pins[] = { |
e1190083 QS |
84 | PINCTRL_PIN(0, "GPIO0"), |
85 | PINCTRL_PIN(1, "GPIO1"), | |
86 | }; | |
87 | ||
23f75d7d QS |
88 | static const struct axp20x_pctrl_desc axp20x_data = { |
89 | .pins = axp209_pins, | |
90 | .npins = ARRAY_SIZE(axp209_pins), | |
91 | .ldo_mask = BIT(0) | BIT(1), | |
92 | .adc_mask = BIT(0) | BIT(1), | |
48e706fb | 93 | .gpio_status_offset = 4, |
a0a4b4c2 | 94 | .adc_mux = AXP20X_MUX_ADC, |
f72f4b44 MR |
95 | }; |
96 | ||
d4c0b614 SH |
97 | static const struct axp20x_pctrl_desc axp22x_data = { |
98 | .pins = axp22x_pins, | |
99 | .npins = ARRAY_SIZE(axp22x_pins), | |
100 | .ldo_mask = BIT(0) | BIT(1), | |
101 | .gpio_status_offset = 0, | |
102 | }; | |
103 | ||
e1190083 | 104 | static const struct axp20x_pctrl_desc axp813_data = { |
d4c0b614 SH |
105 | .pins = axp22x_pins, |
106 | .npins = ARRAY_SIZE(axp22x_pins), | |
e1190083 QS |
107 | .ldo_mask = BIT(0) | BIT(1), |
108 | .adc_mask = BIT(0), | |
109 | .gpio_status_offset = 0, | |
110 | .adc_mux = AXP813_MUX_ADC, | |
111 | }; | |
112 | ||
3cac991e | 113 | static int axp20x_gpio_get_reg(unsigned int offset) |
f72f4b44 MR |
114 | { |
115 | switch (offset) { | |
116 | case 0: | |
117 | return AXP20X_GPIO0_CTRL; | |
118 | case 1: | |
119 | return AXP20X_GPIO1_CTRL; | |
120 | case 2: | |
121 | return AXP20X_GPIO2_CTRL; | |
122 | } | |
123 | ||
124 | return -EINVAL; | |
125 | } | |
126 | ||
3cac991e | 127 | static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset) |
f72f4b44 | 128 | { |
d242e60c | 129 | struct axp20x_pctl *pctl = gpiochip_get_data(chip); |
f72f4b44 | 130 | unsigned int val; |
1d2b2ac0 | 131 | int ret; |
f72f4b44 | 132 | |
44825e5e JM |
133 | /* AXP209 has GPIO3 status sharing the settings register */ |
134 | if (offset == 3) { | |
135 | ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val); | |
136 | if (ret) | |
137 | return ret; | |
138 | return !!(val & BIT(0)); | |
139 | } | |
140 | ||
d242e60c | 141 | ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val); |
f72f4b44 MR |
142 | if (ret) |
143 | return ret; | |
144 | ||
48e706fb | 145 | return !!(val & BIT(offset + pctl->desc->gpio_status_offset)); |
f72f4b44 MR |
146 | } |
147 | ||
3cac991e QS |
148 | static int axp20x_gpio_get_direction(struct gpio_chip *chip, |
149 | unsigned int offset) | |
81d3753d | 150 | { |
d242e60c | 151 | struct axp20x_pctl *pctl = gpiochip_get_data(chip); |
81d3753d MR |
152 | unsigned int val; |
153 | int reg, ret; | |
154 | ||
44825e5e JM |
155 | /* AXP209 GPIO3 settings have a different layout */ |
156 | if (offset == 3) { | |
157 | ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val); | |
158 | if (ret) | |
159 | return ret; | |
160 | if (val & AXP20X_GPIO3_FUNCTION_INPUT) | |
161 | return GPIO_LINE_DIRECTION_IN; | |
162 | ||
163 | return GPIO_LINE_DIRECTION_OUT; | |
164 | } | |
165 | ||
81d3753d MR |
166 | reg = axp20x_gpio_get_reg(offset); |
167 | if (reg < 0) | |
168 | return reg; | |
169 | ||
d242e60c | 170 | ret = regmap_read(pctl->regmap, reg, &val); |
81d3753d MR |
171 | if (ret) |
172 | return ret; | |
173 | ||
174 | /* | |
175 | * This shouldn't really happen if the pin is in use already, | |
176 | * or if it's not in use yet, it doesn't matter since we're | |
177 | * going to change the value soon anyway. Default to output. | |
178 | */ | |
179 | if ((val & AXP20X_GPIO_FUNCTIONS) > 2) | |
3c827873 | 180 | return GPIO_LINE_DIRECTION_OUT; |
81d3753d MR |
181 | |
182 | /* | |
183 | * The GPIO directions are the three lowest values. | |
184 | * 2 is input, 0 and 1 are output | |
185 | */ | |
3c827873 MV |
186 | if (val & 2) |
187 | return GPIO_LINE_DIRECTION_IN; | |
188 | ||
189 | return GPIO_LINE_DIRECTION_OUT; | |
81d3753d MR |
190 | } |
191 | ||
3cac991e | 192 | static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset, |
f72f4b44 | 193 | int value) |
23f75d7d QS |
194 | { |
195 | chip->set(chip, offset, value); | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
201 | int value) | |
f72f4b44 | 202 | { |
d242e60c | 203 | struct axp20x_pctl *pctl = gpiochip_get_data(chip); |
f72f4b44 MR |
204 | int reg; |
205 | ||
44825e5e JM |
206 | /* AXP209 has GPIO3 status sharing the settings register */ |
207 | if (offset == 3) { | |
208 | regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL, | |
209 | AXP20X_GPIO3_FUNCTIONS, | |
210 | value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH : | |
211 | AXP20X_GPIO3_FUNCTION_OUT_LOW); | |
212 | return; | |
213 | } | |
214 | ||
23f75d7d QS |
215 | reg = axp20x_gpio_get_reg(offset); |
216 | if (reg < 0) | |
217 | return; | |
218 | ||
d242e60c | 219 | regmap_update_bits(pctl->regmap, reg, |
23f75d7d QS |
220 | AXP20X_GPIO_FUNCTIONS, |
221 | value ? AXP20X_GPIO_FUNCTION_OUT_HIGH : | |
222 | AXP20X_GPIO_FUNCTION_OUT_LOW); | |
223 | } | |
224 | ||
225 | static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset, | |
226 | u8 config) | |
227 | { | |
d242e60c | 228 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
23f75d7d QS |
229 | int reg; |
230 | ||
44825e5e JM |
231 | /* AXP209 GPIO3 settings have a different layout */ |
232 | if (offset == 3) { | |
233 | return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL, | |
234 | AXP20X_GPIO3_FUNCTIONS, | |
235 | config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW : | |
236 | AXP20X_GPIO3_FUNCTION_INPUT); | |
237 | } | |
238 | ||
f72f4b44 MR |
239 | reg = axp20x_gpio_get_reg(offset); |
240 | if (reg < 0) | |
241 | return reg; | |
242 | ||
d242e60c | 243 | return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS, |
23f75d7d | 244 | config); |
f72f4b44 MR |
245 | } |
246 | ||
23f75d7d QS |
247 | static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev) |
248 | { | |
d242e60c | 249 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
23f75d7d | 250 | |
d242e60c | 251 | return ARRAY_SIZE(pctl->funcs); |
23f75d7d QS |
252 | } |
253 | ||
254 | static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev, | |
255 | unsigned int selector) | |
256 | { | |
d242e60c | 257 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
23f75d7d | 258 | |
d242e60c | 259 | return pctl->funcs[selector].name; |
23f75d7d QS |
260 | } |
261 | ||
262 | static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev, | |
263 | unsigned int selector, | |
264 | const char * const **groups, | |
265 | unsigned int *num_groups) | |
266 | { | |
d242e60c | 267 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
23f75d7d | 268 | |
d242e60c QS |
269 | *groups = pctl->funcs[selector].groups; |
270 | *num_groups = pctl->funcs[selector].ngroups; | |
23f75d7d QS |
271 | |
272 | return 0; | |
273 | } | |
274 | ||
275 | static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev, | |
276 | unsigned int function, unsigned int group) | |
277 | { | |
d242e60c | 278 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
23f75d7d QS |
279 | unsigned int mask; |
280 | ||
281 | /* Every pin supports GPIO_OUT and GPIO_IN functions */ | |
282 | if (function <= AXP20X_FUNC_GPIO_IN) | |
283 | return axp20x_pmx_set(pctldev, group, | |
d242e60c | 284 | pctl->funcs[function].muxval); |
23f75d7d QS |
285 | |
286 | if (function == AXP20X_FUNC_LDO) | |
d242e60c | 287 | mask = pctl->desc->ldo_mask; |
23f75d7d | 288 | else |
d242e60c | 289 | mask = pctl->desc->adc_mask; |
23f75d7d QS |
290 | |
291 | if (!(BIT(group) & mask)) | |
292 | return -EINVAL; | |
293 | ||
294 | /* | |
295 | * We let the regulator framework handle the LDO muxing as muxing bits | |
296 | * are basically also regulators on/off bits. It's better not to enforce | |
297 | * any state of the regulator when selecting LDO mux so that we don't | |
298 | * interfere with the regulator driver. | |
299 | */ | |
300 | if (function == AXP20X_FUNC_LDO) | |
301 | return 0; | |
302 | ||
d242e60c | 303 | return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval); |
23f75d7d QS |
304 | } |
305 | ||
306 | static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
307 | struct pinctrl_gpio_range *range, | |
308 | unsigned int offset, bool input) | |
309 | { | |
d242e60c | 310 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
23f75d7d QS |
311 | |
312 | if (input) | |
313 | return axp20x_pmx_set(pctldev, offset, | |
d242e60c | 314 | pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval); |
23f75d7d QS |
315 | |
316 | return axp20x_pmx_set(pctldev, offset, | |
d242e60c | 317 | pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval); |
23f75d7d QS |
318 | } |
319 | ||
320 | static const struct pinmux_ops axp20x_pmx_ops = { | |
321 | .get_functions_count = axp20x_pmx_func_cnt, | |
322 | .get_function_name = axp20x_pmx_func_name, | |
323 | .get_function_groups = axp20x_pmx_func_groups, | |
324 | .set_mux = axp20x_pmx_set_mux, | |
325 | .gpio_set_direction = axp20x_pmx_gpio_set_direction, | |
326 | .strict = true, | |
327 | }; | |
328 | ||
329 | static int axp20x_groups_cnt(struct pinctrl_dev *pctldev) | |
330 | { | |
d242e60c | 331 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
23f75d7d | 332 | |
d242e60c | 333 | return pctl->desc->npins; |
23f75d7d QS |
334 | } |
335 | ||
336 | static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, | |
337 | const unsigned int **pins, unsigned int *num_pins) | |
338 | { | |
d242e60c | 339 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
23f75d7d | 340 | |
d242e60c | 341 | *pins = (unsigned int *)&pctl->desc->pins[selector]; |
23f75d7d QS |
342 | *num_pins = 1; |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
347 | static const char *axp20x_group_name(struct pinctrl_dev *pctldev, | |
348 | unsigned int selector) | |
f72f4b44 | 349 | { |
d242e60c | 350 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
23f75d7d | 351 | |
d242e60c | 352 | return pctl->desc->pins[selector].name; |
23f75d7d QS |
353 | } |
354 | ||
355 | static const struct pinctrl_ops axp20x_pctrl_ops = { | |
356 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
357 | .dt_free_map = pinconf_generic_dt_free_map, | |
358 | .get_groups_count = axp20x_groups_cnt, | |
359 | .get_group_name = axp20x_group_name, | |
360 | .get_group_pins = axp20x_group_pins, | |
361 | }; | |
362 | ||
504c7697 | 363 | static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask, |
23f75d7d QS |
364 | unsigned int mask_len, |
365 | struct axp20x_pinctrl_function *func, | |
366 | const struct pinctrl_pin_desc *pins) | |
367 | { | |
368 | unsigned long int mask_cpy = mask; | |
369 | const char **group; | |
370 | unsigned int ngroups = hweight8(mask); | |
371 | int bit; | |
372 | ||
373 | func->ngroups = ngroups; | |
374 | if (func->ngroups > 0) { | |
a86854d0 KC |
375 | func->groups = devm_kcalloc(dev, |
376 | ngroups, sizeof(const char *), | |
23f75d7d | 377 | GFP_KERNEL); |
504c7697 AV |
378 | if (!func->groups) |
379 | return -ENOMEM; | |
23f75d7d QS |
380 | group = func->groups; |
381 | for_each_set_bit(bit, &mask_cpy, mask_len) { | |
382 | *group = pins[bit].name; | |
383 | group++; | |
384 | } | |
385 | } | |
504c7697 AV |
386 | |
387 | return 0; | |
23f75d7d QS |
388 | } |
389 | ||
504c7697 | 390 | static int axp20x_build_funcs_groups(struct platform_device *pdev) |
23f75d7d | 391 | { |
d242e60c | 392 | struct axp20x_pctl *pctl = platform_get_drvdata(pdev); |
504c7697 | 393 | int i, ret, pin, npins = pctl->desc->npins; |
d242e60c QS |
394 | |
395 | pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out"; | |
396 | pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT; | |
397 | pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in"; | |
398 | pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN; | |
399 | pctl->funcs[AXP20X_FUNC_LDO].name = "ldo"; | |
23f75d7d QS |
400 | /* |
401 | * Muxval for LDO is useless as we won't use it. | |
402 | * See comment in axp20x_pmx_set_mux. | |
403 | */ | |
d242e60c | 404 | pctl->funcs[AXP20X_FUNC_ADC].name = "adc"; |
a0a4b4c2 | 405 | pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux; |
23f75d7d QS |
406 | |
407 | /* Every pin supports GPIO_OUT and GPIO_IN functions */ | |
408 | for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) { | |
d242e60c | 409 | pctl->funcs[i].ngroups = npins; |
a86854d0 KC |
410 | pctl->funcs[i].groups = devm_kcalloc(&pdev->dev, |
411 | npins, sizeof(char *), | |
23f75d7d | 412 | GFP_KERNEL); |
1adc90c7 AP |
413 | if (!pctl->funcs[i].groups) |
414 | return -ENOMEM; | |
23f75d7d | 415 | for (pin = 0; pin < npins; pin++) |
d242e60c | 416 | pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name; |
23f75d7d QS |
417 | } |
418 | ||
504c7697 | 419 | ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask, |
d242e60c QS |
420 | npins, &pctl->funcs[AXP20X_FUNC_LDO], |
421 | pctl->desc->pins); | |
504c7697 AV |
422 | if (ret) |
423 | return ret; | |
23f75d7d | 424 | |
504c7697 | 425 | ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask, |
d242e60c QS |
426 | npins, &pctl->funcs[AXP20X_FUNC_ADC], |
427 | pctl->desc->pins); | |
504c7697 AV |
428 | if (ret) |
429 | return ret; | |
430 | ||
431 | return 0; | |
f72f4b44 MR |
432 | } |
433 | ||
e1190083 QS |
434 | static const struct of_device_id axp20x_pctl_match[] = { |
435 | { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, }, | |
d4c0b614 | 436 | { .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, }, |
e1190083 QS |
437 | { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, }, |
438 | { } | |
439 | }; | |
440 | MODULE_DEVICE_TABLE(of, axp20x_pctl_match); | |
441 | ||
d242e60c | 442 | static int axp20x_pctl_probe(struct platform_device *pdev) |
f72f4b44 MR |
443 | { |
444 | struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); | |
d242e60c | 445 | struct axp20x_pctl *pctl; |
e1190083 | 446 | struct device *dev = &pdev->dev; |
23f75d7d | 447 | struct pinctrl_desc *pctrl_desc; |
f72f4b44 MR |
448 | int ret; |
449 | ||
450 | if (!of_device_is_available(pdev->dev.of_node)) | |
451 | return -ENODEV; | |
452 | ||
453 | if (!axp20x) { | |
454 | dev_err(&pdev->dev, "Parent drvdata not set\n"); | |
455 | return -EINVAL; | |
456 | } | |
457 | ||
d242e60c QS |
458 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); |
459 | if (!pctl) | |
f72f4b44 MR |
460 | return -ENOMEM; |
461 | ||
d242e60c QS |
462 | pctl->chip.base = -1; |
463 | pctl->chip.can_sleep = true; | |
464 | pctl->chip.request = gpiochip_generic_request; | |
465 | pctl->chip.free = gpiochip_generic_free; | |
466 | pctl->chip.parent = &pdev->dev; | |
467 | pctl->chip.label = dev_name(&pdev->dev); | |
468 | pctl->chip.owner = THIS_MODULE; | |
469 | pctl->chip.get = axp20x_gpio_get; | |
470 | pctl->chip.get_direction = axp20x_gpio_get_direction; | |
471 | pctl->chip.set = axp20x_gpio_set; | |
36077c86 | 472 | pctl->chip.direction_input = pinctrl_gpio_direction_input; |
d242e60c | 473 | pctl->chip.direction_output = axp20x_gpio_output; |
d242e60c | 474 | |
9b8ee3c0 | 475 | pctl->desc = of_device_get_match_data(dev); |
a0498152 QS |
476 | |
477 | pctl->chip.ngpio = pctl->desc->npins; | |
478 | ||
d242e60c QS |
479 | pctl->regmap = axp20x->regmap; |
480 | pctl->dev = &pdev->dev; | |
481 | ||
482 | platform_set_drvdata(pdev, pctl); | |
23f75d7d | 483 | |
504c7697 AV |
484 | ret = axp20x_build_funcs_groups(pdev); |
485 | if (ret) { | |
486 | dev_err(&pdev->dev, "failed to build groups\n"); | |
487 | return ret; | |
488 | } | |
23f75d7d QS |
489 | |
490 | pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL); | |
491 | if (!pctrl_desc) | |
492 | return -ENOMEM; | |
493 | ||
494 | pctrl_desc->name = dev_name(&pdev->dev); | |
495 | pctrl_desc->owner = THIS_MODULE; | |
d242e60c QS |
496 | pctrl_desc->pins = pctl->desc->pins; |
497 | pctrl_desc->npins = pctl->desc->npins; | |
23f75d7d QS |
498 | pctrl_desc->pctlops = &axp20x_pctrl_ops; |
499 | pctrl_desc->pmxops = &axp20x_pmx_ops; | |
500 | ||
d242e60c QS |
501 | pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); |
502 | if (IS_ERR(pctl->pctl_dev)) { | |
23f75d7d | 503 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); |
d242e60c | 504 | return PTR_ERR(pctl->pctl_dev); |
23f75d7d | 505 | } |
f72f4b44 | 506 | |
d242e60c | 507 | ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl); |
f72f4b44 MR |
508 | if (ret) { |
509 | dev_err(&pdev->dev, "Failed to register GPIO chip\n"); | |
510 | return ret; | |
511 | } | |
512 | ||
d242e60c QS |
513 | ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev), |
514 | pctl->desc->pins->number, | |
515 | pctl->desc->pins->number, | |
516 | pctl->desc->npins); | |
23f75d7d QS |
517 | if (ret) { |
518 | dev_err(&pdev->dev, "failed to add pin range\n"); | |
519 | return ret; | |
520 | } | |
521 | ||
522 | dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n"); | |
f72f4b44 MR |
523 | |
524 | return 0; | |
525 | } | |
526 | ||
d242e60c QS |
527 | static struct platform_driver axp20x_pctl_driver = { |
528 | .probe = axp20x_pctl_probe, | |
f72f4b44 MR |
529 | .driver = { |
530 | .name = "axp20x-gpio", | |
d242e60c | 531 | .of_match_table = axp20x_pctl_match, |
f72f4b44 MR |
532 | }, |
533 | }; | |
534 | ||
d242e60c | 535 | module_platform_driver(axp20x_pctl_driver); |
f72f4b44 MR |
536 | |
537 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
23f75d7d QS |
538 | MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>"); |
539 | MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver"); | |
f72f4b44 | 540 | MODULE_LICENSE("GPL"); |