[linux-block.git] / drivers / pinctrl / pinctrl-axp209.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * AXP20x pinctrl and GPIO driver
 *
 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
 */

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/axp20x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

#define AXP20X_GPIO_FUNCTIONS		0x7
#define AXP20X_GPIO_FUNCTION_OUT_LOW	0
#define AXP20X_GPIO_FUNCTION_OUT_HIGH	1
#define AXP20X_GPIO_FUNCTION_INPUT	2

#define AXP20X_FUNC_GPIO_OUT		0
#define AXP20X_FUNC_GPIO_IN		1
#define AXP20X_FUNC_LDO			2
#define AXP20X_FUNC_ADC			3
#define AXP20X_FUNCS_NB			4

#define AXP20X_MUX_GPIO_OUT		0
#define AXP20X_MUX_GPIO_IN		BIT(1)
#define AXP20X_MUX_ADC			BIT(2)

#define AXP813_MUX_ADC			(BIT(2) | BIT(0))

struct axp20x_pctrl_desc {
	const struct pinctrl_pin_desc	*pins;
	unsigned int			npins;
	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	u8				ldo_mask;
	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	u8				adc_mask;
	u8				gpio_status_offset;
	u8				adc_mux;
};

struct axp20x_pinctrl_function {
	const char	*name;
	unsigned int	muxval;
	const char	**groups;
	unsigned int	ngroups;
};

struct axp20x_pctl {
	struct gpio_chip	chip;
	struct regmap		*regmap;
	struct pinctrl_dev			*pctl_dev;
	struct device				*dev;
	const struct axp20x_pctrl_desc		*desc;
	struct axp20x_pinctrl_function		funcs[AXP20X_FUNCS_NB];
};

static const struct pinctrl_pin_desc axp209_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
	PINCTRL_PIN(2, "GPIO2"),
};

static const struct pinctrl_pin_desc axp22x_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
};

static const struct axp20x_pctrl_desc axp20x_data = {
	.pins	= axp209_pins,
	.npins	= ARRAY_SIZE(axp209_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0) | BIT(1),
	.gpio_status_offset = 4,
	.adc_mux = AXP20X_MUX_ADC,
};

static const struct axp20x_pctrl_desc axp22x_data = {
	.pins	= axp22x_pins,
	.npins	= ARRAY_SIZE(axp22x_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.gpio_status_offset = 0,
};

static const struct axp20x_pctrl_desc axp813_data = {
	.pins	= axp22x_pins,
	.npins	= ARRAY_SIZE(axp22x_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0),
	.gpio_status_offset = 0,
	.adc_mux = AXP813_MUX_ADC,
};

static int axp20x_gpio_get_reg(unsigned int offset)
{
	switch (offset) {
	case 0:
		return AXP20X_GPIO0_CTRL;
	case 1:
		return AXP20X_GPIO1_CTRL;
	case 2:
		return AXP20X_GPIO2_CTRL;
	}

	return -EINVAL;
}

static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
{
	return pinctrl_gpio_direction_input(chip->base + offset);
}

static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int ret;

	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
	if (ret)
		return ret;

	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
}

static int axp20x_gpio_get_direction(struct gpio_chip *chip,
				     unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int reg, ret;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	ret = regmap_read(pctl->regmap, reg, &val);
	if (ret)
		return ret;

	/*
	 * This shouldn't really happen if the pin is in use already,
	 * or if it's not in use yet, it doesn't matter since we're
	 * going to change the value soon anyway. Default to output.
	 */
	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
		return GPIO_LINE_DIRECTION_OUT;

	/*
	 * The GPIO directions are the three lowest values.
	 * 2 is input, 0 and 1 are output
	 */
	if (val & 2)
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
			      int value)
{
	chip->set(chip, offset, value);

	return 0;
}

static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
			    int value)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return;

	regmap_update_bits(pctl->regmap, reg,
			   AXP20X_GPIO_FUNCTIONS,
			   value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
			   AXP20X_GPIO_FUNCTION_OUT_LOW);
}

static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
			  u8 config)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
				  config);
}

static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return ARRAY_SIZE(pctl->funcs);
}

static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
					unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->funcs[selector].name;
}

static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
				  unsigned int selector,
				  const char * const **groups,
				  unsigned int *num_groups)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*groups = pctl->funcs[selector].groups;
	*num_groups = pctl->funcs[selector].ngroups;

	return 0;
}

static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
			      unsigned int function, unsigned int group)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	unsigned int mask;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	if (function <= AXP20X_FUNC_GPIO_IN)
		return axp20x_pmx_set(pctldev, group,
				      pctl->funcs[function].muxval);

	if (function == AXP20X_FUNC_LDO)
		mask = pctl->desc->ldo_mask;
	else
		mask = pctl->desc->adc_mask;

	if (!(BIT(group) & mask))
		return -EINVAL;

	/*
	 * We let the regulator framework handle the LDO muxing as muxing bits
	 * are basically also regulators on/off bits. It's better not to enforce
	 * any state of the regulator when selecting LDO mux so that we don't
	 * interfere with the regulator driver.
	 */
	if (function == AXP20X_FUNC_LDO)
		return 0;

	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
}

static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
					 struct pinctrl_gpio_range *range,
					 unsigned int offset, bool input)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	if (input)
		return axp20x_pmx_set(pctldev, offset,
				      pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);

	return axp20x_pmx_set(pctldev, offset,
			      pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
}

static const struct pinmux_ops axp20x_pmx_ops = {
	.get_functions_count	= axp20x_pmx_func_cnt,
	.get_function_name	= axp20x_pmx_func_name,
	.get_function_groups	= axp20x_pmx_func_groups,
	.set_mux		= axp20x_pmx_set_mux,
	.gpio_set_direction	= axp20x_pmx_gpio_set_direction,
	.strict			= true,
};

static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->npins;
}

static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
			     const unsigned int **pins, unsigned int *num_pins)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*pins = (unsigned int *)&pctl->desc->pins[selector];
	*num_pins = 1;

	return 0;
}

static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
				     unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->pins[selector].name;
}

static const struct pinctrl_ops axp20x_pctrl_ops = {
	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
	.dt_free_map		= pinconf_generic_dt_free_map,
	.get_groups_count	= axp20x_groups_cnt,
	.get_group_name		= axp20x_group_name,
	.get_group_pins		= axp20x_group_pins,
};

static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
					  unsigned int mask_len,
					  struct axp20x_pinctrl_function *func,
					  const struct pinctrl_pin_desc *pins)
{
	unsigned long int mask_cpy = mask;
	const char **group;
	unsigned int ngroups = hweight8(mask);
	int bit;

	func->ngroups = ngroups;
	if (func->ngroups > 0) {
		func->groups = devm_kcalloc(dev,
					    ngroups, sizeof(const char *),
					    GFP_KERNEL);
		if (!func->groups)
			return -ENOMEM;
		group = func->groups;
		for_each_set_bit(bit, &mask_cpy, mask_len) {
			*group = pins[bit].name;
			group++;
		}
	}

	return 0;
}

static int axp20x_build_funcs_groups(struct platform_device *pdev)
{
	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
	int i, ret, pin, npins = pctl->desc->npins;

	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
	/*
	 * Muxval for LDO is useless as we won't use it.
	 * See comment in axp20x_pmx_set_mux.
	 */
	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
		pctl->funcs[i].ngroups = npins;
		pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
						     npins, sizeof(char *),
						     GFP_KERNEL);
		if (!pctl->funcs[i].groups)
			return -ENOMEM;
		for (pin = 0; pin < npins; pin++)
			pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
	}

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_LDO],
				      pctl->desc->pins);
	if (ret)
		return ret;

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_ADC],
				      pctl->desc->pins);
	if (ret)
		return ret;

	return 0;
}

static const struct of_device_id axp20x_pctl_match[] = {
	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
	{ .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	{ }
};
MODULE_DEVICE_TABLE(of, axp20x_pctl_match);

static int axp20x_pctl_probe(struct platform_device *pdev)
{
	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
	struct axp20x_pctl *pctl;
	struct device *dev = &pdev->dev;
	struct pinctrl_desc *pctrl_desc;
	int ret;

	if (!of_device_is_available(pdev->dev.of_node))
		return -ENODEV;

	if (!axp20x) {
		dev_err(&pdev->dev, "Parent drvdata not set\n");
		return -EINVAL;
	}

	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
	if (!pctl)
		return -ENOMEM;

	pctl->chip.base			= -1;
	pctl->chip.can_sleep		= true;
	pctl->chip.request		= gpiochip_generic_request;
	pctl->chip.free			= gpiochip_generic_free;
	pctl->chip.parent		= &pdev->dev;
	pctl->chip.label		= dev_name(&pdev->dev);
	pctl->chip.owner		= THIS_MODULE;
	pctl->chip.get			= axp20x_gpio_get;
	pctl->chip.get_direction	= axp20x_gpio_get_direction;
	pctl->chip.set			= axp20x_gpio_set;
	pctl->chip.direction_input	= axp20x_gpio_input;
	pctl->chip.direction_output	= axp20x_gpio_output;

	pctl->desc = of_device_get_match_data(dev);

	pctl->chip.ngpio		= pctl->desc->npins;

	pctl->regmap = axp20x->regmap;
	pctl->dev = &pdev->dev;

	platform_set_drvdata(pdev, pctl);

	ret = axp20x_build_funcs_groups(pdev);
	if (ret) {
		dev_err(&pdev->dev, "failed to build groups\n");
		return ret;
	}

	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	if (!pctrl_desc)
		return -ENOMEM;

	pctrl_desc->name = dev_name(&pdev->dev);
	pctrl_desc->owner = THIS_MODULE;
	pctrl_desc->pins = pctl->desc->pins;
	pctrl_desc->npins = pctl->desc->npins;
	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	pctrl_desc->pmxops = &axp20x_pmx_ops;

	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
	if (IS_ERR(pctl->pctl_dev)) {
		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
		return PTR_ERR(pctl->pctl_dev);
	}

	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register GPIO chip\n");
		return ret;
	}

	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
				     pctl->desc->pins->number,
				     pctl->desc->pins->number,
				     pctl->desc->npins);
	if (ret) {
		dev_err(&pdev->dev, "failed to add pin range\n");
		return ret;
	}

	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");

	return 0;
}

static struct platform_driver axp20x_pctl_driver = {
	.probe		= axp20x_pctl_probe,
	.driver = {
		.name		= "axp20x-gpio",
		.of_match_table	= axp20x_pctl_match,
	},
};

module_platform_driver(axp20x_pctl_driver);

MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
f72f4b44	2	/*
23f75d7d	3	* AXP20x pinctrl and GPIO driver
f72f4b44 MR	4	*
f72f4b44 MR	5	* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
23f75d7d	6	* Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
f72f4b44 MR	7	*/
	8
	9	#include <linux/bitops.h>
	10	#include <linux/device.h>
	11	#include <linux/gpio/driver.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel.h>
	15	#include <linux/mfd/axp20x.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
e1190083	18	#include <linux/of_device.h>
f72f4b44 MR	19	#include <linux/platform_device.h>
	20	#include <linux/regmap.h>
	21	#include <linux/slab.h>
	22
20ce9552 AS	23	#include <linux/pinctrl/consumer.h>
	24	#include <linux/pinctrl/pinconf-generic.h>
	25	#include <linux/pinctrl/pinctrl.h>
	26	#include <linux/pinctrl/pinmux.h>
	27
f72f4b44 MR	28	#define AXP20X_GPIO_FUNCTIONS 0x7
	29	#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
	30	#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
	31	#define AXP20X_GPIO_FUNCTION_INPUT 2
	32
23f75d7d QS	33	#define AXP20X_FUNC_GPIO_OUT 0
	34	#define AXP20X_FUNC_GPIO_IN 1
	35	#define AXP20X_FUNC_LDO 2
	36	#define AXP20X_FUNC_ADC 3
	37	#define AXP20X_FUNCS_NB 4
	38
	39	#define AXP20X_MUX_GPIO_OUT 0
	40	#define AXP20X_MUX_GPIO_IN BIT(1)
	41	#define AXP20X_MUX_ADC BIT(2)
	42
e1190083 QS	43	#define AXP813_MUX_ADC (BIT(2) \| BIT(0))
e1190083 QS	44
23f75d7d QS	45	struct axp20x_pctrl_desc {
	46	const struct pinctrl_pin_desc *pins;
	47	unsigned int npins;
	48	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	49	u8 ldo_mask;
	50	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	51	u8 adc_mask;
48e706fb	52	u8 gpio_status_offset;
a0a4b4c2	53	u8 adc_mux;
23f75d7d QS	54	};
	55
	56	struct axp20x_pinctrl_function {
	57	const char *name;
	58	unsigned int muxval;
	59	const char **groups;
	60	unsigned int ngroups;
	61	};
	62
d242e60c	63	struct axp20x_pctl {
f72f4b44 MR	64	struct gpio_chip chip;
f72f4b44 MR	65	struct regmap *regmap;
23f75d7d QS	66	struct pinctrl_dev *pctl_dev;
	67	struct device *dev;
	68	const struct axp20x_pctrl_desc *desc;
	69	struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
	70	};
	71
	72	static const struct pinctrl_pin_desc axp209_pins[] = {
	73	PINCTRL_PIN(0, "GPIO0"),
	74	PINCTRL_PIN(1, "GPIO1"),
	75	PINCTRL_PIN(2, "GPIO2"),
	76	};
	77
d4c0b614	78	static const struct pinctrl_pin_desc axp22x_pins[] = {
e1190083 QS	79	PINCTRL_PIN(0, "GPIO0"),
	80	PINCTRL_PIN(1, "GPIO1"),
	81	};
	82
23f75d7d QS	83	static const struct axp20x_pctrl_desc axp20x_data = {
	84	.pins = axp209_pins,
	85	.npins = ARRAY_SIZE(axp209_pins),
	86	.ldo_mask = BIT(0) \| BIT(1),
	87	.adc_mask = BIT(0) \| BIT(1),
48e706fb	88	.gpio_status_offset = 4,
a0a4b4c2	89	.adc_mux = AXP20X_MUX_ADC,
f72f4b44 MR	90	};
f72f4b44 MR	91
d4c0b614 SH	92	static const struct axp20x_pctrl_desc axp22x_data = {
	93	.pins = axp22x_pins,
	94	.npins = ARRAY_SIZE(axp22x_pins),
	95	.ldo_mask = BIT(0) \| BIT(1),
	96	.gpio_status_offset = 0,
	97	};
	98
e1190083	99	static const struct axp20x_pctrl_desc axp813_data = {
d4c0b614 SH	100	.pins = axp22x_pins,
d4c0b614 SH	101	.npins = ARRAY_SIZE(axp22x_pins),
e1190083 QS	102	.ldo_mask = BIT(0) \| BIT(1),
	103	.adc_mask = BIT(0),
	104	.gpio_status_offset = 0,
	105	.adc_mux = AXP813_MUX_ADC,
	106	};
	107
3cac991e	108	static int axp20x_gpio_get_reg(unsigned int offset)
f72f4b44 MR	109	{
	110	switch (offset) {
	111	case 0:
	112	return AXP20X_GPIO0_CTRL;
	113	case 1:
	114	return AXP20X_GPIO1_CTRL;
	115	case 2:
	116	return AXP20X_GPIO2_CTRL;
	117	}
	118
	119	return -EINVAL;
	120	}
	121
3cac991e	122	static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
f72f4b44	123	{
23f75d7d	124	return pinctrl_gpio_direction_input(chip->base + offset);
f72f4b44 MR	125	}
f72f4b44 MR	126
3cac991e	127	static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
f72f4b44	128	{
d242e60c	129	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44	130	unsigned int val;
1d2b2ac0	131	int ret;
f72f4b44	132
d242e60c	133	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
f72f4b44 MR	134	if (ret)
	135	return ret;
	136
48e706fb	137	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
f72f4b44 MR	138	}
f72f4b44 MR	139
3cac991e QS	140	static int axp20x_gpio_get_direction(struct gpio_chip *chip,
3cac991e QS	141	unsigned int offset)
81d3753d	142	{
d242e60c	143	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
81d3753d MR	144	unsigned int val;
	145	int reg, ret;
	146
	147	reg = axp20x_gpio_get_reg(offset);
	148	if (reg < 0)
	149	return reg;
	150
d242e60c	151	ret = regmap_read(pctl->regmap, reg, &val);
81d3753d MR	152	if (ret)
	153	return ret;
	154
	155	/*
	156	* This shouldn't really happen if the pin is in use already,
	157	* or if it's not in use yet, it doesn't matter since we're
	158	* going to change the value soon anyway. Default to output.
	159	*/
	160	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
3c827873	161	return GPIO_LINE_DIRECTION_OUT;
81d3753d MR	162
	163	/*
	164	* The GPIO directions are the three lowest values.
	165	* 2 is input, 0 and 1 are output
	166	*/
3c827873 MV	167	if (val & 2)
	168	return GPIO_LINE_DIRECTION_IN;
	169
	170	return GPIO_LINE_DIRECTION_OUT;
81d3753d MR	171	}
81d3753d MR	172
3cac991e	173	static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
f72f4b44	174	int value)
23f75d7d QS	175	{
	176	chip->set(chip, offset, value);
	177
	178	return 0;
	179	}
	180
	181	static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
	182	int value)
f72f4b44	183	{
d242e60c	184	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44 MR	185	int reg;
f72f4b44 MR	186
23f75d7d QS	187	reg = axp20x_gpio_get_reg(offset);
	188	if (reg < 0)
	189	return;
	190
d242e60c	191	regmap_update_bits(pctl->regmap, reg,
23f75d7d QS	192	AXP20X_GPIO_FUNCTIONS,
	193	value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
	194	AXP20X_GPIO_FUNCTION_OUT_LOW);
	195	}
	196
	197	static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
	198	u8 config)
	199	{
d242e60c	200	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	201	int reg;
23f75d7d QS	202
f72f4b44 MR	203	reg = axp20x_gpio_get_reg(offset);
	204	if (reg < 0)
	205	return reg;
	206
d242e60c	207	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
23f75d7d	208	config);
f72f4b44 MR	209	}
f72f4b44 MR	210
23f75d7d QS	211	static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
23f75d7d QS	212	{
d242e60c	213	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	214
d242e60c	215	return ARRAY_SIZE(pctl->funcs);
23f75d7d QS	216	}
	217
	218	static const char axp20x_pmx_func_name(struct pinctrl_dev pctldev,
	219	unsigned int selector)
	220	{
d242e60c	221	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	222
d242e60c	223	return pctl->funcs[selector].name;
23f75d7d QS	224	}
	225
	226	static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
	227	unsigned int selector,
	228	const char * const **groups,
	229	unsigned int *num_groups)
	230	{
d242e60c	231	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	232
d242e60c QS	233	*groups = pctl->funcs[selector].groups;
d242e60c QS	234	*num_groups = pctl->funcs[selector].ngroups;
23f75d7d QS	235
	236	return 0;
	237	}
	238
	239	static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
	240	unsigned int function, unsigned int group)
	241	{
d242e60c	242	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	243	unsigned int mask;
	244
	245	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	246	if (function <= AXP20X_FUNC_GPIO_IN)
	247	return axp20x_pmx_set(pctldev, group,
d242e60c	248	pctl->funcs[function].muxval);
23f75d7d QS	249
23f75d7d QS	250	if (function == AXP20X_FUNC_LDO)
d242e60c	251	mask = pctl->desc->ldo_mask;
23f75d7d	252	else
d242e60c	253	mask = pctl->desc->adc_mask;
23f75d7d QS	254
	255	if (!(BIT(group) & mask))
	256	return -EINVAL;
	257
	258	/*
	259	* We let the regulator framework handle the LDO muxing as muxing bits
	260	* are basically also regulators on/off bits. It's better not to enforce
	261	* any state of the regulator when selecting LDO mux so that we don't
	262	* interfere with the regulator driver.
	263	*/
	264	if (function == AXP20X_FUNC_LDO)
	265	return 0;
	266
d242e60c	267	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
23f75d7d QS	268	}
	269
	270	static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
	271	struct pinctrl_gpio_range *range,
	272	unsigned int offset, bool input)
	273	{
d242e60c	274	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	275
	276	if (input)
	277	return axp20x_pmx_set(pctldev, offset,
d242e60c	278	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
23f75d7d QS	279
23f75d7d QS	280	return axp20x_pmx_set(pctldev, offset,
d242e60c	281	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
23f75d7d QS	282	}
	283
	284	static const struct pinmux_ops axp20x_pmx_ops = {
	285	.get_functions_count = axp20x_pmx_func_cnt,
	286	.get_function_name = axp20x_pmx_func_name,
	287	.get_function_groups = axp20x_pmx_func_groups,
	288	.set_mux = axp20x_pmx_set_mux,
	289	.gpio_set_direction = axp20x_pmx_gpio_set_direction,
	290	.strict = true,
	291	};
	292
	293	static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
	294	{
d242e60c	295	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	296
d242e60c	297	return pctl->desc->npins;
23f75d7d QS	298	}
	299
	300	static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
	301	const unsigned int *pins, unsigned int num_pins)
	302	{
d242e60c	303	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	304
d242e60c	305	pins = (unsigned int )&pctl->desc->pins[selector];
23f75d7d QS	306	*num_pins = 1;
	307
	308	return 0;
	309	}
	310
	311	static const char axp20x_group_name(struct pinctrl_dev pctldev,
	312	unsigned int selector)
f72f4b44	313	{
d242e60c	314	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	315
d242e60c	316	return pctl->desc->pins[selector].name;
23f75d7d QS	317	}
	318
	319	static const struct pinctrl_ops axp20x_pctrl_ops = {
	320	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
	321	.dt_free_map = pinconf_generic_dt_free_map,
	322	.get_groups_count = axp20x_groups_cnt,
	323	.get_group_name = axp20x_group_name,
	324	.get_group_pins = axp20x_group_pins,
	325	};
	326
504c7697	327	static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
23f75d7d QS	328	unsigned int mask_len,
	329	struct axp20x_pinctrl_function *func,
	330	const struct pinctrl_pin_desc *pins)
	331	{
	332	unsigned long int mask_cpy = mask;
	333	const char **group;
	334	unsigned int ngroups = hweight8(mask);
	335	int bit;
	336
	337	func->ngroups = ngroups;
	338	if (func->ngroups > 0) {
a86854d0 KC	339	func->groups = devm_kcalloc(dev,
a86854d0 KC	340	ngroups, sizeof(const char *),
23f75d7d	341	GFP_KERNEL);
504c7697 AV	342	if (!func->groups)
504c7697 AV	343	return -ENOMEM;
23f75d7d QS	344	group = func->groups;
	345	for_each_set_bit(bit, &mask_cpy, mask_len) {
	346	*group = pins[bit].name;
	347	group++;
	348	}
	349	}
504c7697 AV	350
504c7697 AV	351	return 0;
23f75d7d QS	352	}
23f75d7d QS	353
504c7697	354	static int axp20x_build_funcs_groups(struct platform_device *pdev)
23f75d7d	355	{
d242e60c	356	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
504c7697	357	int i, ret, pin, npins = pctl->desc->npins;
d242e60c QS	358
	359	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	360	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	361	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	362	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	363	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
23f75d7d QS	364	/*
	365	* Muxval for LDO is useless as we won't use it.
	366	* See comment in axp20x_pmx_set_mux.
	367	*/
d242e60c	368	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
a0a4b4c2	369	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
23f75d7d QS	370
	371	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	372	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
d242e60c	373	pctl->funcs[i].ngroups = npins;
a86854d0 KC	374	pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
a86854d0 KC	375	npins, sizeof(char *),
23f75d7d	376	GFP_KERNEL);
1adc90c7 AP	377	if (!pctl->funcs[i].groups)
1adc90c7 AP	378	return -ENOMEM;
23f75d7d	379	for (pin = 0; pin < npins; pin++)
d242e60c	380	pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
23f75d7d QS	381	}
23f75d7d QS	382
504c7697	383	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
d242e60c QS	384	npins, &pctl->funcs[AXP20X_FUNC_LDO],
d242e60c QS	385	pctl->desc->pins);
504c7697 AV	386	if (ret)
504c7697 AV	387	return ret;
23f75d7d	388
504c7697	389	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
d242e60c QS	390	npins, &pctl->funcs[AXP20X_FUNC_ADC],
d242e60c QS	391	pctl->desc->pins);
504c7697 AV	392	if (ret)
	393	return ret;
	394
	395	return 0;
f72f4b44 MR	396	}
f72f4b44 MR	397
e1190083 QS	398	static const struct of_device_id axp20x_pctl_match[] = {
e1190083 QS	399	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
d4c0b614	400	{ .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
e1190083 QS	401	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	402	{ }
	403	};
	404	MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
	405
d242e60c	406	static int axp20x_pctl_probe(struct platform_device *pdev)
f72f4b44 MR	407	{
f72f4b44 MR	408	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
d242e60c	409	struct axp20x_pctl *pctl;
e1190083	410	struct device *dev = &pdev->dev;
23f75d7d	411	struct pinctrl_desc *pctrl_desc;
f72f4b44 MR	412	int ret;
	413
	414	if (!of_device_is_available(pdev->dev.of_node))
	415	return -ENODEV;
	416
	417	if (!axp20x) {
	418	dev_err(&pdev->dev, "Parent drvdata not set\n");
	419	return -EINVAL;
	420	}
	421
d242e60c QS	422	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
d242e60c QS	423	if (!pctl)
f72f4b44 MR	424	return -ENOMEM;
f72f4b44 MR	425
d242e60c QS	426	pctl->chip.base = -1;
	427	pctl->chip.can_sleep = true;
	428	pctl->chip.request = gpiochip_generic_request;
	429	pctl->chip.free = gpiochip_generic_free;
	430	pctl->chip.parent = &pdev->dev;
	431	pctl->chip.label = dev_name(&pdev->dev);
	432	pctl->chip.owner = THIS_MODULE;
	433	pctl->chip.get = axp20x_gpio_get;
	434	pctl->chip.get_direction = axp20x_gpio_get_direction;
	435	pctl->chip.set = axp20x_gpio_set;
	436	pctl->chip.direction_input = axp20x_gpio_input;
	437	pctl->chip.direction_output = axp20x_gpio_output;
d242e60c	438
9b8ee3c0	439	pctl->desc = of_device_get_match_data(dev);
a0498152 QS	440
	441	pctl->chip.ngpio = pctl->desc->npins;
	442
d242e60c QS	443	pctl->regmap = axp20x->regmap;
	444	pctl->dev = &pdev->dev;
	445
	446	platform_set_drvdata(pdev, pctl);
23f75d7d	447
504c7697 AV	448	ret = axp20x_build_funcs_groups(pdev);
	449	if (ret) {
	450	dev_err(&pdev->dev, "failed to build groups\n");
	451	return ret;
	452	}
23f75d7d QS	453
	454	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	455	if (!pctrl_desc)
	456	return -ENOMEM;
	457
	458	pctrl_desc->name = dev_name(&pdev->dev);
	459	pctrl_desc->owner = THIS_MODULE;
d242e60c QS	460	pctrl_desc->pins = pctl->desc->pins;
d242e60c QS	461	pctrl_desc->npins = pctl->desc->npins;
23f75d7d QS	462	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	463	pctrl_desc->pmxops = &axp20x_pmx_ops;
	464
d242e60c QS	465	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
d242e60c QS	466	if (IS_ERR(pctl->pctl_dev)) {
23f75d7d	467	dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
d242e60c	468	return PTR_ERR(pctl->pctl_dev);
23f75d7d	469	}
f72f4b44	470
d242e60c	471	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
f72f4b44 MR	472	if (ret) {
	473	dev_err(&pdev->dev, "Failed to register GPIO chip\n");
	474	return ret;
	475	}
	476
d242e60c QS	477	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
	478	pctl->desc->pins->number,
	479	pctl->desc->pins->number,
	480	pctl->desc->npins);
23f75d7d QS	481	if (ret) {
	482	dev_err(&pdev->dev, "failed to add pin range\n");
	483	return ret;
	484	}
	485
	486	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
f72f4b44 MR	487
	488	return 0;
	489	}
	490
d242e60c QS	491	static struct platform_driver axp20x_pctl_driver = {
d242e60c QS	492	.probe = axp20x_pctl_probe,
f72f4b44 MR	493	.driver = {
f72f4b44 MR	494	.name = "axp20x-gpio",
d242e60c	495	.of_match_table = axp20x_pctl_match,
f72f4b44 MR	496	},
	497	};
	498
d242e60c	499	module_platform_driver(axp20x_pctl_driver);
f72f4b44 MR	500
f72f4b44 MR	501	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
23f75d7d QS	502	MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
23f75d7d QS	503	MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
f72f4b44	504	MODULE_LICENSE("GPL");