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6732ae5c JCPV |
1 | /* |
2 | * at91 pinctrl driver based on at91 pinmux core | |
3 | * | |
4 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
5 | * | |
6 | * Under GPLv2 only | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/of_device.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/irqdomain.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/gpio.h> | |
6732ae5c JCPV |
23 | #include <linux/pinctrl/machine.h> |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinctrl.h> | |
26 | #include <linux/pinctrl/pinmux.h> | |
27 | /* Since we request GPIOs from ourself */ | |
28 | #include <linux/pinctrl/consumer.h> | |
29 | ||
30 | #include <asm/mach/irq.h> | |
31 | ||
32 | #include <mach/hardware.h> | |
33 | #include <mach/at91_pio.h> | |
34 | ||
35 | #include "core.h" | |
36 | ||
37 | #define MAX_NB_GPIO_PER_BANK 32 | |
38 | ||
39 | struct at91_pinctrl_mux_ops; | |
40 | ||
41 | struct at91_gpio_chip { | |
42 | struct gpio_chip chip; | |
43 | struct pinctrl_gpio_range range; | |
44 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | |
45 | int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ | |
46 | int pioc_virq; /* PIO bank Linux virtual interrupt */ | |
47 | int pioc_idx; /* PIO bank index */ | |
48 | void __iomem *regbase; /* PIO bank virtual address */ | |
49 | struct clk *clock; /* associated clock */ | |
50 | struct irq_domain *domain; /* associated irq domain */ | |
51 | struct at91_pinctrl_mux_ops *ops; /* ops */ | |
52 | }; | |
53 | ||
54 | #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) | |
55 | ||
56 | static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; | |
57 | ||
58 | static int gpio_banks; | |
59 | ||
525fae21 | 60 | #define PULL_UP (1 << 0) |
6732ae5c JCPV |
61 | #define MULTI_DRIVE (1 << 1) |
62 | ||
63 | /** | |
64 | * struct at91_pmx_func - describes AT91 pinmux functions | |
65 | * @name: the name of this specific function | |
66 | * @groups: corresponding pin groups | |
67 | * @ngroups: the number of groups | |
68 | */ | |
69 | struct at91_pmx_func { | |
70 | const char *name; | |
71 | const char **groups; | |
72 | unsigned ngroups; | |
73 | }; | |
74 | ||
75 | enum at91_mux { | |
76 | AT91_MUX_GPIO = 0, | |
77 | AT91_MUX_PERIPH_A = 1, | |
78 | AT91_MUX_PERIPH_B = 2, | |
79 | AT91_MUX_PERIPH_C = 3, | |
80 | AT91_MUX_PERIPH_D = 4, | |
81 | }; | |
82 | ||
83 | /** | |
84 | * struct at91_pmx_pin - describes an At91 pin mux | |
85 | * @bank: the bank of the pin | |
86 | * @pin: the pin number in the @bank | |
87 | * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. | |
88 | * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... | |
89 | */ | |
90 | struct at91_pmx_pin { | |
91 | uint32_t bank; | |
92 | uint32_t pin; | |
93 | enum at91_mux mux; | |
94 | unsigned long conf; | |
95 | }; | |
96 | ||
97 | /** | |
98 | * struct at91_pin_group - describes an At91 pin group | |
99 | * @name: the name of this specific pin group | |
100 | * @pins_conf: the mux mode for each pin in this group. The size of this | |
101 | * array is the same as pins. | |
102 | * @pins: an array of discrete physical pins used in this group, taken | |
103 | * from the driver-local pin enumeration space | |
104 | * @npins: the number of pins in this group array, i.e. the number of | |
105 | * elements in .pins so we can iterate over that array | |
106 | */ | |
107 | struct at91_pin_group { | |
108 | const char *name; | |
109 | struct at91_pmx_pin *pins_conf; | |
110 | unsigned int *pins; | |
111 | unsigned npins; | |
112 | }; | |
113 | ||
114 | /** | |
115 | * struct at91_pinctrl_mux_ops - describes an At91 mux ops group | |
116 | * on new IP with support for periph C and D the way to mux in | |
117 | * periph A and B has changed | |
118 | * So provide the right call back | |
119 | * if not present means the IP does not support it | |
120 | * @get_periph: return the periph mode configured | |
121 | * @mux_A_periph: mux as periph A | |
122 | * @mux_B_periph: mux as periph B | |
123 | * @mux_C_periph: mux as periph C | |
124 | * @mux_D_periph: mux as periph D | |
125 | * @irq_type: return irq type | |
126 | */ | |
127 | struct at91_pinctrl_mux_ops { | |
128 | enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); | |
129 | void (*mux_A_periph)(void __iomem *pio, unsigned mask); | |
130 | void (*mux_B_periph)(void __iomem *pio, unsigned mask); | |
131 | void (*mux_C_periph)(void __iomem *pio, unsigned mask); | |
132 | void (*mux_D_periph)(void __iomem *pio, unsigned mask); | |
133 | /* irq */ | |
134 | int (*irq_type)(struct irq_data *d, unsigned type); | |
135 | }; | |
136 | ||
137 | static int gpio_irq_type(struct irq_data *d, unsigned type); | |
138 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type); | |
139 | ||
140 | struct at91_pinctrl { | |
141 | struct device *dev; | |
142 | struct pinctrl_dev *pctl; | |
143 | ||
144 | int nbanks; | |
145 | ||
146 | uint32_t *mux_mask; | |
147 | int nmux; | |
148 | ||
149 | struct at91_pmx_func *functions; | |
150 | int nfunctions; | |
151 | ||
152 | struct at91_pin_group *groups; | |
153 | int ngroups; | |
154 | ||
155 | struct at91_pinctrl_mux_ops *ops; | |
156 | }; | |
157 | ||
158 | static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( | |
159 | const struct at91_pinctrl *info, | |
160 | const char *name) | |
161 | { | |
162 | const struct at91_pin_group *grp = NULL; | |
163 | int i; | |
164 | ||
165 | for (i = 0; i < info->ngroups; i++) { | |
166 | if (strcmp(info->groups[i].name, name)) | |
167 | continue; | |
168 | ||
169 | grp = &info->groups[i]; | |
170 | dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); | |
171 | break; | |
172 | } | |
173 | ||
174 | return grp; | |
175 | } | |
176 | ||
177 | static int at91_get_groups_count(struct pinctrl_dev *pctldev) | |
178 | { | |
179 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
180 | ||
181 | return info->ngroups; | |
182 | } | |
183 | ||
184 | static const char *at91_get_group_name(struct pinctrl_dev *pctldev, | |
185 | unsigned selector) | |
186 | { | |
187 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
188 | ||
189 | return info->groups[selector].name; | |
190 | } | |
191 | ||
192 | static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
193 | const unsigned **pins, | |
194 | unsigned *npins) | |
195 | { | |
196 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
197 | ||
198 | if (selector >= info->ngroups) | |
199 | return -EINVAL; | |
200 | ||
201 | *pins = info->groups[selector].pins; | |
202 | *npins = info->groups[selector].npins; | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
208 | unsigned offset) | |
209 | { | |
210 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
211 | } | |
212 | ||
213 | static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, | |
214 | struct device_node *np, | |
215 | struct pinctrl_map **map, unsigned *num_maps) | |
216 | { | |
217 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
218 | const struct at91_pin_group *grp; | |
219 | struct pinctrl_map *new_map; | |
220 | struct device_node *parent; | |
221 | int map_num = 1; | |
222 | int i; | |
6732ae5c JCPV |
223 | |
224 | /* | |
225 | * first find the group of this node and check if we need create | |
226 | * config maps for pins | |
227 | */ | |
228 | grp = at91_pinctrl_find_group_by_name(info, np->name); | |
229 | if (!grp) { | |
230 | dev_err(info->dev, "unable to find group for node %s\n", | |
231 | np->name); | |
232 | return -EINVAL; | |
233 | } | |
234 | ||
235 | map_num += grp->npins; | |
236 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); | |
237 | if (!new_map) | |
238 | return -ENOMEM; | |
239 | ||
240 | *map = new_map; | |
241 | *num_maps = map_num; | |
242 | ||
243 | /* create mux map */ | |
244 | parent = of_get_parent(np); | |
245 | if (!parent) { | |
246 | kfree(new_map); | |
247 | return -EINVAL; | |
248 | } | |
249 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
250 | new_map[0].data.mux.function = parent->name; | |
251 | new_map[0].data.mux.group = np->name; | |
252 | of_node_put(parent); | |
253 | ||
254 | /* create config map */ | |
255 | new_map++; | |
256 | for (i = 0; i < grp->npins; i++) { | |
6732ae5c JCPV |
257 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; |
258 | new_map[i].data.configs.group_or_pin = | |
259 | pin_get_name(pctldev, grp->pins[i]); | |
260 | new_map[i].data.configs.configs = &grp->pins_conf[i].conf; | |
261 | new_map[i].data.configs.num_configs = 1; | |
262 | } | |
263 | ||
264 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
265 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | static void at91_dt_free_map(struct pinctrl_dev *pctldev, | |
271 | struct pinctrl_map *map, unsigned num_maps) | |
272 | { | |
273 | } | |
274 | ||
275 | static struct pinctrl_ops at91_pctrl_ops = { | |
276 | .get_groups_count = at91_get_groups_count, | |
277 | .get_group_name = at91_get_group_name, | |
278 | .get_group_pins = at91_get_group_pins, | |
279 | .pin_dbg_show = at91_pin_dbg_show, | |
280 | .dt_node_to_map = at91_dt_node_to_map, | |
281 | .dt_free_map = at91_dt_free_map, | |
282 | }; | |
283 | ||
284 | static void __iomem * pin_to_controller(struct at91_pinctrl *info, | |
285 | unsigned int bank) | |
286 | { | |
287 | return gpio_chips[bank]->regbase; | |
288 | } | |
289 | ||
290 | static inline int pin_to_bank(unsigned pin) | |
291 | { | |
292 | return pin /= MAX_NB_GPIO_PER_BANK; | |
293 | } | |
294 | ||
295 | static unsigned pin_to_mask(unsigned int pin) | |
296 | { | |
297 | return 1 << pin; | |
298 | } | |
299 | ||
300 | static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) | |
301 | { | |
302 | writel_relaxed(mask, pio + PIO_IDR); | |
303 | } | |
304 | ||
305 | static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) | |
306 | { | |
307 | return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1; | |
308 | } | |
309 | ||
310 | static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) | |
311 | { | |
312 | writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); | |
313 | } | |
314 | ||
315 | static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) | |
316 | { | |
317 | return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; | |
318 | } | |
319 | ||
320 | static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) | |
321 | { | |
322 | writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); | |
323 | } | |
324 | ||
325 | static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) | |
326 | { | |
327 | writel_relaxed(mask, pio + PIO_ASR); | |
328 | } | |
329 | ||
330 | static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) | |
331 | { | |
332 | writel_relaxed(mask, pio + PIO_BSR); | |
333 | } | |
334 | ||
335 | static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) | |
336 | { | |
337 | ||
338 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, | |
339 | pio + PIO_ABCDSR1); | |
340 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
341 | pio + PIO_ABCDSR2); | |
342 | } | |
343 | ||
344 | static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) | |
345 | { | |
346 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, | |
347 | pio + PIO_ABCDSR1); | |
348 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
349 | pio + PIO_ABCDSR2); | |
350 | } | |
351 | ||
352 | static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) | |
353 | { | |
354 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); | |
355 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
356 | } | |
357 | ||
358 | static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) | |
359 | { | |
360 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); | |
361 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
362 | } | |
363 | ||
364 | static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) | |
365 | { | |
366 | unsigned select; | |
367 | ||
368 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
369 | return AT91_MUX_GPIO; | |
370 | ||
371 | select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); | |
372 | select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); | |
373 | ||
374 | return select + 1; | |
375 | } | |
376 | ||
377 | static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) | |
378 | { | |
379 | unsigned select; | |
380 | ||
381 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
382 | return AT91_MUX_GPIO; | |
383 | ||
384 | select = readl_relaxed(pio + PIO_ABSR) & mask; | |
385 | ||
386 | return select + 1; | |
387 | } | |
388 | ||
389 | static struct at91_pinctrl_mux_ops at91rm9200_ops = { | |
390 | .get_periph = at91_mux_get_periph, | |
391 | .mux_A_periph = at91_mux_set_A_periph, | |
392 | .mux_B_periph = at91_mux_set_B_periph, | |
393 | .irq_type = gpio_irq_type, | |
394 | }; | |
395 | ||
396 | static struct at91_pinctrl_mux_ops at91sam9x5_ops = { | |
397 | .get_periph = at91_mux_pio3_get_periph, | |
398 | .mux_A_periph = at91_mux_pio3_set_A_periph, | |
399 | .mux_B_periph = at91_mux_pio3_set_B_periph, | |
400 | .mux_C_periph = at91_mux_pio3_set_C_periph, | |
401 | .mux_D_periph = at91_mux_pio3_set_D_periph, | |
402 | .irq_type = alt_gpio_irq_type, | |
403 | }; | |
404 | ||
405 | static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) | |
406 | { | |
407 | if (pin->mux) { | |
408 | dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", | |
409 | pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); | |
410 | } else { | |
411 | dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", | |
412 | pin->bank + 'A', pin->pin, pin->conf); | |
413 | } | |
414 | } | |
415 | ||
416 | static int pin_check_config(struct at91_pinctrl *info, const char* name, | |
417 | int index, const struct at91_pmx_pin *pin) | |
418 | { | |
419 | int mux; | |
420 | ||
421 | /* check if it's a valid config */ | |
422 | if (pin->bank >= info->nbanks) { | |
423 | dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", | |
424 | name, index, pin->bank, info->nbanks); | |
425 | return -EINVAL; | |
426 | } | |
427 | ||
428 | if (pin->pin >= MAX_NB_GPIO_PER_BANK) { | |
429 | dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", | |
430 | name, index, pin->pin, MAX_NB_GPIO_PER_BANK); | |
431 | return -EINVAL; | |
432 | } | |
433 | ||
434 | if (!pin->mux) | |
435 | return 0; | |
436 | ||
437 | mux = pin->mux - 1; | |
438 | ||
439 | if (mux >= info->nmux) { | |
440 | dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", | |
441 | name, index, mux, info->nmux); | |
442 | return -EINVAL; | |
443 | } | |
444 | ||
445 | if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { | |
446 | dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", | |
447 | name, index, mux, pin->bank + 'A', pin->pin); | |
448 | return -EINVAL; | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) | |
455 | { | |
456 | writel_relaxed(mask, pio + PIO_PDR); | |
457 | } | |
458 | ||
459 | static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) | |
460 | { | |
461 | writel_relaxed(mask, pio + PIO_PER); | |
462 | writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); | |
463 | } | |
464 | ||
465 | static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
466 | unsigned group) | |
467 | { | |
468 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
469 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
470 | const struct at91_pmx_pin *pin; | |
471 | uint32_t npins = info->groups[group].npins; | |
472 | int i, ret; | |
473 | unsigned mask; | |
474 | void __iomem *pio; | |
475 | ||
476 | dev_dbg(info->dev, "enable function %s group %s\n", | |
477 | info->functions[selector].name, info->groups[group].name); | |
478 | ||
479 | /* first check that all the pins of the group are valid with a valid | |
480 | * paramter */ | |
481 | for (i = 0; i < npins; i++) { | |
482 | pin = &pins_conf[i]; | |
483 | ret = pin_check_config(info, info->groups[group].name, i, pin); | |
484 | if (ret) | |
485 | return ret; | |
486 | } | |
487 | ||
488 | for (i = 0; i < npins; i++) { | |
489 | pin = &pins_conf[i]; | |
490 | at91_pin_dbg(info->dev, pin); | |
491 | pio = pin_to_controller(info, pin->bank); | |
492 | mask = pin_to_mask(pin->pin); | |
493 | at91_mux_disable_interrupt(pio, mask); | |
494 | switch(pin->mux) { | |
495 | case AT91_MUX_GPIO: | |
496 | at91_mux_gpio_enable(pio, mask, 1); | |
497 | break; | |
498 | case AT91_MUX_PERIPH_A: | |
499 | info->ops->mux_A_periph(pio, mask); | |
500 | break; | |
501 | case AT91_MUX_PERIPH_B: | |
502 | info->ops->mux_B_periph(pio, mask); | |
503 | break; | |
504 | case AT91_MUX_PERIPH_C: | |
505 | if (!info->ops->mux_C_periph) | |
506 | return -EINVAL; | |
507 | info->ops->mux_C_periph(pio, mask); | |
508 | break; | |
509 | case AT91_MUX_PERIPH_D: | |
510 | if (!info->ops->mux_D_periph) | |
511 | return -EINVAL; | |
512 | info->ops->mux_D_periph(pio, mask); | |
513 | break; | |
514 | } | |
515 | if (pin->mux) | |
516 | at91_mux_gpio_disable(pio, mask); | |
517 | } | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, | |
523 | unsigned group) | |
524 | { | |
525 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
526 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
527 | const struct at91_pmx_pin *pin; | |
528 | uint32_t npins = info->groups[group].npins; | |
529 | int i; | |
530 | unsigned mask; | |
531 | void __iomem *pio; | |
532 | ||
533 | for (i = 0; i < npins; i++) { | |
534 | pin = &pins_conf[i]; | |
535 | at91_pin_dbg(info->dev, pin); | |
536 | pio = pin_to_controller(info, pin->bank); | |
537 | mask = pin_to_mask(pin->pin); | |
538 | at91_mux_gpio_enable(pio, mask, 1); | |
539 | } | |
540 | } | |
541 | ||
542 | static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
543 | { | |
544 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
545 | ||
546 | return info->nfunctions; | |
547 | } | |
548 | ||
549 | static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
550 | unsigned selector) | |
551 | { | |
552 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
553 | ||
554 | return info->functions[selector].name; | |
555 | } | |
556 | ||
557 | static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
558 | const char * const **groups, | |
559 | unsigned * const num_groups) | |
560 | { | |
561 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
562 | ||
563 | *groups = info->functions[selector].groups; | |
564 | *num_groups = info->functions[selector].ngroups; | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
f6f94f66 AL |
569 | static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, |
570 | struct pinctrl_gpio_range *range, | |
571 | unsigned offset) | |
6732ae5c JCPV |
572 | { |
573 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
574 | struct at91_gpio_chip *at91_chip; | |
575 | struct gpio_chip *chip; | |
576 | unsigned mask; | |
577 | ||
578 | if (!range) { | |
579 | dev_err(npct->dev, "invalid range\n"); | |
580 | return -EINVAL; | |
581 | } | |
582 | if (!range->gc) { | |
583 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
584 | return -EINVAL; | |
585 | } | |
586 | chip = range->gc; | |
587 | at91_chip = container_of(chip, struct at91_gpio_chip, chip); | |
588 | ||
589 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
590 | ||
591 | mask = 1 << (offset - chip->base); | |
592 | ||
593 | dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", | |
594 | offset, 'A' + range->id, offset - chip->base, mask); | |
595 | ||
596 | writel_relaxed(mask, at91_chip->regbase + PIO_PER); | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
f6f94f66 AL |
601 | static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, |
602 | struct pinctrl_gpio_range *range, | |
603 | unsigned offset) | |
6732ae5c JCPV |
604 | { |
605 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
606 | ||
607 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
608 | /* Set the pin to some default state, GPIO is usually default */ | |
609 | } | |
610 | ||
611 | static struct pinmux_ops at91_pmx_ops = { | |
612 | .get_functions_count = at91_pmx_get_funcs_count, | |
613 | .get_function_name = at91_pmx_get_func_name, | |
614 | .get_function_groups = at91_pmx_get_groups, | |
615 | .enable = at91_pmx_enable, | |
616 | .disable = at91_pmx_disable, | |
617 | .gpio_request_enable = at91_gpio_request_enable, | |
618 | .gpio_disable_free = at91_gpio_disable_free, | |
619 | }; | |
620 | ||
621 | static int at91_pinconf_get(struct pinctrl_dev *pctldev, | |
622 | unsigned pin_id, unsigned long *config) | |
623 | { | |
624 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
625 | void __iomem *pio; | |
626 | unsigned pin; | |
627 | ||
628 | dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); | |
629 | pio = pin_to_controller(info, pin_to_bank(pin_id)); | |
630 | pin = pin_id % MAX_NB_GPIO_PER_BANK; | |
631 | ||
632 | if (at91_mux_get_multidrive(pio, pin)) | |
633 | *config |= MULTI_DRIVE; | |
634 | ||
635 | if (at91_mux_get_pullup(pio, pin)) | |
636 | *config |= PULL_UP; | |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
641 | static int at91_pinconf_set(struct pinctrl_dev *pctldev, | |
642 | unsigned pin_id, unsigned long config) | |
643 | { | |
644 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
645 | unsigned mask; | |
646 | void __iomem *pio; | |
647 | ||
648 | dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config); | |
649 | pio = pin_to_controller(info, pin_to_bank(pin_id)); | |
650 | mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); | |
651 | ||
652 | at91_mux_set_pullup(pio, mask, config & PULL_UP); | |
653 | at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); | |
654 | return 0; | |
655 | } | |
656 | ||
657 | static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
658 | struct seq_file *s, unsigned pin_id) | |
659 | { | |
660 | ||
661 | } | |
662 | ||
663 | static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
664 | struct seq_file *s, unsigned group) | |
665 | { | |
666 | } | |
667 | ||
668 | struct pinconf_ops at91_pinconf_ops = { | |
669 | .pin_config_get = at91_pinconf_get, | |
670 | .pin_config_set = at91_pinconf_set, | |
671 | .pin_config_dbg_show = at91_pinconf_dbg_show, | |
672 | .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, | |
673 | }; | |
674 | ||
675 | static struct pinctrl_desc at91_pinctrl_desc = { | |
676 | .pctlops = &at91_pctrl_ops, | |
677 | .pmxops = &at91_pmx_ops, | |
678 | .confops = &at91_pinconf_ops, | |
679 | .owner = THIS_MODULE, | |
680 | }; | |
681 | ||
682 | static const char *gpio_compat = "atmel,at91rm9200-gpio"; | |
683 | ||
684 | static void __devinit at91_pinctrl_child_count(struct at91_pinctrl *info, | |
685 | struct device_node *np) | |
686 | { | |
687 | struct device_node *child; | |
688 | ||
689 | for_each_child_of_node(np, child) { | |
690 | if (of_device_is_compatible(child, gpio_compat)) { | |
691 | info->nbanks++; | |
692 | } else { | |
693 | info->nfunctions++; | |
694 | info->ngroups += of_get_child_count(child); | |
695 | } | |
696 | } | |
697 | } | |
698 | ||
699 | static int __devinit at91_pinctrl_mux_mask(struct at91_pinctrl *info, | |
700 | struct device_node *np) | |
701 | { | |
702 | int ret = 0; | |
703 | int size; | |
704 | const const __be32 *list; | |
705 | ||
706 | list = of_get_property(np, "atmel,mux-mask", &size); | |
707 | if (!list) { | |
708 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
709 | return -EINVAL; | |
710 | } | |
711 | ||
712 | size /= sizeof(*list); | |
713 | if (!size || size % info->nbanks) { | |
714 | dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); | |
715 | return -EINVAL; | |
716 | } | |
717 | info->nmux = size / info->nbanks; | |
718 | ||
719 | info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); | |
720 | if (!info->mux_mask) { | |
721 | dev_err(info->dev, "could not alloc mux_mask\n"); | |
722 | return -ENOMEM; | |
723 | } | |
724 | ||
725 | ret = of_property_read_u32_array(np, "atmel,mux-mask", | |
726 | info->mux_mask, size); | |
727 | if (ret) | |
728 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
729 | return ret; | |
730 | } | |
731 | ||
732 | static int __devinit at91_pinctrl_parse_groups(struct device_node *np, | |
733 | struct at91_pin_group *grp, | |
734 | struct at91_pinctrl *info, | |
735 | u32 index) | |
736 | { | |
737 | struct at91_pmx_pin *pin; | |
738 | int size; | |
739 | const const __be32 *list; | |
740 | int i, j; | |
741 | ||
742 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
743 | ||
744 | /* Initialise group */ | |
745 | grp->name = np->name; | |
746 | ||
747 | /* | |
748 | * the binding format is atmel,pins = <bank pin mux CONFIG ...>, | |
749 | * do sanity check and calculate pins number | |
750 | */ | |
751 | list = of_get_property(np, "atmel,pins", &size); | |
752 | /* we do not check return since it's safe node passed down */ | |
753 | size /= sizeof(*list); | |
754 | if (!size || size % 4) { | |
755 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
756 | return -EINVAL; | |
757 | } | |
758 | ||
759 | grp->npins = size / 4; | |
760 | pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), | |
761 | GFP_KERNEL); | |
762 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
763 | GFP_KERNEL); | |
764 | if (!grp->pins_conf || !grp->pins) | |
765 | return -ENOMEM; | |
766 | ||
767 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
768 | pin->bank = be32_to_cpu(*list++); | |
769 | pin->pin = be32_to_cpu(*list++); | |
770 | grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; | |
771 | pin->mux = be32_to_cpu(*list++); | |
772 | pin->conf = be32_to_cpu(*list++); | |
773 | ||
774 | at91_pin_dbg(info->dev, pin); | |
775 | pin++; | |
776 | } | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
781 | static int __devinit at91_pinctrl_parse_functions(struct device_node *np, | |
782 | struct at91_pinctrl *info, u32 index) | |
783 | { | |
784 | struct device_node *child; | |
785 | struct at91_pmx_func *func; | |
786 | struct at91_pin_group *grp; | |
787 | int ret; | |
788 | static u32 grp_index; | |
789 | u32 i = 0; | |
790 | ||
791 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
792 | ||
793 | func = &info->functions[index]; | |
794 | ||
795 | /* Initialise function */ | |
796 | func->name = np->name; | |
797 | func->ngroups = of_get_child_count(np); | |
798 | if (func->ngroups <= 0) { | |
799 | dev_err(info->dev, "no groups defined\n"); | |
800 | return -EINVAL; | |
801 | } | |
802 | func->groups = devm_kzalloc(info->dev, | |
803 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
804 | if (!func->groups) | |
805 | return -ENOMEM; | |
806 | ||
807 | for_each_child_of_node(np, child) { | |
808 | func->groups[i] = child->name; | |
809 | grp = &info->groups[grp_index++]; | |
810 | ret = at91_pinctrl_parse_groups(child, grp, info, i++); | |
811 | if (ret) | |
812 | return ret; | |
813 | } | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
818 | static struct of_device_id at91_pinctrl_of_match[] __devinitdata = { | |
819 | { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, | |
820 | { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, | |
821 | { /* sentinel */ } | |
822 | }; | |
823 | ||
824 | static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev, | |
825 | struct at91_pinctrl *info) | |
826 | { | |
827 | int ret = 0; | |
828 | int i, j; | |
829 | uint32_t *tmp; | |
830 | struct device_node *np = pdev->dev.of_node; | |
831 | struct device_node *child; | |
832 | ||
833 | if (!np) | |
834 | return -ENODEV; | |
835 | ||
836 | info->dev = &pdev->dev; | |
dffa9123 | 837 | info->ops = (struct at91_pinctrl_mux_ops*) |
6732ae5c JCPV |
838 | of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; |
839 | at91_pinctrl_child_count(info, np); | |
840 | ||
841 | if (info->nbanks < 1) { | |
842 | dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); | |
843 | return -EINVAL; | |
844 | } | |
845 | ||
846 | ret = at91_pinctrl_mux_mask(info, np); | |
847 | if (ret) | |
848 | return ret; | |
849 | ||
850 | dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); | |
851 | ||
852 | dev_dbg(&pdev->dev, "mux-mask\n"); | |
853 | tmp = info->mux_mask; | |
854 | for (i = 0; i < info->nbanks; i++) { | |
855 | for (j = 0; j < info->nmux; j++, tmp++) { | |
856 | dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); | |
857 | } | |
858 | } | |
859 | ||
860 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
861 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
862 | info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), | |
863 | GFP_KERNEL); | |
864 | if (!info->functions) | |
865 | return -ENOMEM; | |
866 | ||
867 | info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), | |
868 | GFP_KERNEL); | |
869 | if (!info->groups) | |
870 | return -ENOMEM; | |
871 | ||
872 | dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); | |
873 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
874 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
875 | ||
876 | i = 0; | |
877 | ||
878 | for_each_child_of_node(np, child) { | |
879 | if (of_device_is_compatible(child, gpio_compat)) | |
880 | continue; | |
881 | ret = at91_pinctrl_parse_functions(child, info, i++); | |
882 | if (ret) { | |
883 | dev_err(&pdev->dev, "failed to parse function\n"); | |
884 | return ret; | |
885 | } | |
886 | } | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
891 | static int __devinit at91_pinctrl_probe(struct platform_device *pdev) | |
892 | { | |
893 | struct at91_pinctrl *info; | |
894 | struct pinctrl_pin_desc *pdesc; | |
895 | int ret, i, j ,k; | |
896 | ||
897 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
898 | if (!info) | |
899 | return -ENOMEM; | |
900 | ||
901 | ret = at91_pinctrl_probe_dt(pdev, info); | |
902 | if (ret) | |
903 | return ret; | |
904 | ||
905 | /* | |
906 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
907 | * to obtain references to the struct gpio_chip * for them, and we | |
908 | * need this to proceed. | |
909 | */ | |
910 | for (i = 0; i < info->nbanks; i++) { | |
911 | if (!gpio_chips[i]) { | |
912 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); | |
913 | devm_kfree(&pdev->dev, info); | |
914 | return -EPROBE_DEFER; | |
915 | } | |
916 | } | |
917 | ||
918 | at91_pinctrl_desc.name = dev_name(&pdev->dev); | |
919 | at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; | |
920 | at91_pinctrl_desc.pins = pdesc = | |
921 | devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); | |
922 | ||
923 | if (!at91_pinctrl_desc.pins) | |
924 | return -ENOMEM; | |
925 | ||
926 | for (i = 0 , k = 0; i < info->nbanks; i++) { | |
927 | for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { | |
928 | pdesc->number = k; | |
929 | pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); | |
930 | pdesc++; | |
931 | } | |
932 | } | |
933 | ||
934 | platform_set_drvdata(pdev, info); | |
935 | info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); | |
936 | ||
937 | if (!info->pctl) { | |
938 | dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); | |
939 | ret = -EINVAL; | |
940 | goto err; | |
941 | } | |
942 | ||
943 | /* We will handle a range of GPIO pins */ | |
944 | for (i = 0; i < info->nbanks; i++) | |
945 | pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); | |
946 | ||
947 | dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); | |
948 | ||
949 | return 0; | |
950 | ||
951 | err: | |
952 | return ret; | |
953 | } | |
954 | ||
f6f94f66 | 955 | static int __devexit at91_pinctrl_remove(struct platform_device *pdev) |
6732ae5c JCPV |
956 | { |
957 | struct at91_pinctrl *info = platform_get_drvdata(pdev); | |
958 | ||
959 | pinctrl_unregister(info->pctl); | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
964 | static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) | |
965 | { | |
966 | /* | |
967 | * Map back to global GPIO space and request muxing, the direction | |
968 | * parameter does not matter for this controller. | |
969 | */ | |
970 | int gpio = chip->base + offset; | |
971 | int bank = chip->base / chip->ngpio; | |
972 | ||
973 | dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, | |
974 | 'A' + bank, offset, gpio); | |
975 | ||
976 | return pinctrl_request_gpio(gpio); | |
977 | } | |
978 | ||
979 | static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) | |
980 | { | |
981 | int gpio = chip->base + offset; | |
982 | ||
983 | pinctrl_free_gpio(gpio); | |
984 | } | |
985 | ||
986 | static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
987 | { | |
988 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
989 | void __iomem *pio = at91_gpio->regbase; | |
990 | unsigned mask = 1 << offset; | |
991 | ||
992 | writel_relaxed(mask, pio + PIO_ODR); | |
993 | return 0; | |
994 | } | |
995 | ||
996 | static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) | |
997 | { | |
998 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
999 | void __iomem *pio = at91_gpio->regbase; | |
1000 | unsigned mask = 1 << offset; | |
1001 | u32 pdsr; | |
1002 | ||
1003 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1004 | return (pdsr & mask) != 0; | |
1005 | } | |
1006 | ||
1007 | static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, | |
1008 | int val) | |
1009 | { | |
1010 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1011 | void __iomem *pio = at91_gpio->regbase; | |
1012 | unsigned mask = 1 << offset; | |
1013 | ||
1014 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1015 | } | |
1016 | ||
1017 | static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
1018 | int val) | |
1019 | { | |
1020 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1021 | void __iomem *pio = at91_gpio->regbase; | |
1022 | unsigned mask = 1 << offset; | |
1023 | ||
1024 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1025 | writel_relaxed(mask, pio + PIO_OER); | |
1026 | ||
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
1031 | { | |
1032 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1033 | int virq; | |
1034 | ||
1035 | if (offset < chip->ngpio) | |
1036 | virq = irq_create_mapping(at91_gpio->domain, offset); | |
1037 | else | |
1038 | virq = -ENXIO; | |
1039 | ||
1040 | dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", | |
1041 | chip->label, offset + chip->base, virq); | |
1042 | return virq; | |
1043 | } | |
1044 | ||
1045 | #ifdef CONFIG_DEBUG_FS | |
1046 | static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1047 | { | |
1048 | enum at91_mux mode; | |
1049 | int i; | |
1050 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1051 | void __iomem *pio = at91_gpio->regbase; | |
1052 | ||
1053 | for (i = 0; i < chip->ngpio; i++) { | |
1054 | unsigned pin = chip->base + i; | |
1055 | unsigned mask = pin_to_mask(pin); | |
1056 | const char *gpio_label; | |
1057 | u32 pdsr; | |
1058 | ||
1059 | gpio_label = gpiochip_is_requested(chip, i); | |
1060 | if (!gpio_label) | |
1061 | continue; | |
1062 | mode = at91_gpio->ops->get_periph(pio, mask); | |
1063 | seq_printf(s, "[%s] GPIO%s%d: ", | |
1064 | gpio_label, chip->label, i); | |
1065 | if (mode == AT91_MUX_GPIO) { | |
1066 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1067 | ||
1068 | seq_printf(s, "[gpio] %s\n", | |
1069 | pdsr & mask ? | |
1070 | "set" : "clear"); | |
1071 | } else { | |
1072 | seq_printf(s, "[periph %c]\n", | |
1073 | mode + 'A' - 1); | |
1074 | } | |
1075 | } | |
1076 | } | |
1077 | #else | |
1078 | #define at91_gpio_dbg_show NULL | |
1079 | #endif | |
1080 | ||
1081 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
1082 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
1083 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
1084 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
1085 | * handler. | |
1086 | * First implementation always triggers on rising and falling edges | |
1087 | * whereas the newer PIO3 can be additionally configured to trigger on | |
1088 | * level, edge with any polarity. | |
1089 | * | |
1090 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
1091 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
1092 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
1093 | */ | |
1094 | ||
1095 | static void gpio_irq_mask(struct irq_data *d) | |
1096 | { | |
1097 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1098 | void __iomem *pio = at91_gpio->regbase; | |
1099 | unsigned mask = 1 << d->hwirq; | |
1100 | ||
1101 | if (pio) | |
1102 | writel_relaxed(mask, pio + PIO_IDR); | |
1103 | } | |
1104 | ||
1105 | static void gpio_irq_unmask(struct irq_data *d) | |
1106 | { | |
1107 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1108 | void __iomem *pio = at91_gpio->regbase; | |
1109 | unsigned mask = 1 << d->hwirq; | |
1110 | ||
1111 | if (pio) | |
1112 | writel_relaxed(mask, pio + PIO_IER); | |
1113 | } | |
1114 | ||
1115 | static int gpio_irq_type(struct irq_data *d, unsigned type) | |
1116 | { | |
1117 | switch (type) { | |
1118 | case IRQ_TYPE_NONE: | |
1119 | case IRQ_TYPE_EDGE_BOTH: | |
1120 | return 0; | |
1121 | default: | |
1122 | return -EINVAL; | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | /* Alternate irq type for PIO3 support */ | |
1127 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type) | |
1128 | { | |
1129 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1130 | void __iomem *pio = at91_gpio->regbase; | |
1131 | unsigned mask = 1 << d->hwirq; | |
1132 | ||
1133 | switch (type) { | |
1134 | case IRQ_TYPE_EDGE_RISING: | |
1135 | writel_relaxed(mask, pio + PIO_ESR); | |
1136 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1137 | break; | |
1138 | case IRQ_TYPE_EDGE_FALLING: | |
1139 | writel_relaxed(mask, pio + PIO_ESR); | |
1140 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1141 | break; | |
1142 | case IRQ_TYPE_LEVEL_LOW: | |
1143 | writel_relaxed(mask, pio + PIO_LSR); | |
1144 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1145 | break; | |
1146 | case IRQ_TYPE_LEVEL_HIGH: | |
1147 | writel_relaxed(mask, pio + PIO_LSR); | |
1148 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1149 | break; | |
1150 | case IRQ_TYPE_EDGE_BOTH: | |
1151 | /* | |
1152 | * disable additional interrupt modes: | |
1153 | * fall back to default behavior | |
1154 | */ | |
1155 | writel_relaxed(mask, pio + PIO_AIMDR); | |
1156 | return 0; | |
1157 | case IRQ_TYPE_NONE: | |
1158 | default: | |
1159 | pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); | |
1160 | return -EINVAL; | |
1161 | } | |
1162 | ||
1163 | /* enable additional interrupt modes */ | |
1164 | writel_relaxed(mask, pio + PIO_AIMER); | |
1165 | ||
1166 | return 0; | |
1167 | } | |
1168 | ||
1169 | #ifdef CONFIG_PM | |
1170 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) | |
1171 | { | |
1172 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1173 | unsigned bank = at91_gpio->pioc_idx; | |
1174 | ||
1175 | if (unlikely(bank >= MAX_GPIO_BANKS)) | |
1176 | return -EINVAL; | |
1177 | ||
1178 | irq_set_irq_wake(at91_gpio->pioc_virq, state); | |
1179 | ||
1180 | return 0; | |
1181 | } | |
1182 | #else | |
1183 | #define gpio_irq_set_wake NULL | |
1184 | #endif | |
1185 | ||
1186 | static struct irq_chip gpio_irqchip = { | |
1187 | .name = "GPIO", | |
1188 | .irq_disable = gpio_irq_mask, | |
1189 | .irq_mask = gpio_irq_mask, | |
1190 | .irq_unmask = gpio_irq_unmask, | |
1191 | /* .irq_set_type is set dynamically */ | |
1192 | .irq_set_wake = gpio_irq_set_wake, | |
1193 | }; | |
1194 | ||
1195 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
1196 | { | |
1197 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1198 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
1199 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); | |
1200 | void __iomem *pio = at91_gpio->regbase; | |
1201 | unsigned long isr; | |
1202 | int n; | |
1203 | ||
1204 | chained_irq_enter(chip, desc); | |
1205 | for (;;) { | |
1206 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. | |
1207 | * When there none are pending, we're finished unless we need | |
1208 | * to process multiple banks (like ID_PIOCDE on sam9263). | |
1209 | */ | |
1210 | isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); | |
1211 | if (!isr) { | |
1212 | if (!at91_gpio->next) | |
1213 | break; | |
1214 | at91_gpio = at91_gpio->next; | |
1215 | pio = at91_gpio->regbase; | |
1216 | continue; | |
1217 | } | |
1218 | ||
05daa16a | 1219 | for_each_set_bit(n, &isr, BITS_PER_LONG) { |
6732ae5c | 1220 | generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); |
6732ae5c JCPV |
1221 | } |
1222 | } | |
1223 | chained_irq_exit(chip, desc); | |
1224 | /* now it may re-trigger */ | |
1225 | } | |
1226 | ||
1227 | /* | |
1228 | * This lock class tells lockdep that GPIO irqs are in a different | |
1229 | * category than their parents, so it won't report false recursion. | |
1230 | */ | |
1231 | static struct lock_class_key gpio_lock_class; | |
1232 | ||
1233 | static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq, | |
1234 | irq_hw_number_t hw) | |
1235 | { | |
1236 | struct at91_gpio_chip *at91_gpio = h->host_data; | |
1237 | ||
1238 | irq_set_lockdep_class(virq, &gpio_lock_class); | |
1239 | ||
1240 | /* | |
1241 | * Can use the "simple" and not "edge" handler since it's | |
1242 | * shorter, and the AIC handles interrupts sanely. | |
1243 | */ | |
1244 | irq_set_chip_and_handler(virq, &gpio_irqchip, | |
1245 | handle_simple_irq); | |
1246 | set_irq_flags(virq, IRQF_VALID); | |
1247 | irq_set_chip_data(virq, at91_gpio); | |
1248 | ||
1249 | return 0; | |
1250 | } | |
1251 | ||
f6f94f66 AL |
1252 | static int at91_gpio_irq_domain_xlate(struct irq_domain *d, |
1253 | struct device_node *ctrlr, | |
1254 | const u32 *intspec, unsigned int intsize, | |
1255 | irq_hw_number_t *out_hwirq, | |
1256 | unsigned int *out_type) | |
a728c7cd JCPV |
1257 | { |
1258 | struct at91_gpio_chip *at91_gpio = d->host_data; | |
1259 | int ret; | |
1260 | int pin = at91_gpio->chip.base + intspec[0]; | |
1261 | ||
1262 | if (WARN_ON(intsize < 2)) | |
1263 | return -EINVAL; | |
1264 | *out_hwirq = intspec[0]; | |
1265 | *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; | |
1266 | ||
1267 | ret = gpio_request(pin, ctrlr->full_name); | |
1268 | if (ret) | |
1269 | return ret; | |
1270 | ||
1271 | ret = gpio_direction_input(pin); | |
1272 | if (ret) | |
1273 | return ret; | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
6732ae5c JCPV |
1278 | static struct irq_domain_ops at91_gpio_ops = { |
1279 | .map = at91_gpio_irq_map, | |
a728c7cd | 1280 | .xlate = at91_gpio_irq_domain_xlate, |
6732ae5c JCPV |
1281 | }; |
1282 | ||
1283 | static int at91_gpio_of_irq_setup(struct device_node *node, | |
1284 | struct at91_gpio_chip *at91_gpio) | |
1285 | { | |
1286 | struct at91_gpio_chip *prev = NULL; | |
1287 | struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); | |
1288 | ||
1289 | at91_gpio->pioc_hwirq = irqd_to_hwirq(d); | |
1290 | ||
1291 | /* Setup proper .irq_set_type function */ | |
1292 | gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; | |
1293 | ||
1294 | /* Disable irqs of this PIO controller */ | |
1295 | writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); | |
1296 | ||
1297 | /* Setup irq domain */ | |
1298 | at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, | |
1299 | &at91_gpio_ops, at91_gpio); | |
1300 | if (!at91_gpio->domain) | |
1301 | panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", | |
1302 | at91_gpio->pioc_idx); | |
1303 | ||
1304 | /* Setup chained handler */ | |
1305 | if (at91_gpio->pioc_idx) | |
1306 | prev = gpio_chips[at91_gpio->pioc_idx - 1]; | |
1307 | ||
1308 | /* The toplevel handler handles one bank of GPIOs, except | |
1309 | * on some SoC it can handles up to three... | |
1310 | * We only set up the handler for the first of the list. | |
1311 | */ | |
1312 | if (prev && prev->next == at91_gpio) | |
1313 | return 0; | |
1314 | ||
1315 | irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); | |
1316 | irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | /* This structure is replicated for each GPIO block allocated at probe time */ | |
1322 | static struct gpio_chip at91_gpio_template = { | |
1323 | .request = at91_gpio_request, | |
1324 | .free = at91_gpio_free, | |
1325 | .direction_input = at91_gpio_direction_input, | |
1326 | .get = at91_gpio_get, | |
1327 | .direction_output = at91_gpio_direction_output, | |
1328 | .set = at91_gpio_set, | |
1329 | .to_irq = at91_gpio_to_irq, | |
1330 | .dbg_show = at91_gpio_dbg_show, | |
1331 | .can_sleep = 0, | |
1332 | .ngpio = MAX_NB_GPIO_PER_BANK, | |
1333 | }; | |
1334 | ||
1335 | static void __devinit at91_gpio_probe_fixup(void) | |
1336 | { | |
1337 | unsigned i; | |
1338 | struct at91_gpio_chip *at91_gpio, *last = NULL; | |
1339 | ||
1340 | for (i = 0; i < gpio_banks; i++) { | |
1341 | at91_gpio = gpio_chips[i]; | |
1342 | ||
1343 | /* | |
1344 | * GPIO controller are grouped on some SoC: | |
1345 | * PIOC, PIOD and PIOE can share the same IRQ line | |
1346 | */ | |
1347 | if (last && last->pioc_virq == at91_gpio->pioc_virq) | |
1348 | last->next = at91_gpio; | |
1349 | last = at91_gpio; | |
1350 | } | |
1351 | } | |
1352 | ||
1353 | static struct of_device_id at91_gpio_of_match[] __devinitdata = { | |
1354 | { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, | |
1355 | { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, | |
1356 | { /* sentinel */ } | |
1357 | }; | |
1358 | ||
1359 | static int __devinit at91_gpio_probe(struct platform_device *pdev) | |
1360 | { | |
1361 | struct device_node *np = pdev->dev.of_node; | |
1362 | struct resource *res; | |
1363 | struct at91_gpio_chip *at91_chip = NULL; | |
1364 | struct gpio_chip *chip; | |
1365 | struct pinctrl_gpio_range *range; | |
1366 | int ret = 0; | |
1367 | int irq; | |
1368 | int alias_idx = of_alias_get_id(np, "gpio"); | |
1369 | uint32_t ngpio; | |
1370 | ||
1371 | BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); | |
1372 | if (gpio_chips[alias_idx]) { | |
1373 | ret = -EBUSY; | |
1374 | goto err; | |
1375 | } | |
1376 | ||
1377 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1378 | if (!res) { | |
1379 | ret = -ENOENT; | |
1380 | goto err; | |
1381 | } | |
1382 | ||
1383 | irq = platform_get_irq(pdev, 0); | |
1384 | if (irq < 0) { | |
1385 | ret = irq; | |
1386 | goto err; | |
1387 | } | |
1388 | ||
1389 | at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); | |
1390 | if (!at91_chip) { | |
1391 | ret = -ENOMEM; | |
1392 | goto err; | |
1393 | } | |
1394 | ||
1395 | at91_chip->regbase = devm_request_and_ioremap(&pdev->dev, res); | |
1396 | if (!at91_chip->regbase) { | |
1397 | dev_err(&pdev->dev, "failed to map registers, ignoring.\n"); | |
1398 | ret = -EBUSY; | |
1399 | goto err; | |
1400 | } | |
1401 | ||
dffa9123 | 1402 | at91_chip->ops = (struct at91_pinctrl_mux_ops*) |
6732ae5c JCPV |
1403 | of_match_device(at91_gpio_of_match, &pdev->dev)->data; |
1404 | at91_chip->pioc_virq = irq; | |
1405 | at91_chip->pioc_idx = alias_idx; | |
1406 | ||
1407 | at91_chip->clock = clk_get(&pdev->dev, NULL); | |
1408 | if (IS_ERR(at91_chip->clock)) { | |
1409 | dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); | |
1410 | goto err; | |
1411 | } | |
1412 | ||
1413 | if (clk_prepare(at91_chip->clock)) | |
1414 | goto clk_prep_err; | |
1415 | ||
1416 | /* enable PIO controller's clock */ | |
1417 | if (clk_enable(at91_chip->clock)) { | |
1418 | dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); | |
1419 | goto clk_err; | |
1420 | } | |
1421 | ||
1422 | at91_chip->chip = at91_gpio_template; | |
1423 | ||
1424 | chip = &at91_chip->chip; | |
1425 | chip->of_node = np; | |
1426 | chip->label = dev_name(&pdev->dev); | |
1427 | chip->dev = &pdev->dev; | |
1428 | chip->owner = THIS_MODULE; | |
1429 | chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; | |
1430 | ||
1431 | if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { | |
1432 | if (ngpio >= MAX_NB_GPIO_PER_BANK) | |
1433 | pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", | |
1434 | alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); | |
1435 | else | |
1436 | chip->ngpio = ngpio; | |
1437 | } | |
1438 | ||
1439 | range = &at91_chip->range; | |
1440 | range->name = chip->label; | |
1441 | range->id = alias_idx; | |
1442 | range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; | |
1443 | ||
1444 | range->npins = chip->ngpio; | |
1445 | range->gc = chip; | |
1446 | ||
1447 | ret = gpiochip_add(chip); | |
1448 | if (ret) | |
1449 | goto clk_err; | |
1450 | ||
1451 | gpio_chips[alias_idx] = at91_chip; | |
1452 | gpio_banks = max(gpio_banks, alias_idx + 1); | |
1453 | ||
1454 | at91_gpio_probe_fixup(); | |
1455 | ||
1456 | at91_gpio_of_irq_setup(np, at91_chip); | |
1457 | ||
1458 | dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); | |
1459 | ||
1460 | return 0; | |
1461 | ||
1462 | clk_err: | |
1463 | clk_unprepare(at91_chip->clock); | |
1464 | clk_prep_err: | |
1465 | clk_put(at91_chip->clock); | |
1466 | err: | |
1467 | dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); | |
1468 | ||
1469 | return ret; | |
1470 | } | |
1471 | ||
1472 | static struct platform_driver at91_gpio_driver = { | |
1473 | .driver = { | |
1474 | .name = "gpio-at91", | |
1475 | .owner = THIS_MODULE, | |
1476 | .of_match_table = of_match_ptr(at91_gpio_of_match), | |
1477 | }, | |
1478 | .probe = at91_gpio_probe, | |
1479 | }; | |
1480 | ||
1481 | static struct platform_driver at91_pinctrl_driver = { | |
1482 | .driver = { | |
1483 | .name = "pinctrl-at91", | |
1484 | .owner = THIS_MODULE, | |
1485 | .of_match_table = of_match_ptr(at91_pinctrl_of_match), | |
1486 | }, | |
1487 | .probe = at91_pinctrl_probe, | |
1488 | .remove = __devexit_p(at91_pinctrl_remove), | |
1489 | }; | |
1490 | ||
1491 | static int __init at91_pinctrl_init(void) | |
1492 | { | |
1493 | int ret; | |
1494 | ||
1495 | ret = platform_driver_register(&at91_gpio_driver); | |
1496 | if (ret) | |
1497 | return ret; | |
1498 | return platform_driver_register(&at91_pinctrl_driver); | |
1499 | } | |
1500 | arch_initcall(at91_pinctrl_init); | |
1501 | ||
1502 | static void __exit at91_pinctrl_exit(void) | |
1503 | { | |
1504 | platform_driver_unregister(&at91_pinctrl_driver); | |
1505 | } | |
1506 | ||
1507 | module_exit(at91_pinctrl_exit); | |
1508 | MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); | |
1509 | MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); | |
1510 | MODULE_LICENSE("GPL v2"); |