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6732ae5c JCPV |
1 | /* |
2 | * at91 pinctrl driver based on at91 pinmux core | |
3 | * | |
4 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
5 | * | |
6 | * Under GPLv2 only | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/of_device.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/irqdomain.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/gpio.h> | |
6732ae5c JCPV |
23 | #include <linux/pinctrl/machine.h> |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinctrl.h> | |
26 | #include <linux/pinctrl/pinmux.h> | |
27 | /* Since we request GPIOs from ourself */ | |
28 | #include <linux/pinctrl/consumer.h> | |
29 | ||
30 | #include <asm/mach/irq.h> | |
31 | ||
32 | #include <mach/hardware.h> | |
33 | #include <mach/at91_pio.h> | |
34 | ||
35 | #include "core.h" | |
36 | ||
37 | #define MAX_NB_GPIO_PER_BANK 32 | |
38 | ||
39 | struct at91_pinctrl_mux_ops; | |
40 | ||
41 | struct at91_gpio_chip { | |
42 | struct gpio_chip chip; | |
43 | struct pinctrl_gpio_range range; | |
44 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | |
45 | int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ | |
46 | int pioc_virq; /* PIO bank Linux virtual interrupt */ | |
47 | int pioc_idx; /* PIO bank index */ | |
48 | void __iomem *regbase; /* PIO bank virtual address */ | |
49 | struct clk *clock; /* associated clock */ | |
50 | struct irq_domain *domain; /* associated irq domain */ | |
51 | struct at91_pinctrl_mux_ops *ops; /* ops */ | |
52 | }; | |
53 | ||
54 | #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) | |
55 | ||
56 | static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; | |
57 | ||
58 | static int gpio_banks; | |
59 | ||
525fae21 | 60 | #define PULL_UP (1 << 0) |
6732ae5c JCPV |
61 | #define MULTI_DRIVE (1 << 1) |
62 | ||
63 | /** | |
64 | * struct at91_pmx_func - describes AT91 pinmux functions | |
65 | * @name: the name of this specific function | |
66 | * @groups: corresponding pin groups | |
67 | * @ngroups: the number of groups | |
68 | */ | |
69 | struct at91_pmx_func { | |
70 | const char *name; | |
71 | const char **groups; | |
72 | unsigned ngroups; | |
73 | }; | |
74 | ||
75 | enum at91_mux { | |
76 | AT91_MUX_GPIO = 0, | |
77 | AT91_MUX_PERIPH_A = 1, | |
78 | AT91_MUX_PERIPH_B = 2, | |
79 | AT91_MUX_PERIPH_C = 3, | |
80 | AT91_MUX_PERIPH_D = 4, | |
81 | }; | |
82 | ||
83 | /** | |
84 | * struct at91_pmx_pin - describes an At91 pin mux | |
85 | * @bank: the bank of the pin | |
86 | * @pin: the pin number in the @bank | |
87 | * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. | |
88 | * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... | |
89 | */ | |
90 | struct at91_pmx_pin { | |
91 | uint32_t bank; | |
92 | uint32_t pin; | |
93 | enum at91_mux mux; | |
94 | unsigned long conf; | |
95 | }; | |
96 | ||
97 | /** | |
98 | * struct at91_pin_group - describes an At91 pin group | |
99 | * @name: the name of this specific pin group | |
100 | * @pins_conf: the mux mode for each pin in this group. The size of this | |
101 | * array is the same as pins. | |
102 | * @pins: an array of discrete physical pins used in this group, taken | |
103 | * from the driver-local pin enumeration space | |
104 | * @npins: the number of pins in this group array, i.e. the number of | |
105 | * elements in .pins so we can iterate over that array | |
106 | */ | |
107 | struct at91_pin_group { | |
108 | const char *name; | |
109 | struct at91_pmx_pin *pins_conf; | |
110 | unsigned int *pins; | |
111 | unsigned npins; | |
112 | }; | |
113 | ||
114 | /** | |
115 | * struct at91_pinctrl_mux_ops - describes an At91 mux ops group | |
116 | * on new IP with support for periph C and D the way to mux in | |
117 | * periph A and B has changed | |
118 | * So provide the right call back | |
119 | * if not present means the IP does not support it | |
120 | * @get_periph: return the periph mode configured | |
121 | * @mux_A_periph: mux as periph A | |
122 | * @mux_B_periph: mux as periph B | |
123 | * @mux_C_periph: mux as periph C | |
124 | * @mux_D_periph: mux as periph D | |
125 | * @irq_type: return irq type | |
126 | */ | |
127 | struct at91_pinctrl_mux_ops { | |
128 | enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); | |
129 | void (*mux_A_periph)(void __iomem *pio, unsigned mask); | |
130 | void (*mux_B_periph)(void __iomem *pio, unsigned mask); | |
131 | void (*mux_C_periph)(void __iomem *pio, unsigned mask); | |
132 | void (*mux_D_periph)(void __iomem *pio, unsigned mask); | |
133 | /* irq */ | |
134 | int (*irq_type)(struct irq_data *d, unsigned type); | |
135 | }; | |
136 | ||
137 | static int gpio_irq_type(struct irq_data *d, unsigned type); | |
138 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type); | |
139 | ||
140 | struct at91_pinctrl { | |
141 | struct device *dev; | |
142 | struct pinctrl_dev *pctl; | |
143 | ||
144 | int nbanks; | |
145 | ||
146 | uint32_t *mux_mask; | |
147 | int nmux; | |
148 | ||
149 | struct at91_pmx_func *functions; | |
150 | int nfunctions; | |
151 | ||
152 | struct at91_pin_group *groups; | |
153 | int ngroups; | |
154 | ||
155 | struct at91_pinctrl_mux_ops *ops; | |
156 | }; | |
157 | ||
158 | static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( | |
159 | const struct at91_pinctrl *info, | |
160 | const char *name) | |
161 | { | |
162 | const struct at91_pin_group *grp = NULL; | |
163 | int i; | |
164 | ||
165 | for (i = 0; i < info->ngroups; i++) { | |
166 | if (strcmp(info->groups[i].name, name)) | |
167 | continue; | |
168 | ||
169 | grp = &info->groups[i]; | |
170 | dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); | |
171 | break; | |
172 | } | |
173 | ||
174 | return grp; | |
175 | } | |
176 | ||
177 | static int at91_get_groups_count(struct pinctrl_dev *pctldev) | |
178 | { | |
179 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
180 | ||
181 | return info->ngroups; | |
182 | } | |
183 | ||
184 | static const char *at91_get_group_name(struct pinctrl_dev *pctldev, | |
185 | unsigned selector) | |
186 | { | |
187 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
188 | ||
189 | return info->groups[selector].name; | |
190 | } | |
191 | ||
192 | static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
193 | const unsigned **pins, | |
194 | unsigned *npins) | |
195 | { | |
196 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
197 | ||
198 | if (selector >= info->ngroups) | |
199 | return -EINVAL; | |
200 | ||
201 | *pins = info->groups[selector].pins; | |
202 | *npins = info->groups[selector].npins; | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
208 | unsigned offset) | |
209 | { | |
210 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
211 | } | |
212 | ||
213 | static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, | |
214 | struct device_node *np, | |
215 | struct pinctrl_map **map, unsigned *num_maps) | |
216 | { | |
217 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
218 | const struct at91_pin_group *grp; | |
219 | struct pinctrl_map *new_map; | |
220 | struct device_node *parent; | |
221 | int map_num = 1; | |
222 | int i; | |
223 | struct at91_pmx_pin *pin; | |
224 | ||
225 | /* | |
226 | * first find the group of this node and check if we need create | |
227 | * config maps for pins | |
228 | */ | |
229 | grp = at91_pinctrl_find_group_by_name(info, np->name); | |
230 | if (!grp) { | |
231 | dev_err(info->dev, "unable to find group for node %s\n", | |
232 | np->name); | |
233 | return -EINVAL; | |
234 | } | |
235 | ||
236 | map_num += grp->npins; | |
237 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); | |
238 | if (!new_map) | |
239 | return -ENOMEM; | |
240 | ||
241 | *map = new_map; | |
242 | *num_maps = map_num; | |
243 | ||
244 | /* create mux map */ | |
245 | parent = of_get_parent(np); | |
246 | if (!parent) { | |
247 | kfree(new_map); | |
248 | return -EINVAL; | |
249 | } | |
250 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
251 | new_map[0].data.mux.function = parent->name; | |
252 | new_map[0].data.mux.group = np->name; | |
253 | of_node_put(parent); | |
254 | ||
255 | /* create config map */ | |
256 | new_map++; | |
257 | for (i = 0; i < grp->npins; i++) { | |
258 | pin = &grp->pins_conf[i]; | |
259 | ||
260 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
261 | new_map[i].data.configs.group_or_pin = | |
262 | pin_get_name(pctldev, grp->pins[i]); | |
263 | new_map[i].data.configs.configs = &grp->pins_conf[i].conf; | |
264 | new_map[i].data.configs.num_configs = 1; | |
265 | } | |
266 | ||
267 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
268 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | static void at91_dt_free_map(struct pinctrl_dev *pctldev, | |
274 | struct pinctrl_map *map, unsigned num_maps) | |
275 | { | |
276 | } | |
277 | ||
278 | static struct pinctrl_ops at91_pctrl_ops = { | |
279 | .get_groups_count = at91_get_groups_count, | |
280 | .get_group_name = at91_get_group_name, | |
281 | .get_group_pins = at91_get_group_pins, | |
282 | .pin_dbg_show = at91_pin_dbg_show, | |
283 | .dt_node_to_map = at91_dt_node_to_map, | |
284 | .dt_free_map = at91_dt_free_map, | |
285 | }; | |
286 | ||
287 | static void __iomem * pin_to_controller(struct at91_pinctrl *info, | |
288 | unsigned int bank) | |
289 | { | |
290 | return gpio_chips[bank]->regbase; | |
291 | } | |
292 | ||
293 | static inline int pin_to_bank(unsigned pin) | |
294 | { | |
295 | return pin /= MAX_NB_GPIO_PER_BANK; | |
296 | } | |
297 | ||
298 | static unsigned pin_to_mask(unsigned int pin) | |
299 | { | |
300 | return 1 << pin; | |
301 | } | |
302 | ||
303 | static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) | |
304 | { | |
305 | writel_relaxed(mask, pio + PIO_IDR); | |
306 | } | |
307 | ||
308 | static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) | |
309 | { | |
310 | return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1; | |
311 | } | |
312 | ||
313 | static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) | |
314 | { | |
315 | writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); | |
316 | } | |
317 | ||
318 | static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) | |
319 | { | |
320 | return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; | |
321 | } | |
322 | ||
323 | static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) | |
324 | { | |
325 | writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); | |
326 | } | |
327 | ||
328 | static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) | |
329 | { | |
330 | writel_relaxed(mask, pio + PIO_ASR); | |
331 | } | |
332 | ||
333 | static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) | |
334 | { | |
335 | writel_relaxed(mask, pio + PIO_BSR); | |
336 | } | |
337 | ||
338 | static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) | |
339 | { | |
340 | ||
341 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, | |
342 | pio + PIO_ABCDSR1); | |
343 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
344 | pio + PIO_ABCDSR2); | |
345 | } | |
346 | ||
347 | static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) | |
348 | { | |
349 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, | |
350 | pio + PIO_ABCDSR1); | |
351 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
352 | pio + PIO_ABCDSR2); | |
353 | } | |
354 | ||
355 | static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) | |
356 | { | |
357 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); | |
358 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
359 | } | |
360 | ||
361 | static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) | |
362 | { | |
363 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); | |
364 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
365 | } | |
366 | ||
367 | static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) | |
368 | { | |
369 | unsigned select; | |
370 | ||
371 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
372 | return AT91_MUX_GPIO; | |
373 | ||
374 | select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); | |
375 | select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); | |
376 | ||
377 | return select + 1; | |
378 | } | |
379 | ||
380 | static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) | |
381 | { | |
382 | unsigned select; | |
383 | ||
384 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
385 | return AT91_MUX_GPIO; | |
386 | ||
387 | select = readl_relaxed(pio + PIO_ABSR) & mask; | |
388 | ||
389 | return select + 1; | |
390 | } | |
391 | ||
392 | static struct at91_pinctrl_mux_ops at91rm9200_ops = { | |
393 | .get_periph = at91_mux_get_periph, | |
394 | .mux_A_periph = at91_mux_set_A_periph, | |
395 | .mux_B_periph = at91_mux_set_B_periph, | |
396 | .irq_type = gpio_irq_type, | |
397 | }; | |
398 | ||
399 | static struct at91_pinctrl_mux_ops at91sam9x5_ops = { | |
400 | .get_periph = at91_mux_pio3_get_periph, | |
401 | .mux_A_periph = at91_mux_pio3_set_A_periph, | |
402 | .mux_B_periph = at91_mux_pio3_set_B_periph, | |
403 | .mux_C_periph = at91_mux_pio3_set_C_periph, | |
404 | .mux_D_periph = at91_mux_pio3_set_D_periph, | |
405 | .irq_type = alt_gpio_irq_type, | |
406 | }; | |
407 | ||
408 | static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) | |
409 | { | |
410 | if (pin->mux) { | |
411 | dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", | |
412 | pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); | |
413 | } else { | |
414 | dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", | |
415 | pin->bank + 'A', pin->pin, pin->conf); | |
416 | } | |
417 | } | |
418 | ||
419 | static int pin_check_config(struct at91_pinctrl *info, const char* name, | |
420 | int index, const struct at91_pmx_pin *pin) | |
421 | { | |
422 | int mux; | |
423 | ||
424 | /* check if it's a valid config */ | |
425 | if (pin->bank >= info->nbanks) { | |
426 | dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", | |
427 | name, index, pin->bank, info->nbanks); | |
428 | return -EINVAL; | |
429 | } | |
430 | ||
431 | if (pin->pin >= MAX_NB_GPIO_PER_BANK) { | |
432 | dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", | |
433 | name, index, pin->pin, MAX_NB_GPIO_PER_BANK); | |
434 | return -EINVAL; | |
435 | } | |
436 | ||
437 | if (!pin->mux) | |
438 | return 0; | |
439 | ||
440 | mux = pin->mux - 1; | |
441 | ||
442 | if (mux >= info->nmux) { | |
443 | dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", | |
444 | name, index, mux, info->nmux); | |
445 | return -EINVAL; | |
446 | } | |
447 | ||
448 | if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { | |
449 | dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", | |
450 | name, index, mux, pin->bank + 'A', pin->pin); | |
451 | return -EINVAL; | |
452 | } | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) | |
458 | { | |
459 | writel_relaxed(mask, pio + PIO_PDR); | |
460 | } | |
461 | ||
462 | static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) | |
463 | { | |
464 | writel_relaxed(mask, pio + PIO_PER); | |
465 | writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); | |
466 | } | |
467 | ||
468 | static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
469 | unsigned group) | |
470 | { | |
471 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
472 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
473 | const struct at91_pmx_pin *pin; | |
474 | uint32_t npins = info->groups[group].npins; | |
475 | int i, ret; | |
476 | unsigned mask; | |
477 | void __iomem *pio; | |
478 | ||
479 | dev_dbg(info->dev, "enable function %s group %s\n", | |
480 | info->functions[selector].name, info->groups[group].name); | |
481 | ||
482 | /* first check that all the pins of the group are valid with a valid | |
483 | * paramter */ | |
484 | for (i = 0; i < npins; i++) { | |
485 | pin = &pins_conf[i]; | |
486 | ret = pin_check_config(info, info->groups[group].name, i, pin); | |
487 | if (ret) | |
488 | return ret; | |
489 | } | |
490 | ||
491 | for (i = 0; i < npins; i++) { | |
492 | pin = &pins_conf[i]; | |
493 | at91_pin_dbg(info->dev, pin); | |
494 | pio = pin_to_controller(info, pin->bank); | |
495 | mask = pin_to_mask(pin->pin); | |
496 | at91_mux_disable_interrupt(pio, mask); | |
497 | switch(pin->mux) { | |
498 | case AT91_MUX_GPIO: | |
499 | at91_mux_gpio_enable(pio, mask, 1); | |
500 | break; | |
501 | case AT91_MUX_PERIPH_A: | |
502 | info->ops->mux_A_periph(pio, mask); | |
503 | break; | |
504 | case AT91_MUX_PERIPH_B: | |
505 | info->ops->mux_B_periph(pio, mask); | |
506 | break; | |
507 | case AT91_MUX_PERIPH_C: | |
508 | if (!info->ops->mux_C_periph) | |
509 | return -EINVAL; | |
510 | info->ops->mux_C_periph(pio, mask); | |
511 | break; | |
512 | case AT91_MUX_PERIPH_D: | |
513 | if (!info->ops->mux_D_periph) | |
514 | return -EINVAL; | |
515 | info->ops->mux_D_periph(pio, mask); | |
516 | break; | |
517 | } | |
518 | if (pin->mux) | |
519 | at91_mux_gpio_disable(pio, mask); | |
520 | } | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, | |
526 | unsigned group) | |
527 | { | |
528 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
529 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
530 | const struct at91_pmx_pin *pin; | |
531 | uint32_t npins = info->groups[group].npins; | |
532 | int i; | |
533 | unsigned mask; | |
534 | void __iomem *pio; | |
535 | ||
536 | for (i = 0; i < npins; i++) { | |
537 | pin = &pins_conf[i]; | |
538 | at91_pin_dbg(info->dev, pin); | |
539 | pio = pin_to_controller(info, pin->bank); | |
540 | mask = pin_to_mask(pin->pin); | |
541 | at91_mux_gpio_enable(pio, mask, 1); | |
542 | } | |
543 | } | |
544 | ||
545 | static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
546 | { | |
547 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
548 | ||
549 | return info->nfunctions; | |
550 | } | |
551 | ||
552 | static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
553 | unsigned selector) | |
554 | { | |
555 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
556 | ||
557 | return info->functions[selector].name; | |
558 | } | |
559 | ||
560 | static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
561 | const char * const **groups, | |
562 | unsigned * const num_groups) | |
563 | { | |
564 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
565 | ||
566 | *groups = info->functions[selector].groups; | |
567 | *num_groups = info->functions[selector].ngroups; | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
572 | int at91_gpio_request_enable(struct pinctrl_dev *pctldev, | |
573 | struct pinctrl_gpio_range *range, | |
574 | unsigned offset) | |
575 | { | |
576 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
577 | struct at91_gpio_chip *at91_chip; | |
578 | struct gpio_chip *chip; | |
579 | unsigned mask; | |
580 | ||
581 | if (!range) { | |
582 | dev_err(npct->dev, "invalid range\n"); | |
583 | return -EINVAL; | |
584 | } | |
585 | if (!range->gc) { | |
586 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
587 | return -EINVAL; | |
588 | } | |
589 | chip = range->gc; | |
590 | at91_chip = container_of(chip, struct at91_gpio_chip, chip); | |
591 | ||
592 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
593 | ||
594 | mask = 1 << (offset - chip->base); | |
595 | ||
596 | dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", | |
597 | offset, 'A' + range->id, offset - chip->base, mask); | |
598 | ||
599 | writel_relaxed(mask, at91_chip->regbase + PIO_PER); | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | void at91_gpio_disable_free(struct pinctrl_dev *pctldev, | |
605 | struct pinctrl_gpio_range *range, | |
606 | unsigned offset) | |
607 | { | |
608 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
609 | ||
610 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
611 | /* Set the pin to some default state, GPIO is usually default */ | |
612 | } | |
613 | ||
614 | static struct pinmux_ops at91_pmx_ops = { | |
615 | .get_functions_count = at91_pmx_get_funcs_count, | |
616 | .get_function_name = at91_pmx_get_func_name, | |
617 | .get_function_groups = at91_pmx_get_groups, | |
618 | .enable = at91_pmx_enable, | |
619 | .disable = at91_pmx_disable, | |
620 | .gpio_request_enable = at91_gpio_request_enable, | |
621 | .gpio_disable_free = at91_gpio_disable_free, | |
622 | }; | |
623 | ||
624 | static int at91_pinconf_get(struct pinctrl_dev *pctldev, | |
625 | unsigned pin_id, unsigned long *config) | |
626 | { | |
627 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
628 | void __iomem *pio; | |
629 | unsigned pin; | |
630 | ||
631 | dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); | |
632 | pio = pin_to_controller(info, pin_to_bank(pin_id)); | |
633 | pin = pin_id % MAX_NB_GPIO_PER_BANK; | |
634 | ||
635 | if (at91_mux_get_multidrive(pio, pin)) | |
636 | *config |= MULTI_DRIVE; | |
637 | ||
638 | if (at91_mux_get_pullup(pio, pin)) | |
639 | *config |= PULL_UP; | |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
644 | static int at91_pinconf_set(struct pinctrl_dev *pctldev, | |
645 | unsigned pin_id, unsigned long config) | |
646 | { | |
647 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
648 | unsigned mask; | |
649 | void __iomem *pio; | |
650 | ||
651 | dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config); | |
652 | pio = pin_to_controller(info, pin_to_bank(pin_id)); | |
653 | mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); | |
654 | ||
655 | at91_mux_set_pullup(pio, mask, config & PULL_UP); | |
656 | at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); | |
657 | return 0; | |
658 | } | |
659 | ||
660 | static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
661 | struct seq_file *s, unsigned pin_id) | |
662 | { | |
663 | ||
664 | } | |
665 | ||
666 | static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
667 | struct seq_file *s, unsigned group) | |
668 | { | |
669 | } | |
670 | ||
671 | struct pinconf_ops at91_pinconf_ops = { | |
672 | .pin_config_get = at91_pinconf_get, | |
673 | .pin_config_set = at91_pinconf_set, | |
674 | .pin_config_dbg_show = at91_pinconf_dbg_show, | |
675 | .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, | |
676 | }; | |
677 | ||
678 | static struct pinctrl_desc at91_pinctrl_desc = { | |
679 | .pctlops = &at91_pctrl_ops, | |
680 | .pmxops = &at91_pmx_ops, | |
681 | .confops = &at91_pinconf_ops, | |
682 | .owner = THIS_MODULE, | |
683 | }; | |
684 | ||
685 | static const char *gpio_compat = "atmel,at91rm9200-gpio"; | |
686 | ||
687 | static void __devinit at91_pinctrl_child_count(struct at91_pinctrl *info, | |
688 | struct device_node *np) | |
689 | { | |
690 | struct device_node *child; | |
691 | ||
692 | for_each_child_of_node(np, child) { | |
693 | if (of_device_is_compatible(child, gpio_compat)) { | |
694 | info->nbanks++; | |
695 | } else { | |
696 | info->nfunctions++; | |
697 | info->ngroups += of_get_child_count(child); | |
698 | } | |
699 | } | |
700 | } | |
701 | ||
702 | static int __devinit at91_pinctrl_mux_mask(struct at91_pinctrl *info, | |
703 | struct device_node *np) | |
704 | { | |
705 | int ret = 0; | |
706 | int size; | |
707 | const const __be32 *list; | |
708 | ||
709 | list = of_get_property(np, "atmel,mux-mask", &size); | |
710 | if (!list) { | |
711 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
712 | return -EINVAL; | |
713 | } | |
714 | ||
715 | size /= sizeof(*list); | |
716 | if (!size || size % info->nbanks) { | |
717 | dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); | |
718 | return -EINVAL; | |
719 | } | |
720 | info->nmux = size / info->nbanks; | |
721 | ||
722 | info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); | |
723 | if (!info->mux_mask) { | |
724 | dev_err(info->dev, "could not alloc mux_mask\n"); | |
725 | return -ENOMEM; | |
726 | } | |
727 | ||
728 | ret = of_property_read_u32_array(np, "atmel,mux-mask", | |
729 | info->mux_mask, size); | |
730 | if (ret) | |
731 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
732 | return ret; | |
733 | } | |
734 | ||
735 | static int __devinit at91_pinctrl_parse_groups(struct device_node *np, | |
736 | struct at91_pin_group *grp, | |
737 | struct at91_pinctrl *info, | |
738 | u32 index) | |
739 | { | |
740 | struct at91_pmx_pin *pin; | |
741 | int size; | |
742 | const const __be32 *list; | |
743 | int i, j; | |
744 | ||
745 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
746 | ||
747 | /* Initialise group */ | |
748 | grp->name = np->name; | |
749 | ||
750 | /* | |
751 | * the binding format is atmel,pins = <bank pin mux CONFIG ...>, | |
752 | * do sanity check and calculate pins number | |
753 | */ | |
754 | list = of_get_property(np, "atmel,pins", &size); | |
755 | /* we do not check return since it's safe node passed down */ | |
756 | size /= sizeof(*list); | |
757 | if (!size || size % 4) { | |
758 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
759 | return -EINVAL; | |
760 | } | |
761 | ||
762 | grp->npins = size / 4; | |
763 | pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), | |
764 | GFP_KERNEL); | |
765 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
766 | GFP_KERNEL); | |
767 | if (!grp->pins_conf || !grp->pins) | |
768 | return -ENOMEM; | |
769 | ||
770 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
771 | pin->bank = be32_to_cpu(*list++); | |
772 | pin->pin = be32_to_cpu(*list++); | |
773 | grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; | |
774 | pin->mux = be32_to_cpu(*list++); | |
775 | pin->conf = be32_to_cpu(*list++); | |
776 | ||
777 | at91_pin_dbg(info->dev, pin); | |
778 | pin++; | |
779 | } | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
784 | static int __devinit at91_pinctrl_parse_functions(struct device_node *np, | |
785 | struct at91_pinctrl *info, u32 index) | |
786 | { | |
787 | struct device_node *child; | |
788 | struct at91_pmx_func *func; | |
789 | struct at91_pin_group *grp; | |
790 | int ret; | |
791 | static u32 grp_index; | |
792 | u32 i = 0; | |
793 | ||
794 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
795 | ||
796 | func = &info->functions[index]; | |
797 | ||
798 | /* Initialise function */ | |
799 | func->name = np->name; | |
800 | func->ngroups = of_get_child_count(np); | |
801 | if (func->ngroups <= 0) { | |
802 | dev_err(info->dev, "no groups defined\n"); | |
803 | return -EINVAL; | |
804 | } | |
805 | func->groups = devm_kzalloc(info->dev, | |
806 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
807 | if (!func->groups) | |
808 | return -ENOMEM; | |
809 | ||
810 | for_each_child_of_node(np, child) { | |
811 | func->groups[i] = child->name; | |
812 | grp = &info->groups[grp_index++]; | |
813 | ret = at91_pinctrl_parse_groups(child, grp, info, i++); | |
814 | if (ret) | |
815 | return ret; | |
816 | } | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | static struct of_device_id at91_pinctrl_of_match[] __devinitdata = { | |
822 | { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, | |
823 | { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, | |
824 | { /* sentinel */ } | |
825 | }; | |
826 | ||
827 | static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev, | |
828 | struct at91_pinctrl *info) | |
829 | { | |
830 | int ret = 0; | |
831 | int i, j; | |
832 | uint32_t *tmp; | |
833 | struct device_node *np = pdev->dev.of_node; | |
834 | struct device_node *child; | |
835 | ||
836 | if (!np) | |
837 | return -ENODEV; | |
838 | ||
839 | info->dev = &pdev->dev; | |
dffa9123 | 840 | info->ops = (struct at91_pinctrl_mux_ops*) |
6732ae5c JCPV |
841 | of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; |
842 | at91_pinctrl_child_count(info, np); | |
843 | ||
844 | if (info->nbanks < 1) { | |
845 | dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); | |
846 | return -EINVAL; | |
847 | } | |
848 | ||
849 | ret = at91_pinctrl_mux_mask(info, np); | |
850 | if (ret) | |
851 | return ret; | |
852 | ||
853 | dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); | |
854 | ||
855 | dev_dbg(&pdev->dev, "mux-mask\n"); | |
856 | tmp = info->mux_mask; | |
857 | for (i = 0; i < info->nbanks; i++) { | |
858 | for (j = 0; j < info->nmux; j++, tmp++) { | |
859 | dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); | |
860 | } | |
861 | } | |
862 | ||
863 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
864 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
865 | info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), | |
866 | GFP_KERNEL); | |
867 | if (!info->functions) | |
868 | return -ENOMEM; | |
869 | ||
870 | info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), | |
871 | GFP_KERNEL); | |
872 | if (!info->groups) | |
873 | return -ENOMEM; | |
874 | ||
875 | dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); | |
876 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
877 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
878 | ||
879 | i = 0; | |
880 | ||
881 | for_each_child_of_node(np, child) { | |
882 | if (of_device_is_compatible(child, gpio_compat)) | |
883 | continue; | |
884 | ret = at91_pinctrl_parse_functions(child, info, i++); | |
885 | if (ret) { | |
886 | dev_err(&pdev->dev, "failed to parse function\n"); | |
887 | return ret; | |
888 | } | |
889 | } | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
894 | static int __devinit at91_pinctrl_probe(struct platform_device *pdev) | |
895 | { | |
896 | struct at91_pinctrl *info; | |
897 | struct pinctrl_pin_desc *pdesc; | |
898 | int ret, i, j ,k; | |
899 | ||
900 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
901 | if (!info) | |
902 | return -ENOMEM; | |
903 | ||
904 | ret = at91_pinctrl_probe_dt(pdev, info); | |
905 | if (ret) | |
906 | return ret; | |
907 | ||
908 | /* | |
909 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
910 | * to obtain references to the struct gpio_chip * for them, and we | |
911 | * need this to proceed. | |
912 | */ | |
913 | for (i = 0; i < info->nbanks; i++) { | |
914 | if (!gpio_chips[i]) { | |
915 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); | |
916 | devm_kfree(&pdev->dev, info); | |
917 | return -EPROBE_DEFER; | |
918 | } | |
919 | } | |
920 | ||
921 | at91_pinctrl_desc.name = dev_name(&pdev->dev); | |
922 | at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; | |
923 | at91_pinctrl_desc.pins = pdesc = | |
924 | devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); | |
925 | ||
926 | if (!at91_pinctrl_desc.pins) | |
927 | return -ENOMEM; | |
928 | ||
929 | for (i = 0 , k = 0; i < info->nbanks; i++) { | |
930 | for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { | |
931 | pdesc->number = k; | |
932 | pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); | |
933 | pdesc++; | |
934 | } | |
935 | } | |
936 | ||
937 | platform_set_drvdata(pdev, info); | |
938 | info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); | |
939 | ||
940 | if (!info->pctl) { | |
941 | dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); | |
942 | ret = -EINVAL; | |
943 | goto err; | |
944 | } | |
945 | ||
946 | /* We will handle a range of GPIO pins */ | |
947 | for (i = 0; i < info->nbanks; i++) | |
948 | pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); | |
949 | ||
950 | dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); | |
951 | ||
952 | return 0; | |
953 | ||
954 | err: | |
955 | return ret; | |
956 | } | |
957 | ||
958 | int __devexit at91_pinctrl_remove(struct platform_device *pdev) | |
959 | { | |
960 | struct at91_pinctrl *info = platform_get_drvdata(pdev); | |
961 | ||
962 | pinctrl_unregister(info->pctl); | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
967 | static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) | |
968 | { | |
969 | /* | |
970 | * Map back to global GPIO space and request muxing, the direction | |
971 | * parameter does not matter for this controller. | |
972 | */ | |
973 | int gpio = chip->base + offset; | |
974 | int bank = chip->base / chip->ngpio; | |
975 | ||
976 | dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, | |
977 | 'A' + bank, offset, gpio); | |
978 | ||
979 | return pinctrl_request_gpio(gpio); | |
980 | } | |
981 | ||
982 | static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) | |
983 | { | |
984 | int gpio = chip->base + offset; | |
985 | ||
986 | pinctrl_free_gpio(gpio); | |
987 | } | |
988 | ||
989 | static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
990 | { | |
991 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
992 | void __iomem *pio = at91_gpio->regbase; | |
993 | unsigned mask = 1 << offset; | |
994 | ||
995 | writel_relaxed(mask, pio + PIO_ODR); | |
996 | return 0; | |
997 | } | |
998 | ||
999 | static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) | |
1000 | { | |
1001 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1002 | void __iomem *pio = at91_gpio->regbase; | |
1003 | unsigned mask = 1 << offset; | |
1004 | u32 pdsr; | |
1005 | ||
1006 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1007 | return (pdsr & mask) != 0; | |
1008 | } | |
1009 | ||
1010 | static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, | |
1011 | int val) | |
1012 | { | |
1013 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1014 | void __iomem *pio = at91_gpio->regbase; | |
1015 | unsigned mask = 1 << offset; | |
1016 | ||
1017 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1018 | } | |
1019 | ||
1020 | static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
1021 | int val) | |
1022 | { | |
1023 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1024 | void __iomem *pio = at91_gpio->regbase; | |
1025 | unsigned mask = 1 << offset; | |
1026 | ||
1027 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1028 | writel_relaxed(mask, pio + PIO_OER); | |
1029 | ||
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
1034 | { | |
1035 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1036 | int virq; | |
1037 | ||
1038 | if (offset < chip->ngpio) | |
1039 | virq = irq_create_mapping(at91_gpio->domain, offset); | |
1040 | else | |
1041 | virq = -ENXIO; | |
1042 | ||
1043 | dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", | |
1044 | chip->label, offset + chip->base, virq); | |
1045 | return virq; | |
1046 | } | |
1047 | ||
1048 | #ifdef CONFIG_DEBUG_FS | |
1049 | static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1050 | { | |
1051 | enum at91_mux mode; | |
1052 | int i; | |
1053 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1054 | void __iomem *pio = at91_gpio->regbase; | |
1055 | ||
1056 | for (i = 0; i < chip->ngpio; i++) { | |
1057 | unsigned pin = chip->base + i; | |
1058 | unsigned mask = pin_to_mask(pin); | |
1059 | const char *gpio_label; | |
1060 | u32 pdsr; | |
1061 | ||
1062 | gpio_label = gpiochip_is_requested(chip, i); | |
1063 | if (!gpio_label) | |
1064 | continue; | |
1065 | mode = at91_gpio->ops->get_periph(pio, mask); | |
1066 | seq_printf(s, "[%s] GPIO%s%d: ", | |
1067 | gpio_label, chip->label, i); | |
1068 | if (mode == AT91_MUX_GPIO) { | |
1069 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1070 | ||
1071 | seq_printf(s, "[gpio] %s\n", | |
1072 | pdsr & mask ? | |
1073 | "set" : "clear"); | |
1074 | } else { | |
1075 | seq_printf(s, "[periph %c]\n", | |
1076 | mode + 'A' - 1); | |
1077 | } | |
1078 | } | |
1079 | } | |
1080 | #else | |
1081 | #define at91_gpio_dbg_show NULL | |
1082 | #endif | |
1083 | ||
1084 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
1085 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
1086 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
1087 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
1088 | * handler. | |
1089 | * First implementation always triggers on rising and falling edges | |
1090 | * whereas the newer PIO3 can be additionally configured to trigger on | |
1091 | * level, edge with any polarity. | |
1092 | * | |
1093 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
1094 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
1095 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
1096 | */ | |
1097 | ||
1098 | static void gpio_irq_mask(struct irq_data *d) | |
1099 | { | |
1100 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1101 | void __iomem *pio = at91_gpio->regbase; | |
1102 | unsigned mask = 1 << d->hwirq; | |
1103 | ||
1104 | if (pio) | |
1105 | writel_relaxed(mask, pio + PIO_IDR); | |
1106 | } | |
1107 | ||
1108 | static void gpio_irq_unmask(struct irq_data *d) | |
1109 | { | |
1110 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1111 | void __iomem *pio = at91_gpio->regbase; | |
1112 | unsigned mask = 1 << d->hwirq; | |
1113 | ||
1114 | if (pio) | |
1115 | writel_relaxed(mask, pio + PIO_IER); | |
1116 | } | |
1117 | ||
1118 | static int gpio_irq_type(struct irq_data *d, unsigned type) | |
1119 | { | |
1120 | switch (type) { | |
1121 | case IRQ_TYPE_NONE: | |
1122 | case IRQ_TYPE_EDGE_BOTH: | |
1123 | return 0; | |
1124 | default: | |
1125 | return -EINVAL; | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | /* Alternate irq type for PIO3 support */ | |
1130 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type) | |
1131 | { | |
1132 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1133 | void __iomem *pio = at91_gpio->regbase; | |
1134 | unsigned mask = 1 << d->hwirq; | |
1135 | ||
1136 | switch (type) { | |
1137 | case IRQ_TYPE_EDGE_RISING: | |
1138 | writel_relaxed(mask, pio + PIO_ESR); | |
1139 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1140 | break; | |
1141 | case IRQ_TYPE_EDGE_FALLING: | |
1142 | writel_relaxed(mask, pio + PIO_ESR); | |
1143 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1144 | break; | |
1145 | case IRQ_TYPE_LEVEL_LOW: | |
1146 | writel_relaxed(mask, pio + PIO_LSR); | |
1147 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1148 | break; | |
1149 | case IRQ_TYPE_LEVEL_HIGH: | |
1150 | writel_relaxed(mask, pio + PIO_LSR); | |
1151 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1152 | break; | |
1153 | case IRQ_TYPE_EDGE_BOTH: | |
1154 | /* | |
1155 | * disable additional interrupt modes: | |
1156 | * fall back to default behavior | |
1157 | */ | |
1158 | writel_relaxed(mask, pio + PIO_AIMDR); | |
1159 | return 0; | |
1160 | case IRQ_TYPE_NONE: | |
1161 | default: | |
1162 | pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); | |
1163 | return -EINVAL; | |
1164 | } | |
1165 | ||
1166 | /* enable additional interrupt modes */ | |
1167 | writel_relaxed(mask, pio + PIO_AIMER); | |
1168 | ||
1169 | return 0; | |
1170 | } | |
1171 | ||
1172 | #ifdef CONFIG_PM | |
1173 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) | |
1174 | { | |
1175 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1176 | unsigned bank = at91_gpio->pioc_idx; | |
1177 | ||
1178 | if (unlikely(bank >= MAX_GPIO_BANKS)) | |
1179 | return -EINVAL; | |
1180 | ||
1181 | irq_set_irq_wake(at91_gpio->pioc_virq, state); | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | #else | |
1186 | #define gpio_irq_set_wake NULL | |
1187 | #endif | |
1188 | ||
1189 | static struct irq_chip gpio_irqchip = { | |
1190 | .name = "GPIO", | |
1191 | .irq_disable = gpio_irq_mask, | |
1192 | .irq_mask = gpio_irq_mask, | |
1193 | .irq_unmask = gpio_irq_unmask, | |
1194 | /* .irq_set_type is set dynamically */ | |
1195 | .irq_set_wake = gpio_irq_set_wake, | |
1196 | }; | |
1197 | ||
1198 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
1199 | { | |
1200 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1201 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
1202 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); | |
1203 | void __iomem *pio = at91_gpio->regbase; | |
1204 | unsigned long isr; | |
1205 | int n; | |
1206 | ||
1207 | chained_irq_enter(chip, desc); | |
1208 | for (;;) { | |
1209 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. | |
1210 | * When there none are pending, we're finished unless we need | |
1211 | * to process multiple banks (like ID_PIOCDE on sam9263). | |
1212 | */ | |
1213 | isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); | |
1214 | if (!isr) { | |
1215 | if (!at91_gpio->next) | |
1216 | break; | |
1217 | at91_gpio = at91_gpio->next; | |
1218 | pio = at91_gpio->regbase; | |
1219 | continue; | |
1220 | } | |
1221 | ||
05daa16a | 1222 | for_each_set_bit(n, &isr, BITS_PER_LONG) { |
6732ae5c | 1223 | generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); |
6732ae5c JCPV |
1224 | } |
1225 | } | |
1226 | chained_irq_exit(chip, desc); | |
1227 | /* now it may re-trigger */ | |
1228 | } | |
1229 | ||
1230 | /* | |
1231 | * This lock class tells lockdep that GPIO irqs are in a different | |
1232 | * category than their parents, so it won't report false recursion. | |
1233 | */ | |
1234 | static struct lock_class_key gpio_lock_class; | |
1235 | ||
1236 | static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq, | |
1237 | irq_hw_number_t hw) | |
1238 | { | |
1239 | struct at91_gpio_chip *at91_gpio = h->host_data; | |
1240 | ||
1241 | irq_set_lockdep_class(virq, &gpio_lock_class); | |
1242 | ||
1243 | /* | |
1244 | * Can use the "simple" and not "edge" handler since it's | |
1245 | * shorter, and the AIC handles interrupts sanely. | |
1246 | */ | |
1247 | irq_set_chip_and_handler(virq, &gpio_irqchip, | |
1248 | handle_simple_irq); | |
1249 | set_irq_flags(virq, IRQF_VALID); | |
1250 | irq_set_chip_data(virq, at91_gpio); | |
1251 | ||
1252 | return 0; | |
1253 | } | |
1254 | ||
a728c7cd JCPV |
1255 | int at91_gpio_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
1256 | const u32 *intspec, unsigned int intsize, | |
1257 | irq_hw_number_t *out_hwirq, unsigned int *out_type) | |
1258 | { | |
1259 | struct at91_gpio_chip *at91_gpio = d->host_data; | |
1260 | int ret; | |
1261 | int pin = at91_gpio->chip.base + intspec[0]; | |
1262 | ||
1263 | if (WARN_ON(intsize < 2)) | |
1264 | return -EINVAL; | |
1265 | *out_hwirq = intspec[0]; | |
1266 | *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; | |
1267 | ||
1268 | ret = gpio_request(pin, ctrlr->full_name); | |
1269 | if (ret) | |
1270 | return ret; | |
1271 | ||
1272 | ret = gpio_direction_input(pin); | |
1273 | if (ret) | |
1274 | return ret; | |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
6732ae5c JCPV |
1279 | static struct irq_domain_ops at91_gpio_ops = { |
1280 | .map = at91_gpio_irq_map, | |
a728c7cd | 1281 | .xlate = at91_gpio_irq_domain_xlate, |
6732ae5c JCPV |
1282 | }; |
1283 | ||
1284 | static int at91_gpio_of_irq_setup(struct device_node *node, | |
1285 | struct at91_gpio_chip *at91_gpio) | |
1286 | { | |
1287 | struct at91_gpio_chip *prev = NULL; | |
1288 | struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); | |
1289 | ||
1290 | at91_gpio->pioc_hwirq = irqd_to_hwirq(d); | |
1291 | ||
1292 | /* Setup proper .irq_set_type function */ | |
1293 | gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; | |
1294 | ||
1295 | /* Disable irqs of this PIO controller */ | |
1296 | writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); | |
1297 | ||
1298 | /* Setup irq domain */ | |
1299 | at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, | |
1300 | &at91_gpio_ops, at91_gpio); | |
1301 | if (!at91_gpio->domain) | |
1302 | panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", | |
1303 | at91_gpio->pioc_idx); | |
1304 | ||
1305 | /* Setup chained handler */ | |
1306 | if (at91_gpio->pioc_idx) | |
1307 | prev = gpio_chips[at91_gpio->pioc_idx - 1]; | |
1308 | ||
1309 | /* The toplevel handler handles one bank of GPIOs, except | |
1310 | * on some SoC it can handles up to three... | |
1311 | * We only set up the handler for the first of the list. | |
1312 | */ | |
1313 | if (prev && prev->next == at91_gpio) | |
1314 | return 0; | |
1315 | ||
1316 | irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); | |
1317 | irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); | |
1318 | ||
1319 | return 0; | |
1320 | } | |
1321 | ||
1322 | /* This structure is replicated for each GPIO block allocated at probe time */ | |
1323 | static struct gpio_chip at91_gpio_template = { | |
1324 | .request = at91_gpio_request, | |
1325 | .free = at91_gpio_free, | |
1326 | .direction_input = at91_gpio_direction_input, | |
1327 | .get = at91_gpio_get, | |
1328 | .direction_output = at91_gpio_direction_output, | |
1329 | .set = at91_gpio_set, | |
1330 | .to_irq = at91_gpio_to_irq, | |
1331 | .dbg_show = at91_gpio_dbg_show, | |
1332 | .can_sleep = 0, | |
1333 | .ngpio = MAX_NB_GPIO_PER_BANK, | |
1334 | }; | |
1335 | ||
1336 | static void __devinit at91_gpio_probe_fixup(void) | |
1337 | { | |
1338 | unsigned i; | |
1339 | struct at91_gpio_chip *at91_gpio, *last = NULL; | |
1340 | ||
1341 | for (i = 0; i < gpio_banks; i++) { | |
1342 | at91_gpio = gpio_chips[i]; | |
1343 | ||
1344 | /* | |
1345 | * GPIO controller are grouped on some SoC: | |
1346 | * PIOC, PIOD and PIOE can share the same IRQ line | |
1347 | */ | |
1348 | if (last && last->pioc_virq == at91_gpio->pioc_virq) | |
1349 | last->next = at91_gpio; | |
1350 | last = at91_gpio; | |
1351 | } | |
1352 | } | |
1353 | ||
1354 | static struct of_device_id at91_gpio_of_match[] __devinitdata = { | |
1355 | { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, | |
1356 | { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, | |
1357 | { /* sentinel */ } | |
1358 | }; | |
1359 | ||
1360 | static int __devinit at91_gpio_probe(struct platform_device *pdev) | |
1361 | { | |
1362 | struct device_node *np = pdev->dev.of_node; | |
1363 | struct resource *res; | |
1364 | struct at91_gpio_chip *at91_chip = NULL; | |
1365 | struct gpio_chip *chip; | |
1366 | struct pinctrl_gpio_range *range; | |
1367 | int ret = 0; | |
1368 | int irq; | |
1369 | int alias_idx = of_alias_get_id(np, "gpio"); | |
1370 | uint32_t ngpio; | |
1371 | ||
1372 | BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); | |
1373 | if (gpio_chips[alias_idx]) { | |
1374 | ret = -EBUSY; | |
1375 | goto err; | |
1376 | } | |
1377 | ||
1378 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1379 | if (!res) { | |
1380 | ret = -ENOENT; | |
1381 | goto err; | |
1382 | } | |
1383 | ||
1384 | irq = platform_get_irq(pdev, 0); | |
1385 | if (irq < 0) { | |
1386 | ret = irq; | |
1387 | goto err; | |
1388 | } | |
1389 | ||
1390 | at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); | |
1391 | if (!at91_chip) { | |
1392 | ret = -ENOMEM; | |
1393 | goto err; | |
1394 | } | |
1395 | ||
1396 | at91_chip->regbase = devm_request_and_ioremap(&pdev->dev, res); | |
1397 | if (!at91_chip->regbase) { | |
1398 | dev_err(&pdev->dev, "failed to map registers, ignoring.\n"); | |
1399 | ret = -EBUSY; | |
1400 | goto err; | |
1401 | } | |
1402 | ||
dffa9123 | 1403 | at91_chip->ops = (struct at91_pinctrl_mux_ops*) |
6732ae5c JCPV |
1404 | of_match_device(at91_gpio_of_match, &pdev->dev)->data; |
1405 | at91_chip->pioc_virq = irq; | |
1406 | at91_chip->pioc_idx = alias_idx; | |
1407 | ||
1408 | at91_chip->clock = clk_get(&pdev->dev, NULL); | |
1409 | if (IS_ERR(at91_chip->clock)) { | |
1410 | dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); | |
1411 | goto err; | |
1412 | } | |
1413 | ||
1414 | if (clk_prepare(at91_chip->clock)) | |
1415 | goto clk_prep_err; | |
1416 | ||
1417 | /* enable PIO controller's clock */ | |
1418 | if (clk_enable(at91_chip->clock)) { | |
1419 | dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); | |
1420 | goto clk_err; | |
1421 | } | |
1422 | ||
1423 | at91_chip->chip = at91_gpio_template; | |
1424 | ||
1425 | chip = &at91_chip->chip; | |
1426 | chip->of_node = np; | |
1427 | chip->label = dev_name(&pdev->dev); | |
1428 | chip->dev = &pdev->dev; | |
1429 | chip->owner = THIS_MODULE; | |
1430 | chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; | |
1431 | ||
1432 | if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { | |
1433 | if (ngpio >= MAX_NB_GPIO_PER_BANK) | |
1434 | pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", | |
1435 | alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); | |
1436 | else | |
1437 | chip->ngpio = ngpio; | |
1438 | } | |
1439 | ||
1440 | range = &at91_chip->range; | |
1441 | range->name = chip->label; | |
1442 | range->id = alias_idx; | |
1443 | range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; | |
1444 | ||
1445 | range->npins = chip->ngpio; | |
1446 | range->gc = chip; | |
1447 | ||
1448 | ret = gpiochip_add(chip); | |
1449 | if (ret) | |
1450 | goto clk_err; | |
1451 | ||
1452 | gpio_chips[alias_idx] = at91_chip; | |
1453 | gpio_banks = max(gpio_banks, alias_idx + 1); | |
1454 | ||
1455 | at91_gpio_probe_fixup(); | |
1456 | ||
1457 | at91_gpio_of_irq_setup(np, at91_chip); | |
1458 | ||
1459 | dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); | |
1460 | ||
1461 | return 0; | |
1462 | ||
1463 | clk_err: | |
1464 | clk_unprepare(at91_chip->clock); | |
1465 | clk_prep_err: | |
1466 | clk_put(at91_chip->clock); | |
1467 | err: | |
1468 | dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); | |
1469 | ||
1470 | return ret; | |
1471 | } | |
1472 | ||
1473 | static struct platform_driver at91_gpio_driver = { | |
1474 | .driver = { | |
1475 | .name = "gpio-at91", | |
1476 | .owner = THIS_MODULE, | |
1477 | .of_match_table = of_match_ptr(at91_gpio_of_match), | |
1478 | }, | |
1479 | .probe = at91_gpio_probe, | |
1480 | }; | |
1481 | ||
1482 | static struct platform_driver at91_pinctrl_driver = { | |
1483 | .driver = { | |
1484 | .name = "pinctrl-at91", | |
1485 | .owner = THIS_MODULE, | |
1486 | .of_match_table = of_match_ptr(at91_pinctrl_of_match), | |
1487 | }, | |
1488 | .probe = at91_pinctrl_probe, | |
1489 | .remove = __devexit_p(at91_pinctrl_remove), | |
1490 | }; | |
1491 | ||
1492 | static int __init at91_pinctrl_init(void) | |
1493 | { | |
1494 | int ret; | |
1495 | ||
1496 | ret = platform_driver_register(&at91_gpio_driver); | |
1497 | if (ret) | |
1498 | return ret; | |
1499 | return platform_driver_register(&at91_pinctrl_driver); | |
1500 | } | |
1501 | arch_initcall(at91_pinctrl_init); | |
1502 | ||
1503 | static void __exit at91_pinctrl_exit(void) | |
1504 | { | |
1505 | platform_driver_unregister(&at91_pinctrl_driver); | |
1506 | } | |
1507 | ||
1508 | module_exit(at91_pinctrl_exit); | |
1509 | MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); | |
1510 | MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); | |
1511 | MODULE_LICENSE("GPL v2"); |