Commit | Line | Data |
---|---|---|
9c92ab61 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
77618084 LD |
2 | /* |
3 | * Driver for the Atmel PIO4 controller | |
4 | * | |
5 | * Copyright (C) 2015 Atmel, | |
6 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
77618084 LD |
7 | */ |
8 | ||
ff10e353 | 9 | #include <dt-bindings/pinctrl/at91.h> |
77618084 | 10 | #include <linux/clk.h> |
80036f88 | 11 | #include <linux/gpio/driver.h> |
de4e882f | 12 | #include <linux/interrupt.h> |
77618084 | 13 | #include <linux/io.h> |
f703851a | 14 | #include <linux/init.h> |
77618084 LD |
15 | #include <linux/of.h> |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/pinctrl/pinconf.h> | |
18 | #include <linux/pinctrl/pinconf-generic.h> | |
19 | #include <linux/pinctrl/pinctrl.h> | |
20 | #include <linux/pinctrl/pinmux.h> | |
21 | #include <linux/slab.h> | |
22 | #include "core.h" | |
23 | #include "pinconf.h" | |
24 | #include "pinctrl-utils.h" | |
25 | ||
26 | /* | |
27 | * Warning: | |
28 | * In order to not introduce confusion between Atmel PIO groups and pinctrl | |
29 | * framework groups, Atmel PIO groups will be called banks, line is kept to | |
30 | * designed the pin id into this bank. | |
31 | */ | |
32 | ||
33 | #define ATMEL_PIO_MSKR 0x0000 | |
34 | #define ATMEL_PIO_CFGR 0x0004 | |
35 | #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) | |
36 | #define ATMEL_PIO_DIR_MASK BIT(8) | |
37 | #define ATMEL_PIO_PUEN_MASK BIT(9) | |
38 | #define ATMEL_PIO_PDEN_MASK BIT(10) | |
c709135e | 39 | #define ATMEL_PIO_SR_MASK BIT(11) |
77618084 LD |
40 | #define ATMEL_PIO_IFEN_MASK BIT(12) |
41 | #define ATMEL_PIO_IFSCEN_MASK BIT(13) | |
42 | #define ATMEL_PIO_OPD_MASK BIT(14) | |
43 | #define ATMEL_PIO_SCHMITT_MASK BIT(15) | |
ff10e353 LD |
44 | #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16) |
45 | #define ATMEL_PIO_DRVSTR_OFFSET 16 | |
77618084 LD |
46 | #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) |
47 | #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) | |
48 | #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) | |
49 | #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) | |
50 | #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) | |
51 | #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) | |
52 | #define ATMEL_PIO_PDSR 0x0008 | |
53 | #define ATMEL_PIO_LOCKSR 0x000C | |
54 | #define ATMEL_PIO_SODR 0x0010 | |
55 | #define ATMEL_PIO_CODR 0x0014 | |
56 | #define ATMEL_PIO_ODSR 0x0018 | |
57 | #define ATMEL_PIO_IER 0x0020 | |
58 | #define ATMEL_PIO_IDR 0x0024 | |
59 | #define ATMEL_PIO_IMR 0x0028 | |
60 | #define ATMEL_PIO_ISR 0x002C | |
61 | #define ATMEL_PIO_IOFR 0x003C | |
62 | ||
63 | #define ATMEL_PIO_NPINS_PER_BANK 32 | |
64 | #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) | |
65 | #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) | |
66 | #define ATMEL_PIO_BANK_OFFSET 0x40 | |
67 | ||
68 | #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) | |
69 | #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) | |
70 | #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) | |
71 | ||
ff10e353 LD |
72 | /* Custom pinconf parameters */ |
73 | #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1) | |
74 | ||
b6071c89 EH |
75 | /** |
76 | * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct | |
77 | * @nbanks: number of PIO banks | |
78 | * @last_bank_count: number of lines in the last bank (can be less than | |
79 | * the rest of the banks). | |
c709135e | 80 | * @slew_rate_support: slew rate support |
b6071c89 | 81 | */ |
77618084 | 82 | struct atmel_pioctrl_data { |
b4435b42 CB |
83 | unsigned int nbanks; |
84 | unsigned int last_bank_count; | |
c709135e | 85 | unsigned int slew_rate_support; |
77618084 LD |
86 | }; |
87 | ||
88 | struct atmel_group { | |
89 | const char *name; | |
90 | u32 pin; | |
91 | }; | |
92 | ||
93 | struct atmel_pin { | |
b4435b42 CB |
94 | unsigned int pin_id; |
95 | unsigned int mux; | |
96 | unsigned int ioset; | |
97 | unsigned int bank; | |
98 | unsigned int line; | |
77618084 LD |
99 | const char *device; |
100 | }; | |
101 | ||
102 | /** | |
103 | * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio) | |
104 | * @reg_base: base address of the controller. | |
105 | * @clk: clock of the controller. | |
106 | * @nbanks: number of PIO groups, it can vary depending on the SoC. | |
107 | * @pinctrl_dev: pinctrl device registered. | |
108 | * @groups: groups table to provide group name and pin in the group to pinctrl. | |
109 | * @group_names: group names table to provide all the group/pin names to | |
110 | * pinctrl or gpio. | |
111 | * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line | |
112 | * fields are set at probe time. Other ones are set when parsing dt | |
113 | * pinctrl. | |
114 | * @npins: number of pins. | |
115 | * @gpio_chip: gpio chip registered. | |
116 | * @irq_domain: irq domain for the gpio controller. | |
117 | * @irqs: table containing the hw irq number of the bank. The index of the | |
118 | * table is the bank id. | |
898503ee LJ |
119 | * @pm_wakeup_sources: bitmap of wakeup sources (lines) |
120 | * @pm_suspend_backup: backup/restore register values on suspend/resume | |
77618084 LD |
121 | * @dev: device entry for the Atmel PIO controller. |
122 | * @node: node of the Atmel PIO controller. | |
c709135e | 123 | * @slew_rate_support: slew rate support |
77618084 LD |
124 | */ |
125 | struct atmel_pioctrl { | |
126 | void __iomem *reg_base; | |
127 | struct clk *clk; | |
b4435b42 | 128 | unsigned int nbanks; |
77618084 LD |
129 | struct pinctrl_dev *pinctrl_dev; |
130 | struct atmel_group *groups; | |
131 | const char * const *group_names; | |
132 | struct atmel_pin **pins; | |
b4435b42 | 133 | unsigned int npins; |
77618084 LD |
134 | struct gpio_chip *gpio_chip; |
135 | struct irq_domain *irq_domain; | |
136 | int *irqs; | |
b4435b42 | 137 | unsigned int *pm_wakeup_sources; |
ba9e7f27 AB |
138 | struct { |
139 | u32 imr; | |
140 | u32 odsr; | |
141 | u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; | |
142 | } *pm_suspend_backup; | |
77618084 LD |
143 | struct device *dev; |
144 | struct device_node *node; | |
c709135e | 145 | unsigned int slew_rate_support; |
77618084 LD |
146 | }; |
147 | ||
148 | static const char * const atmel_functions[] = { | |
149 | "GPIO", "A", "B", "C", "D", "E", "F", "G" | |
150 | }; | |
151 | ||
ff10e353 LD |
152 | static const struct pinconf_generic_params atmel_custom_bindings[] = { |
153 | {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0}, | |
154 | }; | |
155 | ||
77618084 LD |
156 | /* --- GPIO --- */ |
157 | static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl, | |
158 | unsigned int bank, unsigned int reg) | |
159 | { | |
160 | return readl_relaxed(atmel_pioctrl->reg_base | |
161 | + ATMEL_PIO_BANK_OFFSET * bank + reg); | |
162 | } | |
163 | ||
164 | static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl, | |
165 | unsigned int bank, unsigned int reg, | |
166 | unsigned int val) | |
167 | { | |
168 | writel_relaxed(val, atmel_pioctrl->reg_base | |
169 | + ATMEL_PIO_BANK_OFFSET * bank + reg); | |
170 | } | |
171 | ||
172 | static void atmel_gpio_irq_ack(struct irq_data *d) | |
173 | { | |
174 | /* | |
175 | * Nothing to do, interrupt is cleared when reading the status | |
176 | * register. | |
177 | */ | |
178 | } | |
179 | ||
b4435b42 | 180 | static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
77618084 LD |
181 | { |
182 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
183 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
b4435b42 | 184 | unsigned int reg; |
77618084 LD |
185 | |
186 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
187 | BIT(pin->line)); | |
188 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
189 | reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); | |
190 | ||
191 | switch (type) { | |
192 | case IRQ_TYPE_EDGE_RISING: | |
3fd550c6 | 193 | irq_set_handler_locked(d, handle_edge_irq); |
77618084 LD |
194 | reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; |
195 | break; | |
196 | case IRQ_TYPE_EDGE_FALLING: | |
3fd550c6 | 197 | irq_set_handler_locked(d, handle_edge_irq); |
77618084 LD |
198 | reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; |
199 | break; | |
200 | case IRQ_TYPE_EDGE_BOTH: | |
3fd550c6 | 201 | irq_set_handler_locked(d, handle_edge_irq); |
77618084 LD |
202 | reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; |
203 | break; | |
204 | case IRQ_TYPE_LEVEL_LOW: | |
3fd550c6 | 205 | irq_set_handler_locked(d, handle_level_irq); |
77618084 LD |
206 | reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; |
207 | break; | |
208 | case IRQ_TYPE_LEVEL_HIGH: | |
3fd550c6 | 209 | irq_set_handler_locked(d, handle_level_irq); |
77618084 LD |
210 | reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; |
211 | break; | |
212 | case IRQ_TYPE_NONE: | |
213 | default: | |
214 | return -EINVAL; | |
215 | } | |
216 | ||
217 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
222 | static void atmel_gpio_irq_mask(struct irq_data *d) | |
223 | { | |
224 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
225 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
226 | ||
227 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, | |
228 | BIT(pin->line)); | |
229 | } | |
230 | ||
231 | static void atmel_gpio_irq_unmask(struct irq_data *d) | |
232 | { | |
233 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
234 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
235 | ||
236 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, | |
237 | BIT(pin->line)); | |
238 | } | |
239 | ||
de4e882f LD |
240 | static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
241 | { | |
242 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
243 | int bank = ATMEL_PIO_BANK(d->hwirq); | |
244 | int line = ATMEL_PIO_LINE(d->hwirq); | |
245 | ||
246 | /* The gpio controller has one interrupt line per bank. */ | |
247 | irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); | |
248 | ||
249 | if (on) | |
250 | atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); | |
251 | else | |
252 | atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); | |
253 | ||
254 | return 0; | |
255 | } | |
de4e882f | 256 | |
77618084 LD |
257 | static struct irq_chip atmel_gpio_irq_chip = { |
258 | .name = "GPIO", | |
259 | .irq_ack = atmel_gpio_irq_ack, | |
260 | .irq_mask = atmel_gpio_irq_mask, | |
261 | .irq_unmask = atmel_gpio_irq_unmask, | |
262 | .irq_set_type = atmel_gpio_irq_set_type, | |
cc701e18 | 263 | .irq_set_wake = pm_sleep_ptr(atmel_gpio_irq_set_wake), |
77618084 LD |
264 | }; |
265 | ||
b4435b42 | 266 | static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) |
e897b386 LW |
267 | { |
268 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); | |
269 | ||
270 | return irq_find_mapping(atmel_pioctrl->irq_domain, offset); | |
271 | } | |
272 | ||
89092fb0 | 273 | static void atmel_gpio_irq_handler(struct irq_desc *desc) |
77618084 | 274 | { |
89092fb0 LD |
275 | unsigned int irq = irq_desc_get_irq(desc); |
276 | struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc); | |
77618084 LD |
277 | struct irq_chip *chip = irq_desc_get_chip(desc); |
278 | unsigned long isr; | |
279 | int n, bank = -1; | |
280 | ||
281 | /* Find from which bank is the irq received. */ | |
282 | for (n = 0; n < atmel_pioctrl->nbanks; n++) { | |
283 | if (atmel_pioctrl->irqs[n] == irq) { | |
284 | bank = n; | |
285 | break; | |
286 | } | |
287 | } | |
288 | ||
289 | if (bank < 0) { | |
290 | dev_err(atmel_pioctrl->dev, | |
291 | "no bank associated to irq %u\n", irq); | |
292 | return; | |
293 | } | |
294 | ||
295 | chained_irq_enter(chip, desc); | |
296 | ||
297 | for (;;) { | |
298 | isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, | |
299 | ATMEL_PIO_ISR); | |
300 | isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, | |
301 | ATMEL_PIO_IMR); | |
302 | if (!isr) | |
303 | break; | |
304 | ||
305 | for_each_set_bit(n, &isr, BITS_PER_LONG) | |
e897b386 LW |
306 | generic_handle_irq(atmel_gpio_to_irq( |
307 | atmel_pioctrl->gpio_chip, | |
308 | bank * ATMEL_PIO_NPINS_PER_BANK + n)); | |
77618084 LD |
309 | } |
310 | ||
311 | chained_irq_exit(chip, desc); | |
312 | } | |
313 | ||
b4435b42 CB |
314 | static int atmel_gpio_direction_input(struct gpio_chip *chip, |
315 | unsigned int offset) | |
77618084 | 316 | { |
80036f88 | 317 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 | 318 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
b4435b42 | 319 | unsigned int reg; |
77618084 LD |
320 | |
321 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
322 | BIT(pin->line)); | |
323 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
324 | reg &= ~ATMEL_PIO_DIR_MASK; | |
325 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
b4435b42 | 330 | static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset) |
77618084 | 331 | { |
80036f88 | 332 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 | 333 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
b4435b42 | 334 | unsigned int reg; |
77618084 LD |
335 | |
336 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); | |
337 | ||
338 | return !!(reg & BIT(pin->line)); | |
339 | } | |
340 | ||
09107a51 AB |
341 | static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
342 | unsigned long *bits) | |
343 | { | |
344 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); | |
345 | unsigned int bank; | |
346 | ||
347 | bitmap_zero(bits, atmel_pioctrl->npins); | |
348 | ||
349 | for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { | |
350 | unsigned int word = bank; | |
351 | unsigned int offset = 0; | |
352 | unsigned int reg; | |
353 | ||
354 | #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG | |
355 | word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); | |
356 | offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG; | |
357 | #endif | |
358 | if (!mask[word]) | |
359 | continue; | |
360 | ||
361 | reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR); | |
362 | bits[word] |= mask[word] & (reg << offset); | |
363 | } | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
b4435b42 CB |
368 | static int atmel_gpio_direction_output(struct gpio_chip *chip, |
369 | unsigned int offset, | |
77618084 LD |
370 | int value) |
371 | { | |
80036f88 | 372 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 | 373 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
b4435b42 | 374 | unsigned int reg; |
77618084 LD |
375 | |
376 | atmel_gpio_write(atmel_pioctrl, pin->bank, | |
377 | value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, | |
378 | BIT(pin->line)); | |
379 | ||
380 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
381 | BIT(pin->line)); | |
382 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
383 | reg |= ATMEL_PIO_DIR_MASK; | |
384 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
b4435b42 | 389 | static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) |
77618084 | 390 | { |
80036f88 | 391 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
392 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
393 | ||
394 | atmel_gpio_write(atmel_pioctrl, pin->bank, | |
395 | val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, | |
396 | BIT(pin->line)); | |
397 | } | |
398 | ||
09107a51 AB |
399 | static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
400 | unsigned long *bits) | |
401 | { | |
402 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); | |
403 | unsigned int bank; | |
404 | ||
405 | for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { | |
406 | unsigned int bitmask; | |
407 | unsigned int word = bank; | |
408 | ||
409 | /* | |
410 | * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over | |
411 | * two 32bit words to handle the whole bitmask | |
412 | */ | |
413 | #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG | |
414 | word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); | |
415 | #endif | |
416 | if (!mask[word]) | |
417 | continue; | |
418 | ||
419 | bitmask = mask[word] & bits[word]; | |
420 | atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask); | |
421 | ||
422 | bitmask = mask[word] & ~bits[word]; | |
423 | atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask); | |
424 | ||
425 | #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG | |
426 | mask[word] >>= ATMEL_PIO_NPINS_PER_BANK; | |
427 | bits[word] >>= ATMEL_PIO_NPINS_PER_BANK; | |
428 | #endif | |
429 | } | |
430 | } | |
431 | ||
77618084 LD |
432 | static struct gpio_chip atmel_gpio_chip = { |
433 | .direction_input = atmel_gpio_direction_input, | |
434 | .get = atmel_gpio_get, | |
09107a51 | 435 | .get_multiple = atmel_gpio_get_multiple, |
77618084 LD |
436 | .direction_output = atmel_gpio_direction_output, |
437 | .set = atmel_gpio_set, | |
09107a51 | 438 | .set_multiple = atmel_gpio_set_multiple, |
77618084 LD |
439 | .to_irq = atmel_gpio_to_irq, |
440 | .base = 0, | |
441 | }; | |
442 | ||
443 | /* --- PINCTRL --- */ | |
444 | static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, | |
b4435b42 | 445 | unsigned int pin_id) |
77618084 LD |
446 | { |
447 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
b4435b42 CB |
448 | unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; |
449 | unsigned int line = atmel_pioctrl->pins[pin_id]->line; | |
77618084 LD |
450 | void __iomem *addr = atmel_pioctrl->reg_base |
451 | + bank * ATMEL_PIO_BANK_OFFSET; | |
452 | ||
453 | writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); | |
454 | /* Have to set MSKR first, to access the right pin CFGR. */ | |
455 | wmb(); | |
456 | ||
457 | return readl_relaxed(addr + ATMEL_PIO_CFGR); | |
458 | } | |
459 | ||
460 | static void atmel_pin_config_write(struct pinctrl_dev *pctldev, | |
b4435b42 | 461 | unsigned int pin_id, u32 conf) |
77618084 LD |
462 | { |
463 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
b4435b42 CB |
464 | unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; |
465 | unsigned int line = atmel_pioctrl->pins[pin_id]->line; | |
77618084 LD |
466 | void __iomem *addr = atmel_pioctrl->reg_base |
467 | + bank * ATMEL_PIO_BANK_OFFSET; | |
468 | ||
469 | writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); | |
470 | /* Have to set MSKR first, to access the right pin CFGR. */ | |
471 | wmb(); | |
472 | writel_relaxed(conf, addr + ATMEL_PIO_CFGR); | |
473 | } | |
474 | ||
475 | static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) | |
476 | { | |
477 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
478 | ||
479 | return atmel_pioctrl->npins; | |
480 | } | |
481 | ||
482 | static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, | |
b4435b42 | 483 | unsigned int selector) |
77618084 LD |
484 | { |
485 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
486 | ||
487 | return atmel_pioctrl->groups[selector].name; | |
488 | } | |
489 | ||
490 | static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, | |
b4435b42 CB |
491 | unsigned int selector, |
492 | const unsigned int **pins, | |
493 | unsigned int *num_pins) | |
77618084 LD |
494 | { |
495 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
496 | ||
b4435b42 | 497 | *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin; |
77618084 LD |
498 | *num_pins = 1; |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
682d68b8 | 503 | static struct atmel_group * |
b4435b42 | 504 | atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin) |
77618084 LD |
505 | { |
506 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
507 | int i; | |
508 | ||
509 | for (i = 0; i < atmel_pioctrl->npins; i++) { | |
510 | struct atmel_group *grp = atmel_pioctrl->groups + i; | |
511 | ||
512 | if (grp->pin == pin) | |
513 | return grp; | |
514 | } | |
515 | ||
516 | return NULL; | |
517 | } | |
518 | ||
519 | static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, | |
520 | struct device_node *np, | |
521 | u32 pinfunc, const char **grp_name, | |
522 | const char **func_name) | |
523 | { | |
524 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
b4435b42 | 525 | unsigned int pin_id, func_id; |
77618084 LD |
526 | struct atmel_group *grp; |
527 | ||
528 | pin_id = ATMEL_GET_PIN_NO(pinfunc); | |
529 | func_id = ATMEL_GET_PIN_FUNC(pinfunc); | |
530 | ||
531 | if (func_id >= ARRAY_SIZE(atmel_functions)) | |
532 | return -EINVAL; | |
533 | ||
534 | *func_name = atmel_functions[func_id]; | |
535 | ||
536 | grp = atmel_pctl_find_group_by_pin(pctldev, pin_id); | |
537 | if (!grp) | |
538 | return -EINVAL; | |
539 | *grp_name = grp->name; | |
540 | ||
541 | atmel_pioctrl->pins[pin_id]->mux = func_id; | |
542 | atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); | |
543 | /* Want the device name not the group one. */ | |
544 | if (np->parent == atmel_pioctrl->node) | |
545 | atmel_pioctrl->pins[pin_id]->device = np->name; | |
546 | else | |
547 | atmel_pioctrl->pins[pin_id]->device = np->parent->name; | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
553 | struct device_node *np, | |
554 | struct pinctrl_map **map, | |
b4435b42 CB |
555 | unsigned int *reserved_maps, |
556 | unsigned int *num_maps) | |
77618084 | 557 | { |
b4435b42 | 558 | unsigned int num_pins, num_configs, reserve; |
77618084 LD |
559 | unsigned long *configs; |
560 | struct property *pins; | |
77618084 LD |
561 | u32 pinfunc; |
562 | int ret, i; | |
563 | ||
564 | pins = of_find_property(np, "pinmux", NULL); | |
565 | if (!pins) | |
566 | return -EINVAL; | |
567 | ||
568 | ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, | |
569 | &num_configs); | |
570 | if (ret < 0) { | |
f5292d06 RH |
571 | dev_err(pctldev->dev, "%pOF: could not parse node property\n", |
572 | np); | |
77618084 LD |
573 | return ret; |
574 | } | |
575 | ||
77618084 LD |
576 | num_pins = pins->length / sizeof(u32); |
577 | if (!num_pins) { | |
f5292d06 | 578 | dev_err(pctldev->dev, "no pins found in node %pOF\n", np); |
e43d2b75 LD |
579 | ret = -EINVAL; |
580 | goto exit; | |
77618084 LD |
581 | } |
582 | ||
583 | /* | |
584 | * Reserve maps, at least there is a mux map and an optional conf | |
585 | * map for each pin. | |
586 | */ | |
587 | reserve = 1; | |
b97760ae | 588 | if (num_configs) |
77618084 LD |
589 | reserve++; |
590 | reserve *= num_pins; | |
591 | ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, | |
592 | reserve); | |
593 | if (ret < 0) | |
e43d2b75 | 594 | goto exit; |
77618084 LD |
595 | |
596 | for (i = 0; i < num_pins; i++) { | |
597 | const char *group, *func; | |
598 | ||
599 | ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); | |
600 | if (ret) | |
e43d2b75 | 601 | goto exit; |
77618084 LD |
602 | |
603 | ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, | |
604 | &func); | |
605 | if (ret) | |
e43d2b75 | 606 | goto exit; |
77618084 LD |
607 | |
608 | pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, | |
609 | group, func); | |
610 | ||
b97760ae | 611 | if (num_configs) { |
77618084 LD |
612 | ret = pinctrl_utils_add_map_configs(pctldev, map, |
613 | reserved_maps, num_maps, group, | |
614 | configs, num_configs, | |
615 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
616 | if (ret < 0) | |
e43d2b75 | 617 | goto exit; |
77618084 LD |
618 | } |
619 | } | |
620 | ||
e43d2b75 LD |
621 | exit: |
622 | kfree(configs); | |
623 | return ret; | |
77618084 LD |
624 | } |
625 | ||
626 | static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
627 | struct device_node *np_config, | |
628 | struct pinctrl_map **map, | |
b4435b42 | 629 | unsigned int *num_maps) |
77618084 LD |
630 | { |
631 | struct device_node *np; | |
b4435b42 | 632 | unsigned int reserved_maps; |
77618084 LD |
633 | int ret; |
634 | ||
635 | *map = NULL; | |
636 | *num_maps = 0; | |
637 | reserved_maps = 0; | |
638 | ||
639 | /* | |
640 | * If all the pins of a device have the same configuration (or no one), | |
641 | * it is useless to add a subnode, so directly parse node referenced by | |
642 | * phandle. | |
643 | */ | |
644 | ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map, | |
645 | &reserved_maps, num_maps); | |
646 | if (ret) { | |
647 | for_each_child_of_node(np_config, np) { | |
648 | ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map, | |
649 | &reserved_maps, num_maps); | |
21816364 JL |
650 | if (ret < 0) { |
651 | of_node_put(np); | |
77618084 | 652 | break; |
21816364 | 653 | } |
77618084 LD |
654 | } |
655 | } | |
656 | ||
657 | if (ret < 0) { | |
d32f7fd3 | 658 | pinctrl_utils_free_map(pctldev, *map, *num_maps); |
f5292d06 RH |
659 | dev_err(pctldev->dev, "can't create maps for node %pOF\n", |
660 | np_config); | |
77618084 LD |
661 | } |
662 | ||
663 | return ret; | |
664 | } | |
665 | ||
666 | static const struct pinctrl_ops atmel_pctlops = { | |
667 | .get_groups_count = atmel_pctl_get_groups_count, | |
668 | .get_group_name = atmel_pctl_get_group_name, | |
669 | .get_group_pins = atmel_pctl_get_group_pins, | |
670 | .dt_node_to_map = atmel_pctl_dt_node_to_map, | |
d32f7fd3 | 671 | .dt_free_map = pinctrl_utils_free_map, |
77618084 LD |
672 | }; |
673 | ||
674 | static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) | |
675 | { | |
676 | return ARRAY_SIZE(atmel_functions); | |
677 | } | |
678 | ||
679 | static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, | |
b4435b42 | 680 | unsigned int selector) |
77618084 LD |
681 | { |
682 | return atmel_functions[selector]; | |
683 | } | |
684 | ||
685 | static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, | |
b4435b42 | 686 | unsigned int selector, |
77618084 LD |
687 | const char * const **groups, |
688 | unsigned * const num_groups) | |
689 | { | |
690 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
691 | ||
692 | *groups = atmel_pioctrl->group_names; | |
693 | *num_groups = atmel_pioctrl->npins; | |
694 | ||
695 | return 0; | |
696 | } | |
697 | ||
698 | static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, | |
b4435b42 CB |
699 | unsigned int function, |
700 | unsigned int group) | |
77618084 LD |
701 | { |
702 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
b4435b42 | 703 | unsigned int pin; |
77618084 LD |
704 | u32 conf; |
705 | ||
706 | dev_dbg(pctldev->dev, "enable function %s group %s\n", | |
707 | atmel_functions[function], atmel_pioctrl->groups[group].name); | |
708 | ||
709 | pin = atmel_pioctrl->groups[group].pin; | |
710 | conf = atmel_pin_config_read(pctldev, pin); | |
711 | conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); | |
712 | conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK); | |
713 | dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); | |
714 | atmel_pin_config_write(pctldev, pin, conf); | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
719 | static const struct pinmux_ops atmel_pmxops = { | |
720 | .get_functions_count = atmel_pmx_get_functions_count, | |
721 | .get_function_name = atmel_pmx_get_function_name, | |
722 | .get_function_groups = atmel_pmx_get_function_groups, | |
723 | .set_mux = atmel_pmx_set_mux, | |
724 | }; | |
725 | ||
726 | static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, | |
b4435b42 | 727 | unsigned int group, |
77618084 LD |
728 | unsigned long *config) |
729 | { | |
730 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
b4435b42 | 731 | unsigned int param = pinconf_to_config_param(*config), arg = 0; |
77618084 | 732 | struct atmel_group *grp = atmel_pioctrl->groups + group; |
b4435b42 | 733 | unsigned int pin_id = grp->pin; |
77618084 LD |
734 | u32 res; |
735 | ||
736 | res = atmel_pin_config_read(pctldev, pin_id); | |
737 | ||
738 | switch (param) { | |
739 | case PIN_CONFIG_BIAS_PULL_UP: | |
740 | if (!(res & ATMEL_PIO_PUEN_MASK)) | |
741 | return -EINVAL; | |
742 | arg = 1; | |
743 | break; | |
744 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
745 | if ((res & ATMEL_PIO_PUEN_MASK) || | |
746 | (!(res & ATMEL_PIO_PDEN_MASK))) | |
747 | return -EINVAL; | |
748 | arg = 1; | |
749 | break; | |
750 | case PIN_CONFIG_BIAS_DISABLE: | |
751 | if ((res & ATMEL_PIO_PUEN_MASK) || | |
752 | ((res & ATMEL_PIO_PDEN_MASK))) | |
753 | return -EINVAL; | |
754 | arg = 1; | |
755 | break; | |
756 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
757 | if (!(res & ATMEL_PIO_OPD_MASK)) | |
758 | return -EINVAL; | |
759 | arg = 1; | |
760 | break; | |
761 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
762 | if (!(res & ATMEL_PIO_SCHMITT_MASK)) | |
763 | return -EINVAL; | |
764 | arg = 1; | |
765 | break; | |
c709135e CB |
766 | case PIN_CONFIG_SLEW_RATE: |
767 | if (!atmel_pioctrl->slew_rate_support) | |
768 | return -EOPNOTSUPP; | |
769 | if (!(res & ATMEL_PIO_SR_MASK)) | |
770 | return -EINVAL; | |
771 | arg = 1; | |
772 | break; | |
ff10e353 LD |
773 | case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: |
774 | if (!(res & ATMEL_PIO_DRVSTR_MASK)) | |
775 | return -EINVAL; | |
776 | arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET; | |
777 | break; | |
eaa4c8f9 RW |
778 | case PIN_CONFIG_PERSIST_STATE: |
779 | return -ENOTSUPP; | |
77618084 LD |
780 | default: |
781 | return -ENOTSUPP; | |
782 | } | |
783 | ||
784 | *config = pinconf_to_config_packed(param, arg); | |
785 | return 0; | |
786 | } | |
787 | ||
788 | static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, | |
b4435b42 | 789 | unsigned int group, |
77618084 | 790 | unsigned long *configs, |
b4435b42 | 791 | unsigned int num_configs) |
77618084 LD |
792 | { |
793 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
794 | struct atmel_group *grp = atmel_pioctrl->groups + group; | |
b4435b42 | 795 | unsigned int bank, pin, pin_id = grp->pin; |
77618084 LD |
796 | u32 mask, conf = 0; |
797 | int i; | |
798 | ||
799 | conf = atmel_pin_config_read(pctldev, pin_id); | |
800 | ||
cbde6c82 TA |
801 | /* Keep slew rate enabled by default. */ |
802 | if (atmel_pioctrl->slew_rate_support) | |
803 | conf |= ATMEL_PIO_SR_MASK; | |
804 | ||
77618084 | 805 | for (i = 0; i < num_configs; i++) { |
b4435b42 CB |
806 | unsigned int param = pinconf_to_config_param(configs[i]); |
807 | unsigned int arg = pinconf_to_config_argument(configs[i]); | |
77618084 LD |
808 | |
809 | dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", | |
810 | __func__, pin_id, configs[i]); | |
811 | ||
812 | switch (param) { | |
813 | case PIN_CONFIG_BIAS_DISABLE: | |
814 | conf &= (~ATMEL_PIO_PUEN_MASK); | |
815 | conf &= (~ATMEL_PIO_PDEN_MASK); | |
816 | break; | |
817 | case PIN_CONFIG_BIAS_PULL_UP: | |
818 | conf |= ATMEL_PIO_PUEN_MASK; | |
5305a7b7 | 819 | conf &= (~ATMEL_PIO_PDEN_MASK); |
77618084 LD |
820 | break; |
821 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
822 | conf |= ATMEL_PIO_PDEN_MASK; | |
5305a7b7 | 823 | conf &= (~ATMEL_PIO_PUEN_MASK); |
77618084 LD |
824 | break; |
825 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
826 | if (arg == 0) | |
827 | conf &= (~ATMEL_PIO_OPD_MASK); | |
828 | else | |
829 | conf |= ATMEL_PIO_OPD_MASK; | |
830 | break; | |
831 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
832 | if (arg == 0) | |
833 | conf |= ATMEL_PIO_SCHMITT_MASK; | |
834 | else | |
835 | conf &= (~ATMEL_PIO_SCHMITT_MASK); | |
836 | break; | |
837 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
838 | if (arg == 0) { | |
839 | conf &= (~ATMEL_PIO_IFEN_MASK); | |
840 | conf &= (~ATMEL_PIO_IFSCEN_MASK); | |
841 | } else { | |
842 | /* | |
843 | * We don't care about the debounce value for several reasons: | |
844 | * - can't have different debounce periods inside a same group, | |
845 | * - the register to configure this period is a secure register. | |
846 | * The debouncing filter can filter a pulse with a duration of less | |
847 | * than 1/2 slow clock period. | |
848 | */ | |
849 | conf |= ATMEL_PIO_IFEN_MASK; | |
850 | conf |= ATMEL_PIO_IFSCEN_MASK; | |
851 | } | |
852 | break; | |
853 | case PIN_CONFIG_OUTPUT: | |
854 | conf |= ATMEL_PIO_DIR_MASK; | |
855 | bank = ATMEL_PIO_BANK(pin_id); | |
856 | pin = ATMEL_PIO_LINE(pin_id); | |
857 | mask = 1 << pin; | |
858 | ||
859 | if (arg == 0) { | |
860 | writel_relaxed(mask, atmel_pioctrl->reg_base + | |
861 | bank * ATMEL_PIO_BANK_OFFSET + | |
862 | ATMEL_PIO_CODR); | |
863 | } else { | |
864 | writel_relaxed(mask, atmel_pioctrl->reg_base + | |
865 | bank * ATMEL_PIO_BANK_OFFSET + | |
866 | ATMEL_PIO_SODR); | |
867 | } | |
868 | break; | |
c709135e CB |
869 | case PIN_CONFIG_SLEW_RATE: |
870 | if (!atmel_pioctrl->slew_rate_support) | |
871 | break; | |
872 | /* And remove it if explicitly requested. */ | |
873 | if (arg == 0) | |
874 | conf &= ~ATMEL_PIO_SR_MASK; | |
875 | break; | |
ff10e353 LD |
876 | case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: |
877 | switch (arg) { | |
878 | case ATMEL_PIO_DRVSTR_LO: | |
879 | case ATMEL_PIO_DRVSTR_ME: | |
880 | case ATMEL_PIO_DRVSTR_HI: | |
881 | conf &= (~ATMEL_PIO_DRVSTR_MASK); | |
882 | conf |= arg << ATMEL_PIO_DRVSTR_OFFSET; | |
883 | break; | |
884 | default: | |
885 | dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n"); | |
886 | } | |
887 | break; | |
eaa4c8f9 RW |
888 | case PIN_CONFIG_PERSIST_STATE: |
889 | return -ENOTSUPP; | |
77618084 LD |
890 | default: |
891 | dev_warn(pctldev->dev, | |
892 | "unsupported configuration parameter: %u\n", | |
893 | param); | |
894 | continue; | |
895 | } | |
896 | } | |
897 | ||
898 | dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); | |
899 | atmel_pin_config_write(pctldev, pin_id, conf); | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
fcd76317 RW |
904 | static int atmel_conf_pin_config_set(struct pinctrl_dev *pctldev, |
905 | unsigned pin, | |
906 | unsigned long *configs, | |
907 | unsigned num_configs) | |
908 | { | |
909 | struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin); | |
910 | ||
911 | return atmel_conf_pin_config_group_set(pctldev, grp->pin, configs, num_configs); | |
912 | } | |
913 | ||
914 | static int atmel_conf_pin_config_get(struct pinctrl_dev *pctldev, | |
915 | unsigned pin, | |
916 | unsigned long *configs) | |
917 | { | |
918 | struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin); | |
919 | ||
920 | return atmel_conf_pin_config_group_get(pctldev, grp->pin, configs); | |
921 | } | |
922 | ||
77618084 | 923 | static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, |
b4435b42 CB |
924 | struct seq_file *s, |
925 | unsigned int pin_id) | |
77618084 LD |
926 | { |
927 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
928 | u32 conf; | |
929 | ||
930 | if (!atmel_pioctrl->pins[pin_id]->device) | |
931 | return; | |
932 | ||
933 | if (atmel_pioctrl->pins[pin_id]) | |
934 | seq_printf(s, " (%s, ioset %u) ", | |
935 | atmel_pioctrl->pins[pin_id]->device, | |
936 | atmel_pioctrl->pins[pin_id]->ioset); | |
937 | ||
938 | conf = atmel_pin_config_read(pctldev, pin_id); | |
939 | if (conf & ATMEL_PIO_PUEN_MASK) | |
940 | seq_printf(s, "%s ", "pull-up"); | |
941 | if (conf & ATMEL_PIO_PDEN_MASK) | |
942 | seq_printf(s, "%s ", "pull-down"); | |
943 | if (conf & ATMEL_PIO_IFEN_MASK) | |
944 | seq_printf(s, "%s ", "debounce"); | |
945 | if (conf & ATMEL_PIO_OPD_MASK) | |
946 | seq_printf(s, "%s ", "open-drain"); | |
947 | if (conf & ATMEL_PIO_SCHMITT_MASK) | |
948 | seq_printf(s, "%s ", "schmitt"); | |
c709135e CB |
949 | if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK)) |
950 | seq_printf(s, "%s ", "slew-rate"); | |
ff10e353 LD |
951 | if (conf & ATMEL_PIO_DRVSTR_MASK) { |
952 | switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) { | |
953 | case ATMEL_PIO_DRVSTR_ME: | |
954 | seq_printf(s, "%s ", "medium-drive"); | |
955 | break; | |
956 | case ATMEL_PIO_DRVSTR_HI: | |
957 | seq_printf(s, "%s ", "high-drive"); | |
958 | break; | |
959 | /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */ | |
960 | default: | |
961 | seq_printf(s, "%s ", "low-drive"); | |
962 | } | |
963 | } | |
77618084 LD |
964 | } |
965 | ||
966 | static const struct pinconf_ops atmel_confops = { | |
967 | .pin_config_group_get = atmel_conf_pin_config_group_get, | |
968 | .pin_config_group_set = atmel_conf_pin_config_group_set, | |
969 | .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, | |
fcd76317 RW |
970 | .pin_config_set = atmel_conf_pin_config_set, |
971 | .pin_config_get = atmel_conf_pin_config_get, | |
77618084 LD |
972 | }; |
973 | ||
974 | static struct pinctrl_desc atmel_pinctrl_desc = { | |
975 | .name = "atmel_pinctrl", | |
976 | .confops = &atmel_confops, | |
977 | .pctlops = &atmel_pctlops, | |
978 | .pmxops = &atmel_pmxops, | |
979 | }; | |
980 | ||
6be2a3a0 | 981 | static int __maybe_unused atmel_pctrl_suspend(struct device *dev) |
de4e882f | 982 | { |
1ccb0426 | 983 | struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev); |
ba9e7f27 | 984 | int i, j; |
de4e882f LD |
985 | |
986 | /* | |
987 | * For each bank, save IMR to restore it later and disable all GPIO | |
988 | * interrupts excepting the ones marked as wakeup sources. | |
989 | */ | |
990 | for (i = 0; i < atmel_pioctrl->nbanks; i++) { | |
ba9e7f27 | 991 | atmel_pioctrl->pm_suspend_backup[i].imr = |
de4e882f LD |
992 | atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR); |
993 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR, | |
994 | ~atmel_pioctrl->pm_wakeup_sources[i]); | |
ba9e7f27 AB |
995 | atmel_pioctrl->pm_suspend_backup[i].odsr = |
996 | atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR); | |
997 | for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { | |
998 | atmel_gpio_write(atmel_pioctrl, i, | |
999 | ATMEL_PIO_MSKR, BIT(j)); | |
1000 | atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = | |
1001 | atmel_gpio_read(atmel_pioctrl, i, | |
1002 | ATMEL_PIO_CFGR); | |
1003 | } | |
de4e882f LD |
1004 | } |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
6be2a3a0 | 1009 | static int __maybe_unused atmel_pctrl_resume(struct device *dev) |
de4e882f | 1010 | { |
1ccb0426 | 1011 | struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev); |
ba9e7f27 | 1012 | int i, j; |
de4e882f | 1013 | |
ba9e7f27 | 1014 | for (i = 0; i < atmel_pioctrl->nbanks; i++) { |
de4e882f | 1015 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER, |
ba9e7f27 AB |
1016 | atmel_pioctrl->pm_suspend_backup[i].imr); |
1017 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR, | |
1018 | atmel_pioctrl->pm_suspend_backup[i].odsr); | |
1019 | for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { | |
1020 | atmel_gpio_write(atmel_pioctrl, i, | |
1021 | ATMEL_PIO_MSKR, BIT(j)); | |
1022 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR, | |
1023 | atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); | |
1024 | } | |
1025 | } | |
de4e882f LD |
1026 | |
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static const struct dev_pm_ops atmel_pctrl_pm_ops = { | |
1031 | SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume) | |
1032 | }; | |
1033 | ||
77618084 LD |
1034 | /* |
1035 | * The number of banks can be different from a SoC to another one. | |
1036 | * We can have up to 16 banks. | |
1037 | */ | |
1038 | static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { | |
b6071c89 EH |
1039 | .nbanks = 4, |
1040 | .last_bank_count = ATMEL_PIO_NPINS_PER_BANK, | |
77618084 LD |
1041 | }; |
1042 | ||
737894d2 | 1043 | static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { |
b6071c89 EH |
1044 | .nbanks = 5, |
1045 | .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ | |
c709135e | 1046 | .slew_rate_support = 1, |
737894d2 EH |
1047 | }; |
1048 | ||
77618084 LD |
1049 | static const struct of_device_id atmel_pctrl_of_match[] = { |
1050 | { | |
1051 | .compatible = "atmel,sama5d2-pinctrl", | |
1052 | .data = &atmel_sama5d2_pioctrl_data, | |
737894d2 EH |
1053 | }, { |
1054 | .compatible = "microchip,sama7g5-pinctrl", | |
1055 | .data = µchip_sama7g5_pioctrl_data, | |
77618084 LD |
1056 | }, { |
1057 | /* sentinel */ | |
1058 | } | |
1059 | }; | |
77618084 LD |
1060 | |
1061 | static int atmel_pinctrl_probe(struct platform_device *pdev) | |
1062 | { | |
1063 | struct device *dev = &pdev->dev; | |
1064 | struct pinctrl_pin_desc *pin_desc; | |
1065 | const char **group_names; | |
1066 | const struct of_device_id *match; | |
1067 | int i, ret; | |
77618084 | 1068 | struct atmel_pioctrl *atmel_pioctrl; |
8b74c7d3 | 1069 | const struct atmel_pioctrl_data *atmel_pioctrl_data; |
77618084 LD |
1070 | |
1071 | atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); | |
1072 | if (!atmel_pioctrl) | |
1073 | return -ENOMEM; | |
1074 | atmel_pioctrl->dev = dev; | |
1075 | atmel_pioctrl->node = dev->of_node; | |
1076 | platform_set_drvdata(pdev, atmel_pioctrl); | |
1077 | ||
1078 | match = of_match_node(atmel_pctrl_of_match, dev->of_node); | |
1079 | if (!match) { | |
1080 | dev_err(dev, "unknown compatible string\n"); | |
1081 | return -ENODEV; | |
1082 | } | |
8b74c7d3 | 1083 | atmel_pioctrl_data = match->data; |
77618084 LD |
1084 | atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; |
1085 | atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; | |
b6071c89 EH |
1086 | /* if last bank has limited number of pins, adjust accordingly */ |
1087 | if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) { | |
1088 | atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; | |
1089 | atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; | |
1090 | } | |
c709135e | 1091 | atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support; |
77618084 | 1092 | |
4b024225 | 1093 | atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); |
77618084 | 1094 | if (IS_ERR(atmel_pioctrl->reg_base)) |
b5d9ff10 | 1095 | return PTR_ERR(atmel_pioctrl->reg_base); |
77618084 LD |
1096 | |
1097 | atmel_pioctrl->clk = devm_clk_get(dev, NULL); | |
1098 | if (IS_ERR(atmel_pioctrl->clk)) { | |
1099 | dev_err(dev, "failed to get clock\n"); | |
1100 | return PTR_ERR(atmel_pioctrl->clk); | |
1101 | } | |
1102 | ||
a86854d0 KC |
1103 | atmel_pioctrl->pins = devm_kcalloc(dev, |
1104 | atmel_pioctrl->npins, | |
1105 | sizeof(*atmel_pioctrl->pins), | |
1106 | GFP_KERNEL); | |
77618084 LD |
1107 | if (!atmel_pioctrl->pins) |
1108 | return -ENOMEM; | |
1109 | ||
a86854d0 KC |
1110 | pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc), |
1111 | GFP_KERNEL); | |
77618084 LD |
1112 | if (!pin_desc) |
1113 | return -ENOMEM; | |
1114 | atmel_pinctrl_desc.pins = pin_desc; | |
1115 | atmel_pinctrl_desc.npins = atmel_pioctrl->npins; | |
ff10e353 LD |
1116 | atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings); |
1117 | atmel_pinctrl_desc.custom_params = atmel_custom_bindings; | |
77618084 LD |
1118 | |
1119 | /* One pin is one group since a pin can achieve all functions. */ | |
a86854d0 KC |
1120 | group_names = devm_kcalloc(dev, |
1121 | atmel_pioctrl->npins, sizeof(*group_names), | |
1122 | GFP_KERNEL); | |
77618084 LD |
1123 | if (!group_names) |
1124 | return -ENOMEM; | |
1125 | atmel_pioctrl->group_names = group_names; | |
1126 | ||
a86854d0 KC |
1127 | atmel_pioctrl->groups = devm_kcalloc(&pdev->dev, |
1128 | atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups), | |
77618084 LD |
1129 | GFP_KERNEL); |
1130 | if (!atmel_pioctrl->groups) | |
1131 | return -ENOMEM; | |
1132 | for (i = 0 ; i < atmel_pioctrl->npins; i++) { | |
1133 | struct atmel_group *group = atmel_pioctrl->groups + i; | |
b4435b42 CB |
1134 | unsigned int bank = ATMEL_PIO_BANK(i); |
1135 | unsigned int line = ATMEL_PIO_LINE(i); | |
77618084 LD |
1136 | |
1137 | atmel_pioctrl->pins[i] = devm_kzalloc(dev, | |
1138 | sizeof(**atmel_pioctrl->pins), GFP_KERNEL); | |
1139 | if (!atmel_pioctrl->pins[i]) | |
1140 | return -ENOMEM; | |
1141 | ||
1142 | atmel_pioctrl->pins[i]->pin_id = i; | |
1143 | atmel_pioctrl->pins[i]->bank = bank; | |
1144 | atmel_pioctrl->pins[i]->line = line; | |
1145 | ||
1146 | pin_desc[i].number = i; | |
1147 | /* Pin naming convention: P(bank_name)(bank_pin_number). */ | |
1148 | pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", | |
1149 | bank + 'A', line); | |
1150 | ||
1151 | group->name = group_names[i] = pin_desc[i].name; | |
1152 | group->pin = pin_desc[i].number; | |
1153 | ||
1154 | dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); | |
1155 | } | |
1156 | ||
1157 | atmel_pioctrl->gpio_chip = &atmel_gpio_chip; | |
77618084 LD |
1158 | atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; |
1159 | atmel_pioctrl->gpio_chip->label = dev_name(dev); | |
58383c78 | 1160 | atmel_pioctrl->gpio_chip->parent = dev; |
77618084 | 1161 | atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; |
fcd76317 | 1162 | atmel_pioctrl->gpio_chip->set_config = gpiochip_generic_config; |
77618084 | 1163 | |
a86854d0 KC |
1164 | atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev, |
1165 | atmel_pioctrl->nbanks, | |
1166 | sizeof(*atmel_pioctrl->pm_wakeup_sources), | |
1167 | GFP_KERNEL); | |
de4e882f LD |
1168 | if (!atmel_pioctrl->pm_wakeup_sources) |
1169 | return -ENOMEM; | |
1170 | ||
a86854d0 KC |
1171 | atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev, |
1172 | atmel_pioctrl->nbanks, | |
1173 | sizeof(*atmel_pioctrl->pm_suspend_backup), | |
1174 | GFP_KERNEL); | |
de4e882f LD |
1175 | if (!atmel_pioctrl->pm_suspend_backup) |
1176 | return -ENOMEM; | |
1177 | ||
a86854d0 KC |
1178 | atmel_pioctrl->irqs = devm_kcalloc(dev, |
1179 | atmel_pioctrl->nbanks, | |
1180 | sizeof(*atmel_pioctrl->irqs), | |
1181 | GFP_KERNEL); | |
77618084 LD |
1182 | if (!atmel_pioctrl->irqs) |
1183 | return -ENOMEM; | |
1184 | ||
1185 | /* There is one controller but each bank has its own irq line. */ | |
1186 | for (i = 0; i < atmel_pioctrl->nbanks; i++) { | |
c00cdc32 LP |
1187 | ret = platform_get_irq(pdev, i); |
1188 | if (ret < 0) { | |
1189 | dev_dbg(dev, "missing irq resource for group %c\n", | |
77618084 | 1190 | 'A' + i); |
c00cdc32 | 1191 | return ret; |
77618084 | 1192 | } |
c00cdc32 LP |
1193 | atmel_pioctrl->irqs[i] = ret; |
1194 | irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl); | |
1195 | dev_dbg(dev, "bank %i: irq=%d\n", i, ret); | |
77618084 LD |
1196 | } |
1197 | ||
1198 | atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, | |
1199 | atmel_pioctrl->gpio_chip->ngpio, | |
1200 | &irq_domain_simple_ops, NULL); | |
1201 | if (!atmel_pioctrl->irq_domain) { | |
1202 | dev_err(dev, "can't add the irq domain\n"); | |
1203 | return -ENODEV; | |
1204 | } | |
1205 | atmel_pioctrl->irq_domain->name = "atmel gpio"; | |
1206 | ||
1207 | for (i = 0; i < atmel_pioctrl->npins; i++) { | |
1208 | int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); | |
1209 | ||
1210 | irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip, | |
1211 | handle_simple_irq); | |
1212 | irq_set_chip_data(irq, atmel_pioctrl); | |
1213 | dev_dbg(dev, | |
1214 | "atmel gpio irq domain: hwirq: %d, linux irq: %d\n", | |
1215 | i, irq); | |
1216 | } | |
1217 | ||
1218 | ret = clk_prepare_enable(atmel_pioctrl->clk); | |
1219 | if (ret) { | |
1220 | dev_err(dev, "failed to prepare and enable clock\n"); | |
1221 | goto clk_prepare_enable_error; | |
1222 | } | |
1223 | ||
5d3fc884 LD |
1224 | atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev, |
1225 | &atmel_pinctrl_desc, | |
1226 | atmel_pioctrl); | |
1227 | if (IS_ERR(atmel_pioctrl->pinctrl_dev)) { | |
1228 | ret = PTR_ERR(atmel_pioctrl->pinctrl_dev); | |
77618084 | 1229 | dev_err(dev, "pinctrl registration failed\n"); |
5d3fc884 | 1230 | goto clk_unprep; |
77618084 LD |
1231 | } |
1232 | ||
80036f88 | 1233 | ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl); |
77618084 LD |
1234 | if (ret) { |
1235 | dev_err(dev, "failed to add gpiochip\n"); | |
5d3fc884 | 1236 | goto clk_unprep; |
77618084 LD |
1237 | } |
1238 | ||
1239 | ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), | |
1240 | 0, 0, atmel_pioctrl->gpio_chip->ngpio); | |
1241 | if (ret) { | |
1242 | dev_err(dev, "failed to add gpio pin range\n"); | |
1243 | goto gpiochip_add_pin_range_error; | |
1244 | } | |
1245 | ||
1246 | dev_info(&pdev->dev, "atmel pinctrl initialized\n"); | |
1247 | ||
1248 | return 0; | |
1249 | ||
77618084 LD |
1250 | gpiochip_add_pin_range_error: |
1251 | gpiochip_remove(atmel_pioctrl->gpio_chip); | |
1252 | ||
5d3fc884 LD |
1253 | clk_unprep: |
1254 | clk_disable_unprepare(atmel_pioctrl->clk); | |
1255 | ||
1256 | clk_prepare_enable_error: | |
1257 | irq_domain_remove(atmel_pioctrl->irq_domain); | |
1258 | ||
77618084 LD |
1259 | return ret; |
1260 | } | |
1261 | ||
77618084 LD |
1262 | static struct platform_driver atmel_pinctrl_driver = { |
1263 | .driver = { | |
1264 | .name = "pinctrl-at91-pio4", | |
1265 | .of_match_table = atmel_pctrl_of_match, | |
de4e882f | 1266 | .pm = &atmel_pctrl_pm_ops, |
f703851a | 1267 | .suppress_bind_attrs = true, |
77618084 LD |
1268 | }, |
1269 | .probe = atmel_pinctrl_probe, | |
77618084 | 1270 | }; |
f703851a | 1271 | builtin_platform_driver(atmel_pinctrl_driver); |