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77618084 LD |
1 | /* |
2 | * Driver for the Atmel PIO4 controller | |
3 | * | |
4 | * Copyright (C) 2015 Atmel, | |
5 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pinctrl/pinconf.h> | |
24 | #include <linux/pinctrl/pinconf-generic.h> | |
25 | #include <linux/pinctrl/pinctrl.h> | |
26 | #include <linux/pinctrl/pinmux.h> | |
27 | #include <linux/slab.h> | |
28 | #include "core.h" | |
29 | #include "pinconf.h" | |
30 | #include "pinctrl-utils.h" | |
31 | ||
32 | /* | |
33 | * Warning: | |
34 | * In order to not introduce confusion between Atmel PIO groups and pinctrl | |
35 | * framework groups, Atmel PIO groups will be called banks, line is kept to | |
36 | * designed the pin id into this bank. | |
37 | */ | |
38 | ||
39 | #define ATMEL_PIO_MSKR 0x0000 | |
40 | #define ATMEL_PIO_CFGR 0x0004 | |
41 | #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) | |
42 | #define ATMEL_PIO_DIR_MASK BIT(8) | |
43 | #define ATMEL_PIO_PUEN_MASK BIT(9) | |
44 | #define ATMEL_PIO_PDEN_MASK BIT(10) | |
45 | #define ATMEL_PIO_IFEN_MASK BIT(12) | |
46 | #define ATMEL_PIO_IFSCEN_MASK BIT(13) | |
47 | #define ATMEL_PIO_OPD_MASK BIT(14) | |
48 | #define ATMEL_PIO_SCHMITT_MASK BIT(15) | |
49 | #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) | |
50 | #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) | |
51 | #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) | |
52 | #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) | |
53 | #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) | |
54 | #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) | |
55 | #define ATMEL_PIO_PDSR 0x0008 | |
56 | #define ATMEL_PIO_LOCKSR 0x000C | |
57 | #define ATMEL_PIO_SODR 0x0010 | |
58 | #define ATMEL_PIO_CODR 0x0014 | |
59 | #define ATMEL_PIO_ODSR 0x0018 | |
60 | #define ATMEL_PIO_IER 0x0020 | |
61 | #define ATMEL_PIO_IDR 0x0024 | |
62 | #define ATMEL_PIO_IMR 0x0028 | |
63 | #define ATMEL_PIO_ISR 0x002C | |
64 | #define ATMEL_PIO_IOFR 0x003C | |
65 | ||
66 | #define ATMEL_PIO_NPINS_PER_BANK 32 | |
67 | #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) | |
68 | #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) | |
69 | #define ATMEL_PIO_BANK_OFFSET 0x40 | |
70 | ||
71 | #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) | |
72 | #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) | |
73 | #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) | |
74 | ||
75 | struct atmel_pioctrl_data { | |
76 | unsigned nbanks; | |
77 | }; | |
78 | ||
79 | struct atmel_group { | |
80 | const char *name; | |
81 | u32 pin; | |
82 | }; | |
83 | ||
84 | struct atmel_pin { | |
85 | unsigned pin_id; | |
86 | unsigned mux; | |
87 | unsigned ioset; | |
88 | unsigned bank; | |
89 | unsigned line; | |
90 | const char *device; | |
91 | }; | |
92 | ||
93 | /** | |
94 | * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio) | |
95 | * @reg_base: base address of the controller. | |
96 | * @clk: clock of the controller. | |
97 | * @nbanks: number of PIO groups, it can vary depending on the SoC. | |
98 | * @pinctrl_dev: pinctrl device registered. | |
99 | * @groups: groups table to provide group name and pin in the group to pinctrl. | |
100 | * @group_names: group names table to provide all the group/pin names to | |
101 | * pinctrl or gpio. | |
102 | * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line | |
103 | * fields are set at probe time. Other ones are set when parsing dt | |
104 | * pinctrl. | |
105 | * @npins: number of pins. | |
106 | * @gpio_chip: gpio chip registered. | |
107 | * @irq_domain: irq domain for the gpio controller. | |
108 | * @irqs: table containing the hw irq number of the bank. The index of the | |
109 | * table is the bank id. | |
110 | * @dev: device entry for the Atmel PIO controller. | |
111 | * @node: node of the Atmel PIO controller. | |
112 | */ | |
113 | struct atmel_pioctrl { | |
114 | void __iomem *reg_base; | |
115 | struct clk *clk; | |
116 | unsigned nbanks; | |
117 | struct pinctrl_dev *pinctrl_dev; | |
118 | struct atmel_group *groups; | |
119 | const char * const *group_names; | |
120 | struct atmel_pin **pins; | |
121 | unsigned npins; | |
122 | struct gpio_chip *gpio_chip; | |
123 | struct irq_domain *irq_domain; | |
124 | int *irqs; | |
125 | struct device *dev; | |
126 | struct device_node *node; | |
127 | }; | |
128 | ||
129 | static const char * const atmel_functions[] = { | |
130 | "GPIO", "A", "B", "C", "D", "E", "F", "G" | |
131 | }; | |
132 | ||
133 | /* --- GPIO --- */ | |
134 | static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl, | |
135 | unsigned int bank, unsigned int reg) | |
136 | { | |
137 | return readl_relaxed(atmel_pioctrl->reg_base | |
138 | + ATMEL_PIO_BANK_OFFSET * bank + reg); | |
139 | } | |
140 | ||
141 | static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl, | |
142 | unsigned int bank, unsigned int reg, | |
143 | unsigned int val) | |
144 | { | |
145 | writel_relaxed(val, atmel_pioctrl->reg_base | |
146 | + ATMEL_PIO_BANK_OFFSET * bank + reg); | |
147 | } | |
148 | ||
149 | static void atmel_gpio_irq_ack(struct irq_data *d) | |
150 | { | |
151 | /* | |
152 | * Nothing to do, interrupt is cleared when reading the status | |
153 | * register. | |
154 | */ | |
155 | } | |
156 | ||
157 | static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) | |
158 | { | |
159 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
160 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
161 | unsigned reg; | |
162 | ||
163 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
164 | BIT(pin->line)); | |
165 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
166 | reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); | |
167 | ||
168 | switch (type) { | |
169 | case IRQ_TYPE_EDGE_RISING: | |
170 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
171 | reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; | |
172 | break; | |
173 | case IRQ_TYPE_EDGE_FALLING: | |
174 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
175 | reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; | |
176 | break; | |
177 | case IRQ_TYPE_EDGE_BOTH: | |
178 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
179 | reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; | |
180 | break; | |
181 | case IRQ_TYPE_LEVEL_LOW: | |
182 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
183 | reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; | |
184 | break; | |
185 | case IRQ_TYPE_LEVEL_HIGH: | |
186 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
187 | reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; | |
188 | break; | |
189 | case IRQ_TYPE_NONE: | |
190 | default: | |
191 | return -EINVAL; | |
192 | } | |
193 | ||
194 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | static void atmel_gpio_irq_mask(struct irq_data *d) | |
200 | { | |
201 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
202 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
203 | ||
204 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, | |
205 | BIT(pin->line)); | |
206 | } | |
207 | ||
208 | static void atmel_gpio_irq_unmask(struct irq_data *d) | |
209 | { | |
210 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
211 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
212 | ||
213 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, | |
214 | BIT(pin->line)); | |
215 | } | |
216 | ||
217 | static struct irq_chip atmel_gpio_irq_chip = { | |
218 | .name = "GPIO", | |
219 | .irq_ack = atmel_gpio_irq_ack, | |
220 | .irq_mask = atmel_gpio_irq_mask, | |
221 | .irq_unmask = atmel_gpio_irq_unmask, | |
222 | .irq_set_type = atmel_gpio_irq_set_type, | |
223 | }; | |
224 | ||
225 | static void atmel_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
226 | { | |
227 | struct atmel_pioctrl *atmel_pioctrl = irq_get_handler_data(irq); | |
228 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
229 | unsigned long isr; | |
230 | int n, bank = -1; | |
231 | ||
232 | /* Find from which bank is the irq received. */ | |
233 | for (n = 0; n < atmel_pioctrl->nbanks; n++) { | |
234 | if (atmel_pioctrl->irqs[n] == irq) { | |
235 | bank = n; | |
236 | break; | |
237 | } | |
238 | } | |
239 | ||
240 | if (bank < 0) { | |
241 | dev_err(atmel_pioctrl->dev, | |
242 | "no bank associated to irq %u\n", irq); | |
243 | return; | |
244 | } | |
245 | ||
246 | chained_irq_enter(chip, desc); | |
247 | ||
248 | for (;;) { | |
249 | isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, | |
250 | ATMEL_PIO_ISR); | |
251 | isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, | |
252 | ATMEL_PIO_IMR); | |
253 | if (!isr) | |
254 | break; | |
255 | ||
256 | for_each_set_bit(n, &isr, BITS_PER_LONG) | |
257 | generic_handle_irq(gpio_to_irq(bank * | |
258 | ATMEL_PIO_NPINS_PER_BANK + n)); | |
259 | } | |
260 | ||
261 | chained_irq_exit(chip, desc); | |
262 | } | |
263 | ||
264 | static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
265 | { | |
266 | struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); | |
267 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; | |
268 | unsigned reg; | |
269 | ||
270 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
271 | BIT(pin->line)); | |
272 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
273 | reg &= ~ATMEL_PIO_DIR_MASK; | |
274 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) | |
280 | { | |
281 | struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); | |
282 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; | |
283 | unsigned reg; | |
284 | ||
285 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); | |
286 | ||
287 | return !!(reg & BIT(pin->line)); | |
288 | } | |
289 | ||
290 | static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
291 | int value) | |
292 | { | |
293 | struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); | |
294 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; | |
295 | unsigned reg; | |
296 | ||
297 | atmel_gpio_write(atmel_pioctrl, pin->bank, | |
298 | value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, | |
299 | BIT(pin->line)); | |
300 | ||
301 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
302 | BIT(pin->line)); | |
303 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
304 | reg |= ATMEL_PIO_DIR_MASK; | |
305 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
311 | { | |
312 | struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); | |
313 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; | |
314 | ||
315 | atmel_gpio_write(atmel_pioctrl, pin->bank, | |
316 | val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, | |
317 | BIT(pin->line)); | |
318 | } | |
319 | ||
320 | static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
321 | { | |
322 | struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); | |
323 | ||
324 | return irq_find_mapping(atmel_pioctrl->irq_domain, offset); | |
325 | } | |
326 | ||
327 | static struct gpio_chip atmel_gpio_chip = { | |
328 | .direction_input = atmel_gpio_direction_input, | |
329 | .get = atmel_gpio_get, | |
330 | .direction_output = atmel_gpio_direction_output, | |
331 | .set = atmel_gpio_set, | |
332 | .to_irq = atmel_gpio_to_irq, | |
333 | .base = 0, | |
334 | }; | |
335 | ||
336 | /* --- PINCTRL --- */ | |
337 | static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, | |
338 | unsigned pin_id) | |
339 | { | |
340 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
341 | unsigned bank = atmel_pioctrl->pins[pin_id]->bank; | |
342 | unsigned line = atmel_pioctrl->pins[pin_id]->line; | |
343 | void __iomem *addr = atmel_pioctrl->reg_base | |
344 | + bank * ATMEL_PIO_BANK_OFFSET; | |
345 | ||
346 | writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); | |
347 | /* Have to set MSKR first, to access the right pin CFGR. */ | |
348 | wmb(); | |
349 | ||
350 | return readl_relaxed(addr + ATMEL_PIO_CFGR); | |
351 | } | |
352 | ||
353 | static void atmel_pin_config_write(struct pinctrl_dev *pctldev, | |
354 | unsigned pin_id, u32 conf) | |
355 | { | |
356 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
357 | unsigned bank = atmel_pioctrl->pins[pin_id]->bank; | |
358 | unsigned line = atmel_pioctrl->pins[pin_id]->line; | |
359 | void __iomem *addr = atmel_pioctrl->reg_base | |
360 | + bank * ATMEL_PIO_BANK_OFFSET; | |
361 | ||
362 | writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); | |
363 | /* Have to set MSKR first, to access the right pin CFGR. */ | |
364 | wmb(); | |
365 | writel_relaxed(conf, addr + ATMEL_PIO_CFGR); | |
366 | } | |
367 | ||
368 | static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) | |
369 | { | |
370 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
371 | ||
372 | return atmel_pioctrl->npins; | |
373 | } | |
374 | ||
375 | static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, | |
376 | unsigned selector) | |
377 | { | |
378 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
379 | ||
380 | return atmel_pioctrl->groups[selector].name; | |
381 | } | |
382 | ||
383 | static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, | |
384 | unsigned selector, const unsigned **pins, | |
385 | unsigned *num_pins) | |
386 | { | |
387 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
388 | ||
389 | *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; | |
390 | *num_pins = 1; | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | struct atmel_group *atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, | |
396 | unsigned pin) | |
397 | { | |
398 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
399 | int i; | |
400 | ||
401 | for (i = 0; i < atmel_pioctrl->npins; i++) { | |
402 | struct atmel_group *grp = atmel_pioctrl->groups + i; | |
403 | ||
404 | if (grp->pin == pin) | |
405 | return grp; | |
406 | } | |
407 | ||
408 | return NULL; | |
409 | } | |
410 | ||
411 | static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, | |
412 | struct device_node *np, | |
413 | u32 pinfunc, const char **grp_name, | |
414 | const char **func_name) | |
415 | { | |
416 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
417 | unsigned pin_id, func_id; | |
418 | struct atmel_group *grp; | |
419 | ||
420 | pin_id = ATMEL_GET_PIN_NO(pinfunc); | |
421 | func_id = ATMEL_GET_PIN_FUNC(pinfunc); | |
422 | ||
423 | if (func_id >= ARRAY_SIZE(atmel_functions)) | |
424 | return -EINVAL; | |
425 | ||
426 | *func_name = atmel_functions[func_id]; | |
427 | ||
428 | grp = atmel_pctl_find_group_by_pin(pctldev, pin_id); | |
429 | if (!grp) | |
430 | return -EINVAL; | |
431 | *grp_name = grp->name; | |
432 | ||
433 | atmel_pioctrl->pins[pin_id]->mux = func_id; | |
434 | atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); | |
435 | /* Want the device name not the group one. */ | |
436 | if (np->parent == atmel_pioctrl->node) | |
437 | atmel_pioctrl->pins[pin_id]->device = np->name; | |
438 | else | |
439 | atmel_pioctrl->pins[pin_id]->device = np->parent->name; | |
440 | ||
441 | return 0; | |
442 | } | |
443 | ||
444 | static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
445 | struct device_node *np, | |
446 | struct pinctrl_map **map, | |
447 | unsigned *reserved_maps, | |
448 | unsigned *num_maps) | |
449 | { | |
450 | unsigned num_pins, num_configs, reserve; | |
451 | unsigned long *configs; | |
452 | struct property *pins; | |
453 | bool has_config; | |
454 | u32 pinfunc; | |
455 | int ret, i; | |
456 | ||
457 | pins = of_find_property(np, "pinmux", NULL); | |
458 | if (!pins) | |
459 | return -EINVAL; | |
460 | ||
461 | ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, | |
462 | &num_configs); | |
463 | if (ret < 0) { | |
464 | dev_err(pctldev->dev, "%s: could not parse node property\n", | |
465 | of_node_full_name(np)); | |
466 | return ret; | |
467 | } | |
468 | ||
469 | if (num_configs) | |
470 | has_config = true; | |
471 | ||
472 | num_pins = pins->length / sizeof(u32); | |
473 | if (!num_pins) { | |
474 | dev_err(pctldev->dev, "no pins found in node %s\n", | |
475 | of_node_full_name(np)); | |
476 | return -EINVAL; | |
477 | } | |
478 | ||
479 | /* | |
480 | * Reserve maps, at least there is a mux map and an optional conf | |
481 | * map for each pin. | |
482 | */ | |
483 | reserve = 1; | |
484 | if (has_config && num_pins >= 1) | |
485 | reserve++; | |
486 | reserve *= num_pins; | |
487 | ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, | |
488 | reserve); | |
489 | if (ret < 0) | |
490 | return ret; | |
491 | ||
492 | for (i = 0; i < num_pins; i++) { | |
493 | const char *group, *func; | |
494 | ||
495 | ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); | |
496 | if (ret) | |
497 | return ret; | |
498 | ||
499 | ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, | |
500 | &func); | |
501 | if (ret) | |
502 | return ret; | |
503 | ||
504 | pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, | |
505 | group, func); | |
506 | ||
507 | if (has_config) { | |
508 | ret = pinctrl_utils_add_map_configs(pctldev, map, | |
509 | reserved_maps, num_maps, group, | |
510 | configs, num_configs, | |
511 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
512 | if (ret < 0) | |
513 | return ret; | |
514 | } | |
515 | } | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
521 | struct device_node *np_config, | |
522 | struct pinctrl_map **map, | |
523 | unsigned *num_maps) | |
524 | { | |
525 | struct device_node *np; | |
526 | unsigned reserved_maps; | |
527 | int ret; | |
528 | ||
529 | *map = NULL; | |
530 | *num_maps = 0; | |
531 | reserved_maps = 0; | |
532 | ||
533 | /* | |
534 | * If all the pins of a device have the same configuration (or no one), | |
535 | * it is useless to add a subnode, so directly parse node referenced by | |
536 | * phandle. | |
537 | */ | |
538 | ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map, | |
539 | &reserved_maps, num_maps); | |
540 | if (ret) { | |
541 | for_each_child_of_node(np_config, np) { | |
542 | ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map, | |
543 | &reserved_maps, num_maps); | |
544 | if (ret < 0) | |
545 | break; | |
546 | } | |
547 | } | |
548 | ||
549 | if (ret < 0) { | |
550 | pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); | |
551 | dev_err(pctldev->dev, "can't create maps for node %s\n", | |
552 | np_config->full_name); | |
553 | } | |
554 | ||
555 | return ret; | |
556 | } | |
557 | ||
558 | static const struct pinctrl_ops atmel_pctlops = { | |
559 | .get_groups_count = atmel_pctl_get_groups_count, | |
560 | .get_group_name = atmel_pctl_get_group_name, | |
561 | .get_group_pins = atmel_pctl_get_group_pins, | |
562 | .dt_node_to_map = atmel_pctl_dt_node_to_map, | |
563 | .dt_free_map = pinctrl_utils_dt_free_map, | |
564 | }; | |
565 | ||
566 | static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) | |
567 | { | |
568 | return ARRAY_SIZE(atmel_functions); | |
569 | } | |
570 | ||
571 | static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, | |
572 | unsigned selector) | |
573 | { | |
574 | return atmel_functions[selector]; | |
575 | } | |
576 | ||
577 | static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, | |
578 | unsigned selector, | |
579 | const char * const **groups, | |
580 | unsigned * const num_groups) | |
581 | { | |
582 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
583 | ||
584 | *groups = atmel_pioctrl->group_names; | |
585 | *num_groups = atmel_pioctrl->npins; | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, | |
591 | unsigned function, | |
592 | unsigned group) | |
593 | { | |
594 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
595 | unsigned pin; | |
596 | u32 conf; | |
597 | ||
598 | dev_dbg(pctldev->dev, "enable function %s group %s\n", | |
599 | atmel_functions[function], atmel_pioctrl->groups[group].name); | |
600 | ||
601 | pin = atmel_pioctrl->groups[group].pin; | |
602 | conf = atmel_pin_config_read(pctldev, pin); | |
603 | conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); | |
604 | conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK); | |
605 | dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); | |
606 | atmel_pin_config_write(pctldev, pin, conf); | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | static const struct pinmux_ops atmel_pmxops = { | |
612 | .get_functions_count = atmel_pmx_get_functions_count, | |
613 | .get_function_name = atmel_pmx_get_function_name, | |
614 | .get_function_groups = atmel_pmx_get_function_groups, | |
615 | .set_mux = atmel_pmx_set_mux, | |
616 | }; | |
617 | ||
618 | static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, | |
619 | unsigned group, | |
620 | unsigned long *config) | |
621 | { | |
622 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
623 | unsigned param = pinconf_to_config_param(*config), arg = 0; | |
624 | struct atmel_group *grp = atmel_pioctrl->groups + group; | |
625 | unsigned pin_id = grp->pin; | |
626 | u32 res; | |
627 | ||
628 | res = atmel_pin_config_read(pctldev, pin_id); | |
629 | ||
630 | switch (param) { | |
631 | case PIN_CONFIG_BIAS_PULL_UP: | |
632 | if (!(res & ATMEL_PIO_PUEN_MASK)) | |
633 | return -EINVAL; | |
634 | arg = 1; | |
635 | break; | |
636 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
637 | if ((res & ATMEL_PIO_PUEN_MASK) || | |
638 | (!(res & ATMEL_PIO_PDEN_MASK))) | |
639 | return -EINVAL; | |
640 | arg = 1; | |
641 | break; | |
642 | case PIN_CONFIG_BIAS_DISABLE: | |
643 | if ((res & ATMEL_PIO_PUEN_MASK) || | |
644 | ((res & ATMEL_PIO_PDEN_MASK))) | |
645 | return -EINVAL; | |
646 | arg = 1; | |
647 | break; | |
648 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
649 | if (!(res & ATMEL_PIO_OPD_MASK)) | |
650 | return -EINVAL; | |
651 | arg = 1; | |
652 | break; | |
653 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
654 | if (!(res & ATMEL_PIO_SCHMITT_MASK)) | |
655 | return -EINVAL; | |
656 | arg = 1; | |
657 | break; | |
658 | default: | |
659 | return -ENOTSUPP; | |
660 | } | |
661 | ||
662 | *config = pinconf_to_config_packed(param, arg); | |
663 | return 0; | |
664 | } | |
665 | ||
666 | static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, | |
667 | unsigned group, | |
668 | unsigned long *configs, | |
669 | unsigned num_configs) | |
670 | { | |
671 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
672 | struct atmel_group *grp = atmel_pioctrl->groups + group; | |
673 | unsigned bank, pin, pin_id = grp->pin; | |
674 | u32 mask, conf = 0; | |
675 | int i; | |
676 | ||
677 | conf = atmel_pin_config_read(pctldev, pin_id); | |
678 | ||
679 | for (i = 0; i < num_configs; i++) { | |
680 | unsigned param = pinconf_to_config_param(configs[i]); | |
681 | unsigned arg = pinconf_to_config_argument(configs[i]); | |
682 | ||
683 | dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", | |
684 | __func__, pin_id, configs[i]); | |
685 | ||
686 | switch (param) { | |
687 | case PIN_CONFIG_BIAS_DISABLE: | |
688 | conf &= (~ATMEL_PIO_PUEN_MASK); | |
689 | conf &= (~ATMEL_PIO_PDEN_MASK); | |
690 | break; | |
691 | case PIN_CONFIG_BIAS_PULL_UP: | |
692 | conf |= ATMEL_PIO_PUEN_MASK; | |
693 | break; | |
694 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
695 | conf |= ATMEL_PIO_PDEN_MASK; | |
696 | break; | |
697 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
698 | if (arg == 0) | |
699 | conf &= (~ATMEL_PIO_OPD_MASK); | |
700 | else | |
701 | conf |= ATMEL_PIO_OPD_MASK; | |
702 | break; | |
703 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
704 | if (arg == 0) | |
705 | conf |= ATMEL_PIO_SCHMITT_MASK; | |
706 | else | |
707 | conf &= (~ATMEL_PIO_SCHMITT_MASK); | |
708 | break; | |
709 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
710 | if (arg == 0) { | |
711 | conf &= (~ATMEL_PIO_IFEN_MASK); | |
712 | conf &= (~ATMEL_PIO_IFSCEN_MASK); | |
713 | } else { | |
714 | /* | |
715 | * We don't care about the debounce value for several reasons: | |
716 | * - can't have different debounce periods inside a same group, | |
717 | * - the register to configure this period is a secure register. | |
718 | * The debouncing filter can filter a pulse with a duration of less | |
719 | * than 1/2 slow clock period. | |
720 | */ | |
721 | conf |= ATMEL_PIO_IFEN_MASK; | |
722 | conf |= ATMEL_PIO_IFSCEN_MASK; | |
723 | } | |
724 | break; | |
725 | case PIN_CONFIG_OUTPUT: | |
726 | conf |= ATMEL_PIO_DIR_MASK; | |
727 | bank = ATMEL_PIO_BANK(pin_id); | |
728 | pin = ATMEL_PIO_LINE(pin_id); | |
729 | mask = 1 << pin; | |
730 | ||
731 | if (arg == 0) { | |
732 | writel_relaxed(mask, atmel_pioctrl->reg_base + | |
733 | bank * ATMEL_PIO_BANK_OFFSET + | |
734 | ATMEL_PIO_CODR); | |
735 | } else { | |
736 | writel_relaxed(mask, atmel_pioctrl->reg_base + | |
737 | bank * ATMEL_PIO_BANK_OFFSET + | |
738 | ATMEL_PIO_SODR); | |
739 | } | |
740 | break; | |
741 | default: | |
742 | dev_warn(pctldev->dev, | |
743 | "unsupported configuration parameter: %u\n", | |
744 | param); | |
745 | continue; | |
746 | } | |
747 | } | |
748 | ||
749 | dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); | |
750 | atmel_pin_config_write(pctldev, pin_id, conf); | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, | |
756 | struct seq_file *s, unsigned pin_id) | |
757 | { | |
758 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
759 | u32 conf; | |
760 | ||
761 | if (!atmel_pioctrl->pins[pin_id]->device) | |
762 | return; | |
763 | ||
764 | if (atmel_pioctrl->pins[pin_id]) | |
765 | seq_printf(s, " (%s, ioset %u) ", | |
766 | atmel_pioctrl->pins[pin_id]->device, | |
767 | atmel_pioctrl->pins[pin_id]->ioset); | |
768 | ||
769 | conf = atmel_pin_config_read(pctldev, pin_id); | |
770 | if (conf & ATMEL_PIO_PUEN_MASK) | |
771 | seq_printf(s, "%s ", "pull-up"); | |
772 | if (conf & ATMEL_PIO_PDEN_MASK) | |
773 | seq_printf(s, "%s ", "pull-down"); | |
774 | if (conf & ATMEL_PIO_IFEN_MASK) | |
775 | seq_printf(s, "%s ", "debounce"); | |
776 | if (conf & ATMEL_PIO_OPD_MASK) | |
777 | seq_printf(s, "%s ", "open-drain"); | |
778 | if (conf & ATMEL_PIO_SCHMITT_MASK) | |
779 | seq_printf(s, "%s ", "schmitt"); | |
780 | } | |
781 | ||
782 | static const struct pinconf_ops atmel_confops = { | |
783 | .pin_config_group_get = atmel_conf_pin_config_group_get, | |
784 | .pin_config_group_set = atmel_conf_pin_config_group_set, | |
785 | .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, | |
786 | }; | |
787 | ||
788 | static struct pinctrl_desc atmel_pinctrl_desc = { | |
789 | .name = "atmel_pinctrl", | |
790 | .confops = &atmel_confops, | |
791 | .pctlops = &atmel_pctlops, | |
792 | .pmxops = &atmel_pmxops, | |
793 | }; | |
794 | ||
795 | /* | |
796 | * The number of banks can be different from a SoC to another one. | |
797 | * We can have up to 16 banks. | |
798 | */ | |
799 | static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { | |
800 | .nbanks = 4, | |
801 | }; | |
802 | ||
803 | static const struct of_device_id atmel_pctrl_of_match[] = { | |
804 | { | |
805 | .compatible = "atmel,sama5d2-pinctrl", | |
806 | .data = &atmel_sama5d2_pioctrl_data, | |
807 | }, { | |
808 | /* sentinel */ | |
809 | } | |
810 | }; | |
811 | MODULE_DEVICE_TABLE(of, atmel_pctrl_of_match); | |
812 | ||
813 | static int atmel_pinctrl_probe(struct platform_device *pdev) | |
814 | { | |
815 | struct device *dev = &pdev->dev; | |
816 | struct pinctrl_pin_desc *pin_desc; | |
817 | const char **group_names; | |
818 | const struct of_device_id *match; | |
819 | int i, ret; | |
820 | struct resource *res; | |
821 | struct atmel_pioctrl *atmel_pioctrl; | |
822 | struct atmel_pioctrl_data *atmel_pioctrl_data; | |
823 | ||
824 | atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); | |
825 | if (!atmel_pioctrl) | |
826 | return -ENOMEM; | |
827 | atmel_pioctrl->dev = dev; | |
828 | atmel_pioctrl->node = dev->of_node; | |
829 | platform_set_drvdata(pdev, atmel_pioctrl); | |
830 | ||
831 | match = of_match_node(atmel_pctrl_of_match, dev->of_node); | |
832 | if (!match) { | |
833 | dev_err(dev, "unknown compatible string\n"); | |
834 | return -ENODEV; | |
835 | } | |
836 | atmel_pioctrl_data = (struct atmel_pioctrl_data *)match->data; | |
837 | atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; | |
838 | atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; | |
839 | ||
840 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
841 | if (!res) { | |
842 | dev_err(dev, "unable to get atmel pinctrl resource\n"); | |
843 | return -EINVAL; | |
844 | } | |
845 | atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res); | |
846 | if (IS_ERR(atmel_pioctrl->reg_base)) | |
847 | return -EINVAL; | |
848 | ||
849 | atmel_pioctrl->clk = devm_clk_get(dev, NULL); | |
850 | if (IS_ERR(atmel_pioctrl->clk)) { | |
851 | dev_err(dev, "failed to get clock\n"); | |
852 | return PTR_ERR(atmel_pioctrl->clk); | |
853 | } | |
854 | ||
855 | atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins) | |
856 | * atmel_pioctrl->npins, GFP_KERNEL); | |
857 | if (!atmel_pioctrl->pins) | |
858 | return -ENOMEM; | |
859 | ||
860 | pin_desc = devm_kzalloc(dev, sizeof(*pin_desc) | |
861 | * atmel_pioctrl->npins, GFP_KERNEL); | |
862 | if (!pin_desc) | |
863 | return -ENOMEM; | |
864 | atmel_pinctrl_desc.pins = pin_desc; | |
865 | atmel_pinctrl_desc.npins = atmel_pioctrl->npins; | |
866 | ||
867 | /* One pin is one group since a pin can achieve all functions. */ | |
868 | group_names = devm_kzalloc(dev, sizeof(*group_names) | |
869 | * atmel_pioctrl->npins, GFP_KERNEL); | |
870 | if (!group_names) | |
871 | return -ENOMEM; | |
872 | atmel_pioctrl->group_names = group_names; | |
873 | ||
874 | atmel_pioctrl->groups = devm_kzalloc(&pdev->dev, | |
875 | sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins, | |
876 | GFP_KERNEL); | |
877 | if (!atmel_pioctrl->groups) | |
878 | return -ENOMEM; | |
879 | for (i = 0 ; i < atmel_pioctrl->npins; i++) { | |
880 | struct atmel_group *group = atmel_pioctrl->groups + i; | |
881 | unsigned bank = ATMEL_PIO_BANK(i); | |
882 | unsigned line = ATMEL_PIO_LINE(i); | |
883 | ||
884 | atmel_pioctrl->pins[i] = devm_kzalloc(dev, | |
885 | sizeof(**atmel_pioctrl->pins), GFP_KERNEL); | |
886 | if (!atmel_pioctrl->pins[i]) | |
887 | return -ENOMEM; | |
888 | ||
889 | atmel_pioctrl->pins[i]->pin_id = i; | |
890 | atmel_pioctrl->pins[i]->bank = bank; | |
891 | atmel_pioctrl->pins[i]->line = line; | |
892 | ||
893 | pin_desc[i].number = i; | |
894 | /* Pin naming convention: P(bank_name)(bank_pin_number). */ | |
895 | pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", | |
896 | bank + 'A', line); | |
897 | ||
898 | group->name = group_names[i] = pin_desc[i].name; | |
899 | group->pin = pin_desc[i].number; | |
900 | ||
901 | dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); | |
902 | } | |
903 | ||
904 | atmel_pioctrl->gpio_chip = &atmel_gpio_chip; | |
905 | atmel_pioctrl->gpio_chip->of_node = dev->of_node; | |
906 | atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; | |
907 | atmel_pioctrl->gpio_chip->label = dev_name(dev); | |
908 | atmel_pioctrl->gpio_chip->dev = dev; | |
909 | atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; | |
910 | ||
911 | atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs) | |
912 | * atmel_pioctrl->nbanks, GFP_KERNEL); | |
913 | if (!atmel_pioctrl->irqs) | |
914 | return -ENOMEM; | |
915 | ||
916 | /* There is one controller but each bank has its own irq line. */ | |
917 | for (i = 0; i < atmel_pioctrl->nbanks; i++) { | |
918 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); | |
919 | if (!res) { | |
920 | dev_err(dev, "missing irq resource for group %c\n", | |
921 | 'A' + i); | |
922 | return -EINVAL; | |
923 | } | |
924 | atmel_pioctrl->irqs[i] = res->start; | |
925 | irq_set_chained_handler(res->start, atmel_gpio_irq_handler); | |
926 | irq_set_handler_data(res->start, atmel_pioctrl); | |
927 | dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start); | |
928 | } | |
929 | ||
930 | atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, | |
931 | atmel_pioctrl->gpio_chip->ngpio, | |
932 | &irq_domain_simple_ops, NULL); | |
933 | if (!atmel_pioctrl->irq_domain) { | |
934 | dev_err(dev, "can't add the irq domain\n"); | |
935 | return -ENODEV; | |
936 | } | |
937 | atmel_pioctrl->irq_domain->name = "atmel gpio"; | |
938 | ||
939 | for (i = 0; i < atmel_pioctrl->npins; i++) { | |
940 | int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); | |
941 | ||
942 | irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip, | |
943 | handle_simple_irq); | |
944 | irq_set_chip_data(irq, atmel_pioctrl); | |
945 | dev_dbg(dev, | |
946 | "atmel gpio irq domain: hwirq: %d, linux irq: %d\n", | |
947 | i, irq); | |
948 | } | |
949 | ||
950 | ret = clk_prepare_enable(atmel_pioctrl->clk); | |
951 | if (ret) { | |
952 | dev_err(dev, "failed to prepare and enable clock\n"); | |
953 | goto clk_prepare_enable_error; | |
954 | } | |
955 | ||
956 | atmel_pioctrl->pinctrl_dev = pinctrl_register(&atmel_pinctrl_desc, | |
957 | &pdev->dev, | |
958 | atmel_pioctrl); | |
959 | if (!atmel_pioctrl->pinctrl_dev) { | |
960 | dev_err(dev, "pinctrl registration failed\n"); | |
961 | goto pinctrl_register_error; | |
962 | } | |
963 | ||
964 | ret = gpiochip_add(atmel_pioctrl->gpio_chip); | |
965 | if (ret) { | |
966 | dev_err(dev, "failed to add gpiochip\n"); | |
967 | goto gpiochip_add_error; | |
968 | } | |
969 | ||
970 | ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), | |
971 | 0, 0, atmel_pioctrl->gpio_chip->ngpio); | |
972 | if (ret) { | |
973 | dev_err(dev, "failed to add gpio pin range\n"); | |
974 | goto gpiochip_add_pin_range_error; | |
975 | } | |
976 | ||
977 | dev_info(&pdev->dev, "atmel pinctrl initialized\n"); | |
978 | ||
979 | return 0; | |
980 | ||
981 | clk_prepare_enable_error: | |
982 | irq_domain_remove(atmel_pioctrl->irq_domain); | |
983 | pinctrl_register_error: | |
984 | clk_disable_unprepare(atmel_pioctrl->clk); | |
985 | gpiochip_add_error: | |
986 | pinctrl_unregister(atmel_pioctrl->pinctrl_dev); | |
987 | gpiochip_add_pin_range_error: | |
988 | gpiochip_remove(atmel_pioctrl->gpio_chip); | |
989 | ||
990 | return ret; | |
991 | } | |
992 | ||
993 | int atmel_pinctrl_remove(struct platform_device *pdev) | |
994 | { | |
995 | struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); | |
996 | ||
997 | irq_domain_remove(atmel_pioctrl->irq_domain); | |
998 | clk_disable_unprepare(atmel_pioctrl->clk); | |
999 | pinctrl_unregister(atmel_pioctrl->pinctrl_dev); | |
1000 | gpiochip_remove(atmel_pioctrl->gpio_chip); | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static struct platform_driver atmel_pinctrl_driver = { | |
1006 | .driver = { | |
1007 | .name = "pinctrl-at91-pio4", | |
1008 | .of_match_table = atmel_pctrl_of_match, | |
1009 | }, | |
1010 | .probe = atmel_pinctrl_probe, | |
1011 | .remove = atmel_pinctrl_remove, | |
1012 | }; | |
1013 | module_platform_driver(atmel_pinctrl_driver); | |
1014 | ||
1015 | MODULE_AUTHOR(Ludovic Desroches <ludovic.desroches@atmel.com>); | |
1016 | MODULE_DESCRIPTION("Atmel PIO4 pinctrl driver"); | |
1017 | MODULE_LICENSE("GPL v2"); |