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77618084 LD |
1 | /* |
2 | * Driver for the Atmel PIO4 controller | |
3 | * | |
4 | * Copyright (C) 2015 Atmel, | |
5 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
80036f88 LW |
18 | #include <linux/gpio/driver.h> |
19 | /* FIXME: needed for gpio_to_irq(), get rid of this */ | |
77618084 | 20 | #include <linux/gpio.h> |
de4e882f | 21 | #include <linux/interrupt.h> |
77618084 | 22 | #include <linux/io.h> |
f703851a | 23 | #include <linux/init.h> |
77618084 LD |
24 | #include <linux/of.h> |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/pinctrl/pinconf.h> | |
27 | #include <linux/pinctrl/pinconf-generic.h> | |
28 | #include <linux/pinctrl/pinctrl.h> | |
29 | #include <linux/pinctrl/pinmux.h> | |
30 | #include <linux/slab.h> | |
31 | #include "core.h" | |
32 | #include "pinconf.h" | |
33 | #include "pinctrl-utils.h" | |
34 | ||
35 | /* | |
36 | * Warning: | |
37 | * In order to not introduce confusion between Atmel PIO groups and pinctrl | |
38 | * framework groups, Atmel PIO groups will be called banks, line is kept to | |
39 | * designed the pin id into this bank. | |
40 | */ | |
41 | ||
42 | #define ATMEL_PIO_MSKR 0x0000 | |
43 | #define ATMEL_PIO_CFGR 0x0004 | |
44 | #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) | |
45 | #define ATMEL_PIO_DIR_MASK BIT(8) | |
46 | #define ATMEL_PIO_PUEN_MASK BIT(9) | |
47 | #define ATMEL_PIO_PDEN_MASK BIT(10) | |
48 | #define ATMEL_PIO_IFEN_MASK BIT(12) | |
49 | #define ATMEL_PIO_IFSCEN_MASK BIT(13) | |
50 | #define ATMEL_PIO_OPD_MASK BIT(14) | |
51 | #define ATMEL_PIO_SCHMITT_MASK BIT(15) | |
52 | #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) | |
53 | #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) | |
54 | #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) | |
55 | #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) | |
56 | #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) | |
57 | #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) | |
58 | #define ATMEL_PIO_PDSR 0x0008 | |
59 | #define ATMEL_PIO_LOCKSR 0x000C | |
60 | #define ATMEL_PIO_SODR 0x0010 | |
61 | #define ATMEL_PIO_CODR 0x0014 | |
62 | #define ATMEL_PIO_ODSR 0x0018 | |
63 | #define ATMEL_PIO_IER 0x0020 | |
64 | #define ATMEL_PIO_IDR 0x0024 | |
65 | #define ATMEL_PIO_IMR 0x0028 | |
66 | #define ATMEL_PIO_ISR 0x002C | |
67 | #define ATMEL_PIO_IOFR 0x003C | |
68 | ||
69 | #define ATMEL_PIO_NPINS_PER_BANK 32 | |
70 | #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) | |
71 | #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) | |
72 | #define ATMEL_PIO_BANK_OFFSET 0x40 | |
73 | ||
74 | #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) | |
75 | #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) | |
76 | #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) | |
77 | ||
78 | struct atmel_pioctrl_data { | |
79 | unsigned nbanks; | |
80 | }; | |
81 | ||
82 | struct atmel_group { | |
83 | const char *name; | |
84 | u32 pin; | |
85 | }; | |
86 | ||
87 | struct atmel_pin { | |
88 | unsigned pin_id; | |
89 | unsigned mux; | |
90 | unsigned ioset; | |
91 | unsigned bank; | |
92 | unsigned line; | |
93 | const char *device; | |
94 | }; | |
95 | ||
96 | /** | |
97 | * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio) | |
98 | * @reg_base: base address of the controller. | |
99 | * @clk: clock of the controller. | |
100 | * @nbanks: number of PIO groups, it can vary depending on the SoC. | |
101 | * @pinctrl_dev: pinctrl device registered. | |
102 | * @groups: groups table to provide group name and pin in the group to pinctrl. | |
103 | * @group_names: group names table to provide all the group/pin names to | |
104 | * pinctrl or gpio. | |
105 | * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line | |
106 | * fields are set at probe time. Other ones are set when parsing dt | |
107 | * pinctrl. | |
108 | * @npins: number of pins. | |
109 | * @gpio_chip: gpio chip registered. | |
110 | * @irq_domain: irq domain for the gpio controller. | |
111 | * @irqs: table containing the hw irq number of the bank. The index of the | |
112 | * table is the bank id. | |
113 | * @dev: device entry for the Atmel PIO controller. | |
114 | * @node: node of the Atmel PIO controller. | |
115 | */ | |
116 | struct atmel_pioctrl { | |
117 | void __iomem *reg_base; | |
118 | struct clk *clk; | |
119 | unsigned nbanks; | |
120 | struct pinctrl_dev *pinctrl_dev; | |
121 | struct atmel_group *groups; | |
122 | const char * const *group_names; | |
123 | struct atmel_pin **pins; | |
124 | unsigned npins; | |
125 | struct gpio_chip *gpio_chip; | |
126 | struct irq_domain *irq_domain; | |
127 | int *irqs; | |
de4e882f | 128 | unsigned *pm_wakeup_sources; |
ba9e7f27 AB |
129 | struct { |
130 | u32 imr; | |
131 | u32 odsr; | |
132 | u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; | |
133 | } *pm_suspend_backup; | |
77618084 LD |
134 | struct device *dev; |
135 | struct device_node *node; | |
136 | }; | |
137 | ||
138 | static const char * const atmel_functions[] = { | |
139 | "GPIO", "A", "B", "C", "D", "E", "F", "G" | |
140 | }; | |
141 | ||
142 | /* --- GPIO --- */ | |
143 | static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl, | |
144 | unsigned int bank, unsigned int reg) | |
145 | { | |
146 | return readl_relaxed(atmel_pioctrl->reg_base | |
147 | + ATMEL_PIO_BANK_OFFSET * bank + reg); | |
148 | } | |
149 | ||
150 | static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl, | |
151 | unsigned int bank, unsigned int reg, | |
152 | unsigned int val) | |
153 | { | |
154 | writel_relaxed(val, atmel_pioctrl->reg_base | |
155 | + ATMEL_PIO_BANK_OFFSET * bank + reg); | |
156 | } | |
157 | ||
158 | static void atmel_gpio_irq_ack(struct irq_data *d) | |
159 | { | |
160 | /* | |
161 | * Nothing to do, interrupt is cleared when reading the status | |
162 | * register. | |
163 | */ | |
164 | } | |
165 | ||
166 | static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) | |
167 | { | |
168 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
169 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
170 | unsigned reg; | |
171 | ||
172 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
173 | BIT(pin->line)); | |
174 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
175 | reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); | |
176 | ||
177 | switch (type) { | |
178 | case IRQ_TYPE_EDGE_RISING: | |
3fd550c6 | 179 | irq_set_handler_locked(d, handle_edge_irq); |
77618084 LD |
180 | reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; |
181 | break; | |
182 | case IRQ_TYPE_EDGE_FALLING: | |
3fd550c6 | 183 | irq_set_handler_locked(d, handle_edge_irq); |
77618084 LD |
184 | reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; |
185 | break; | |
186 | case IRQ_TYPE_EDGE_BOTH: | |
3fd550c6 | 187 | irq_set_handler_locked(d, handle_edge_irq); |
77618084 LD |
188 | reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; |
189 | break; | |
190 | case IRQ_TYPE_LEVEL_LOW: | |
3fd550c6 | 191 | irq_set_handler_locked(d, handle_level_irq); |
77618084 LD |
192 | reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; |
193 | break; | |
194 | case IRQ_TYPE_LEVEL_HIGH: | |
3fd550c6 | 195 | irq_set_handler_locked(d, handle_level_irq); |
77618084 LD |
196 | reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; |
197 | break; | |
198 | case IRQ_TYPE_NONE: | |
199 | default: | |
200 | return -EINVAL; | |
201 | } | |
202 | ||
203 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | static void atmel_gpio_irq_mask(struct irq_data *d) | |
209 | { | |
210 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
211 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
212 | ||
213 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, | |
214 | BIT(pin->line)); | |
215 | } | |
216 | ||
217 | static void atmel_gpio_irq_unmask(struct irq_data *d) | |
218 | { | |
219 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
220 | struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; | |
221 | ||
222 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, | |
223 | BIT(pin->line)); | |
224 | } | |
225 | ||
de4e882f LD |
226 | #ifdef CONFIG_PM_SLEEP |
227 | ||
228 | static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |
229 | { | |
230 | struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); | |
231 | int bank = ATMEL_PIO_BANK(d->hwirq); | |
232 | int line = ATMEL_PIO_LINE(d->hwirq); | |
233 | ||
234 | /* The gpio controller has one interrupt line per bank. */ | |
235 | irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); | |
236 | ||
237 | if (on) | |
238 | atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); | |
239 | else | |
240 | atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | #else | |
245 | #define atmel_gpio_irq_set_wake NULL | |
246 | #endif /* CONFIG_PM_SLEEP */ | |
247 | ||
77618084 LD |
248 | static struct irq_chip atmel_gpio_irq_chip = { |
249 | .name = "GPIO", | |
250 | .irq_ack = atmel_gpio_irq_ack, | |
251 | .irq_mask = atmel_gpio_irq_mask, | |
252 | .irq_unmask = atmel_gpio_irq_unmask, | |
253 | .irq_set_type = atmel_gpio_irq_set_type, | |
de4e882f | 254 | .irq_set_wake = atmel_gpio_irq_set_wake, |
77618084 LD |
255 | }; |
256 | ||
89092fb0 | 257 | static void atmel_gpio_irq_handler(struct irq_desc *desc) |
77618084 | 258 | { |
89092fb0 LD |
259 | unsigned int irq = irq_desc_get_irq(desc); |
260 | struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc); | |
77618084 LD |
261 | struct irq_chip *chip = irq_desc_get_chip(desc); |
262 | unsigned long isr; | |
263 | int n, bank = -1; | |
264 | ||
265 | /* Find from which bank is the irq received. */ | |
266 | for (n = 0; n < atmel_pioctrl->nbanks; n++) { | |
267 | if (atmel_pioctrl->irqs[n] == irq) { | |
268 | bank = n; | |
269 | break; | |
270 | } | |
271 | } | |
272 | ||
273 | if (bank < 0) { | |
274 | dev_err(atmel_pioctrl->dev, | |
275 | "no bank associated to irq %u\n", irq); | |
276 | return; | |
277 | } | |
278 | ||
279 | chained_irq_enter(chip, desc); | |
280 | ||
281 | for (;;) { | |
282 | isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, | |
283 | ATMEL_PIO_ISR); | |
284 | isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, | |
285 | ATMEL_PIO_IMR); | |
286 | if (!isr) | |
287 | break; | |
288 | ||
289 | for_each_set_bit(n, &isr, BITS_PER_LONG) | |
290 | generic_handle_irq(gpio_to_irq(bank * | |
291 | ATMEL_PIO_NPINS_PER_BANK + n)); | |
292 | } | |
293 | ||
294 | chained_irq_exit(chip, desc); | |
295 | } | |
296 | ||
297 | static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
298 | { | |
80036f88 | 299 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
300 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
301 | unsigned reg; | |
302 | ||
303 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
304 | BIT(pin->line)); | |
305 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
306 | reg &= ~ATMEL_PIO_DIR_MASK; | |
307 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) | |
313 | { | |
80036f88 | 314 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
315 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
316 | unsigned reg; | |
317 | ||
318 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); | |
319 | ||
320 | return !!(reg & BIT(pin->line)); | |
321 | } | |
322 | ||
323 | static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
324 | int value) | |
325 | { | |
80036f88 | 326 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
327 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
328 | unsigned reg; | |
329 | ||
330 | atmel_gpio_write(atmel_pioctrl, pin->bank, | |
331 | value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, | |
332 | BIT(pin->line)); | |
333 | ||
334 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, | |
335 | BIT(pin->line)); | |
336 | reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); | |
337 | reg |= ATMEL_PIO_DIR_MASK; | |
338 | atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
343 | static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
344 | { | |
80036f88 | 345 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
346 | struct atmel_pin *pin = atmel_pioctrl->pins[offset]; |
347 | ||
348 | atmel_gpio_write(atmel_pioctrl, pin->bank, | |
349 | val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, | |
350 | BIT(pin->line)); | |
351 | } | |
352 | ||
353 | static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
354 | { | |
80036f88 | 355 | struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); |
77618084 LD |
356 | |
357 | return irq_find_mapping(atmel_pioctrl->irq_domain, offset); | |
358 | } | |
359 | ||
360 | static struct gpio_chip atmel_gpio_chip = { | |
361 | .direction_input = atmel_gpio_direction_input, | |
362 | .get = atmel_gpio_get, | |
363 | .direction_output = atmel_gpio_direction_output, | |
364 | .set = atmel_gpio_set, | |
365 | .to_irq = atmel_gpio_to_irq, | |
366 | .base = 0, | |
367 | }; | |
368 | ||
369 | /* --- PINCTRL --- */ | |
370 | static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, | |
371 | unsigned pin_id) | |
372 | { | |
373 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
374 | unsigned bank = atmel_pioctrl->pins[pin_id]->bank; | |
375 | unsigned line = atmel_pioctrl->pins[pin_id]->line; | |
376 | void __iomem *addr = atmel_pioctrl->reg_base | |
377 | + bank * ATMEL_PIO_BANK_OFFSET; | |
378 | ||
379 | writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); | |
380 | /* Have to set MSKR first, to access the right pin CFGR. */ | |
381 | wmb(); | |
382 | ||
383 | return readl_relaxed(addr + ATMEL_PIO_CFGR); | |
384 | } | |
385 | ||
386 | static void atmel_pin_config_write(struct pinctrl_dev *pctldev, | |
387 | unsigned pin_id, u32 conf) | |
388 | { | |
389 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
390 | unsigned bank = atmel_pioctrl->pins[pin_id]->bank; | |
391 | unsigned line = atmel_pioctrl->pins[pin_id]->line; | |
392 | void __iomem *addr = atmel_pioctrl->reg_base | |
393 | + bank * ATMEL_PIO_BANK_OFFSET; | |
394 | ||
395 | writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); | |
396 | /* Have to set MSKR first, to access the right pin CFGR. */ | |
397 | wmb(); | |
398 | writel_relaxed(conf, addr + ATMEL_PIO_CFGR); | |
399 | } | |
400 | ||
401 | static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) | |
402 | { | |
403 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
404 | ||
405 | return atmel_pioctrl->npins; | |
406 | } | |
407 | ||
408 | static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, | |
409 | unsigned selector) | |
410 | { | |
411 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
412 | ||
413 | return atmel_pioctrl->groups[selector].name; | |
414 | } | |
415 | ||
416 | static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, | |
417 | unsigned selector, const unsigned **pins, | |
418 | unsigned *num_pins) | |
419 | { | |
420 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
421 | ||
422 | *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; | |
423 | *num_pins = 1; | |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
682d68b8 BD |
428 | static struct atmel_group * |
429 | atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin) | |
77618084 LD |
430 | { |
431 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
432 | int i; | |
433 | ||
434 | for (i = 0; i < atmel_pioctrl->npins; i++) { | |
435 | struct atmel_group *grp = atmel_pioctrl->groups + i; | |
436 | ||
437 | if (grp->pin == pin) | |
438 | return grp; | |
439 | } | |
440 | ||
441 | return NULL; | |
442 | } | |
443 | ||
444 | static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, | |
445 | struct device_node *np, | |
446 | u32 pinfunc, const char **grp_name, | |
447 | const char **func_name) | |
448 | { | |
449 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
450 | unsigned pin_id, func_id; | |
451 | struct atmel_group *grp; | |
452 | ||
453 | pin_id = ATMEL_GET_PIN_NO(pinfunc); | |
454 | func_id = ATMEL_GET_PIN_FUNC(pinfunc); | |
455 | ||
456 | if (func_id >= ARRAY_SIZE(atmel_functions)) | |
457 | return -EINVAL; | |
458 | ||
459 | *func_name = atmel_functions[func_id]; | |
460 | ||
461 | grp = atmel_pctl_find_group_by_pin(pctldev, pin_id); | |
462 | if (!grp) | |
463 | return -EINVAL; | |
464 | *grp_name = grp->name; | |
465 | ||
466 | atmel_pioctrl->pins[pin_id]->mux = func_id; | |
467 | atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); | |
468 | /* Want the device name not the group one. */ | |
469 | if (np->parent == atmel_pioctrl->node) | |
470 | atmel_pioctrl->pins[pin_id]->device = np->name; | |
471 | else | |
472 | atmel_pioctrl->pins[pin_id]->device = np->parent->name; | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
478 | struct device_node *np, | |
479 | struct pinctrl_map **map, | |
480 | unsigned *reserved_maps, | |
481 | unsigned *num_maps) | |
482 | { | |
483 | unsigned num_pins, num_configs, reserve; | |
484 | unsigned long *configs; | |
485 | struct property *pins; | |
486 | bool has_config; | |
487 | u32 pinfunc; | |
488 | int ret, i; | |
489 | ||
490 | pins = of_find_property(np, "pinmux", NULL); | |
491 | if (!pins) | |
492 | return -EINVAL; | |
493 | ||
494 | ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, | |
495 | &num_configs); | |
496 | if (ret < 0) { | |
f5292d06 RH |
497 | dev_err(pctldev->dev, "%pOF: could not parse node property\n", |
498 | np); | |
77618084 LD |
499 | return ret; |
500 | } | |
501 | ||
502 | if (num_configs) | |
503 | has_config = true; | |
504 | ||
505 | num_pins = pins->length / sizeof(u32); | |
506 | if (!num_pins) { | |
f5292d06 | 507 | dev_err(pctldev->dev, "no pins found in node %pOF\n", np); |
e43d2b75 LD |
508 | ret = -EINVAL; |
509 | goto exit; | |
77618084 LD |
510 | } |
511 | ||
512 | /* | |
513 | * Reserve maps, at least there is a mux map and an optional conf | |
514 | * map for each pin. | |
515 | */ | |
516 | reserve = 1; | |
517 | if (has_config && num_pins >= 1) | |
518 | reserve++; | |
519 | reserve *= num_pins; | |
520 | ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, | |
521 | reserve); | |
522 | if (ret < 0) | |
e43d2b75 | 523 | goto exit; |
77618084 LD |
524 | |
525 | for (i = 0; i < num_pins; i++) { | |
526 | const char *group, *func; | |
527 | ||
528 | ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); | |
529 | if (ret) | |
e43d2b75 | 530 | goto exit; |
77618084 LD |
531 | |
532 | ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, | |
533 | &func); | |
534 | if (ret) | |
e43d2b75 | 535 | goto exit; |
77618084 LD |
536 | |
537 | pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, | |
538 | group, func); | |
539 | ||
540 | if (has_config) { | |
541 | ret = pinctrl_utils_add_map_configs(pctldev, map, | |
542 | reserved_maps, num_maps, group, | |
543 | configs, num_configs, | |
544 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
545 | if (ret < 0) | |
e43d2b75 | 546 | goto exit; |
77618084 LD |
547 | } |
548 | } | |
549 | ||
e43d2b75 LD |
550 | exit: |
551 | kfree(configs); | |
552 | return ret; | |
77618084 LD |
553 | } |
554 | ||
555 | static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
556 | struct device_node *np_config, | |
557 | struct pinctrl_map **map, | |
558 | unsigned *num_maps) | |
559 | { | |
560 | struct device_node *np; | |
561 | unsigned reserved_maps; | |
562 | int ret; | |
563 | ||
564 | *map = NULL; | |
565 | *num_maps = 0; | |
566 | reserved_maps = 0; | |
567 | ||
568 | /* | |
569 | * If all the pins of a device have the same configuration (or no one), | |
570 | * it is useless to add a subnode, so directly parse node referenced by | |
571 | * phandle. | |
572 | */ | |
573 | ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map, | |
574 | &reserved_maps, num_maps); | |
575 | if (ret) { | |
576 | for_each_child_of_node(np_config, np) { | |
577 | ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map, | |
578 | &reserved_maps, num_maps); | |
21816364 JL |
579 | if (ret < 0) { |
580 | of_node_put(np); | |
77618084 | 581 | break; |
21816364 | 582 | } |
77618084 LD |
583 | } |
584 | } | |
585 | ||
586 | if (ret < 0) { | |
d32f7fd3 | 587 | pinctrl_utils_free_map(pctldev, *map, *num_maps); |
f5292d06 RH |
588 | dev_err(pctldev->dev, "can't create maps for node %pOF\n", |
589 | np_config); | |
77618084 LD |
590 | } |
591 | ||
592 | return ret; | |
593 | } | |
594 | ||
595 | static const struct pinctrl_ops atmel_pctlops = { | |
596 | .get_groups_count = atmel_pctl_get_groups_count, | |
597 | .get_group_name = atmel_pctl_get_group_name, | |
598 | .get_group_pins = atmel_pctl_get_group_pins, | |
599 | .dt_node_to_map = atmel_pctl_dt_node_to_map, | |
d32f7fd3 | 600 | .dt_free_map = pinctrl_utils_free_map, |
77618084 LD |
601 | }; |
602 | ||
603 | static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) | |
604 | { | |
605 | return ARRAY_SIZE(atmel_functions); | |
606 | } | |
607 | ||
608 | static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, | |
609 | unsigned selector) | |
610 | { | |
611 | return atmel_functions[selector]; | |
612 | } | |
613 | ||
614 | static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, | |
615 | unsigned selector, | |
616 | const char * const **groups, | |
617 | unsigned * const num_groups) | |
618 | { | |
619 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
620 | ||
621 | *groups = atmel_pioctrl->group_names; | |
622 | *num_groups = atmel_pioctrl->npins; | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, | |
628 | unsigned function, | |
629 | unsigned group) | |
630 | { | |
631 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
632 | unsigned pin; | |
633 | u32 conf; | |
634 | ||
635 | dev_dbg(pctldev->dev, "enable function %s group %s\n", | |
636 | atmel_functions[function], atmel_pioctrl->groups[group].name); | |
637 | ||
638 | pin = atmel_pioctrl->groups[group].pin; | |
639 | conf = atmel_pin_config_read(pctldev, pin); | |
640 | conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); | |
641 | conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK); | |
642 | dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); | |
643 | atmel_pin_config_write(pctldev, pin, conf); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | static const struct pinmux_ops atmel_pmxops = { | |
649 | .get_functions_count = atmel_pmx_get_functions_count, | |
650 | .get_function_name = atmel_pmx_get_function_name, | |
651 | .get_function_groups = atmel_pmx_get_function_groups, | |
652 | .set_mux = atmel_pmx_set_mux, | |
653 | }; | |
654 | ||
655 | static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, | |
656 | unsigned group, | |
657 | unsigned long *config) | |
658 | { | |
659 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
660 | unsigned param = pinconf_to_config_param(*config), arg = 0; | |
661 | struct atmel_group *grp = atmel_pioctrl->groups + group; | |
662 | unsigned pin_id = grp->pin; | |
663 | u32 res; | |
664 | ||
665 | res = atmel_pin_config_read(pctldev, pin_id); | |
666 | ||
667 | switch (param) { | |
668 | case PIN_CONFIG_BIAS_PULL_UP: | |
669 | if (!(res & ATMEL_PIO_PUEN_MASK)) | |
670 | return -EINVAL; | |
671 | arg = 1; | |
672 | break; | |
673 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
674 | if ((res & ATMEL_PIO_PUEN_MASK) || | |
675 | (!(res & ATMEL_PIO_PDEN_MASK))) | |
676 | return -EINVAL; | |
677 | arg = 1; | |
678 | break; | |
679 | case PIN_CONFIG_BIAS_DISABLE: | |
680 | if ((res & ATMEL_PIO_PUEN_MASK) || | |
681 | ((res & ATMEL_PIO_PDEN_MASK))) | |
682 | return -EINVAL; | |
683 | arg = 1; | |
684 | break; | |
685 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
686 | if (!(res & ATMEL_PIO_OPD_MASK)) | |
687 | return -EINVAL; | |
688 | arg = 1; | |
689 | break; | |
690 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
691 | if (!(res & ATMEL_PIO_SCHMITT_MASK)) | |
692 | return -EINVAL; | |
693 | arg = 1; | |
694 | break; | |
695 | default: | |
696 | return -ENOTSUPP; | |
697 | } | |
698 | ||
699 | *config = pinconf_to_config_packed(param, arg); | |
700 | return 0; | |
701 | } | |
702 | ||
703 | static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, | |
704 | unsigned group, | |
705 | unsigned long *configs, | |
706 | unsigned num_configs) | |
707 | { | |
708 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
709 | struct atmel_group *grp = atmel_pioctrl->groups + group; | |
710 | unsigned bank, pin, pin_id = grp->pin; | |
711 | u32 mask, conf = 0; | |
712 | int i; | |
713 | ||
714 | conf = atmel_pin_config_read(pctldev, pin_id); | |
715 | ||
716 | for (i = 0; i < num_configs; i++) { | |
717 | unsigned param = pinconf_to_config_param(configs[i]); | |
718 | unsigned arg = pinconf_to_config_argument(configs[i]); | |
719 | ||
720 | dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", | |
721 | __func__, pin_id, configs[i]); | |
722 | ||
723 | switch (param) { | |
724 | case PIN_CONFIG_BIAS_DISABLE: | |
725 | conf &= (~ATMEL_PIO_PUEN_MASK); | |
726 | conf &= (~ATMEL_PIO_PDEN_MASK); | |
727 | break; | |
728 | case PIN_CONFIG_BIAS_PULL_UP: | |
729 | conf |= ATMEL_PIO_PUEN_MASK; | |
5305a7b7 | 730 | conf &= (~ATMEL_PIO_PDEN_MASK); |
77618084 LD |
731 | break; |
732 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
733 | conf |= ATMEL_PIO_PDEN_MASK; | |
5305a7b7 | 734 | conf &= (~ATMEL_PIO_PUEN_MASK); |
77618084 LD |
735 | break; |
736 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
737 | if (arg == 0) | |
738 | conf &= (~ATMEL_PIO_OPD_MASK); | |
739 | else | |
740 | conf |= ATMEL_PIO_OPD_MASK; | |
741 | break; | |
742 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
743 | if (arg == 0) | |
744 | conf |= ATMEL_PIO_SCHMITT_MASK; | |
745 | else | |
746 | conf &= (~ATMEL_PIO_SCHMITT_MASK); | |
747 | break; | |
748 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
749 | if (arg == 0) { | |
750 | conf &= (~ATMEL_PIO_IFEN_MASK); | |
751 | conf &= (~ATMEL_PIO_IFSCEN_MASK); | |
752 | } else { | |
753 | /* | |
754 | * We don't care about the debounce value for several reasons: | |
755 | * - can't have different debounce periods inside a same group, | |
756 | * - the register to configure this period is a secure register. | |
757 | * The debouncing filter can filter a pulse with a duration of less | |
758 | * than 1/2 slow clock period. | |
759 | */ | |
760 | conf |= ATMEL_PIO_IFEN_MASK; | |
761 | conf |= ATMEL_PIO_IFSCEN_MASK; | |
762 | } | |
763 | break; | |
764 | case PIN_CONFIG_OUTPUT: | |
765 | conf |= ATMEL_PIO_DIR_MASK; | |
766 | bank = ATMEL_PIO_BANK(pin_id); | |
767 | pin = ATMEL_PIO_LINE(pin_id); | |
768 | mask = 1 << pin; | |
769 | ||
770 | if (arg == 0) { | |
771 | writel_relaxed(mask, atmel_pioctrl->reg_base + | |
772 | bank * ATMEL_PIO_BANK_OFFSET + | |
773 | ATMEL_PIO_CODR); | |
774 | } else { | |
775 | writel_relaxed(mask, atmel_pioctrl->reg_base + | |
776 | bank * ATMEL_PIO_BANK_OFFSET + | |
777 | ATMEL_PIO_SODR); | |
778 | } | |
779 | break; | |
780 | default: | |
781 | dev_warn(pctldev->dev, | |
782 | "unsupported configuration parameter: %u\n", | |
783 | param); | |
784 | continue; | |
785 | } | |
786 | } | |
787 | ||
788 | dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); | |
789 | atmel_pin_config_write(pctldev, pin_id, conf); | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
794 | static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, | |
795 | struct seq_file *s, unsigned pin_id) | |
796 | { | |
797 | struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); | |
798 | u32 conf; | |
799 | ||
800 | if (!atmel_pioctrl->pins[pin_id]->device) | |
801 | return; | |
802 | ||
803 | if (atmel_pioctrl->pins[pin_id]) | |
804 | seq_printf(s, " (%s, ioset %u) ", | |
805 | atmel_pioctrl->pins[pin_id]->device, | |
806 | atmel_pioctrl->pins[pin_id]->ioset); | |
807 | ||
808 | conf = atmel_pin_config_read(pctldev, pin_id); | |
809 | if (conf & ATMEL_PIO_PUEN_MASK) | |
810 | seq_printf(s, "%s ", "pull-up"); | |
811 | if (conf & ATMEL_PIO_PDEN_MASK) | |
812 | seq_printf(s, "%s ", "pull-down"); | |
813 | if (conf & ATMEL_PIO_IFEN_MASK) | |
814 | seq_printf(s, "%s ", "debounce"); | |
815 | if (conf & ATMEL_PIO_OPD_MASK) | |
816 | seq_printf(s, "%s ", "open-drain"); | |
817 | if (conf & ATMEL_PIO_SCHMITT_MASK) | |
818 | seq_printf(s, "%s ", "schmitt"); | |
819 | } | |
820 | ||
821 | static const struct pinconf_ops atmel_confops = { | |
822 | .pin_config_group_get = atmel_conf_pin_config_group_get, | |
823 | .pin_config_group_set = atmel_conf_pin_config_group_set, | |
824 | .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, | |
825 | }; | |
826 | ||
827 | static struct pinctrl_desc atmel_pinctrl_desc = { | |
828 | .name = "atmel_pinctrl", | |
829 | .confops = &atmel_confops, | |
830 | .pctlops = &atmel_pctlops, | |
831 | .pmxops = &atmel_pmxops, | |
832 | }; | |
833 | ||
6be2a3a0 | 834 | static int __maybe_unused atmel_pctrl_suspend(struct device *dev) |
de4e882f LD |
835 | { |
836 | struct platform_device *pdev = to_platform_device(dev); | |
837 | struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); | |
ba9e7f27 | 838 | int i, j; |
de4e882f LD |
839 | |
840 | /* | |
841 | * For each bank, save IMR to restore it later and disable all GPIO | |
842 | * interrupts excepting the ones marked as wakeup sources. | |
843 | */ | |
844 | for (i = 0; i < atmel_pioctrl->nbanks; i++) { | |
ba9e7f27 | 845 | atmel_pioctrl->pm_suspend_backup[i].imr = |
de4e882f LD |
846 | atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR); |
847 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR, | |
848 | ~atmel_pioctrl->pm_wakeup_sources[i]); | |
ba9e7f27 AB |
849 | atmel_pioctrl->pm_suspend_backup[i].odsr = |
850 | atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR); | |
851 | for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { | |
852 | atmel_gpio_write(atmel_pioctrl, i, | |
853 | ATMEL_PIO_MSKR, BIT(j)); | |
854 | atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = | |
855 | atmel_gpio_read(atmel_pioctrl, i, | |
856 | ATMEL_PIO_CFGR); | |
857 | } | |
de4e882f LD |
858 | } |
859 | ||
860 | return 0; | |
861 | } | |
862 | ||
6be2a3a0 | 863 | static int __maybe_unused atmel_pctrl_resume(struct device *dev) |
de4e882f LD |
864 | { |
865 | struct platform_device *pdev = to_platform_device(dev); | |
866 | struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); | |
ba9e7f27 | 867 | int i, j; |
de4e882f | 868 | |
ba9e7f27 | 869 | for (i = 0; i < atmel_pioctrl->nbanks; i++) { |
de4e882f | 870 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER, |
ba9e7f27 AB |
871 | atmel_pioctrl->pm_suspend_backup[i].imr); |
872 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR, | |
873 | atmel_pioctrl->pm_suspend_backup[i].odsr); | |
874 | for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { | |
875 | atmel_gpio_write(atmel_pioctrl, i, | |
876 | ATMEL_PIO_MSKR, BIT(j)); | |
877 | atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR, | |
878 | atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); | |
879 | } | |
880 | } | |
de4e882f LD |
881 | |
882 | return 0; | |
883 | } | |
884 | ||
885 | static const struct dev_pm_ops atmel_pctrl_pm_ops = { | |
886 | SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume) | |
887 | }; | |
888 | ||
77618084 LD |
889 | /* |
890 | * The number of banks can be different from a SoC to another one. | |
891 | * We can have up to 16 banks. | |
892 | */ | |
893 | static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { | |
894 | .nbanks = 4, | |
895 | }; | |
896 | ||
897 | static const struct of_device_id atmel_pctrl_of_match[] = { | |
898 | { | |
899 | .compatible = "atmel,sama5d2-pinctrl", | |
900 | .data = &atmel_sama5d2_pioctrl_data, | |
901 | }, { | |
902 | /* sentinel */ | |
903 | } | |
904 | }; | |
77618084 LD |
905 | |
906 | static int atmel_pinctrl_probe(struct platform_device *pdev) | |
907 | { | |
908 | struct device *dev = &pdev->dev; | |
909 | struct pinctrl_pin_desc *pin_desc; | |
910 | const char **group_names; | |
911 | const struct of_device_id *match; | |
912 | int i, ret; | |
913 | struct resource *res; | |
914 | struct atmel_pioctrl *atmel_pioctrl; | |
8b74c7d3 | 915 | const struct atmel_pioctrl_data *atmel_pioctrl_data; |
77618084 LD |
916 | |
917 | atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); | |
918 | if (!atmel_pioctrl) | |
919 | return -ENOMEM; | |
920 | atmel_pioctrl->dev = dev; | |
921 | atmel_pioctrl->node = dev->of_node; | |
922 | platform_set_drvdata(pdev, atmel_pioctrl); | |
923 | ||
924 | match = of_match_node(atmel_pctrl_of_match, dev->of_node); | |
925 | if (!match) { | |
926 | dev_err(dev, "unknown compatible string\n"); | |
927 | return -ENODEV; | |
928 | } | |
8b74c7d3 | 929 | atmel_pioctrl_data = match->data; |
77618084 LD |
930 | atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; |
931 | atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; | |
932 | ||
933 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
934 | if (!res) { | |
935 | dev_err(dev, "unable to get atmel pinctrl resource\n"); | |
936 | return -EINVAL; | |
937 | } | |
938 | atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res); | |
939 | if (IS_ERR(atmel_pioctrl->reg_base)) | |
940 | return -EINVAL; | |
941 | ||
942 | atmel_pioctrl->clk = devm_clk_get(dev, NULL); | |
943 | if (IS_ERR(atmel_pioctrl->clk)) { | |
944 | dev_err(dev, "failed to get clock\n"); | |
945 | return PTR_ERR(atmel_pioctrl->clk); | |
946 | } | |
947 | ||
948 | atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins) | |
949 | * atmel_pioctrl->npins, GFP_KERNEL); | |
950 | if (!atmel_pioctrl->pins) | |
951 | return -ENOMEM; | |
952 | ||
953 | pin_desc = devm_kzalloc(dev, sizeof(*pin_desc) | |
954 | * atmel_pioctrl->npins, GFP_KERNEL); | |
955 | if (!pin_desc) | |
956 | return -ENOMEM; | |
957 | atmel_pinctrl_desc.pins = pin_desc; | |
958 | atmel_pinctrl_desc.npins = atmel_pioctrl->npins; | |
959 | ||
960 | /* One pin is one group since a pin can achieve all functions. */ | |
961 | group_names = devm_kzalloc(dev, sizeof(*group_names) | |
962 | * atmel_pioctrl->npins, GFP_KERNEL); | |
963 | if (!group_names) | |
964 | return -ENOMEM; | |
965 | atmel_pioctrl->group_names = group_names; | |
966 | ||
967 | atmel_pioctrl->groups = devm_kzalloc(&pdev->dev, | |
968 | sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins, | |
969 | GFP_KERNEL); | |
970 | if (!atmel_pioctrl->groups) | |
971 | return -ENOMEM; | |
972 | for (i = 0 ; i < atmel_pioctrl->npins; i++) { | |
973 | struct atmel_group *group = atmel_pioctrl->groups + i; | |
974 | unsigned bank = ATMEL_PIO_BANK(i); | |
975 | unsigned line = ATMEL_PIO_LINE(i); | |
976 | ||
977 | atmel_pioctrl->pins[i] = devm_kzalloc(dev, | |
978 | sizeof(**atmel_pioctrl->pins), GFP_KERNEL); | |
979 | if (!atmel_pioctrl->pins[i]) | |
980 | return -ENOMEM; | |
981 | ||
982 | atmel_pioctrl->pins[i]->pin_id = i; | |
983 | atmel_pioctrl->pins[i]->bank = bank; | |
984 | atmel_pioctrl->pins[i]->line = line; | |
985 | ||
986 | pin_desc[i].number = i; | |
987 | /* Pin naming convention: P(bank_name)(bank_pin_number). */ | |
988 | pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", | |
989 | bank + 'A', line); | |
990 | ||
991 | group->name = group_names[i] = pin_desc[i].name; | |
992 | group->pin = pin_desc[i].number; | |
993 | ||
994 | dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); | |
995 | } | |
996 | ||
997 | atmel_pioctrl->gpio_chip = &atmel_gpio_chip; | |
998 | atmel_pioctrl->gpio_chip->of_node = dev->of_node; | |
999 | atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; | |
1000 | atmel_pioctrl->gpio_chip->label = dev_name(dev); | |
58383c78 | 1001 | atmel_pioctrl->gpio_chip->parent = dev; |
77618084 LD |
1002 | atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; |
1003 | ||
de4e882f LD |
1004 | atmel_pioctrl->pm_wakeup_sources = devm_kzalloc(dev, |
1005 | sizeof(*atmel_pioctrl->pm_wakeup_sources) | |
1006 | * atmel_pioctrl->nbanks, GFP_KERNEL); | |
1007 | if (!atmel_pioctrl->pm_wakeup_sources) | |
1008 | return -ENOMEM; | |
1009 | ||
1010 | atmel_pioctrl->pm_suspend_backup = devm_kzalloc(dev, | |
1011 | sizeof(*atmel_pioctrl->pm_suspend_backup) | |
1012 | * atmel_pioctrl->nbanks, GFP_KERNEL); | |
1013 | if (!atmel_pioctrl->pm_suspend_backup) | |
1014 | return -ENOMEM; | |
1015 | ||
77618084 LD |
1016 | atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs) |
1017 | * atmel_pioctrl->nbanks, GFP_KERNEL); | |
1018 | if (!atmel_pioctrl->irqs) | |
1019 | return -ENOMEM; | |
1020 | ||
1021 | /* There is one controller but each bank has its own irq line. */ | |
1022 | for (i = 0; i < atmel_pioctrl->nbanks; i++) { | |
1023 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); | |
1024 | if (!res) { | |
1025 | dev_err(dev, "missing irq resource for group %c\n", | |
1026 | 'A' + i); | |
1027 | return -EINVAL; | |
1028 | } | |
1029 | atmel_pioctrl->irqs[i] = res->start; | |
1030 | irq_set_chained_handler(res->start, atmel_gpio_irq_handler); | |
1031 | irq_set_handler_data(res->start, atmel_pioctrl); | |
32844138 | 1032 | dev_dbg(dev, "bank %i: irq=%pr\n", i, res); |
77618084 LD |
1033 | } |
1034 | ||
1035 | atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, | |
1036 | atmel_pioctrl->gpio_chip->ngpio, | |
1037 | &irq_domain_simple_ops, NULL); | |
1038 | if (!atmel_pioctrl->irq_domain) { | |
1039 | dev_err(dev, "can't add the irq domain\n"); | |
1040 | return -ENODEV; | |
1041 | } | |
1042 | atmel_pioctrl->irq_domain->name = "atmel gpio"; | |
1043 | ||
1044 | for (i = 0; i < atmel_pioctrl->npins; i++) { | |
1045 | int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); | |
1046 | ||
1047 | irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip, | |
1048 | handle_simple_irq); | |
1049 | irq_set_chip_data(irq, atmel_pioctrl); | |
1050 | dev_dbg(dev, | |
1051 | "atmel gpio irq domain: hwirq: %d, linux irq: %d\n", | |
1052 | i, irq); | |
1053 | } | |
1054 | ||
1055 | ret = clk_prepare_enable(atmel_pioctrl->clk); | |
1056 | if (ret) { | |
1057 | dev_err(dev, "failed to prepare and enable clock\n"); | |
1058 | goto clk_prepare_enable_error; | |
1059 | } | |
1060 | ||
5d3fc884 LD |
1061 | atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev, |
1062 | &atmel_pinctrl_desc, | |
1063 | atmel_pioctrl); | |
1064 | if (IS_ERR(atmel_pioctrl->pinctrl_dev)) { | |
1065 | ret = PTR_ERR(atmel_pioctrl->pinctrl_dev); | |
77618084 | 1066 | dev_err(dev, "pinctrl registration failed\n"); |
5d3fc884 | 1067 | goto clk_unprep; |
77618084 LD |
1068 | } |
1069 | ||
80036f88 | 1070 | ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl); |
77618084 LD |
1071 | if (ret) { |
1072 | dev_err(dev, "failed to add gpiochip\n"); | |
5d3fc884 | 1073 | goto clk_unprep; |
77618084 LD |
1074 | } |
1075 | ||
1076 | ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), | |
1077 | 0, 0, atmel_pioctrl->gpio_chip->ngpio); | |
1078 | if (ret) { | |
1079 | dev_err(dev, "failed to add gpio pin range\n"); | |
1080 | goto gpiochip_add_pin_range_error; | |
1081 | } | |
1082 | ||
1083 | dev_info(&pdev->dev, "atmel pinctrl initialized\n"); | |
1084 | ||
1085 | return 0; | |
1086 | ||
77618084 LD |
1087 | gpiochip_add_pin_range_error: |
1088 | gpiochip_remove(atmel_pioctrl->gpio_chip); | |
1089 | ||
5d3fc884 LD |
1090 | clk_unprep: |
1091 | clk_disable_unprepare(atmel_pioctrl->clk); | |
1092 | ||
1093 | clk_prepare_enable_error: | |
1094 | irq_domain_remove(atmel_pioctrl->irq_domain); | |
1095 | ||
77618084 LD |
1096 | return ret; |
1097 | } | |
1098 | ||
77618084 LD |
1099 | static struct platform_driver atmel_pinctrl_driver = { |
1100 | .driver = { | |
1101 | .name = "pinctrl-at91-pio4", | |
1102 | .of_match_table = atmel_pctrl_of_match, | |
de4e882f | 1103 | .pm = &atmel_pctrl_pm_ops, |
f703851a | 1104 | .suppress_bind_attrs = true, |
77618084 LD |
1105 | }, |
1106 | .probe = atmel_pinctrl_probe, | |
77618084 | 1107 | }; |
f703851a | 1108 | builtin_platform_driver(atmel_pinctrl_driver); |