[linux-block.git] / drivers / pinctrl / pinctrl-apple-gpio.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Apple SoC pinctrl+GPIO+external IRQ driver
 *
 * Copyright (C) The Asahi Linux Contributors
 * Copyright (C) 2020 Corellium LLC
 *
 * Based on: pinctrl-pistachio.c
 * Copyright (C) 2014 Imagination Technologies Ltd.
 * Copyright (C) 2014 Google, Inc.
 */

#include <dt-bindings/pinctrl/apple.h>
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#include "pinctrl-utils.h"
#include "core.h"
#include "pinmux.h"

struct apple_gpio_pinctrl {
	struct device *dev;
	struct pinctrl_dev *pctldev;

	void __iomem *base;
	struct regmap *map;

	struct pinctrl_desc pinctrl_desc;
	struct gpio_chip gpio_chip;
	u8 irqgrps[];
};

#define REG_GPIO(x)          (4 * (x))
#define REG_GPIOx_DATA       BIT(0)
#define REG_GPIOx_MODE       GENMASK(3, 1)
#define REG_GPIOx_OUT        1
#define REG_GPIOx_IN_IRQ_HI  2
#define REG_GPIOx_IN_IRQ_LO  3
#define REG_GPIOx_IN_IRQ_UP  4
#define REG_GPIOx_IN_IRQ_DN  5
#define REG_GPIOx_IN_IRQ_ANY 6
#define REG_GPIOx_IN_IRQ_OFF 7
#define REG_GPIOx_PERIPH     GENMASK(6, 5)
#define REG_GPIOx_PULL       GENMASK(8, 7)
#define REG_GPIOx_PULL_OFF   0
#define REG_GPIOx_PULL_DOWN  1
#define REG_GPIOx_PULL_UP_STRONG 2
#define REG_GPIOx_PULL_UP    3
#define REG_GPIOx_INPUT_ENABLE BIT(9)
#define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10)
#define REG_GPIOx_SCHMITT    BIT(15)
#define REG_GPIOx_GRP        GENMASK(18, 16)
#define REG_GPIOx_LOCK       BIT(21)
#define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
#define REG_IRQ(g, x)        (0x800 + 0x40 * (g) + 4 * ((x) >> 5))

struct regmap_config regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.cache_type = REGCACHE_FLAT,
	.max_register = 512 * sizeof(u32),
	.num_reg_defaults_raw = 512,
	.use_relaxed_mmio = true,
	.use_raw_spinlock = true,
};

/* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
                               unsigned int pin, u32 mask, u32 value)
{
	regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
}

static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
                              unsigned int pin)
{
	int ret;
	u32 val;

	ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
	if (ret)
		return 0;

	return val;
}

/* Pin controller functions */

static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
                                     struct device_node *node,
                                     struct pinctrl_map **map,
                                     unsigned *num_maps)
{
	unsigned reserved_maps;
	struct apple_gpio_pinctrl *pctl;
	u32 pinfunc, pin, func;
	int num_pins, i, ret;
	const char *group_name;
	const char *function_name;

	*map = NULL;
	*num_maps = 0;
	reserved_maps = 0;

	pctl = pinctrl_dev_get_drvdata(pctldev);

	ret = of_property_count_u32_elems(node, "pinmux");
	if (ret <= 0) {
		dev_err(pctl->dev,
			"missing or empty pinmux property in node %pOFn.\n",
			node);
		return ret ? ret : -EINVAL;
	}

	num_pins = ret;

	ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins);
	if (ret)
		return ret;

	for (i = 0; i < num_pins; i++) {
		ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
		if (ret)
			goto free_map;

		pin = APPLE_PIN(pinfunc);
		func = APPLE_FUNC(pinfunc);

		if (func >= pinmux_generic_get_function_count(pctldev)) {
			ret = -EINVAL;
			goto free_map;
		}

		group_name = pinctrl_generic_get_group_name(pctldev, pin);
		function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
		ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
		                                &reserved_maps, num_maps,
		                                group_name, function_name);
		if (ret)
			goto free_map;
	}

free_map:
	if (ret < 0)
		pinctrl_utils_free_map(pctldev, *map, *num_maps);

	return ret;
}

static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
	.get_groups_count = pinctrl_generic_get_group_count,
	.get_group_name = pinctrl_generic_get_group_name,
	.get_group_pins = pinctrl_generic_get_group_pins,
	.dt_node_to_map = apple_gpio_dt_node_to_map,
	.dt_free_map = pinctrl_utils_free_map,
};

/* Pin multiplexer functions */

static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
                                 unsigned group)
{
	struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);

	apple_gpio_set_reg(
		pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE,
		FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE);

	return 0;
}

static const struct pinmux_ops apple_gpio_pinmux_ops = {
	.get_functions_count = pinmux_generic_get_function_count,
	.get_function_name = pinmux_generic_get_function_name,
	.get_function_groups = pinmux_generic_get_function_groups,
	.set_mux = apple_gpio_pinmux_set,
	.strict = true,
};

/* GPIO chip functions */

static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
	unsigned int reg = apple_gpio_get_reg(pctl, offset);

	if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT)
		return GPIO_LINE_DIRECTION_OUT;
	return GPIO_LINE_DIRECTION_IN;
}

static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
	unsigned int reg = apple_gpio_get_reg(pctl, offset);

	/*
	 * If this is an input GPIO, read the actual value (not the
	 * cached regmap value)
	 */
	if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT)
		reg = readl_relaxed(pctl->base + REG_GPIO(offset));

	return !!(reg & REG_GPIOx_DATA);
}

static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);

	apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
}

static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);

	apple_gpio_set_reg(pctl, offset,
			   REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA |
				   REG_GPIOx_INPUT_ENABLE,
			   FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) |
				   REG_GPIOx_INPUT_ENABLE);
	return 0;
}

static int apple_gpio_direction_output(struct gpio_chip *chip,
                                       unsigned int offset, int value)
{
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);

	apple_gpio_set_reg(pctl, offset,
			   REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA,
			   FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) |
				   (value ? REG_GPIOx_DATA : 0));
	return 0;
}

/* IRQ chip functions */

static void apple_gpio_irq_ack(struct irq_data *data)
{
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
	unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));

	writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
}

static unsigned int apple_gpio_irq_type(unsigned int type)
{
	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		return REG_GPIOx_IN_IRQ_UP;
	case IRQ_TYPE_EDGE_FALLING:
		return REG_GPIOx_IN_IRQ_DN;
	case IRQ_TYPE_EDGE_BOTH:
		return REG_GPIOx_IN_IRQ_ANY;
	case IRQ_TYPE_LEVEL_HIGH:
		return REG_GPIOx_IN_IRQ_HI;
	case IRQ_TYPE_LEVEL_LOW:
		return REG_GPIOx_IN_IRQ_LO;
	default:
		return REG_GPIOx_IN_IRQ_OFF;
	}
}

static void apple_gpio_irq_mask(struct irq_data *data)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);

	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
	                   FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
	gpiochip_disable_irq(gc, data->hwirq);
}

static void apple_gpio_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
	unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));

	gpiochip_enable_irq(gc, data->hwirq);
	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
	                   FIELD_PREP(REG_GPIOx_MODE, irqtype));
}

static unsigned int apple_gpio_irq_startup(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);

	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
	                   FIELD_PREP(REG_GPIOx_GRP, 0));

	apple_gpio_direction_input(chip, data->hwirq);
	apple_gpio_irq_unmask(data);

	return 0;
}

static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
	unsigned int irqtype = apple_gpio_irq_type(type);

	if (irqtype == REG_GPIOx_IN_IRQ_OFF)
		return -EINVAL;

	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
	                   FIELD_PREP(REG_GPIOx_MODE, irqtype));

	if (type & IRQ_TYPE_LEVEL_MASK)
		irq_set_handler_locked(data, handle_level_irq);
	else
		irq_set_handler_locked(data, handle_edge_irq);
	return 0;
}

static void apple_gpio_irq_handler(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	u8 *grpp = irq_desc_get_handler_data(desc);
	struct apple_gpio_pinctrl *pctl;
	unsigned int pinh, pinl;
	unsigned long pending;
	struct gpio_chip *gc;

	pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]);
	gc = &pctl->gpio_chip;

	chained_irq_enter(chip, desc);
	for (pinh = 0; pinh < gc->ngpio; pinh += 32) {
		pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh));
		for_each_set_bit(pinl, &pending, 32)
			generic_handle_domain_irq(gc->irq.domain, pinh + pinl);
	}
	chained_irq_exit(chip, desc);
}

static const struct irq_chip apple_gpio_irqchip = {
	.name			= "Apple-GPIO",
	.irq_startup		= apple_gpio_irq_startup,
	.irq_ack		= apple_gpio_irq_ack,
	.irq_mask		= apple_gpio_irq_mask,
	.irq_unmask		= apple_gpio_irq_unmask,
	.irq_set_type		= apple_gpio_irq_set_type,
	.flags			= IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

/* Probe & register */

static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
{
	struct gpio_irq_chip *girq = &pctl->gpio_chip.irq;
	void **irq_data = NULL;
	int ret;

	pctl->gpio_chip.label = dev_name(pctl->dev);
	pctl->gpio_chip.request = gpiochip_generic_request;
	pctl->gpio_chip.free = gpiochip_generic_free;
	pctl->gpio_chip.get_direction = apple_gpio_get_direction;
	pctl->gpio_chip.direction_input = apple_gpio_direction_input;
	pctl->gpio_chip.direction_output = apple_gpio_direction_output;
	pctl->gpio_chip.get = apple_gpio_get;
	pctl->gpio_chip.set = apple_gpio_set;
	pctl->gpio_chip.base = -1;
	pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
	pctl->gpio_chip.parent = pctl->dev;

	if (girq->num_parents) {
		int i;

		gpio_irq_chip_set_chip(girq, &apple_gpio_irqchip);
		girq->parent_handler = apple_gpio_irq_handler;

		girq->parents = kmalloc_array(girq->num_parents,
					      sizeof(*girq->parents),
					      GFP_KERNEL);
		irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data),
					 GFP_KERNEL);
		if (!girq->parents || !irq_data) {
			ret = -ENOMEM;
			goto out_free_irq_data;
		}

		for (i = 0; i < girq->num_parents; i++) {
			ret = platform_get_irq(to_platform_device(pctl->dev), i);
			if (ret < 0)
				goto out_free_irq_data;

			girq->parents[i] = ret;
			pctl->irqgrps[i] = i;
			irq_data[i] = &pctl->irqgrps[i];
		}

		girq->parent_handler_data_array = irq_data;
		girq->per_parent_data = true;
		girq->default_type = IRQ_TYPE_NONE;
		girq->handler = handle_level_irq;
	}

	ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);

out_free_irq_data:
	kfree(girq->parents);
	kfree(irq_data);

	return ret;
}

static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
{
	struct apple_gpio_pinctrl *pctl;
	struct pinctrl_pin_desc *pins;
	unsigned int npins;
	const char **pin_names;
	unsigned int *pin_nums;
	static const char* pinmux_functions[] = {
		"gpio", "periph1", "periph2", "periph3"
	};
	unsigned int i, nirqs = 0;
	int res;

	if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
		res = platform_irq_count(pdev);
		if (res > 0)
			nirqs = res;
	}

	pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs),
			    GFP_KERNEL);
	if (!pctl)
		return -ENOMEM;
	pctl->dev = &pdev->dev;
	pctl->gpio_chip.irq.num_parents = nirqs;
	dev_set_drvdata(&pdev->dev, pctl);

	if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins))
		return dev_err_probe(&pdev->dev, -EINVAL,
				     "apple,npins property not found\n");

	pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]),
				  GFP_KERNEL);
	pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]),
				       GFP_KERNEL);
	pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]),
				      GFP_KERNEL);
	if (!pins || !pin_names || !pin_nums)
		return -ENOMEM;

	pctl->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pctl->base))
		return PTR_ERR(pctl->base);

	pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, &regmap_config);
	if (IS_ERR(pctl->map))
		return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map),
				     "Failed to create regmap\n");

	for (i = 0; i < npins; i++) {
		pins[i].number = i;
		pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i);
		pins[i].drv_data = pctl;
		pin_names[i] = pins[i].name;
		pin_nums[i] = i;
	}

	pctl->pinctrl_desc.name = dev_name(pctl->dev);
	pctl->pinctrl_desc.pins = pins;
	pctl->pinctrl_desc.npins = npins;
	pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops;
	pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops;

	pctl->pctldev =	devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl);
	if (IS_ERR(pctl->pctldev))
		return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev),
				     "Failed to register pinctrl device.\n");

	for (i = 0; i < npins; i++) {
		res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name,
						pin_nums + i, 1, pctl);
		if (res < 0)
			return dev_err_probe(pctl->dev, res,
					     "Failed to register group");
	}

	for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) {
		res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i],
						  pin_names, npins, pctl);
		if (res < 0)
			return dev_err_probe(pctl->dev, res,
					     "Failed to register function.");
	}

	return apple_gpio_register(pctl);
}

static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
	{ .compatible = "apple,pinctrl", },
	{ }
};
MODULE_DEVICE_TABLE(of, apple_gpio_pinctrl_of_match);

static struct platform_driver apple_gpio_pinctrl_driver = {
	.driver = {
		.name = "apple-gpio-pinctrl",
		.of_match_table = apple_gpio_pinctrl_of_match,
		.suppress_bind_attrs = true,
	},
	.probe = apple_gpio_pinctrl_probe,
};
module_platform_driver(apple_gpio_pinctrl_driver);

MODULE_DESCRIPTION("Apple pinctrl/GPIO driver");
MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>");
MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a0f160ff JG	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Apple SoC pinctrl+GPIO+external IRQ driver
	4	*
	5	* Copyright (C) The Asahi Linux Contributors
	6	* Copyright (C) 2020 Corellium LLC
	7	*
	8	* Based on: pinctrl-pistachio.c
	9	* Copyright (C) 2014 Imagination Technologies Ltd.
	10	* Copyright (C) 2014 Google, Inc.
	11	*/
	12
	13	#include <dt-bindings/pinctrl/apple.h>
7c06f080	14	#include <linux/bits.h>
a0f160ff JG	15	#include <linux/gpio/driver.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_irq.h>
	21	#include <linux/pinctrl/pinctrl.h>
	22	#include <linux/pinctrl/pinmux.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/regmap.h>
	25
	26	#include "pinctrl-utils.h"
	27	#include "core.h"
	28	#include "pinmux.h"
	29
	30	struct apple_gpio_pinctrl {
	31	struct device *dev;
	32	struct pinctrl_dev *pctldev;
	33
	34	void __iomem *base;
	35	struct regmap *map;
	36
	37	struct pinctrl_desc pinctrl_desc;
	38	struct gpio_chip gpio_chip;
f3e3e637	39	u8 irqgrps[];
a0f160ff JG	40	};
	41
	42	#define REG_GPIO(x) (4 * (x))
	43	#define REG_GPIOx_DATA BIT(0)
	44	#define REG_GPIOx_MODE GENMASK(3, 1)
	45	#define REG_GPIOx_OUT 1
	46	#define REG_GPIOx_IN_IRQ_HI 2
	47	#define REG_GPIOx_IN_IRQ_LO 3
	48	#define REG_GPIOx_IN_IRQ_UP 4
	49	#define REG_GPIOx_IN_IRQ_DN 5
	50	#define REG_GPIOx_IN_IRQ_ANY 6
	51	#define REG_GPIOx_IN_IRQ_OFF 7
	52	#define REG_GPIOx_PERIPH GENMASK(6, 5)
	53	#define REG_GPIOx_PULL GENMASK(8, 7)
	54	#define REG_GPIOx_PULL_OFF 0
	55	#define REG_GPIOx_PULL_DOWN 1
	56	#define REG_GPIOx_PULL_UP_STRONG 2
	57	#define REG_GPIOx_PULL_UP 3
	58	#define REG_GPIOx_INPUT_ENABLE BIT(9)
	59	#define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10)
	60	#define REG_GPIOx_SCHMITT BIT(15)
	61	#define REG_GPIOx_GRP GENMASK(18, 16)
	62	#define REG_GPIOx_LOCK BIT(21)
	63	#define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
	64	#define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5))
	65
	66	struct regmap_config regmap_config = {
	67	.reg_bits = 32,
	68	.val_bits = 32,
	69	.reg_stride = 4,
	70	.cache_type = REGCACHE_FLAT,
	71	.max_register = 512 * sizeof(u32),
	72	.num_reg_defaults_raw = 512,
5ad6973d	73	.use_relaxed_mmio = true,
83969805	74	.use_raw_spinlock = true,
a0f160ff JG	75	};
a0f160ff JG	76
67a6c281	77	/* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
a0f160ff	78	static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
361856dd	79	unsigned int pin, u32 mask, u32 value)
a0f160ff JG	80	{
	81	regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
	82	}
	83
3605f104	84	static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
361856dd	85	unsigned int pin)
a0f160ff	86	{
3605f104 JG	87	int ret;
	88	u32 val;
	89
	90	ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
	91	if (ret)
	92	return 0;
a0f160ff	93
a0f160ff JG	94	return val;
	95	}
	96
	97	/* Pin controller functions */
	98
	99	static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
361856dd JG	100	struct device_node *node,
	101	struct pinctrl_map **map,
	102	unsigned *num_maps)
a0f160ff JG	103	{
	104	unsigned reserved_maps;
	105	struct apple_gpio_pinctrl *pctl;
	106	u32 pinfunc, pin, func;
	107	int num_pins, i, ret;
	108	const char *group_name;
	109	const char *function_name;
	110
	111	*map = NULL;
	112	*num_maps = 0;
	113	reserved_maps = 0;
	114
	115	pctl = pinctrl_dev_get_drvdata(pctldev);
	116
	117	ret = of_property_count_u32_elems(node, "pinmux");
	118	if (ret <= 0) {
	119	dev_err(pctl->dev,
	120	"missing or empty pinmux property in node %pOFn.\n",
	121	node);
839930ca	122	return ret ? ret : -EINVAL;
a0f160ff JG	123	}
	124
	125	num_pins = ret;
	126
361856dd	127	ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins);
a0f160ff JG	128	if (ret)
	129	return ret;
	130
	131	for (i = 0; i < num_pins; i++) {
	132	ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
	133	if (ret)
	134	goto free_map;
	135
	136	pin = APPLE_PIN(pinfunc);
	137	func = APPLE_FUNC(pinfunc);
	138
	139	if (func >= pinmux_generic_get_function_count(pctldev)) {
	140	ret = -EINVAL;
	141	goto free_map;
	142	}
	143
	144	group_name = pinctrl_generic_get_group_name(pctldev, pin);
361856dd	145	function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
a0f160ff	146	ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
361856dd JG	147	&reserved_maps, num_maps,
361856dd JG	148	group_name, function_name);
a0f160ff JG	149	if (ret)
	150	goto free_map;
	151	}
	152
	153	free_map:
	154	if (ret < 0)
	155	pinctrl_utils_free_map(pctldev, map, num_maps);
	156
	157	return ret;
	158	}
	159
	160	static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
	161	.get_groups_count = pinctrl_generic_get_group_count,
	162	.get_group_name = pinctrl_generic_get_group_name,
	163	.get_group_pins = pinctrl_generic_get_group_pins,
	164	.dt_node_to_map = apple_gpio_dt_node_to_map,
	165	.dt_free_map = pinctrl_utils_free_map,
	166	};
	167
	168	/* Pin multiplexer functions */
	169
	170	static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
361856dd	171	unsigned group)
a0f160ff JG	172	{
	173	struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
	174
	175	apple_gpio_set_reg(
	176	pctl, group, REG_GPIOx_PERIPH \| REG_GPIOx_INPUT_ENABLE,
	177	FIELD_PREP(REG_GPIOx_PERIPH, func) \| REG_GPIOx_INPUT_ENABLE);
	178
	179	return 0;
	180	}
	181
	182	static const struct pinmux_ops apple_gpio_pinmux_ops = {
	183	.get_functions_count = pinmux_generic_get_function_count,
	184	.get_function_name = pinmux_generic_get_function_name,
	185	.get_function_groups = pinmux_generic_get_function_groups,
	186	.set_mux = apple_gpio_pinmux_set,
	187	.strict = true,
	188	};
	189
	190	/* GPIO chip functions */
	191
361856dd	192	static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
a0f160ff JG	193	{
	194	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
	195	unsigned int reg = apple_gpio_get_reg(pctl, offset);
	196
7d264917 JG	197	if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT)
	198	return GPIO_LINE_DIRECTION_OUT;
	199	return GPIO_LINE_DIRECTION_IN;
a0f160ff JG	200	}
	201
	202	static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
	203	{
	204	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
	205	unsigned int reg = apple_gpio_get_reg(pctl, offset);
	206
	207	/*
	208	* If this is an input GPIO, read the actual value (not the
	209	* cached regmap value)
	210	*/
	211	if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT)
	212	reg = readl_relaxed(pctl->base + REG_GPIO(offset));
	213
	214	return !!(reg & REG_GPIOx_DATA);
	215	}
	216
361856dd	217	static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
a0f160ff JG	218	{
	219	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
	220
361856dd	221	apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
a0f160ff JG	222	}
a0f160ff JG	223
361856dd	224	static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
a0f160ff JG	225	{
	226	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
	227
	228	apple_gpio_set_reg(pctl, offset,
	229	REG_GPIOx_PERIPH \| REG_GPIOx_MODE \| REG_GPIOx_DATA \|
	230	REG_GPIOx_INPUT_ENABLE,
	231	FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) \|
	232	REG_GPIOx_INPUT_ENABLE);
	233	return 0;
	234	}
	235
	236	static int apple_gpio_direction_output(struct gpio_chip *chip,
361856dd	237	unsigned int offset, int value)
a0f160ff JG	238	{
	239	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
	240
	241	apple_gpio_set_reg(pctl, offset,
	242	REG_GPIOx_PERIPH \| REG_GPIOx_MODE \| REG_GPIOx_DATA,
	243	FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) \|
	244	(value ? REG_GPIOx_DATA : 0));
	245	return 0;
	246	}
	247
	248	/* IRQ chip functions */
	249
	250	static void apple_gpio_irq_ack(struct irq_data *data)
	251	{
361856dd JG	252	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
361856dd JG	253	unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
a0f160ff	254
077db34c	255	writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
a0f160ff JG	256	}
a0f160ff JG	257
9b3b94e9	258	static unsigned int apple_gpio_irq_type(unsigned int type)
a0f160ff JG	259	{
	260	switch (type & IRQ_TYPE_SENSE_MASK) {
	261	case IRQ_TYPE_EDGE_RISING:
	262	return REG_GPIOx_IN_IRQ_UP;
	263	case IRQ_TYPE_EDGE_FALLING:
	264	return REG_GPIOx_IN_IRQ_DN;
	265	case IRQ_TYPE_EDGE_BOTH:
	266	return REG_GPIOx_IN_IRQ_ANY;
	267	case IRQ_TYPE_LEVEL_HIGH:
	268	return REG_GPIOx_IN_IRQ_HI;
	269	case IRQ_TYPE_LEVEL_LOW:
	270	return REG_GPIOx_IN_IRQ_LO;
	271	default:
9b3b94e9	272	return REG_GPIOx_IN_IRQ_OFF;
a0f160ff JG	273	}
	274	}
	275
	276	static void apple_gpio_irq_mask(struct irq_data *data)
	277	{
374b87a0 MZ	278	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
374b87a0 MZ	279	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
361856dd	280
a0f160ff	281	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
361856dd	282	FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
374b87a0	283	gpiochip_disable_irq(gc, data->hwirq);
a0f160ff JG	284	}
	285
	286	static void apple_gpio_irq_unmask(struct irq_data *data)
	287	{
374b87a0 MZ	288	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
374b87a0 MZ	289	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
9b3b94e9	290	unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
a0f160ff	291
374b87a0	292	gpiochip_enable_irq(gc, data->hwirq);
a0f160ff	293	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
361856dd	294	FIELD_PREP(REG_GPIOx_MODE, irqtype));
a0f160ff JG	295	}
	296
	297	static unsigned int apple_gpio_irq_startup(struct irq_data *data)
	298	{
	299	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	300	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
	301
	302	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
361856dd	303	FIELD_PREP(REG_GPIOx_GRP, 0));
a0f160ff JG	304
	305	apple_gpio_direction_input(chip, data->hwirq);
	306	apple_gpio_irq_unmask(data);
	307
	308	return 0;
	309	}
	310
361856dd	311	static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
a0f160ff	312	{
361856dd	313	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
9b3b94e9	314	unsigned int irqtype = apple_gpio_irq_type(type);
a0f160ff	315
9b3b94e9 SP	316	if (irqtype == REG_GPIOx_IN_IRQ_OFF)
9b3b94e9 SP	317	return -EINVAL;
a0f160ff JG	318
a0f160ff JG	319	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
361856dd	320	FIELD_PREP(REG_GPIOx_MODE, irqtype));
a0f160ff JG	321
	322	if (type & IRQ_TYPE_LEVEL_MASK)
	323	irq_set_handler_locked(data, handle_level_irq);
	324	else
	325	irq_set_handler_locked(data, handle_edge_irq);
	326	return 0;
	327	}
	328
	329	static void apple_gpio_irq_handler(struct irq_desc *desc)
	330	{
	331	struct irq_chip *chip = irq_desc_get_chip(desc);
	332	u8 *grpp = irq_desc_get_handler_data(desc);
	333	struct apple_gpio_pinctrl *pctl;
	334	unsigned int pinh, pinl;
	335	unsigned long pending;
	336	struct gpio_chip *gc;
	337
	338	pctl = container_of(grpp - grpp, typeof(pctl), irqgrps[0]);
	339	gc = &pctl->gpio_chip;
	340
	341	chained_irq_enter(chip, desc);
	342	for (pinh = 0; pinh < gc->ngpio; pinh += 32) {
	343	pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh));
	344	for_each_set_bit(pinl, &pending, 32)
	345	generic_handle_domain_irq(gc->irq.domain, pinh + pinl);
	346	}
	347	chained_irq_exit(chip, desc);
	348	}
	349
374b87a0 MZ	350	static const struct irq_chip apple_gpio_irqchip = {
	351	.name = "Apple-GPIO",
	352	.irq_startup = apple_gpio_irq_startup,
	353	.irq_ack = apple_gpio_irq_ack,
	354	.irq_mask = apple_gpio_irq_mask,
	355	.irq_unmask = apple_gpio_irq_unmask,
	356	.irq_set_type = apple_gpio_irq_set_type,
	357	.flags = IRQCHIP_IMMUTABLE,
	358	GPIOCHIP_IRQ_RESOURCE_HELPERS,
a0f160ff JG	359	};
	360
	361	/* Probe & register */
	362
	363	static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
	364	{
	365	struct gpio_irq_chip *girq = &pctl->gpio_chip.irq;
	366	void **irq_data = NULL;
	367	int ret;
	368
a0f160ff JG	369	pctl->gpio_chip.label = dev_name(pctl->dev);
	370	pctl->gpio_chip.request = gpiochip_generic_request;
	371	pctl->gpio_chip.free = gpiochip_generic_free;
	372	pctl->gpio_chip.get_direction = apple_gpio_get_direction;
	373	pctl->gpio_chip.direction_input = apple_gpio_direction_input;
	374	pctl->gpio_chip.direction_output = apple_gpio_direction_output;
	375	pctl->gpio_chip.get = apple_gpio_get;
	376	pctl->gpio_chip.set = apple_gpio_set;
	377	pctl->gpio_chip.base = -1;
	378	pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
	379	pctl->gpio_chip.parent = pctl->dev;
a0f160ff JG	380
	381	if (girq->num_parents) {
	382	int i;
	383
374b87a0	384	gpio_irq_chip_set_chip(girq, &apple_gpio_irqchip);
a0f160ff JG	385	girq->parent_handler = apple_gpio_irq_handler;
	386
	387	girq->parents = kmalloc_array(girq->num_parents,
	388	sizeof(*girq->parents),
	389	GFP_KERNEL);
	390	irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data),
	391	GFP_KERNEL);
	392	if (!girq->parents \|\| !irq_data) {
	393	ret = -ENOMEM;
a8888e64	394	goto out_free_irq_data;
a0f160ff JG	395	}
	396
	397	for (i = 0; i < girq->num_parents; i++) {
361856dd	398	ret = platform_get_irq(to_platform_device(pctl->dev), i);
a0f160ff	399	if (ret < 0)
a8888e64	400	goto out_free_irq_data;
a0f160ff JG	401
	402	girq->parents[i] = ret;
	403	pctl->irqgrps[i] = i;
	404	irq_data[i] = &pctl->irqgrps[i];
	405	}
	406
	407	girq->parent_handler_data_array = irq_data;
	408	girq->per_parent_data = true;
	409	girq->default_type = IRQ_TYPE_NONE;
	410	girq->handler = handle_level_irq;
	411	}
	412
	413	ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
a8888e64 JG	414
a8888e64 JG	415	out_free_irq_data:
a0f160ff JG	416	kfree(girq->parents);
	417	kfree(irq_data);
	418
	419	return ret;
	420	}
	421
	422	static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
	423	{
	424	struct apple_gpio_pinctrl *pctl;
	425	struct pinctrl_pin_desc *pins;
	426	unsigned int npins;
	427	const char **pin_names;
	428	unsigned int *pin_nums;
	429	static const char* pinmux_functions[] = {
	430	"gpio", "periph1", "periph2", "periph3"
	431	};
	432	unsigned int i, nirqs = 0;
	433	int res;
	434
	435	if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
	436	res = platform_irq_count(pdev);
	437	if (res > 0)
	438	nirqs = res;
	439	}
	440
	441	pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs),
	442	GFP_KERNEL);
	443	if (!pctl)
	444	return -ENOMEM;
	445	pctl->dev = &pdev->dev;
	446	pctl->gpio_chip.irq.num_parents = nirqs;
	447	dev_set_drvdata(&pdev->dev, pctl);
	448
	449	if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins))
	450	return dev_err_probe(&pdev->dev, -EINVAL,
	451	"apple,npins property not found\n");
	452
	453	pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]),
	454	GFP_KERNEL);
	455	pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]),
	456	GFP_KERNEL);
	457	pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]),
	458	GFP_KERNEL);
	459	if (!pins \|\| !pin_names \|\| !pin_nums)
	460	return -ENOMEM;
	461
	462	pctl->base = devm_platform_ioremap_resource(pdev, 0);
	463	if (IS_ERR(pctl->base))
	464	return PTR_ERR(pctl->base);
	465
	466	pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, &regmap_config);
	467	if (IS_ERR(pctl->map))
	468	return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map),
	469	"Failed to create regmap\n");
	470
	471	for (i = 0; i < npins; i++) {
	472	pins[i].number = i;
	473	pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i);
	474	pins[i].drv_data = pctl;
	475	pin_names[i] = pins[i].name;
	476	pin_nums[i] = i;
	477	}
	478
	479	pctl->pinctrl_desc.name = dev_name(pctl->dev);
480	pctl->pinctrl_desc.pins = pins;
481	pctl->pinctrl_desc.npins = npins;
482	pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops;
483	pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops;
484
485	pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl);
486	if (IS_ERR(pctl->pctldev))
487	return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev),
488	"Failed to register pinctrl device.\n");
489
490	for (i = 0; i < npins; i++) {
491	res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name,
492	pin_nums + i, 1, pctl);
493	if (res < 0)
494	return dev_err_probe(pctl->dev, res,
495	"Failed to register group");
496	}
497
498	for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) {
499	res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i],
500	pin_names, npins, pctl);
501	if (res < 0)
502	return dev_err_probe(pctl->dev, res,
503	"Failed to register function.");
504	}
505
506	return apple_gpio_register(pctl);
507	}
508
509	static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
510	{ .compatible = "apple,pinctrl", },
511	{ }
512	};
b983d423	513	MODULE_DEVICE_TABLE(of, apple_gpio_pinctrl_of_match);
a0f160ff JG	514
	515	static struct platform_driver apple_gpio_pinctrl_driver = {
	516	.driver = {
	517	.name = "apple-gpio-pinctrl",
	518	.of_match_table = apple_gpio_pinctrl_of_match,
	519	.suppress_bind_attrs = true,
	520	},
	521	.probe = apple_gpio_pinctrl_probe,
	522	};
	523	module_platform_driver(apple_gpio_pinctrl_driver);
	524
	525	MODULE_DESCRIPTION("Apple pinctrl/GPIO driver");
	526	MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>");
	527	MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>");
	528	MODULE_LICENSE("GPL v2");