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pinctrl: amd: Fix newline declaration in debugfs output
[linux-block.git] / drivers / pinctrl / pinctrl-amd.c
CommitLineData
75a6faf6 1// SPDX-License-Identifier: GPL-2.0-only
dbad75dd
KX		 2/*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
8 *
dbad75dd
KX		 9 */
10
11#include <linux/err.h>
12#include <linux/bug.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/compiler.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/log2.h>
20#include <linux/io.h>
1c5fb66a 21#include <linux/gpio/driver.h>
dbad75dd
KX		 22#include <linux/slab.h>
23#include <linux/platform_device.h>
24#include <linux/mutex.h>
25#include <linux/acpi.h>
26#include <linux/seq_file.h>
27#include <linux/interrupt.h>
28#include <linux/list.h>
29#include <linux/bitops.h>
dbad75dd
KX		 30#include <linux/pinctrl/pinconf.h>
31#include <linux/pinctrl/pinconf-generic.h>
72440158 32#include <linux/pinctrl/pinmux.h>
dbad75dd 33
79d2c8be 34#include "core.h"
dbad75dd
KX		 35#include "pinctrl-utils.h"
36#include "pinctrl-amd.h"
37
12b10f47
DK		 38static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
39{
40 unsigned long flags;
41 u32 pin_reg;
42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
43
44 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4);
46 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
47
3c827873
MV		 48 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
49 return GPIO_LINE_DIRECTION_OUT;
50
51 return GPIO_LINE_DIRECTION_IN;
12b10f47
DK		 52}
53
dbad75dd
KX		 54static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
55{
56 unsigned long flags;
57 u32 pin_reg;
04d36723 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 59
229710fe 60 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 61 pin_reg = readl(gpio_dev->base + offset * 4);
dbad75dd
KX		 62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
63 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 64 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 65
66 return 0;
67}
68
69static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
70 int value)
71{
72 u32 pin_reg;
73 unsigned long flags;
04d36723 74 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 75
229710fe 76 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 77 pin_reg = readl(gpio_dev->base + offset * 4);
78 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
79 if (value)
80 pin_reg |= BIT(OUTPUT_VALUE_OFF);
81 else
82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
83 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 84 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 85
86 return 0;
87}
88
89static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
90{
91 u32 pin_reg;
92 unsigned long flags;
04d36723 93 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 94
229710fe 95 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 96 pin_reg = readl(gpio_dev->base + offset * 4);
229710fe 97 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 98
99 return !!(pin_reg & BIT(PIN_STS_OFF));
100}
101
102static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
103{
104 u32 pin_reg;
105 unsigned long flags;
04d36723 106 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 107
229710fe 108 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 109 pin_reg = readl(gpio_dev->base + offset * 4);
110 if (value)
111 pin_reg |= BIT(OUTPUT_VALUE_OFF);
112 else
113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
114 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 115 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 116}
117
118static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
119 unsigned debounce)
120{
dbad75dd 121 u32 time;
25a853d0
KX		 122 u32 pin_reg;
123 int ret = 0;
dbad75dd 124 unsigned long flags;
04d36723 125 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 126
229710fe 127 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 128 pin_reg = readl(gpio_dev->base + offset * 4);
129
130 if (debounce) {
131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
132 pin_reg &= ~DB_TMR_OUT_MASK;
133 /*
134 Debounce Debounce Timer Max
135 TmrLarge TmrOutUnit Unit Debounce
136 Time
137 0 0 61 usec (2 RtcClk) 976 usec
138 0 1 244 usec (8 RtcClk) 3.9 msec
139 1 0 15.6 msec (512 RtcClk) 250 msec
140 1 1 62.5 msec (2048 RtcClk) 1 sec
141 */
142
143 if (debounce < 61) {
144 pin_reg |= 1;
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
147 } else if (debounce < 976) {
148 time = debounce / 61;
149 pin_reg |= time & DB_TMR_OUT_MASK;
150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
152 } else if (debounce < 3900) {
153 time = debounce / 244;
154 pin_reg |= time & DB_TMR_OUT_MASK;
155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
157 } else if (debounce < 250000) {
c64a6a0d 158 time = debounce / 15625;
dbad75dd
KX		 159 pin_reg |= time & DB_TMR_OUT_MASK;
160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
161 pin_reg |= BIT(DB_TMR_LARGE_OFF);
162 } else if (debounce < 1000000) {
163 time = debounce / 62500;
164 pin_reg |= time & DB_TMR_OUT_MASK;
165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
166 pin_reg |= BIT(DB_TMR_LARGE_OFF);
167 } else {
06abe829 168 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
25a853d0 169 ret = -EINVAL;
dbad75dd
KX		 170 }
171 } else {
172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
174 pin_reg &= ~DB_TMR_OUT_MASK;
06abe829 175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
dbad75dd
KX		 176 }
177 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 178 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 179
25a853d0 180 return ret;
dbad75dd
KX		 181}
182
2956b5d9
MW		 183static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
184 unsigned long config)
185{
186 u32 debounce;
187
188 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
189 return -ENOTSUPP;
190
191 debounce = pinconf_to_config_argument(config);
192 return amd_gpio_set_debounce(gc, offset, debounce);
193}
194
dbad75dd
KX		 195#ifdef CONFIG_DEBUG_FS
196static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
197{
198 u32 pin_reg;
39cc1d33 199 u32 db_cntrl;
dbad75dd
KX		 200 unsigned long flags;
201 unsigned int bank, i, pin_num;
04d36723 202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 203
39cc1d33
CX		 204 bool tmr_out_unit;
205 unsigned int time;
206 unsigned int unit;
207 bool tmr_large;
208
dbad75dd
KX		 209 char *level_trig;
210 char *active_level;
211 char *interrupt_enable;
212 char *interrupt_mask;
213 char *wake_cntrl0;
214 char *wake_cntrl1;
215 char *wake_cntrl2;
216 char *pin_sts;
217 char *pull_up_sel;
218 char *pull_up_enable;
219 char *pull_down_enable;
220 char *output_value;
221 char *output_enable;
39cc1d33
CX		 222 char debounce_value[40];
223 char *debounce_enable;
dbad75dd 224
3bfd4430 225 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
dc24b753 226 seq_printf(s, "GPIO bank%d\n", bank);
dbad75dd
KX		 227
228 switch (bank) {
229 case 0:
230 i = 0;
231 pin_num = AMD_GPIO_PINS_BANK0;
232 break;
233 case 1:
234 i = 64;
235 pin_num = AMD_GPIO_PINS_BANK1 + i;
236 break;
237 case 2:
238 i = 128;
239 pin_num = AMD_GPIO_PINS_BANK2 + i;
240 break;
3bfd4430
SN		 241 case 3:
242 i = 192;
243 pin_num = AMD_GPIO_PINS_BANK3 + i;
244 break;
6ac4c1ad
LW		 245 default:
246 /* Illegal bank number, ignore */
247 continue;
dbad75dd 248 }
dbad75dd
KX		 249 for (; i < pin_num; i++) {
250 seq_printf(s, "pin%d\t", i);
229710fe 251 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 252 pin_reg = readl(gpio_dev->base + i * 4);
229710fe 253 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 254
255 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
1766e4b7
DK		 256 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
257 ACTIVE_LEVEL_MASK;
dbad75dd
KX		 258 interrupt_enable = "interrupt is enabled|";
259
1766e4b7 260 if (level == ACTIVE_LEVEL_HIGH)
dbad75dd 261 active_level = "Active high|";
1766e4b7
DK		 262 else if (level == ACTIVE_LEVEL_LOW)
263 active_level = "Active low|";
264 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
265 level == ACTIVE_LEVEL_BOTH)
dbad75dd
KX		 266 active_level = "Active on both|";
267 else
0a95160e 268 active_level = "Unknown Active level|";
dbad75dd
KX		 269
270 if (pin_reg & BIT(LEVEL_TRIG_OFF))
271 level_trig = "Level trigger|";
272 else
273 level_trig = "Edge trigger|";
274
275 } else {
276 interrupt_enable =
277 "interrupt is disabled|";
278 active_level = " ";
279 level_trig = " ";
280 }
281
282 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
283 interrupt_mask =
284 "interrupt is unmasked|";
285 else
286 interrupt_mask =
287 "interrupt is masked|";
288
3bfd4430 289 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
dbad75dd
KX		 290 wake_cntrl0 = "enable wakeup in S0i3 state|";
291 else
292 wake_cntrl0 = "disable wakeup in S0i3 state|";
293
3bfd4430 294 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
dbad75dd
KX		 295 wake_cntrl1 = "enable wakeup in S3 state|";
296 else
297 wake_cntrl1 = "disable wakeup in S3 state|";
298
3bfd4430 299 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
dbad75dd
KX		 300 wake_cntrl2 = "enable wakeup in S4/S5 state|";
301 else
302 wake_cntrl2 = "disable wakeup in S4/S5 state|";
303
304 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
305 pull_up_enable = "pull-up is enabled|";
306 if (pin_reg & BIT(PULL_UP_SEL_OFF))
307 pull_up_sel = "8k pull-up|";
308 else
309 pull_up_sel = "4k pull-up|";
310 } else {
311 pull_up_enable = "pull-up is disabled|";
312 pull_up_sel = " ";
313 }
314
315 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
316 pull_down_enable = "pull-down is enabled|";
317 else
318 pull_down_enable = "Pull-down is disabled|";
319
320 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
321 pin_sts = " ";
322 output_enable = "output is enabled|";
323 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
324 output_value = "output is high|";
325 else
326 output_value = "output is low|";
327 } else {
328 output_enable = "output is disabled|";
329 output_value = " ";
330
331 if (pin_reg & BIT(PIN_STS_OFF))
332 pin_sts = "input is high|";
333 else
334 pin_sts = "input is low|";
335 }
336
39cc1d33
CX		 337 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
338 if (db_cntrl) {
339 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
340 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
341 time = pin_reg & DB_TMR_OUT_MASK;
342 if (tmr_large) {
343 if (tmr_out_unit)
344 unit = 62500;
345 else
346 unit = 15625;
347 } else {
348 if (tmr_out_unit)
349 unit = 244;
350 else
351 unit = 61;
352 }
353 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
354 debounce_enable = "debouncing filter (high and low) enabled|";
355 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
356 debounce_enable = "debouncing filter (low) enabled|";
357 else
358 debounce_enable = "debouncing filter (high) enabled|";
359
360 snprintf(debounce_value, sizeof(debounce_value),
361 "debouncing timeout is %u (us)|", time * unit);
362 } else {
363 debounce_enable = "debouncing filter disabled|";
364 snprintf(debounce_value, sizeof(debounce_value), " ");
365 }
366
dbad75dd 367 seq_printf(s, "%s %s %s %s %s %s\n"
39cc1d33 368 " %s %s %s %s %s %s %s %s %s 0x%x\n",
dbad75dd
KX		 369 level_trig, active_level, interrupt_enable,
370 interrupt_mask, wake_cntrl0, wake_cntrl1,
371 wake_cntrl2, pin_sts, pull_up_sel,
372 pull_up_enable, pull_down_enable,
39cc1d33
CX		 373 output_value, output_enable,
374 debounce_enable, debounce_value, pin_reg);
dbad75dd
KX		 375 }
376 }
377}
378#else
379#define amd_gpio_dbg_show NULL
380#endif
381
382static void amd_gpio_irq_enable(struct irq_data *d)
383{
384 u32 pin_reg;
385 unsigned long flags;
386 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 387 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 388
6173e56f
MZ		 389 gpiochip_enable_irq(gc, d->hwirq);
390
229710fe 391 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 392 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
dbad75dd
KX		 393 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
394 pin_reg |= BIT(INTERRUPT_MASK_OFF);
395 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 396 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 397}
398
399static void amd_gpio_irq_disable(struct irq_data *d)
400{
401 u32 pin_reg;
402 unsigned long flags;
403 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 404 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 405
229710fe 406 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 407 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
408 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
409 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
410 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 411 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
6173e56f
MZ		 412
413 gpiochip_disable_irq(gc, d->hwirq);
dbad75dd
KX		 414}
415
416static void amd_gpio_irq_mask(struct irq_data *d)
417{
418 u32 pin_reg;
419 unsigned long flags;
420 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 421 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 422
229710fe 423 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 424 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
425 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
426 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 427 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 428}
429
430static void amd_gpio_irq_unmask(struct irq_data *d)
431{
432 u32 pin_reg;
433 unsigned long flags;
434 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 435 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 436
229710fe 437 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 438 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
439 pin_reg |= BIT(INTERRUPT_MASK_OFF);
440 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 441 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 442}
443
d62bd5ce
RR		 444static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
445{
446 u32 pin_reg;
447 unsigned long flags;
448 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
449 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
c4b68e51 450 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
acd47b9f 451 int err;
d62bd5ce
RR		 452
453 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
454 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
455
456 if (on)
457 pin_reg |= wake_mask;
458 else
459 pin_reg &= ~wake_mask;
460
461 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
462 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
463
acd47b9f
BN		 464 if (on)
465 err = enable_irq_wake(gpio_dev->irq);
466 else
467 err = disable_irq_wake(gpio_dev->irq);
468
469 if (err)
470 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
471 on ? "enable" : "disable");
472
d62bd5ce
RR		 473 return 0;
474}
475
dbad75dd
KX		 476static void amd_gpio_irq_eoi(struct irq_data *d)
477{
478 u32 reg;
479 unsigned long flags;
480 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 481 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 482
229710fe 483 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 484 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
485 reg |= EOI_MASK;
486 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
229710fe 487 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 488}
489
490static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
491{
492 int ret = 0;
b85bfa24 493 u32 pin_reg, pin_reg_irq_en, mask;
5f4962dd 494 unsigned long flags;
dbad75dd 495 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 496 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 497
229710fe 498 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 499 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
500
501 switch (type & IRQ_TYPE_SENSE_MASK) {
502 case IRQ_TYPE_EDGE_RISING:
503 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
504 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
505 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
9d829314 506 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 507 break;
508
509 case IRQ_TYPE_EDGE_FALLING:
510 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
511 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
512 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
9d829314 513 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 514 break;
515
516 case IRQ_TYPE_EDGE_BOTH:
517 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
518 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
519 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
9d829314 520 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 521 break;
522
523 case IRQ_TYPE_LEVEL_HIGH:
524 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
525 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
526 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
9d829314 527 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 528 break;
529
530 case IRQ_TYPE_LEVEL_LOW:
531 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
532 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
533 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
9d829314 534 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 535 break;
536
537 case IRQ_TYPE_NONE:
538 break;
539
540 default:
541 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
542 ret = -EINVAL;
dbad75dd
KX		 543 }
544
545 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
b85bfa24
DK		 546 /*
547 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
548 * debounce registers of any GPIO will block wake/interrupt status
48c67f1f 549 * generation for *all* GPIOs for a length of time that depends on
b85bfa24
DK		 550 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
551 * INTERRUPT_ENABLE bit will read as 0.
552 *
553 * We temporarily enable irq for the GPIO whose configuration is
554 * changing, and then wait for it to read back as 1 to know when
555 * debounce has settled and then disable the irq again.
556 * We do this polling with the spinlock held to ensure other GPIO
557 * access routines do not read an incorrect value for the irq enable
558 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
559 * spurious irqs, and disable the irq again after polling.
560 */
561 mask = BIT(INTERRUPT_ENABLE_OFF);
562 pin_reg_irq_en = pin_reg;
563 pin_reg_irq_en |= mask;
564 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
565 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
566 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
567 continue;
dbad75dd 568 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 569 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 570
dbad75dd
KX		 571 return ret;
572}
573
574static void amd_irq_ack(struct irq_data *d)
575{
576 /*
577 * based on HW design,there is no need to ack HW
578 * before handle current irq. But this routine is
579 * necessary for handle_edge_irq
580 */
581}
582
6173e56f 583static const struct irq_chip amd_gpio_irqchip = {
dbad75dd
KX		 584 .name = "amd_gpio",
585 .irq_ack = amd_irq_ack,
586 .irq_enable = amd_gpio_irq_enable,
587 .irq_disable = amd_gpio_irq_disable,
588 .irq_mask = amd_gpio_irq_mask,
589 .irq_unmask = amd_gpio_irq_unmask,
d62bd5ce 590 .irq_set_wake = amd_gpio_irq_set_wake,
dbad75dd
KX		 591 .irq_eoi = amd_gpio_irq_eoi,
592 .irq_set_type = amd_gpio_irq_set_type,
d62bd5ce
RR		 593 /*
594 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
595 * also generates an IRQ. We need the IRQ so the irq_handler can clear
596 * the wake event. Otherwise the wake event will never clear and
597 * prevent the system from suspending.
598 */
6173e56f
MZ		 599 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
600 GPIOCHIP_IRQ_RESOURCE_HELPERS,
dbad75dd
KX		 601};
602
ba714a9c
TG		 603#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
604
2d54067f 605static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
dbad75dd 606{
ba714a9c
TG		 607 struct amd_gpio *gpio_dev = dev_id;
608 struct gpio_chip *gc = &gpio_dev->gc;
ba714a9c 609 unsigned int i, irqnr;
dbad75dd 610 unsigned long flags;
10ff58aa 611 u32 __iomem *regs;
2d54067f 612 bool ret = false;
10ff58aa 613 u32 regval;
ba714a9c 614 u64 status, mask;
dbad75dd 615
ba714a9c 616 /* Read the wake status */
229710fe 617 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
ba714a9c
TG		 618 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
619 status <<= 32;
620 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
229710fe 621 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 622
ba714a9c
TG		 623 /* Bit 0-45 contain the relevant status bits */
624 status &= (1ULL << 46) - 1;
625 regs = gpio_dev->base;
626 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
627 if (!(status & mask))
628 continue;
629 status &= ~mask;
630
631 /* Each status bit covers four pins */
632 for (i = 0; i < 4; i++) {
633 regval = readl(regs + i);
2d54067f
ML		 634 /* caused wake on resume context for shared IRQ */
635 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) {
636 dev_dbg(&gpio_dev->pdev->dev,
637 "Waking due to GPIO %d: 0x%x",
638 irqnr + i, regval);
639 return true;
640 }
641
8bbed1ee
DK		 642 if (!(regval & PIN_IRQ_PENDING) ||
643 !(regval & BIT(INTERRUPT_MASK_OFF)))
ba714a9c 644 continue;
a9cb09b7 645 generic_handle_domain_irq(gc->irq.domain, irqnr + i);
6afb1026
DD		 646
647 /* Clear interrupt.
648 * We must read the pin register again, in case the
649 * value was changed while executing
a9cb09b7 650 * generic_handle_domain_irq() above.
d21b8adb
DD		 651 * If we didn't find a mapping for the interrupt,
652 * disable it in order to avoid a system hang caused
653 * by an interrupt storm.
6afb1026
DD		 654 */
655 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
656 regval = readl(regs + i);
d21b8adb
DD		 657 if (irq == 0) {
658 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
659 dev_dbg(&gpio_dev->pdev->dev,
660 "Disabling spurious GPIO IRQ %d\n",
661 irqnr + i);
662 }
ba714a9c 663 writel(regval, regs + i);
6afb1026 664 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
2d54067f 665 ret = true;
dbad75dd
KX		 666 }
667 }
2d54067f
ML		 668 /* did not cause wake on resume context for shared IRQ */
669 if (irq < 0)
670 return false;
dbad75dd 671
ba714a9c 672 /* Signal EOI to the GPIO unit */
229710fe 673 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
ba714a9c
TG		 674 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
675 regval |= EOI_MASK;
676 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
229710fe 677 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 678
ba714a9c 679 return ret;
dbad75dd
KX		 680}
681
2d54067f
ML		 682static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
683{
684 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
685}
686
687static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
688{
689 return do_amd_gpio_irq_handler(-1, dev_id);
690}
691
dbad75dd
KX		 692static int amd_get_groups_count(struct pinctrl_dev *pctldev)
693{
694 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
695
696 return gpio_dev->ngroups;
697}
698
699static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
700 unsigned group)
701{
702 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
703
704 return gpio_dev->groups[group].name;
705}
706
707static int amd_get_group_pins(struct pinctrl_dev *pctldev,
708 unsigned group,
709 const unsigned **pins,
710 unsigned *num_pins)
711{
712 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
713
714 *pins = gpio_dev->groups[group].pins;
715 *num_pins = gpio_dev->groups[group].npins;
716 return 0;
717}
718
719static const struct pinctrl_ops amd_pinctrl_ops = {
720 .get_groups_count = amd_get_groups_count,
721 .get_group_name = amd_get_group_name,
722 .get_group_pins = amd_get_group_pins,
723#ifdef CONFIG_OF
724 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
d32f7fd3 725 .dt_free_map = pinctrl_utils_free_map,
dbad75dd
KX		 726#endif
727};
728
729static int amd_pinconf_get(struct pinctrl_dev *pctldev,
730 unsigned int pin,
731 unsigned long *config)
732{
733 u32 pin_reg;
734 unsigned arg;
735 unsigned long flags;
736 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
737 enum pin_config_param param = pinconf_to_config_param(*config);
738
229710fe 739 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 740 pin_reg = readl(gpio_dev->base + pin*4);
229710fe 741 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 742 switch (param) {
743 case PIN_CONFIG_INPUT_DEBOUNCE:
744 arg = pin_reg & DB_TMR_OUT_MASK;
745 break;
746
747 case PIN_CONFIG_BIAS_PULL_DOWN:
748 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
749 break;
750
751 case PIN_CONFIG_BIAS_PULL_UP:
752 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
753 break;
754
755 case PIN_CONFIG_DRIVE_STRENGTH:
756 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
757 break;
758
759 default:
760 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
761 param);
762 return -ENOTSUPP;
763 }
764
765 *config = pinconf_to_config_packed(param, arg);
766
767 return 0;
768}
769
770static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
771 unsigned long *configs, unsigned num_configs)
772{
773 int i;
dbad75dd 774 u32 arg;
25a853d0
KX		 775 int ret = 0;
776 u32 pin_reg;
dbad75dd
KX		 777 unsigned long flags;
778 enum pin_config_param param;
779 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
780
229710fe 781 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 782 for (i = 0; i < num_configs; i++) {
783 param = pinconf_to_config_param(configs[i]);
784 arg = pinconf_to_config_argument(configs[i]);
785 pin_reg = readl(gpio_dev->base + pin*4);
786
787 switch (param) {
788 case PIN_CONFIG_INPUT_DEBOUNCE:
789 pin_reg &= ~DB_TMR_OUT_MASK;
790 pin_reg |= arg & DB_TMR_OUT_MASK;
791 break;
792
793 case PIN_CONFIG_BIAS_PULL_DOWN:
794 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
795 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
796 break;
797
798 case PIN_CONFIG_BIAS_PULL_UP:
799 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
800 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
801 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
802 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
803 break;
804
805 case PIN_CONFIG_DRIVE_STRENGTH:
806 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
807 << DRV_STRENGTH_SEL_OFF);
808 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
809 << DRV_STRENGTH_SEL_OFF;
810 break;
811
812 default:
813 dev_err(&gpio_dev->pdev->dev,
814 "Invalid config param %04x\n", param);
25a853d0 815 ret = -ENOTSUPP;
dbad75dd
KX		 816 }
817
818 writel(pin_reg, gpio_dev->base + pin*4);
819 }
229710fe 820 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 821
25a853d0 822 return ret;
dbad75dd
KX		 823}
824
825static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
826 unsigned int group,
827 unsigned long *config)
828{
829 const unsigned *pins;
830 unsigned npins;
831 int ret;
832
833 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
834 if (ret)
835 return ret;
836
837 if (amd_pinconf_get(pctldev, pins[0], config))
838 return -ENOTSUPP;
839
840 return 0;
841}
842
843static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
844 unsigned group, unsigned long *configs,
845 unsigned num_configs)
846{
847 const unsigned *pins;
848 unsigned npins;
849 int i, ret;
850
851 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
852 if (ret)
853 return ret;
854 for (i = 0; i < npins; i++) {
855 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
856 return -ENOTSUPP;
857 }
858 return 0;
859}
860
861static const struct pinconf_ops amd_pinconf_ops = {
862 .pin_config_get = amd_pinconf_get,
863 .pin_config_set = amd_pinconf_set,
864 .pin_config_group_get = amd_pinconf_group_get,
865 .pin_config_group_set = amd_pinconf_group_set,
866};
867
4e5a04be
SK		 868static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
869{
870 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
871 unsigned long flags;
872 u32 pin_reg, mask;
873 int i;
874
875 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
876 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
877 BIT(WAKE_CNTRL_OFF_S4);
878
879 for (i = 0; i < desc->npins; i++) {
880 int pin = desc->pins[i].number;
881 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
882
883 if (!pd)
884 continue;
885
886 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
887
888 pin_reg = readl(gpio_dev->base + i * 4);
889 pin_reg &= ~mask;
890 writel(pin_reg, gpio_dev->base + i * 4);
891
892 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
893 }
894}
895
79d2c8be
DD		 896#ifdef CONFIG_PM_SLEEP
897static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
898{
899 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
900
901 if (!pd)
902 return false;
903
904 /*
905 * Only restore the pin if it is actually in use by the kernel (or
906 * by userspace).
907 */
908 if (pd->mux_owner || pd->gpio_owner ||
909 gpiochip_line_is_irq(&gpio_dev->gc, pin))
910 return true;
911
912 return false;
913}
914
2d71dfa2 915static int amd_gpio_suspend(struct device *dev)
79d2c8be 916{
9f540c3e 917 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
79d2c8be 918 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
b8c824a8 919 unsigned long flags;
79d2c8be
DD		 920 int i;
921
922 for (i = 0; i < desc->npins; i++) {
923 int pin = desc->pins[i].number;
924
925 if (!amd_gpio_should_save(gpio_dev, pin))
926 continue;
927
b8c824a8
BN		 928 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
929 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
930 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
79d2c8be
DD		 931 }
932
933 return 0;
934}
935
2d71dfa2 936static int amd_gpio_resume(struct device *dev)
79d2c8be 937{
9f540c3e 938 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
79d2c8be 939 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
b8c824a8 940 unsigned long flags;
79d2c8be
DD		 941 int i;
942
943 for (i = 0; i < desc->npins; i++) {
944 int pin = desc->pins[i].number;
945
946 if (!amd_gpio_should_save(gpio_dev, pin))
947 continue;
948
b8c824a8
BN		 949 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
950 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
951 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
952 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
79d2c8be
DD		 953 }
954
955 return 0;
956}
957
958static const struct dev_pm_ops amd_gpio_pm_ops = {
959 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
960 amd_gpio_resume)
961};
962#endif
963
72440158
BN		 964static int amd_get_functions_count(struct pinctrl_dev *pctldev)
965{
966 return ARRAY_SIZE(pmx_functions);
967}
968
969static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
970{
971 return pmx_functions[selector].name;
972}
973
974static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
975 const char * const **groups,
976 unsigned int * const num_groups)
977{
978 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
979
980 if (!gpio_dev->iomux_base) {
981 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
982 return -EINVAL;
983 }
984
985 *groups = pmx_functions[selector].groups;
986 *num_groups = pmx_functions[selector].ngroups;
987 return 0;
988}
989
990static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
991{
992 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
993 struct device *dev = &gpio_dev->pdev->dev;
994 struct pin_desc *pd;
995 int ind, index;
996
997 if (!gpio_dev->iomux_base)
998 return -EINVAL;
999
1000 for (index = 0; index < NSELECTS; index++) {
1001 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
1002 continue;
1003
1004 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
1005 FUNCTION_INVALID) {
1006 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1007 pmx_functions[function].index);
1008 return -EINVAL;
1009 }
1010
1011 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
1012
1013 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
1014 FUNCTION_MASK)) {
1015 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1016 pmx_functions[function].index);
1017 return -EINVAL;
1018 }
1019
1020 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
1021 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
1022 continue;
1023
1024 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
1025 pd->mux_owner = gpio_dev->groups[group].name;
1026 }
1027 break;
1028 }
1029
1030 return 0;
1031}
1032
1033static const struct pinmux_ops amd_pmxops = {
1034 .get_functions_count = amd_get_functions_count,
1035 .get_function_name = amd_get_fname,
1036 .get_function_groups = amd_get_groups,
1037 .set_mux = amd_set_mux,
1038};
1039
dbad75dd
KX		 1040static struct pinctrl_desc amd_pinctrl_desc = {
1041 .pins = kerncz_pins,
1042 .npins = ARRAY_SIZE(kerncz_pins),
1043 .pctlops = &amd_pinctrl_ops,
72440158 1044 .pmxops = &amd_pmxops,
dbad75dd
KX		 1045 .confops = &amd_pinconf_ops,
1046 .owner = THIS_MODULE,
1047};
1048
79bb5c7f
BN		 1049static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
1050{
1051 struct pinctrl_desc *desc = &amd_pinctrl_desc;
1052 struct device *dev = &gpio_dev->pdev->dev;
1053 int index;
1054
1055 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
1056 if (index < 0) {
1057 dev_warn(dev, "failed to get iomux index\n");
1058 goto out_no_pinmux;
1059 }
1060
1061 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
1062 if (IS_ERR(gpio_dev->iomux_base)) {
1063 dev_warn(dev, "Failed to get iomux %d io resource\n", index);
1064 goto out_no_pinmux;
1065 }
1066
1067 return;
1068
1069out_no_pinmux:
1070 desc->pmxops = NULL;
1071}
1072
dbad75dd
KX		 1073static int amd_gpio_probe(struct platform_device *pdev)
1074{
1075 int ret = 0;
dbad75dd
KX		 1076 struct resource *res;
1077 struct amd_gpio *gpio_dev;
e81376eb 1078 struct gpio_irq_chip *girq;
dbad75dd
KX		 1079
1080 gpio_dev = devm_kzalloc(&pdev->dev,
1081 sizeof(struct amd_gpio), GFP_KERNEL);
1082 if (!gpio_dev)
1083 return -ENOMEM;
1084
229710fe 1085 raw_spin_lock_init(&gpio_dev->lock);
dbad75dd 1086
21793d22
BN		 1087 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1088 if (IS_ERR(gpio_dev->base)) {
dbad75dd 1089 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
21793d22 1090 return PTR_ERR(gpio_dev->base);
dbad75dd
KX		 1091 }
1092
7e6f8d6f
BN		 1093 gpio_dev->irq = platform_get_irq(pdev, 0);
1094 if (gpio_dev->irq < 0)
1095 return gpio_dev->irq;
dbad75dd 1096
79d2c8be
DD		 1097#ifdef CONFIG_PM_SLEEP
1098 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
1099 sizeof(*gpio_dev->saved_regs),
1100 GFP_KERNEL);
1101 if (!gpio_dev->saved_regs)
1102 return -ENOMEM;
1103#endif
1104
dbad75dd 1105 gpio_dev->pdev = pdev;
12b10f47 1106 gpio_dev->gc.get_direction = amd_gpio_get_direction;
dbad75dd
KX		 1107 gpio_dev->gc.direction_input = amd_gpio_direction_input;
1108 gpio_dev->gc.direction_output = amd_gpio_direction_output;
1109 gpio_dev->gc.get = amd_gpio_get_value;
1110 gpio_dev->gc.set = amd_gpio_set_value;
2956b5d9 1111 gpio_dev->gc.set_config = amd_gpio_set_config;
dbad75dd
KX		 1112 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
1113
3bfd4430 1114 gpio_dev->gc.base = -1;
dbad75dd
KX		 1115 gpio_dev->gc.label = pdev->name;
1116 gpio_dev->gc.owner = THIS_MODULE;
58383c78 1117 gpio_dev->gc.parent = &pdev->dev;
3bfd4430 1118 gpio_dev->gc.ngpio = resource_size(res) / 4;
dbad75dd 1119
3bfd4430 1120 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
dbad75dd
KX		 1121 gpio_dev->groups = kerncz_groups;
1122 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1123
1124 amd_pinctrl_desc.name = dev_name(&pdev->dev);
79bb5c7f 1125 amd_get_iomux_res(gpio_dev);
251e22ab
LD		 1126 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1127 gpio_dev);
323de9ef 1128 if (IS_ERR(gpio_dev->pctrl)) {
dbad75dd 1129 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
323de9ef 1130 return PTR_ERR(gpio_dev->pctrl);
dbad75dd
KX		 1131 }
1132
4e5a04be
SK		 1133 /* Disable and mask interrupts */
1134 amd_gpio_irq_init(gpio_dev);
1135
e81376eb 1136 girq = &gpio_dev->gc.irq;
6173e56f 1137 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
e81376eb
LW		 1138 /* This will let us handle the parent IRQ in the driver */
1139 girq->parent_handler = NULL;
1140 girq->num_parents = 0;
1141 girq->parents = NULL;
1142 girq->default_type = IRQ_TYPE_NONE;
1143 girq->handler = handle_simple_irq;
1144
04d36723 1145 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
dbad75dd 1146 if (ret)
251e22ab 1147 return ret;
dbad75dd
KX		 1148
1149 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
3bfd4430 1150 0, 0, gpio_dev->gc.ngpio);
dbad75dd
KX		 1151 if (ret) {
1152 dev_err(&pdev->dev, "Failed to add pin range\n");
1153 goto out2;
1154 }
1155
7e6f8d6f 1156 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
279ffafa 1157 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
ba714a9c
TG		 1158 if (ret)
1159 goto out2;
1160
dbad75dd 1161 platform_set_drvdata(pdev, gpio_dev);
2d54067f 1162 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
dbad75dd
KX		 1163
1164 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1165 return ret;
1166
1167out2:
1168 gpiochip_remove(&gpio_dev->gc);
1169
dbad75dd
KX		 1170 return ret;
1171}
1172
1173static int amd_gpio_remove(struct platform_device *pdev)
1174{
1175 struct amd_gpio *gpio_dev;
1176
1177 gpio_dev = platform_get_drvdata(pdev);
1178
1179 gpiochip_remove(&gpio_dev->gc);
2d54067f 1180 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
dbad75dd
KX		 1181
1182 return 0;
1183}
1184
de4334f7 1185#ifdef CONFIG_ACPI
dbad75dd
KX		 1186static const struct acpi_device_id amd_gpio_acpi_match[] = {
1187 { "AMD0030", 0 },
42a44402 1188 { "AMDI0030", 0},
1ca46d3e 1189 { "AMDI0031", 0},
dbad75dd
KX		 1190 { },
1191};
1192MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
de4334f7 1193#endif
dbad75dd
KX		 1194
1195static struct platform_driver amd_gpio_driver = {
1196 .driver = {
1197 .name = "amd_gpio",
dbad75dd 1198 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
79d2c8be
DD		 1199#ifdef CONFIG_PM_SLEEP
1200 .pm = &amd_gpio_pm_ops,
1201#endif
dbad75dd
KX		 1202 },
1203 .probe = amd_gpio_probe,
1204 .remove = amd_gpio_remove,
1205};
1206
1207module_platform_driver(amd_gpio_driver);
1208
1209MODULE_LICENSE("GPL v2");
1210MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1211MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux 6.x block layer and io_uring tree(s)