projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'nfs-for-6.2-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
[linux-block.git] / drivers / pinctrl / pinctrl-amd.c
CommitLineData
75a6faf6 1// SPDX-License-Identifier: GPL-2.0-only
dbad75dd
KX		 2/*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
8 *
dbad75dd
KX		 9 */
10
11#include <linux/err.h>
12#include <linux/bug.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/compiler.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/log2.h>
20#include <linux/io.h>
1c5fb66a 21#include <linux/gpio/driver.h>
dbad75dd
KX		 22#include <linux/slab.h>
23#include <linux/platform_device.h>
24#include <linux/mutex.h>
25#include <linux/acpi.h>
26#include <linux/seq_file.h>
27#include <linux/interrupt.h>
28#include <linux/list.h>
29#include <linux/bitops.h>
dbad75dd
KX		 30#include <linux/pinctrl/pinconf.h>
31#include <linux/pinctrl/pinconf-generic.h>
72440158 32#include <linux/pinctrl/pinmux.h>
dbad75dd 33
79d2c8be 34#include "core.h"
dbad75dd
KX		 35#include "pinctrl-utils.h"
36#include "pinctrl-amd.h"
37
12b10f47
DK		 38static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
39{
40 unsigned long flags;
41 u32 pin_reg;
42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
43
44 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4);
46 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
47
3c827873
MV		 48 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
49 return GPIO_LINE_DIRECTION_OUT;
50
51 return GPIO_LINE_DIRECTION_IN;
12b10f47
DK		 52}
53
dbad75dd
KX		 54static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
55{
56 unsigned long flags;
57 u32 pin_reg;
04d36723 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 59
229710fe 60 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 61 pin_reg = readl(gpio_dev->base + offset * 4);
dbad75dd
KX		 62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
63 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 64 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 65
66 return 0;
67}
68
69static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
70 int value)
71{
72 u32 pin_reg;
73 unsigned long flags;
04d36723 74 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 75
229710fe 76 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 77 pin_reg = readl(gpio_dev->base + offset * 4);
78 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
79 if (value)
80 pin_reg |= BIT(OUTPUT_VALUE_OFF);
81 else
82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
83 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 84 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 85
86 return 0;
87}
88
89static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
90{
91 u32 pin_reg;
92 unsigned long flags;
04d36723 93 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 94
229710fe 95 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 96 pin_reg = readl(gpio_dev->base + offset * 4);
229710fe 97 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 98
99 return !!(pin_reg & BIT(PIN_STS_OFF));
100}
101
102static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
103{
104 u32 pin_reg;
105 unsigned long flags;
04d36723 106 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 107
229710fe 108 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 109 pin_reg = readl(gpio_dev->base + offset * 4);
110 if (value)
111 pin_reg |= BIT(OUTPUT_VALUE_OFF);
112 else
113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
114 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 115 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 116}
117
118static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
119 unsigned debounce)
120{
dbad75dd 121 u32 time;
25a853d0
KX		 122 u32 pin_reg;
123 int ret = 0;
dbad75dd 124 unsigned long flags;
04d36723 125 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 126
229710fe 127 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 128 pin_reg = readl(gpio_dev->base + offset * 4);
129
130 if (debounce) {
131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
132 pin_reg &= ~DB_TMR_OUT_MASK;
133 /*
134 Debounce Debounce Timer Max
135 TmrLarge TmrOutUnit Unit Debounce
136 Time
137 0 0 61 usec (2 RtcClk) 976 usec
138 0 1 244 usec (8 RtcClk) 3.9 msec
139 1 0 15.6 msec (512 RtcClk) 250 msec
140 1 1 62.5 msec (2048 RtcClk) 1 sec
141 */
142
143 if (debounce < 61) {
144 pin_reg |= 1;
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
147 } else if (debounce < 976) {
148 time = debounce / 61;
149 pin_reg |= time & DB_TMR_OUT_MASK;
150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
152 } else if (debounce < 3900) {
153 time = debounce / 244;
154 pin_reg |= time & DB_TMR_OUT_MASK;
155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
157 } else if (debounce < 250000) {
c64a6a0d 158 time = debounce / 15625;
dbad75dd
KX		 159 pin_reg |= time & DB_TMR_OUT_MASK;
160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
161 pin_reg |= BIT(DB_TMR_LARGE_OFF);
162 } else if (debounce < 1000000) {
163 time = debounce / 62500;
164 pin_reg |= time & DB_TMR_OUT_MASK;
165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
166 pin_reg |= BIT(DB_TMR_LARGE_OFF);
167 } else {
06abe829 168 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
25a853d0 169 ret = -EINVAL;
dbad75dd
KX		 170 }
171 } else {
172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
174 pin_reg &= ~DB_TMR_OUT_MASK;
06abe829 175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
dbad75dd
KX		 176 }
177 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 178 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 179
25a853d0 180 return ret;
dbad75dd
KX		 181}
182
2956b5d9
MW		 183static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
184 unsigned long config)
185{
186 u32 debounce;
187
188 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
189 return -ENOTSUPP;
190
191 debounce = pinconf_to_config_argument(config);
192 return amd_gpio_set_debounce(gc, offset, debounce);
193}
194
dbad75dd
KX		 195#ifdef CONFIG_DEBUG_FS
196static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
197{
198 u32 pin_reg;
39cc1d33 199 u32 db_cntrl;
dbad75dd
KX		 200 unsigned long flags;
201 unsigned int bank, i, pin_num;
04d36723 202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 203
39cc1d33 204 bool tmr_out_unit;
39cc1d33
CX		 205 bool tmr_large;
206
dbad75dd
KX		 207 char *level_trig;
208 char *active_level;
209 char *interrupt_enable;
210 char *interrupt_mask;
211 char *wake_cntrl0;
212 char *wake_cntrl1;
213 char *wake_cntrl2;
214 char *pin_sts;
215 char *pull_up_sel;
216 char *pull_up_enable;
217 char *pull_down_enable;
e8129a07 218 char *orientation;
39cc1d33
CX		 219 char debounce_value[40];
220 char *debounce_enable;
dbad75dd 221
3bfd4430 222 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
e8129a07
ML		 223 unsigned int time = 0;
224 unsigned int unit = 0;
dbad75dd
KX		 225
226 switch (bank) {
227 case 0:
228 i = 0;
229 pin_num = AMD_GPIO_PINS_BANK0;
230 break;
231 case 1:
232 i = 64;
233 pin_num = AMD_GPIO_PINS_BANK1 + i;
234 break;
235 case 2:
236 i = 128;
237 pin_num = AMD_GPIO_PINS_BANK2 + i;
238 break;
3bfd4430
SN		 239 case 3:
240 i = 192;
241 pin_num = AMD_GPIO_PINS_BANK3 + i;
242 break;
6ac4c1ad
LW		 243 default:
244 /* Illegal bank number, ignore */
245 continue;
dbad75dd 246 }
e8129a07 247 seq_printf(s, "GPIO bank%d\n", bank);
dbad75dd 248 for (; i < pin_num; i++) {
76e55d93 249 seq_printf(s, "#%d\t", i);
229710fe 250 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 251 pin_reg = readl(gpio_dev->base + i * 4);
229710fe 252 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 253
254 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
1766e4b7
DK		 255 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
256 ACTIVE_LEVEL_MASK;
e8129a07 257 interrupt_enable = "+";
dbad75dd 258
1766e4b7 259 if (level == ACTIVE_LEVEL_HIGH)
e8129a07 260 active_level = "↑";
1766e4b7 261 else if (level == ACTIVE_LEVEL_LOW)
e8129a07 262 active_level = "↓";
1766e4b7
DK		 263 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
264 level == ACTIVE_LEVEL_BOTH)
e8129a07 265 active_level = "b";
dbad75dd 266 else
e8129a07 267 active_level = "?";
dbad75dd
KX		 268
269 if (pin_reg & BIT(LEVEL_TRIG_OFF))
e8129a07 270 level_trig = "level";
dbad75dd 271 else
e8129a07 272 level_trig = " edge";
dbad75dd
KX		 273
274 } else {
e8129a07
ML		 275 interrupt_enable = "∅";
276 active_level = "∅";
277 level_trig = " ∅";
dbad75dd
KX		 278 }
279
280 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
76e55d93 281 interrupt_mask = "😛";
dbad75dd 282 else
76e55d93
ML		 283 interrupt_mask = "😷";
284 seq_printf(s, "int %s (%s)| active-%s| %s-⚡| ",
e8129a07
ML		 285 interrupt_enable,
286 interrupt_mask,
287 active_level,
288 level_trig);
dbad75dd 289
3bfd4430 290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
76e55d93 291 wake_cntrl0 = "⏰";
dbad75dd 292 else
76e55d93
ML		 293 wake_cntrl0 = " ∅";
294 seq_printf(s, "S0i3 %s| ", wake_cntrl0);
dbad75dd 295
3bfd4430 296 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
76e55d93 297 wake_cntrl1 = "⏰";
dbad75dd 298 else
76e55d93
ML		 299 wake_cntrl1 = " ∅";
300 seq_printf(s, "S3 %s| ", wake_cntrl1);
dbad75dd 301
3bfd4430 302 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
76e55d93 303 wake_cntrl2 = "⏰";
dbad75dd 304 else
76e55d93
ML		 305 wake_cntrl2 = " ∅";
306 seq_printf(s, "S4/S5 %s| ", wake_cntrl2);
dbad75dd
KX		 307
308 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
e8129a07 309 pull_up_enable = "+";
dbad75dd 310 if (pin_reg & BIT(PULL_UP_SEL_OFF))
e8129a07 311 pull_up_sel = "8k";
dbad75dd 312 else
e8129a07 313 pull_up_sel = "4k";
dbad75dd 314 } else {
e8129a07
ML		 315 pull_up_enable = "∅";
316 pull_up_sel = " ";
dbad75dd 317 }
e8129a07
ML		 318 seq_printf(s, "pull-↑ %s (%s)| ",
319 pull_up_enable,
320 pull_up_sel);
dbad75dd
KX		 321
322 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
e8129a07 323 pull_down_enable = "+";
dbad75dd 324 else
e8129a07
ML		 325 pull_down_enable = "∅";
326 seq_printf(s, "pull-↓ %s| ", pull_down_enable);
dbad75dd
KX		 327
328 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
e8129a07 329 pin_sts = "output";
dbad75dd 330 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
e8129a07 331 orientation = "↑";
dbad75dd 332 else
e8129a07 333 orientation = "↓";
dbad75dd 334 } else {
e8129a07 335 pin_sts = "input ";
dbad75dd 336 if (pin_reg & BIT(PIN_STS_OFF))
e8129a07 337 orientation = "↑";
dbad75dd 338 else
e8129a07 339 orientation = "↓";
dbad75dd 340 }
e8129a07 341 seq_printf(s, "%s %s| ", pin_sts, orientation);
dbad75dd 342
39cc1d33
CX		 343 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
344 if (db_cntrl) {
345 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
346 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
347 time = pin_reg & DB_TMR_OUT_MASK;
348 if (tmr_large) {
349 if (tmr_out_unit)
350 unit = 62500;
351 else
352 unit = 15625;
353 } else {
354 if (tmr_out_unit)
355 unit = 244;
356 else
357 unit = 61;
358 }
359 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
e8129a07 360 debounce_enable = "b +";
39cc1d33 361 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
e8129a07 362 debounce_enable = "↓ +";
39cc1d33 363 else
e8129a07 364 debounce_enable = "↑ +";
39cc1d33 365
39cc1d33 366 } else {
e8129a07 367 debounce_enable = " ∅";
39cc1d33 368 }
e8129a07 369 snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit);
76e55d93 370 seq_printf(s, "debounce %s (🕑 %sus)| ", debounce_enable, debounce_value);
e8129a07 371 seq_printf(s, " 0x%x\n", pin_reg);
dbad75dd
KX		 372 }
373 }
374}
375#else
376#define amd_gpio_dbg_show NULL
377#endif
378
379static void amd_gpio_irq_enable(struct irq_data *d)
380{
381 u32 pin_reg;
382 unsigned long flags;
383 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 384 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 385
6173e56f
MZ		 386 gpiochip_enable_irq(gc, d->hwirq);
387
229710fe 388 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 389 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
dbad75dd
KX		 390 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
391 pin_reg |= BIT(INTERRUPT_MASK_OFF);
392 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 393 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 394}
395
396static void amd_gpio_irq_disable(struct irq_data *d)
397{
398 u32 pin_reg;
399 unsigned long flags;
400 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 401 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 402
229710fe 403 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 404 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
405 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
406 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
407 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 408 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
6173e56f
MZ		 409
410 gpiochip_disable_irq(gc, d->hwirq);
dbad75dd
KX		 411}
412
413static void amd_gpio_irq_mask(struct irq_data *d)
414{
415 u32 pin_reg;
416 unsigned long flags;
417 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 418 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 419
229710fe 420 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 421 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
422 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
423 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 424 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 425}
426
427static void amd_gpio_irq_unmask(struct irq_data *d)
428{
429 u32 pin_reg;
430 unsigned long flags;
431 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 432 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 433
229710fe 434 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 435 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
436 pin_reg |= BIT(INTERRUPT_MASK_OFF);
437 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 438 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 439}
440
d62bd5ce
RR		 441static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
442{
443 u32 pin_reg;
444 unsigned long flags;
445 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
446 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
c4b68e51 447 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
acd47b9f 448 int err;
d62bd5ce
RR		 449
450 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
451 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
452
453 if (on)
454 pin_reg |= wake_mask;
455 else
456 pin_reg &= ~wake_mask;
457
458 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
459 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
460
acd47b9f
BN		 461 if (on)
462 err = enable_irq_wake(gpio_dev->irq);
463 else
464 err = disable_irq_wake(gpio_dev->irq);
465
466 if (err)
467 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
468 on ? "enable" : "disable");
469
d62bd5ce
RR		 470 return 0;
471}
472
dbad75dd
KX		 473static void amd_gpio_irq_eoi(struct irq_data *d)
474{
475 u32 reg;
476 unsigned long flags;
477 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 478 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 479
229710fe 480 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 481 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
482 reg |= EOI_MASK;
483 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
229710fe 484 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 485}
486
487static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
488{
489 int ret = 0;
b85bfa24 490 u32 pin_reg, pin_reg_irq_en, mask;
5f4962dd 491 unsigned long flags;
dbad75dd 492 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 493 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 494
229710fe 495 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 496 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
497
498 switch (type & IRQ_TYPE_SENSE_MASK) {
499 case IRQ_TYPE_EDGE_RISING:
500 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
501 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
502 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
9d829314 503 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 504 break;
505
506 case IRQ_TYPE_EDGE_FALLING:
507 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
508 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
509 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
9d829314 510 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 511 break;
512
513 case IRQ_TYPE_EDGE_BOTH:
514 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
515 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
516 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
9d829314 517 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 518 break;
519
520 case IRQ_TYPE_LEVEL_HIGH:
521 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
522 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
523 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
9d829314 524 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 525 break;
526
527 case IRQ_TYPE_LEVEL_LOW:
528 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
529 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
530 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
9d829314 531 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 532 break;
533
534 case IRQ_TYPE_NONE:
535 break;
536
537 default:
538 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
539 ret = -EINVAL;
dbad75dd
KX		 540 }
541
542 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
b85bfa24
DK		 543 /*
544 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
545 * debounce registers of any GPIO will block wake/interrupt status
48c67f1f 546 * generation for *all* GPIOs for a length of time that depends on
b85bfa24
DK		 547 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
548 * INTERRUPT_ENABLE bit will read as 0.
549 *
550 * We temporarily enable irq for the GPIO whose configuration is
551 * changing, and then wait for it to read back as 1 to know when
552 * debounce has settled and then disable the irq again.
553 * We do this polling with the spinlock held to ensure other GPIO
554 * access routines do not read an incorrect value for the irq enable
555 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
556 * spurious irqs, and disable the irq again after polling.
557 */
558 mask = BIT(INTERRUPT_ENABLE_OFF);
559 pin_reg_irq_en = pin_reg;
560 pin_reg_irq_en |= mask;
561 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
562 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
563 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
564 continue;
dbad75dd 565 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 566 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 567
dbad75dd
KX		 568 return ret;
569}
570
571static void amd_irq_ack(struct irq_data *d)
572{
573 /*
574 * based on HW design,there is no need to ack HW
575 * before handle current irq. But this routine is
576 * necessary for handle_edge_irq
577 */
578}
579
6173e56f 580static const struct irq_chip amd_gpio_irqchip = {
dbad75dd
KX		 581 .name = "amd_gpio",
582 .irq_ack = amd_irq_ack,
583 .irq_enable = amd_gpio_irq_enable,
584 .irq_disable = amd_gpio_irq_disable,
585 .irq_mask = amd_gpio_irq_mask,
586 .irq_unmask = amd_gpio_irq_unmask,
d62bd5ce 587 .irq_set_wake = amd_gpio_irq_set_wake,
dbad75dd
KX		 588 .irq_eoi = amd_gpio_irq_eoi,
589 .irq_set_type = amd_gpio_irq_set_type,
d62bd5ce
RR		 590 /*
591 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
592 * also generates an IRQ. We need the IRQ so the irq_handler can clear
593 * the wake event. Otherwise the wake event will never clear and
594 * prevent the system from suspending.
595 */
6173e56f
MZ		 596 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
597 GPIOCHIP_IRQ_RESOURCE_HELPERS,
dbad75dd
KX		 598};
599
ba714a9c
TG		 600#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
601
2d54067f 602static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
dbad75dd 603{
ba714a9c
TG		 604 struct amd_gpio *gpio_dev = dev_id;
605 struct gpio_chip *gc = &gpio_dev->gc;
ba714a9c 606 unsigned int i, irqnr;
dbad75dd 607 unsigned long flags;
10ff58aa 608 u32 __iomem *regs;
2d54067f 609 bool ret = false;
10ff58aa 610 u32 regval;
ba714a9c 611 u64 status, mask;
dbad75dd 612
ba714a9c 613 /* Read the wake status */
229710fe 614 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
ba714a9c
TG		 615 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
616 status <<= 32;
617 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
229710fe 618 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 619
ba714a9c
TG		 620 /* Bit 0-45 contain the relevant status bits */
621 status &= (1ULL << 46) - 1;
622 regs = gpio_dev->base;
623 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
624 if (!(status & mask))
625 continue;
626 status &= ~mask;
627
628 /* Each status bit covers four pins */
629 for (i = 0; i < 4; i++) {
630 regval = readl(regs + i);
1d66e379
ML		 631
632 if (regval & PIN_IRQ_PENDING)
2d54067f 633 dev_dbg(&gpio_dev->pdev->dev,
1d66e379 634 "GPIO %d is active: 0x%x",
2d54067f 635 irqnr + i, regval);
1d66e379
ML		 636
637 /* caused wake on resume context for shared IRQ */
638 if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))
2d54067f 639 return true;
2d54067f 640
8bbed1ee
DK		 641 if (!(regval & PIN_IRQ_PENDING) ||
642 !(regval & BIT(INTERRUPT_MASK_OFF)))
ba714a9c 643 continue;
f460c701 644 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i);
6afb1026
DD		 645
646 /* Clear interrupt.
647 * We must read the pin register again, in case the
648 * value was changed while executing
a9cb09b7 649 * generic_handle_domain_irq() above.
d21b8adb
DD		 650 * If we didn't find a mapping for the interrupt,
651 * disable it in order to avoid a system hang caused
652 * by an interrupt storm.
6afb1026
DD		 653 */
654 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
655 regval = readl(regs + i);
d21b8adb
DD		 656 if (irq == 0) {
657 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
658 dev_dbg(&gpio_dev->pdev->dev,
659 "Disabling spurious GPIO IRQ %d\n",
660 irqnr + i);
661 }
ba714a9c 662 writel(regval, regs + i);
6afb1026 663 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
2d54067f 664 ret = true;
dbad75dd
KX		 665 }
666 }
2d54067f
ML		 667 /* did not cause wake on resume context for shared IRQ */
668 if (irq < 0)
669 return false;
dbad75dd 670
ba714a9c 671 /* Signal EOI to the GPIO unit */
229710fe 672 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
ba714a9c
TG		 673 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
674 regval |= EOI_MASK;
675 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
229710fe 676 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 677
ba714a9c 678 return ret;
dbad75dd
KX		 679}
680
2d54067f
ML		 681static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
682{
683 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
684}
685
686static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
687{
688 return do_amd_gpio_irq_handler(-1, dev_id);
689}
690
dbad75dd
KX		 691static int amd_get_groups_count(struct pinctrl_dev *pctldev)
692{
693 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
694
695 return gpio_dev->ngroups;
696}
697
698static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
699 unsigned group)
700{
701 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
702
703 return gpio_dev->groups[group].name;
704}
705
706static int amd_get_group_pins(struct pinctrl_dev *pctldev,
707 unsigned group,
708 const unsigned **pins,
709 unsigned *num_pins)
710{
711 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
712
713 *pins = gpio_dev->groups[group].pins;
714 *num_pins = gpio_dev->groups[group].npins;
715 return 0;
716}
717
718static const struct pinctrl_ops amd_pinctrl_ops = {
719 .get_groups_count = amd_get_groups_count,
720 .get_group_name = amd_get_group_name,
721 .get_group_pins = amd_get_group_pins,
722#ifdef CONFIG_OF
723 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
d32f7fd3 724 .dt_free_map = pinctrl_utils_free_map,
dbad75dd
KX		 725#endif
726};
727
728static int amd_pinconf_get(struct pinctrl_dev *pctldev,
729 unsigned int pin,
730 unsigned long *config)
731{
732 u32 pin_reg;
733 unsigned arg;
734 unsigned long flags;
735 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
736 enum pin_config_param param = pinconf_to_config_param(*config);
737
229710fe 738 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 739 pin_reg = readl(gpio_dev->base + pin*4);
229710fe 740 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 741 switch (param) {
742 case PIN_CONFIG_INPUT_DEBOUNCE:
743 arg = pin_reg & DB_TMR_OUT_MASK;
744 break;
745
746 case PIN_CONFIG_BIAS_PULL_DOWN:
747 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
748 break;
749
750 case PIN_CONFIG_BIAS_PULL_UP:
751 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
752 break;
753
754 case PIN_CONFIG_DRIVE_STRENGTH:
755 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
756 break;
757
758 default:
759 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
760 param);
761 return -ENOTSUPP;
762 }
763
764 *config = pinconf_to_config_packed(param, arg);
765
766 return 0;
767}
768
769static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
770 unsigned long *configs, unsigned num_configs)
771{
772 int i;
dbad75dd 773 u32 arg;
25a853d0
KX		 774 int ret = 0;
775 u32 pin_reg;
dbad75dd
KX		 776 unsigned long flags;
777 enum pin_config_param param;
778 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
779
229710fe 780 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 781 for (i = 0; i < num_configs; i++) {
782 param = pinconf_to_config_param(configs[i]);
783 arg = pinconf_to_config_argument(configs[i]);
784 pin_reg = readl(gpio_dev->base + pin*4);
785
786 switch (param) {
787 case PIN_CONFIG_INPUT_DEBOUNCE:
788 pin_reg &= ~DB_TMR_OUT_MASK;
789 pin_reg |= arg & DB_TMR_OUT_MASK;
790 break;
791
792 case PIN_CONFIG_BIAS_PULL_DOWN:
793 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
794 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
795 break;
796
797 case PIN_CONFIG_BIAS_PULL_UP:
798 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
799 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
800 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
801 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
802 break;
803
804 case PIN_CONFIG_DRIVE_STRENGTH:
805 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
806 << DRV_STRENGTH_SEL_OFF);
807 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
808 << DRV_STRENGTH_SEL_OFF;
809 break;
810
811 default:
812 dev_err(&gpio_dev->pdev->dev,
813 "Invalid config param %04x\n", param);
25a853d0 814 ret = -ENOTSUPP;
dbad75dd
KX		 815 }
816
817 writel(pin_reg, gpio_dev->base + pin*4);
818 }
229710fe 819 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 820
25a853d0 821 return ret;
dbad75dd
KX		 822}
823
824static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
825 unsigned int group,
826 unsigned long *config)
827{
828 const unsigned *pins;
829 unsigned npins;
830 int ret;
831
832 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
833 if (ret)
834 return ret;
835
836 if (amd_pinconf_get(pctldev, pins[0], config))
837 return -ENOTSUPP;
838
839 return 0;
840}
841
842static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
843 unsigned group, unsigned long *configs,
844 unsigned num_configs)
845{
846 const unsigned *pins;
847 unsigned npins;
848 int i, ret;
849
850 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
851 if (ret)
852 return ret;
853 for (i = 0; i < npins; i++) {
854 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
855 return -ENOTSUPP;
856 }
857 return 0;
858}
859
860static const struct pinconf_ops amd_pinconf_ops = {
861 .pin_config_get = amd_pinconf_get,
862 .pin_config_set = amd_pinconf_set,
863 .pin_config_group_get = amd_pinconf_group_get,
864 .pin_config_group_set = amd_pinconf_group_set,
865};
866
4e5a04be
SK		 867static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
868{
869 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
870 unsigned long flags;
871 u32 pin_reg, mask;
872 int i;
873
874 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
875 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
876 BIT(WAKE_CNTRL_OFF_S4);
877
878 for (i = 0; i < desc->npins; i++) {
879 int pin = desc->pins[i].number;
880 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
881
882 if (!pd)
883 continue;
884
885 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
886
887 pin_reg = readl(gpio_dev->base + i * 4);
888 pin_reg &= ~mask;
889 writel(pin_reg, gpio_dev->base + i * 4);
890
891 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
892 }
893}
894
79d2c8be
DD		 895#ifdef CONFIG_PM_SLEEP
896static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
897{
898 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
899
900 if (!pd)
901 return false;
902
903 /*
904 * Only restore the pin if it is actually in use by the kernel (or
905 * by userspace).
906 */
907 if (pd->mux_owner || pd->gpio_owner ||
908 gpiochip_line_is_irq(&gpio_dev->gc, pin))
909 return true;
910
911 return false;
912}
913
2d71dfa2 914static int amd_gpio_suspend(struct device *dev)
79d2c8be 915{
9f540c3e 916 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
79d2c8be 917 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
b8c824a8 918 unsigned long flags;
79d2c8be
DD		 919 int i;
920
921 for (i = 0; i < desc->npins; i++) {
922 int pin = desc->pins[i].number;
923
924 if (!amd_gpio_should_save(gpio_dev, pin))
925 continue;
926
b8c824a8
BN		 927 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
928 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
929 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
79d2c8be
DD		 930 }
931
932 return 0;
933}
934
2d71dfa2 935static int amd_gpio_resume(struct device *dev)
79d2c8be 936{
9f540c3e 937 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
79d2c8be 938 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
b8c824a8 939 unsigned long flags;
79d2c8be
DD		 940 int i;
941
942 for (i = 0; i < desc->npins; i++) {
943 int pin = desc->pins[i].number;
944
945 if (!amd_gpio_should_save(gpio_dev, pin))
946 continue;
947
b8c824a8
BN		 948 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
949 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
950 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
951 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
79d2c8be
DD		 952 }
953
954 return 0;
955}
956
957static const struct dev_pm_ops amd_gpio_pm_ops = {
958 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
959 amd_gpio_resume)
960};
961#endif
962
72440158
BN		 963static int amd_get_functions_count(struct pinctrl_dev *pctldev)
964{
965 return ARRAY_SIZE(pmx_functions);
966}
967
968static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
969{
970 return pmx_functions[selector].name;
971}
972
973static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
974 const char * const **groups,
975 unsigned int * const num_groups)
976{
977 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
978
979 if (!gpio_dev->iomux_base) {
980 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
981 return -EINVAL;
982 }
983
984 *groups = pmx_functions[selector].groups;
985 *num_groups = pmx_functions[selector].ngroups;
986 return 0;
987}
988
989static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
990{
991 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
992 struct device *dev = &gpio_dev->pdev->dev;
993 struct pin_desc *pd;
994 int ind, index;
995
996 if (!gpio_dev->iomux_base)
997 return -EINVAL;
998
999 for (index = 0; index < NSELECTS; index++) {
1000 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
1001 continue;
1002
1003 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
1004 FUNCTION_INVALID) {
1005 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1006 pmx_functions[function].index);
1007 return -EINVAL;
1008 }
1009
1010 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
1011
1012 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
1013 FUNCTION_MASK)) {
1014 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1015 pmx_functions[function].index);
1016 return -EINVAL;
1017 }
1018
1019 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
1020 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
1021 continue;
1022
1023 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
1024 pd->mux_owner = gpio_dev->groups[group].name;
1025 }
1026 break;
1027 }
1028
1029 return 0;
1030}
1031
1032static const struct pinmux_ops amd_pmxops = {
1033 .get_functions_count = amd_get_functions_count,
1034 .get_function_name = amd_get_fname,
1035 .get_function_groups = amd_get_groups,
1036 .set_mux = amd_set_mux,
1037};
1038
dbad75dd
KX		 1039static struct pinctrl_desc amd_pinctrl_desc = {
1040 .pins = kerncz_pins,
1041 .npins = ARRAY_SIZE(kerncz_pins),
1042 .pctlops = &amd_pinctrl_ops,
72440158 1043 .pmxops = &amd_pmxops,
dbad75dd
KX		 1044 .confops = &amd_pinconf_ops,
1045 .owner = THIS_MODULE,
1046};
1047
79bb5c7f
BN		 1048static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
1049{
1050 struct pinctrl_desc *desc = &amd_pinctrl_desc;
1051 struct device *dev = &gpio_dev->pdev->dev;
1052 int index;
1053
1054 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
1055 if (index < 0) {
3160b37e 1056 dev_dbg(dev, "iomux not supported\n");
79bb5c7f
BN		 1057 goto out_no_pinmux;
1058 }
1059
1060 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
1061 if (IS_ERR(gpio_dev->iomux_base)) {
3160b37e 1062 dev_dbg(dev, "iomux not supported %d io resource\n", index);
79bb5c7f
BN		 1063 goto out_no_pinmux;
1064 }
1065
1066 return;
1067
1068out_no_pinmux:
1069 desc->pmxops = NULL;
1070}
1071
dbad75dd
KX		 1072static int amd_gpio_probe(struct platform_device *pdev)
1073{
1074 int ret = 0;
dbad75dd
KX		 1075 struct resource *res;
1076 struct amd_gpio *gpio_dev;
e81376eb 1077 struct gpio_irq_chip *girq;
dbad75dd
KX		 1078
1079 gpio_dev = devm_kzalloc(&pdev->dev,
1080 sizeof(struct amd_gpio), GFP_KERNEL);
1081 if (!gpio_dev)
1082 return -ENOMEM;
1083
229710fe 1084 raw_spin_lock_init(&gpio_dev->lock);
dbad75dd 1085
21793d22
BN		 1086 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1087 if (IS_ERR(gpio_dev->base)) {
dbad75dd 1088 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
21793d22 1089 return PTR_ERR(gpio_dev->base);
dbad75dd
KX		 1090 }
1091
7e6f8d6f
BN		 1092 gpio_dev->irq = platform_get_irq(pdev, 0);
1093 if (gpio_dev->irq < 0)
1094 return gpio_dev->irq;
dbad75dd 1095
79d2c8be
DD		 1096#ifdef CONFIG_PM_SLEEP
1097 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
1098 sizeof(*gpio_dev->saved_regs),
1099 GFP_KERNEL);
1100 if (!gpio_dev->saved_regs)
1101 return -ENOMEM;
1102#endif
1103
dbad75dd 1104 gpio_dev->pdev = pdev;
12b10f47 1105 gpio_dev->gc.get_direction = amd_gpio_get_direction;
dbad75dd
KX		 1106 gpio_dev->gc.direction_input = amd_gpio_direction_input;
1107 gpio_dev->gc.direction_output = amd_gpio_direction_output;
1108 gpio_dev->gc.get = amd_gpio_get_value;
1109 gpio_dev->gc.set = amd_gpio_set_value;
2956b5d9 1110 gpio_dev->gc.set_config = amd_gpio_set_config;
dbad75dd
KX		 1111 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
1112
3bfd4430 1113 gpio_dev->gc.base = -1;
dbad75dd
KX		 1114 gpio_dev->gc.label = pdev->name;
1115 gpio_dev->gc.owner = THIS_MODULE;
58383c78 1116 gpio_dev->gc.parent = &pdev->dev;
3bfd4430 1117 gpio_dev->gc.ngpio = resource_size(res) / 4;
dbad75dd 1118
3bfd4430 1119 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
dbad75dd
KX		 1120 gpio_dev->groups = kerncz_groups;
1121 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1122
1123 amd_pinctrl_desc.name = dev_name(&pdev->dev);
79bb5c7f 1124 amd_get_iomux_res(gpio_dev);
251e22ab
LD		 1125 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1126 gpio_dev);
323de9ef 1127 if (IS_ERR(gpio_dev->pctrl)) {
dbad75dd 1128 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
323de9ef 1129 return PTR_ERR(gpio_dev->pctrl);
dbad75dd
KX		 1130 }
1131
4e5a04be
SK		 1132 /* Disable and mask interrupts */
1133 amd_gpio_irq_init(gpio_dev);
1134
e81376eb 1135 girq = &gpio_dev->gc.irq;
6173e56f 1136 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
e81376eb
LW		 1137 /* This will let us handle the parent IRQ in the driver */
1138 girq->parent_handler = NULL;
1139 girq->num_parents = 0;
1140 girq->parents = NULL;
1141 girq->default_type = IRQ_TYPE_NONE;
1142 girq->handler = handle_simple_irq;
1143
04d36723 1144 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
dbad75dd 1145 if (ret)
251e22ab 1146 return ret;
dbad75dd
KX		 1147
1148 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
3bfd4430 1149 0, 0, gpio_dev->gc.ngpio);
dbad75dd
KX		 1150 if (ret) {
1151 dev_err(&pdev->dev, "Failed to add pin range\n");
1152 goto out2;
1153 }
1154
7e6f8d6f 1155 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
279ffafa 1156 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
ba714a9c
TG		 1157 if (ret)
1158 goto out2;
1159
dbad75dd 1160 platform_set_drvdata(pdev, gpio_dev);
2d54067f 1161 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
dbad75dd
KX		 1162
1163 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1164 return ret;
1165
1166out2:
1167 gpiochip_remove(&gpio_dev->gc);
1168
dbad75dd
KX		 1169 return ret;
1170}
1171
1172static int amd_gpio_remove(struct platform_device *pdev)
1173{
1174 struct amd_gpio *gpio_dev;
1175
1176 gpio_dev = platform_get_drvdata(pdev);
1177
1178 gpiochip_remove(&gpio_dev->gc);
2d54067f 1179 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
dbad75dd
KX		 1180
1181 return 0;
1182}
1183
de4334f7 1184#ifdef CONFIG_ACPI
dbad75dd
KX		 1185static const struct acpi_device_id amd_gpio_acpi_match[] = {
1186 { "AMD0030", 0 },
42a44402 1187 { "AMDI0030", 0},
1ca46d3e 1188 { "AMDI0031", 0},
dbad75dd
KX		 1189 { },
1190};
1191MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
de4334f7 1192#endif
dbad75dd
KX		 1193
1194static struct platform_driver amd_gpio_driver = {
1195 .driver = {
1196 .name = "amd_gpio",
dbad75dd 1197 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
79d2c8be
DD		 1198#ifdef CONFIG_PM_SLEEP
1199 .pm = &amd_gpio_pm_ops,
1200#endif
dbad75dd
KX		 1201 },
1202 .probe = amd_gpio_probe,
1203 .remove = amd_gpio_remove,
1204};
1205
1206module_platform_driver(amd_gpio_driver);
1207
1208MODULE_LICENSE("GPL v2");
1209MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1210MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux 6.x block layer and io_uring tree(s)