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dbad75dd KX |
1 | /* |
2 | * GPIO driver for AMD | |
3 | * | |
4 | * Copyright (c) 2014,2015 AMD Corporation. | |
5 | * Authors: Ken Xue <Ken.Xue@amd.com> | |
6 | * Wu, Jeff <Jeff.Wu@amd.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/err.h> | |
14 | #include <linux/bug.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/compiler.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/log2.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/gpio.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/mutex.h> | |
27 | #include <linux/acpi.h> | |
28 | #include <linux/seq_file.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/list.h> | |
31 | #include <linux/bitops.h> | |
dbad75dd KX |
32 | #include <linux/pinctrl/pinconf.h> |
33 | #include <linux/pinctrl/pinconf-generic.h> | |
34 | ||
35 | #include "pinctrl-utils.h" | |
36 | #include "pinctrl-amd.h" | |
37 | ||
dbad75dd KX |
38 | static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) |
39 | { | |
40 | unsigned long flags; | |
41 | u32 pin_reg; | |
04d36723 | 42 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
43 | |
44 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
45 | pin_reg = readl(gpio_dev->base + offset * 4); | |
dbad75dd KX |
46 | pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); |
47 | writel(pin_reg, gpio_dev->base + offset * 4); | |
48 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
49 | ||
50 | return 0; | |
51 | } | |
52 | ||
53 | static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, | |
54 | int value) | |
55 | { | |
56 | u32 pin_reg; | |
57 | unsigned long flags; | |
04d36723 | 58 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
59 | |
60 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
61 | pin_reg = readl(gpio_dev->base + offset * 4); | |
62 | pin_reg |= BIT(OUTPUT_ENABLE_OFF); | |
63 | if (value) | |
64 | pin_reg |= BIT(OUTPUT_VALUE_OFF); | |
65 | else | |
66 | pin_reg &= ~BIT(OUTPUT_VALUE_OFF); | |
67 | writel(pin_reg, gpio_dev->base + offset * 4); | |
68 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
69 | ||
70 | return 0; | |
71 | } | |
72 | ||
73 | static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) | |
74 | { | |
75 | u32 pin_reg; | |
76 | unsigned long flags; | |
04d36723 | 77 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
78 | |
79 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
80 | pin_reg = readl(gpio_dev->base + offset * 4); | |
81 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
82 | ||
83 | return !!(pin_reg & BIT(PIN_STS_OFF)); | |
84 | } | |
85 | ||
86 | static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) | |
87 | { | |
88 | u32 pin_reg; | |
89 | unsigned long flags; | |
04d36723 | 90 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
91 | |
92 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
93 | pin_reg = readl(gpio_dev->base + offset * 4); | |
94 | if (value) | |
95 | pin_reg |= BIT(OUTPUT_VALUE_OFF); | |
96 | else | |
97 | pin_reg &= ~BIT(OUTPUT_VALUE_OFF); | |
98 | writel(pin_reg, gpio_dev->base + offset * 4); | |
99 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
100 | } | |
101 | ||
102 | static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, | |
103 | unsigned debounce) | |
104 | { | |
dbad75dd | 105 | u32 time; |
25a853d0 KX |
106 | u32 pin_reg; |
107 | int ret = 0; | |
dbad75dd | 108 | unsigned long flags; |
04d36723 | 109 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
110 | |
111 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
112 | pin_reg = readl(gpio_dev->base + offset * 4); | |
113 | ||
114 | if (debounce) { | |
115 | pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; | |
116 | pin_reg &= ~DB_TMR_OUT_MASK; | |
117 | /* | |
118 | Debounce Debounce Timer Max | |
119 | TmrLarge TmrOutUnit Unit Debounce | |
120 | Time | |
121 | 0 0 61 usec (2 RtcClk) 976 usec | |
122 | 0 1 244 usec (8 RtcClk) 3.9 msec | |
123 | 1 0 15.6 msec (512 RtcClk) 250 msec | |
124 | 1 1 62.5 msec (2048 RtcClk) 1 sec | |
125 | */ | |
126 | ||
127 | if (debounce < 61) { | |
128 | pin_reg |= 1; | |
129 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
130 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
131 | } else if (debounce < 976) { | |
132 | time = debounce / 61; | |
133 | pin_reg |= time & DB_TMR_OUT_MASK; | |
134 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
135 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
136 | } else if (debounce < 3900) { | |
137 | time = debounce / 244; | |
138 | pin_reg |= time & DB_TMR_OUT_MASK; | |
139 | pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); | |
140 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
141 | } else if (debounce < 250000) { | |
142 | time = debounce / 15600; | |
143 | pin_reg |= time & DB_TMR_OUT_MASK; | |
144 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
145 | pin_reg |= BIT(DB_TMR_LARGE_OFF); | |
146 | } else if (debounce < 1000000) { | |
147 | time = debounce / 62500; | |
148 | pin_reg |= time & DB_TMR_OUT_MASK; | |
149 | pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); | |
150 | pin_reg |= BIT(DB_TMR_LARGE_OFF); | |
151 | } else { | |
152 | pin_reg &= ~DB_CNTRl_MASK; | |
25a853d0 | 153 | ret = -EINVAL; |
dbad75dd KX |
154 | } |
155 | } else { | |
156 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
157 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
158 | pin_reg &= ~DB_TMR_OUT_MASK; | |
159 | pin_reg &= ~DB_CNTRl_MASK; | |
160 | } | |
161 | writel(pin_reg, gpio_dev->base + offset * 4); | |
162 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
163 | ||
25a853d0 | 164 | return ret; |
dbad75dd KX |
165 | } |
166 | ||
167 | #ifdef CONFIG_DEBUG_FS | |
168 | static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) | |
169 | { | |
170 | u32 pin_reg; | |
171 | unsigned long flags; | |
172 | unsigned int bank, i, pin_num; | |
04d36723 | 173 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
174 | |
175 | char *level_trig; | |
176 | char *active_level; | |
177 | char *interrupt_enable; | |
178 | char *interrupt_mask; | |
179 | char *wake_cntrl0; | |
180 | char *wake_cntrl1; | |
181 | char *wake_cntrl2; | |
182 | char *pin_sts; | |
183 | char *pull_up_sel; | |
184 | char *pull_up_enable; | |
185 | char *pull_down_enable; | |
186 | char *output_value; | |
187 | char *output_enable; | |
188 | ||
189 | for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) { | |
190 | seq_printf(s, "GPIO bank%d\t", bank); | |
191 | ||
192 | switch (bank) { | |
193 | case 0: | |
194 | i = 0; | |
195 | pin_num = AMD_GPIO_PINS_BANK0; | |
196 | break; | |
197 | case 1: | |
198 | i = 64; | |
199 | pin_num = AMD_GPIO_PINS_BANK1 + i; | |
200 | break; | |
201 | case 2: | |
202 | i = 128; | |
203 | pin_num = AMD_GPIO_PINS_BANK2 + i; | |
204 | break; | |
205 | } | |
206 | ||
207 | for (; i < pin_num; i++) { | |
208 | seq_printf(s, "pin%d\t", i); | |
209 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
210 | pin_reg = readl(gpio_dev->base + i * 4); | |
211 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
212 | ||
213 | if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { | |
214 | interrupt_enable = "interrupt is enabled|"; | |
215 | ||
216 | if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) | |
217 | && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) | |
218 | active_level = "Active low|"; | |
219 | else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) | |
220 | && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) | |
221 | active_level = "Active high|"; | |
222 | else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) | |
223 | && pin_reg & BIT(ACTIVE_LEVEL_OFF+1)) | |
224 | active_level = "Active on both|"; | |
225 | else | |
226 | active_level = "Unknow Active level|"; | |
227 | ||
228 | if (pin_reg & BIT(LEVEL_TRIG_OFF)) | |
229 | level_trig = "Level trigger|"; | |
230 | else | |
231 | level_trig = "Edge trigger|"; | |
232 | ||
233 | } else { | |
234 | interrupt_enable = | |
235 | "interrupt is disabled|"; | |
236 | active_level = " "; | |
237 | level_trig = " "; | |
238 | } | |
239 | ||
240 | if (pin_reg & BIT(INTERRUPT_MASK_OFF)) | |
241 | interrupt_mask = | |
242 | "interrupt is unmasked|"; | |
243 | else | |
244 | interrupt_mask = | |
245 | "interrupt is masked|"; | |
246 | ||
247 | if (pin_reg & BIT(WAKE_CNTRL_OFF)) | |
248 | wake_cntrl0 = "enable wakeup in S0i3 state|"; | |
249 | else | |
250 | wake_cntrl0 = "disable wakeup in S0i3 state|"; | |
251 | ||
252 | if (pin_reg & BIT(WAKE_CNTRL_OFF)) | |
253 | wake_cntrl1 = "enable wakeup in S3 state|"; | |
254 | else | |
255 | wake_cntrl1 = "disable wakeup in S3 state|"; | |
256 | ||
257 | if (pin_reg & BIT(WAKE_CNTRL_OFF)) | |
258 | wake_cntrl2 = "enable wakeup in S4/S5 state|"; | |
259 | else | |
260 | wake_cntrl2 = "disable wakeup in S4/S5 state|"; | |
261 | ||
262 | if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { | |
263 | pull_up_enable = "pull-up is enabled|"; | |
264 | if (pin_reg & BIT(PULL_UP_SEL_OFF)) | |
265 | pull_up_sel = "8k pull-up|"; | |
266 | else | |
267 | pull_up_sel = "4k pull-up|"; | |
268 | } else { | |
269 | pull_up_enable = "pull-up is disabled|"; | |
270 | pull_up_sel = " "; | |
271 | } | |
272 | ||
273 | if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) | |
274 | pull_down_enable = "pull-down is enabled|"; | |
275 | else | |
276 | pull_down_enable = "Pull-down is disabled|"; | |
277 | ||
278 | if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { | |
279 | pin_sts = " "; | |
280 | output_enable = "output is enabled|"; | |
281 | if (pin_reg & BIT(OUTPUT_VALUE_OFF)) | |
282 | output_value = "output is high|"; | |
283 | else | |
284 | output_value = "output is low|"; | |
285 | } else { | |
286 | output_enable = "output is disabled|"; | |
287 | output_value = " "; | |
288 | ||
289 | if (pin_reg & BIT(PIN_STS_OFF)) | |
290 | pin_sts = "input is high|"; | |
291 | else | |
292 | pin_sts = "input is low|"; | |
293 | } | |
294 | ||
295 | seq_printf(s, "%s %s %s %s %s %s\n" | |
296 | " %s %s %s %s %s %s %s 0x%x\n", | |
297 | level_trig, active_level, interrupt_enable, | |
298 | interrupt_mask, wake_cntrl0, wake_cntrl1, | |
299 | wake_cntrl2, pin_sts, pull_up_sel, | |
300 | pull_up_enable, pull_down_enable, | |
301 | output_value, output_enable, pin_reg); | |
302 | } | |
303 | } | |
304 | } | |
305 | #else | |
306 | #define amd_gpio_dbg_show NULL | |
307 | #endif | |
308 | ||
309 | static void amd_gpio_irq_enable(struct irq_data *d) | |
310 | { | |
311 | u32 pin_reg; | |
312 | unsigned long flags; | |
313 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 314 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
315 | |
316 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
317 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
dbad75dd KX |
318 | pin_reg |= BIT(INTERRUPT_ENABLE_OFF); |
319 | pin_reg |= BIT(INTERRUPT_MASK_OFF); | |
320 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
321 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
322 | } | |
323 | ||
324 | static void amd_gpio_irq_disable(struct irq_data *d) | |
325 | { | |
326 | u32 pin_reg; | |
327 | unsigned long flags; | |
328 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 329 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
330 | |
331 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
332 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
333 | pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); | |
334 | pin_reg &= ~BIT(INTERRUPT_MASK_OFF); | |
335 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
336 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
337 | } | |
338 | ||
339 | static void amd_gpio_irq_mask(struct irq_data *d) | |
340 | { | |
341 | u32 pin_reg; | |
342 | unsigned long flags; | |
343 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 344 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
345 | |
346 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
347 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
348 | pin_reg &= ~BIT(INTERRUPT_MASK_OFF); | |
349 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
350 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
351 | } | |
352 | ||
353 | static void amd_gpio_irq_unmask(struct irq_data *d) | |
354 | { | |
355 | u32 pin_reg; | |
356 | unsigned long flags; | |
357 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 358 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
359 | |
360 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
361 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
362 | pin_reg |= BIT(INTERRUPT_MASK_OFF); | |
363 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
364 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
365 | } | |
366 | ||
367 | static void amd_gpio_irq_eoi(struct irq_data *d) | |
368 | { | |
369 | u32 reg; | |
370 | unsigned long flags; | |
371 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 372 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
373 | |
374 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
375 | reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); | |
376 | reg |= EOI_MASK; | |
377 | writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); | |
378 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
379 | } | |
380 | ||
381 | static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
382 | { | |
383 | int ret = 0; | |
384 | u32 pin_reg; | |
385 | unsigned long flags; | |
386 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 387 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
388 | |
389 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
390 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
391 | ||
392 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
393 | case IRQ_TYPE_EDGE_RISING: | |
394 | pin_reg &= ~BIT(LEVEL_TRIG_OFF); | |
395 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
396 | pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; | |
397 | pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 398 | irq_set_handler_locked(d, handle_edge_irq); |
dbad75dd KX |
399 | break; |
400 | ||
401 | case IRQ_TYPE_EDGE_FALLING: | |
402 | pin_reg &= ~BIT(LEVEL_TRIG_OFF); | |
403 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
404 | pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; | |
405 | pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 406 | irq_set_handler_locked(d, handle_edge_irq); |
dbad75dd KX |
407 | break; |
408 | ||
409 | case IRQ_TYPE_EDGE_BOTH: | |
410 | pin_reg &= ~BIT(LEVEL_TRIG_OFF); | |
411 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
412 | pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; | |
413 | pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 414 | irq_set_handler_locked(d, handle_edge_irq); |
dbad75dd KX |
415 | break; |
416 | ||
417 | case IRQ_TYPE_LEVEL_HIGH: | |
418 | pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; | |
419 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
420 | pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; | |
421 | pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); | |
422 | pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 423 | irq_set_handler_locked(d, handle_level_irq); |
dbad75dd KX |
424 | break; |
425 | ||
426 | case IRQ_TYPE_LEVEL_LOW: | |
427 | pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; | |
428 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
429 | pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; | |
430 | pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); | |
431 | pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 432 | irq_set_handler_locked(d, handle_level_irq); |
dbad75dd KX |
433 | break; |
434 | ||
435 | case IRQ_TYPE_NONE: | |
436 | break; | |
437 | ||
438 | default: | |
439 | dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); | |
440 | ret = -EINVAL; | |
dbad75dd KX |
441 | } |
442 | ||
443 | pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; | |
444 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
445 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
446 | ||
dbad75dd KX |
447 | return ret; |
448 | } | |
449 | ||
450 | static void amd_irq_ack(struct irq_data *d) | |
451 | { | |
452 | /* | |
453 | * based on HW design,there is no need to ack HW | |
454 | * before handle current irq. But this routine is | |
455 | * necessary for handle_edge_irq | |
456 | */ | |
457 | } | |
458 | ||
459 | static struct irq_chip amd_gpio_irqchip = { | |
460 | .name = "amd_gpio", | |
461 | .irq_ack = amd_irq_ack, | |
462 | .irq_enable = amd_gpio_irq_enable, | |
463 | .irq_disable = amd_gpio_irq_disable, | |
464 | .irq_mask = amd_gpio_irq_mask, | |
465 | .irq_unmask = amd_gpio_irq_unmask, | |
466 | .irq_eoi = amd_gpio_irq_eoi, | |
467 | .irq_set_type = amd_gpio_irq_set_type, | |
468 | }; | |
469 | ||
bd0b9ac4 | 470 | static void amd_gpio_irq_handler(struct irq_desc *desc) |
dbad75dd KX |
471 | { |
472 | u32 i; | |
473 | u32 off; | |
474 | u32 reg; | |
475 | u32 pin_reg; | |
476 | u64 reg64; | |
477 | int handled = 0; | |
bd0b9ac4 | 478 | unsigned int irq; |
dbad75dd | 479 | unsigned long flags; |
5663bb27 | 480 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dbad75dd | 481 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
04d36723 | 482 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
483 | |
484 | chained_irq_enter(chip, desc); | |
485 | /*enable GPIO interrupt again*/ | |
486 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
487 | reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); | |
488 | reg64 = reg; | |
489 | reg64 = reg64 << 32; | |
490 | ||
491 | reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); | |
492 | reg64 |= reg; | |
493 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
494 | ||
495 | /* | |
496 | * first 46 bits indicates interrupt status. | |
497 | * one bit represents four interrupt sources. | |
498 | */ | |
499 | for (off = 0; off < 46 ; off++) { | |
500 | if (reg64 & BIT(off)) { | |
501 | for (i = 0; i < 4; i++) { | |
502 | pin_reg = readl(gpio_dev->base + | |
503 | (off * 4 + i) * 4); | |
504 | if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || | |
505 | (pin_reg & BIT(WAKE_STS_OFF))) { | |
506 | irq = irq_find_mapping(gc->irqdomain, | |
507 | off * 4 + i); | |
508 | generic_handle_irq(irq); | |
509 | writel(pin_reg, | |
510 | gpio_dev->base | |
511 | + (off * 4 + i) * 4); | |
512 | handled++; | |
513 | } | |
514 | } | |
515 | } | |
516 | } | |
517 | ||
518 | if (handled == 0) | |
bd0b9ac4 | 519 | handle_bad_irq(desc); |
dbad75dd KX |
520 | |
521 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
522 | reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); | |
523 | reg |= EOI_MASK; | |
524 | writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); | |
525 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
526 | ||
527 | chained_irq_exit(chip, desc); | |
528 | } | |
529 | ||
530 | static int amd_get_groups_count(struct pinctrl_dev *pctldev) | |
531 | { | |
532 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
533 | ||
534 | return gpio_dev->ngroups; | |
535 | } | |
536 | ||
537 | static const char *amd_get_group_name(struct pinctrl_dev *pctldev, | |
538 | unsigned group) | |
539 | { | |
540 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
541 | ||
542 | return gpio_dev->groups[group].name; | |
543 | } | |
544 | ||
545 | static int amd_get_group_pins(struct pinctrl_dev *pctldev, | |
546 | unsigned group, | |
547 | const unsigned **pins, | |
548 | unsigned *num_pins) | |
549 | { | |
550 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
551 | ||
552 | *pins = gpio_dev->groups[group].pins; | |
553 | *num_pins = gpio_dev->groups[group].npins; | |
554 | return 0; | |
555 | } | |
556 | ||
557 | static const struct pinctrl_ops amd_pinctrl_ops = { | |
558 | .get_groups_count = amd_get_groups_count, | |
559 | .get_group_name = amd_get_group_name, | |
560 | .get_group_pins = amd_get_group_pins, | |
561 | #ifdef CONFIG_OF | |
562 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
d32f7fd3 | 563 | .dt_free_map = pinctrl_utils_free_map, |
dbad75dd KX |
564 | #endif |
565 | }; | |
566 | ||
567 | static int amd_pinconf_get(struct pinctrl_dev *pctldev, | |
568 | unsigned int pin, | |
569 | unsigned long *config) | |
570 | { | |
571 | u32 pin_reg; | |
572 | unsigned arg; | |
573 | unsigned long flags; | |
574 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
575 | enum pin_config_param param = pinconf_to_config_param(*config); | |
576 | ||
577 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
578 | pin_reg = readl(gpio_dev->base + pin*4); | |
579 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
580 | switch (param) { | |
581 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
582 | arg = pin_reg & DB_TMR_OUT_MASK; | |
583 | break; | |
584 | ||
585 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
586 | arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); | |
587 | break; | |
588 | ||
589 | case PIN_CONFIG_BIAS_PULL_UP: | |
590 | arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); | |
591 | break; | |
592 | ||
593 | case PIN_CONFIG_DRIVE_STRENGTH: | |
594 | arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; | |
595 | break; | |
596 | ||
597 | default: | |
598 | dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", | |
599 | param); | |
600 | return -ENOTSUPP; | |
601 | } | |
602 | ||
603 | *config = pinconf_to_config_packed(param, arg); | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
608 | static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
609 | unsigned long *configs, unsigned num_configs) | |
610 | { | |
611 | int i; | |
dbad75dd | 612 | u32 arg; |
25a853d0 KX |
613 | int ret = 0; |
614 | u32 pin_reg; | |
dbad75dd KX |
615 | unsigned long flags; |
616 | enum pin_config_param param; | |
617 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
618 | ||
619 | spin_lock_irqsave(&gpio_dev->lock, flags); | |
620 | for (i = 0; i < num_configs; i++) { | |
621 | param = pinconf_to_config_param(configs[i]); | |
622 | arg = pinconf_to_config_argument(configs[i]); | |
623 | pin_reg = readl(gpio_dev->base + pin*4); | |
624 | ||
625 | switch (param) { | |
626 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
627 | pin_reg &= ~DB_TMR_OUT_MASK; | |
628 | pin_reg |= arg & DB_TMR_OUT_MASK; | |
629 | break; | |
630 | ||
631 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
632 | pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); | |
633 | pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; | |
634 | break; | |
635 | ||
636 | case PIN_CONFIG_BIAS_PULL_UP: | |
637 | pin_reg &= ~BIT(PULL_UP_SEL_OFF); | |
638 | pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; | |
639 | pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); | |
640 | pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; | |
641 | break; | |
642 | ||
643 | case PIN_CONFIG_DRIVE_STRENGTH: | |
644 | pin_reg &= ~(DRV_STRENGTH_SEL_MASK | |
645 | << DRV_STRENGTH_SEL_OFF); | |
646 | pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) | |
647 | << DRV_STRENGTH_SEL_OFF; | |
648 | break; | |
649 | ||
650 | default: | |
651 | dev_err(&gpio_dev->pdev->dev, | |
652 | "Invalid config param %04x\n", param); | |
25a853d0 | 653 | ret = -ENOTSUPP; |
dbad75dd KX |
654 | } |
655 | ||
656 | writel(pin_reg, gpio_dev->base + pin*4); | |
657 | } | |
658 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
659 | ||
25a853d0 | 660 | return ret; |
dbad75dd KX |
661 | } |
662 | ||
663 | static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, | |
664 | unsigned int group, | |
665 | unsigned long *config) | |
666 | { | |
667 | const unsigned *pins; | |
668 | unsigned npins; | |
669 | int ret; | |
670 | ||
671 | ret = amd_get_group_pins(pctldev, group, &pins, &npins); | |
672 | if (ret) | |
673 | return ret; | |
674 | ||
675 | if (amd_pinconf_get(pctldev, pins[0], config)) | |
676 | return -ENOTSUPP; | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
681 | static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, | |
682 | unsigned group, unsigned long *configs, | |
683 | unsigned num_configs) | |
684 | { | |
685 | const unsigned *pins; | |
686 | unsigned npins; | |
687 | int i, ret; | |
688 | ||
689 | ret = amd_get_group_pins(pctldev, group, &pins, &npins); | |
690 | if (ret) | |
691 | return ret; | |
692 | for (i = 0; i < npins; i++) { | |
693 | if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) | |
694 | return -ENOTSUPP; | |
695 | } | |
696 | return 0; | |
697 | } | |
698 | ||
699 | static const struct pinconf_ops amd_pinconf_ops = { | |
700 | .pin_config_get = amd_pinconf_get, | |
701 | .pin_config_set = amd_pinconf_set, | |
702 | .pin_config_group_get = amd_pinconf_group_get, | |
703 | .pin_config_group_set = amd_pinconf_group_set, | |
704 | }; | |
705 | ||
706 | static struct pinctrl_desc amd_pinctrl_desc = { | |
707 | .pins = kerncz_pins, | |
708 | .npins = ARRAY_SIZE(kerncz_pins), | |
709 | .pctlops = &amd_pinctrl_ops, | |
710 | .confops = &amd_pinconf_ops, | |
711 | .owner = THIS_MODULE, | |
712 | }; | |
713 | ||
714 | static int amd_gpio_probe(struct platform_device *pdev) | |
715 | { | |
716 | int ret = 0; | |
25a853d0 | 717 | int irq_base; |
dbad75dd KX |
718 | struct resource *res; |
719 | struct amd_gpio *gpio_dev; | |
720 | ||
721 | gpio_dev = devm_kzalloc(&pdev->dev, | |
722 | sizeof(struct amd_gpio), GFP_KERNEL); | |
723 | if (!gpio_dev) | |
724 | return -ENOMEM; | |
725 | ||
726 | spin_lock_init(&gpio_dev->lock); | |
727 | ||
728 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
729 | if (!res) { | |
730 | dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); | |
731 | return -EINVAL; | |
732 | } | |
733 | ||
734 | gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, | |
735 | resource_size(res)); | |
424a6c60 WY |
736 | if (!gpio_dev->base) |
737 | return -ENOMEM; | |
dbad75dd KX |
738 | |
739 | irq_base = platform_get_irq(pdev, 0); | |
740 | if (irq_base < 0) { | |
741 | dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); | |
742 | return -EINVAL; | |
743 | } | |
744 | ||
745 | gpio_dev->pdev = pdev; | |
746 | gpio_dev->gc.direction_input = amd_gpio_direction_input; | |
747 | gpio_dev->gc.direction_output = amd_gpio_direction_output; | |
748 | gpio_dev->gc.get = amd_gpio_get_value; | |
749 | gpio_dev->gc.set = amd_gpio_set_value; | |
750 | gpio_dev->gc.set_debounce = amd_gpio_set_debounce; | |
751 | gpio_dev->gc.dbg_show = amd_gpio_dbg_show; | |
752 | ||
753 | gpio_dev->gc.base = 0; | |
754 | gpio_dev->gc.label = pdev->name; | |
755 | gpio_dev->gc.owner = THIS_MODULE; | |
58383c78 | 756 | gpio_dev->gc.parent = &pdev->dev; |
dbad75dd KX |
757 | gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS; |
758 | #if defined(CONFIG_OF_GPIO) | |
759 | gpio_dev->gc.of_node = pdev->dev.of_node; | |
760 | #endif | |
761 | ||
762 | gpio_dev->groups = kerncz_groups; | |
763 | gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); | |
764 | ||
765 | amd_pinctrl_desc.name = dev_name(&pdev->dev); | |
251e22ab LD |
766 | gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, |
767 | gpio_dev); | |
323de9ef | 768 | if (IS_ERR(gpio_dev->pctrl)) { |
dbad75dd | 769 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
323de9ef | 770 | return PTR_ERR(gpio_dev->pctrl); |
dbad75dd KX |
771 | } |
772 | ||
04d36723 | 773 | ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); |
dbad75dd | 774 | if (ret) |
251e22ab | 775 | return ret; |
dbad75dd KX |
776 | |
777 | ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), | |
778 | 0, 0, TOTAL_NUMBER_OF_PINS); | |
779 | if (ret) { | |
780 | dev_err(&pdev->dev, "Failed to add pin range\n"); | |
781 | goto out2; | |
782 | } | |
783 | ||
784 | ret = gpiochip_irqchip_add(&gpio_dev->gc, | |
785 | &amd_gpio_irqchip, | |
786 | 0, | |
787 | handle_simple_irq, | |
788 | IRQ_TYPE_NONE); | |
789 | if (ret) { | |
790 | dev_err(&pdev->dev, "could not add irqchip\n"); | |
791 | ret = -ENODEV; | |
792 | goto out2; | |
793 | } | |
794 | ||
795 | gpiochip_set_chained_irqchip(&gpio_dev->gc, | |
796 | &amd_gpio_irqchip, | |
797 | irq_base, | |
798 | amd_gpio_irq_handler); | |
799 | ||
800 | platform_set_drvdata(pdev, gpio_dev); | |
801 | ||
802 | dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); | |
803 | return ret; | |
804 | ||
805 | out2: | |
806 | gpiochip_remove(&gpio_dev->gc); | |
807 | ||
dbad75dd KX |
808 | return ret; |
809 | } | |
810 | ||
811 | static int amd_gpio_remove(struct platform_device *pdev) | |
812 | { | |
813 | struct amd_gpio *gpio_dev; | |
814 | ||
815 | gpio_dev = platform_get_drvdata(pdev); | |
816 | ||
817 | gpiochip_remove(&gpio_dev->gc); | |
dbad75dd KX |
818 | |
819 | return 0; | |
820 | } | |
821 | ||
822 | static const struct acpi_device_id amd_gpio_acpi_match[] = { | |
823 | { "AMD0030", 0 }, | |
42a44402 | 824 | { "AMDI0030", 0}, |
dbad75dd KX |
825 | { }, |
826 | }; | |
827 | MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); | |
828 | ||
829 | static struct platform_driver amd_gpio_driver = { | |
830 | .driver = { | |
831 | .name = "amd_gpio", | |
dbad75dd KX |
832 | .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), |
833 | }, | |
834 | .probe = amd_gpio_probe, | |
835 | .remove = amd_gpio_remove, | |
836 | }; | |
837 | ||
838 | module_platform_driver(amd_gpio_driver); | |
839 | ||
840 | MODULE_LICENSE("GPL v2"); | |
841 | MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); | |
842 | MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); |