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pinctrl: imx: use generic pinmux helpers for managing functions
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-amd.c
CommitLineData
dbad75dd
KX		 1/*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/bug.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/compiler.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/log2.h>
22#include <linux/io.h>
23#include <linux/gpio.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <linux/mutex.h>
27#include <linux/acpi.h>
28#include <linux/seq_file.h>
29#include <linux/interrupt.h>
30#include <linux/list.h>
31#include <linux/bitops.h>
dbad75dd
KX		 32#include <linux/pinctrl/pinconf.h>
33#include <linux/pinctrl/pinconf-generic.h>
34
35#include "pinctrl-utils.h"
36#include "pinctrl-amd.h"
37
dbad75dd
KX		 38static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
39{
40 unsigned long flags;
41 u32 pin_reg;
04d36723 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 43
44 spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4);
dbad75dd
KX		 46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
47 writel(pin_reg, gpio_dev->base + offset * 4);
48 spin_unlock_irqrestore(&gpio_dev->lock, flags);
49
50 return 0;
51}
52
53static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
54 int value)
55{
56 u32 pin_reg;
57 unsigned long flags;
04d36723 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 59
60 spin_lock_irqsave(&gpio_dev->lock, flags);
61 pin_reg = readl(gpio_dev->base + offset * 4);
62 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
63 if (value)
64 pin_reg |= BIT(OUTPUT_VALUE_OFF);
65 else
66 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
67 writel(pin_reg, gpio_dev->base + offset * 4);
68 spin_unlock_irqrestore(&gpio_dev->lock, flags);
69
70 return 0;
71}
72
73static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
74{
75 u32 pin_reg;
76 unsigned long flags;
04d36723 77 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 78
79 spin_lock_irqsave(&gpio_dev->lock, flags);
80 pin_reg = readl(gpio_dev->base + offset * 4);
81 spin_unlock_irqrestore(&gpio_dev->lock, flags);
82
83 return !!(pin_reg & BIT(PIN_STS_OFF));
84}
85
86static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
87{
88 u32 pin_reg;
89 unsigned long flags;
04d36723 90 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 91
92 spin_lock_irqsave(&gpio_dev->lock, flags);
93 pin_reg = readl(gpio_dev->base + offset * 4);
94 if (value)
95 pin_reg |= BIT(OUTPUT_VALUE_OFF);
96 else
97 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
98 writel(pin_reg, gpio_dev->base + offset * 4);
99 spin_unlock_irqrestore(&gpio_dev->lock, flags);
100}
101
102static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
103 unsigned debounce)
104{
dbad75dd 105 u32 time;
25a853d0
KX		 106 u32 pin_reg;
107 int ret = 0;
dbad75dd 108 unsigned long flags;
04d36723 109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 110
111 spin_lock_irqsave(&gpio_dev->lock, flags);
112 pin_reg = readl(gpio_dev->base + offset * 4);
113
114 if (debounce) {
115 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
116 pin_reg &= ~DB_TMR_OUT_MASK;
117 /*
118 Debounce Debounce Timer Max
119 TmrLarge TmrOutUnit Unit Debounce
120 Time
121 0 0 61 usec (2 RtcClk) 976 usec
122 0 1 244 usec (8 RtcClk) 3.9 msec
123 1 0 15.6 msec (512 RtcClk) 250 msec
124 1 1 62.5 msec (2048 RtcClk) 1 sec
125 */
126
127 if (debounce < 61) {
128 pin_reg |= 1;
129 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
130 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
131 } else if (debounce < 976) {
132 time = debounce / 61;
133 pin_reg |= time & DB_TMR_OUT_MASK;
134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
136 } else if (debounce < 3900) {
137 time = debounce / 244;
138 pin_reg |= time & DB_TMR_OUT_MASK;
139 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
141 } else if (debounce < 250000) {
142 time = debounce / 15600;
143 pin_reg |= time & DB_TMR_OUT_MASK;
144 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
145 pin_reg |= BIT(DB_TMR_LARGE_OFF);
146 } else if (debounce < 1000000) {
147 time = debounce / 62500;
148 pin_reg |= time & DB_TMR_OUT_MASK;
149 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
150 pin_reg |= BIT(DB_TMR_LARGE_OFF);
151 } else {
152 pin_reg &= ~DB_CNTRl_MASK;
25a853d0 153 ret = -EINVAL;
dbad75dd
KX		 154 }
155 } else {
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 pin_reg &= ~DB_TMR_OUT_MASK;
159 pin_reg &= ~DB_CNTRl_MASK;
160 }
161 writel(pin_reg, gpio_dev->base + offset * 4);
162 spin_unlock_irqrestore(&gpio_dev->lock, flags);
163
25a853d0 164 return ret;
dbad75dd
KX		 165}
166
167#ifdef CONFIG_DEBUG_FS
168static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
169{
170 u32 pin_reg;
171 unsigned long flags;
172 unsigned int bank, i, pin_num;
04d36723 173 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 174
175 char *level_trig;
176 char *active_level;
177 char *interrupt_enable;
178 char *interrupt_mask;
179 char *wake_cntrl0;
180 char *wake_cntrl1;
181 char *wake_cntrl2;
182 char *pin_sts;
183 char *pull_up_sel;
184 char *pull_up_enable;
185 char *pull_down_enable;
186 char *output_value;
187 char *output_enable;
188
3bfd4430 189 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
dbad75dd
KX		 190 seq_printf(s, "GPIO bank%d\t", bank);
191
192 switch (bank) {
193 case 0:
194 i = 0;
195 pin_num = AMD_GPIO_PINS_BANK0;
196 break;
197 case 1:
198 i = 64;
199 pin_num = AMD_GPIO_PINS_BANK1 + i;
200 break;
201 case 2:
202 i = 128;
203 pin_num = AMD_GPIO_PINS_BANK2 + i;
204 break;
3bfd4430
SN		 205 case 3:
206 i = 192;
207 pin_num = AMD_GPIO_PINS_BANK3 + i;
208 break;
dbad75dd 209 }
dbad75dd
KX		 210 for (; i < pin_num; i++) {
211 seq_printf(s, "pin%d\t", i);
212 spin_lock_irqsave(&gpio_dev->lock, flags);
213 pin_reg = readl(gpio_dev->base + i * 4);
214 spin_unlock_irqrestore(&gpio_dev->lock, flags);
215
216 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
217 interrupt_enable = "interrupt is enabled|";
218
3bfd4430 219 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
dbad75dd
KX		 220 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
221 active_level = "Active low|";
222 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
223 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
224 active_level = "Active high|";
225 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
226 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
227 active_level = "Active on both|";
228 else
229 active_level = "Unknow Active level|";
230
231 if (pin_reg & BIT(LEVEL_TRIG_OFF))
232 level_trig = "Level trigger|";
233 else
234 level_trig = "Edge trigger|";
235
236 } else {
237 interrupt_enable =
238 "interrupt is disabled|";
239 active_level = " ";
240 level_trig = " ";
241 }
242
243 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
244 interrupt_mask =
245 "interrupt is unmasked|";
246 else
247 interrupt_mask =
248 "interrupt is masked|";
249
3bfd4430 250 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
dbad75dd
KX		 251 wake_cntrl0 = "enable wakeup in S0i3 state|";
252 else
253 wake_cntrl0 = "disable wakeup in S0i3 state|";
254
3bfd4430 255 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
dbad75dd
KX		 256 wake_cntrl1 = "enable wakeup in S3 state|";
257 else
258 wake_cntrl1 = "disable wakeup in S3 state|";
259
3bfd4430 260 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
dbad75dd
KX		 261 wake_cntrl2 = "enable wakeup in S4/S5 state|";
262 else
263 wake_cntrl2 = "disable wakeup in S4/S5 state|";
264
265 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
266 pull_up_enable = "pull-up is enabled|";
267 if (pin_reg & BIT(PULL_UP_SEL_OFF))
268 pull_up_sel = "8k pull-up|";
269 else
270 pull_up_sel = "4k pull-up|";
271 } else {
272 pull_up_enable = "pull-up is disabled|";
273 pull_up_sel = " ";
274 }
275
276 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
277 pull_down_enable = "pull-down is enabled|";
278 else
279 pull_down_enable = "Pull-down is disabled|";
280
281 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
282 pin_sts = " ";
283 output_enable = "output is enabled|";
284 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
285 output_value = "output is high|";
286 else
287 output_value = "output is low|";
288 } else {
289 output_enable = "output is disabled|";
290 output_value = " ";
291
292 if (pin_reg & BIT(PIN_STS_OFF))
293 pin_sts = "input is high|";
294 else
295 pin_sts = "input is low|";
296 }
297
298 seq_printf(s, "%s %s %s %s %s %s\n"
299 " %s %s %s %s %s %s %s 0x%x\n",
300 level_trig, active_level, interrupt_enable,
301 interrupt_mask, wake_cntrl0, wake_cntrl1,
302 wake_cntrl2, pin_sts, pull_up_sel,
303 pull_up_enable, pull_down_enable,
304 output_value, output_enable, pin_reg);
305 }
306 }
307}
308#else
309#define amd_gpio_dbg_show NULL
310#endif
311
312static void amd_gpio_irq_enable(struct irq_data *d)
313{
314 u32 pin_reg;
315 unsigned long flags;
316 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 317 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 318
319 spin_lock_irqsave(&gpio_dev->lock, flags);
320 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
dbad75dd
KX		 321 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
322 pin_reg |= BIT(INTERRUPT_MASK_OFF);
323 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
324 spin_unlock_irqrestore(&gpio_dev->lock, flags);
325}
326
327static void amd_gpio_irq_disable(struct irq_data *d)
328{
329 u32 pin_reg;
330 unsigned long flags;
331 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 332 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 333
334 spin_lock_irqsave(&gpio_dev->lock, flags);
335 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
336 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
337 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
338 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
339 spin_unlock_irqrestore(&gpio_dev->lock, flags);
340}
341
342static void amd_gpio_irq_mask(struct irq_data *d)
343{
344 u32 pin_reg;
345 unsigned long flags;
346 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 347 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 348
349 spin_lock_irqsave(&gpio_dev->lock, flags);
350 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
351 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
352 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
353 spin_unlock_irqrestore(&gpio_dev->lock, flags);
354}
355
356static void amd_gpio_irq_unmask(struct irq_data *d)
357{
358 u32 pin_reg;
359 unsigned long flags;
360 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 361 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 362
363 spin_lock_irqsave(&gpio_dev->lock, flags);
364 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
365 pin_reg |= BIT(INTERRUPT_MASK_OFF);
366 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
367 spin_unlock_irqrestore(&gpio_dev->lock, flags);
368}
369
370static void amd_gpio_irq_eoi(struct irq_data *d)
371{
372 u32 reg;
373 unsigned long flags;
374 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 375 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 376
377 spin_lock_irqsave(&gpio_dev->lock, flags);
378 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
379 reg |= EOI_MASK;
380 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
381 spin_unlock_irqrestore(&gpio_dev->lock, flags);
382}
383
384static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
385{
386 int ret = 0;
387 u32 pin_reg;
388 unsigned long flags;
e084448b 389 bool level_trig;
499c7196 390 u32 active_level;
dbad75dd 391 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 392 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 393
394 spin_lock_irqsave(&gpio_dev->lock, flags);
395 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
396
499c7196
AN		 397 /*
398 * When level_trig is set EDGE and active_level is set HIGH in BIOS
399 * default settings, ignore incoming settings from client and use
400 * BIOS settings to configure GPIO register.
401 */
e084448b 402 level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF));
499c7196
AN		 403 active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
404
e084448b
AN		 405 if(level_trig &&
406 ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH))
499c7196 407 type = IRQ_TYPE_EDGE_FALLING;
499c7196 408
dbad75dd
KX		 409 switch (type & IRQ_TYPE_SENSE_MASK) {
410 case IRQ_TYPE_EDGE_RISING:
411 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
412 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
413 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
414 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 415 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 416 break;
417
418 case IRQ_TYPE_EDGE_FALLING:
419 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
420 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
421 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
422 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 423 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 424 break;
425
426 case IRQ_TYPE_EDGE_BOTH:
427 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
428 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
429 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
430 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 431 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 432 break;
433
434 case IRQ_TYPE_LEVEL_HIGH:
435 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
436 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
437 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
438 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
439 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
9d829314 440 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 441 break;
442
443 case IRQ_TYPE_LEVEL_LOW:
444 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
445 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
446 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
447 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
448 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
9d829314 449 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 450 break;
451
452 case IRQ_TYPE_NONE:
453 break;
454
455 default:
456 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
457 ret = -EINVAL;
dbad75dd
KX		 458 }
459
460 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
461 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
462 spin_unlock_irqrestore(&gpio_dev->lock, flags);
463
dbad75dd
KX		 464 return ret;
465}
466
467static void amd_irq_ack(struct irq_data *d)
468{
469 /*
470 * based on HW design,there is no need to ack HW
471 * before handle current irq. But this routine is
472 * necessary for handle_edge_irq
473 */
474}
475
476static struct irq_chip amd_gpio_irqchip = {
477 .name = "amd_gpio",
478 .irq_ack = amd_irq_ack,
479 .irq_enable = amd_gpio_irq_enable,
480 .irq_disable = amd_gpio_irq_disable,
481 .irq_mask = amd_gpio_irq_mask,
482 .irq_unmask = amd_gpio_irq_unmask,
483 .irq_eoi = amd_gpio_irq_eoi,
484 .irq_set_type = amd_gpio_irq_set_type,
3bfd4430 485 .flags = IRQCHIP_SKIP_SET_WAKE,
dbad75dd
KX		 486};
487
bd0b9ac4 488static void amd_gpio_irq_handler(struct irq_desc *desc)
dbad75dd
KX		 489{
490 u32 i;
491 u32 off;
492 u32 reg;
493 u32 pin_reg;
494 u64 reg64;
495 int handled = 0;
bd0b9ac4 496 unsigned int irq;
dbad75dd 497 unsigned long flags;
5663bb27 498 struct irq_chip *chip = irq_desc_get_chip(desc);
dbad75dd 499 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
04d36723 500 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 501
502 chained_irq_enter(chip, desc);
503 /*enable GPIO interrupt again*/
504 spin_lock_irqsave(&gpio_dev->lock, flags);
505 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
506 reg64 = reg;
507 reg64 = reg64 << 32;
508
509 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
510 reg64 |= reg;
511 spin_unlock_irqrestore(&gpio_dev->lock, flags);
512
513 /*
514 * first 46 bits indicates interrupt status.
515 * one bit represents four interrupt sources.
516 */
517 for (off = 0; off < 46 ; off++) {
518 if (reg64 & BIT(off)) {
519 for (i = 0; i < 4; i++) {
520 pin_reg = readl(gpio_dev->base +
521 (off * 4 + i) * 4);
522 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
523 (pin_reg & BIT(WAKE_STS_OFF))) {
524 irq = irq_find_mapping(gc->irqdomain,
525 off * 4 + i);
526 generic_handle_irq(irq);
527 writel(pin_reg,
528 gpio_dev->base
529 + (off * 4 + i) * 4);
530 handled++;
531 }
532 }
533 }
534 }
535
536 if (handled == 0)
bd0b9ac4 537 handle_bad_irq(desc);
dbad75dd
KX		 538
539 spin_lock_irqsave(&gpio_dev->lock, flags);
540 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
541 reg |= EOI_MASK;
542 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
543 spin_unlock_irqrestore(&gpio_dev->lock, flags);
544
545 chained_irq_exit(chip, desc);
546}
547
548static int amd_get_groups_count(struct pinctrl_dev *pctldev)
549{
550 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
551
552 return gpio_dev->ngroups;
553}
554
555static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
556 unsigned group)
557{
558 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
559
560 return gpio_dev->groups[group].name;
561}
562
563static int amd_get_group_pins(struct pinctrl_dev *pctldev,
564 unsigned group,
565 const unsigned **pins,
566 unsigned *num_pins)
567{
568 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
569
570 *pins = gpio_dev->groups[group].pins;
571 *num_pins = gpio_dev->groups[group].npins;
572 return 0;
573}
574
575static const struct pinctrl_ops amd_pinctrl_ops = {
576 .get_groups_count = amd_get_groups_count,
577 .get_group_name = amd_get_group_name,
578 .get_group_pins = amd_get_group_pins,
579#ifdef CONFIG_OF
580 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
d32f7fd3 581 .dt_free_map = pinctrl_utils_free_map,
dbad75dd
KX		 582#endif
583};
584
585static int amd_pinconf_get(struct pinctrl_dev *pctldev,
586 unsigned int pin,
587 unsigned long *config)
588{
589 u32 pin_reg;
590 unsigned arg;
591 unsigned long flags;
592 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
593 enum pin_config_param param = pinconf_to_config_param(*config);
594
595 spin_lock_irqsave(&gpio_dev->lock, flags);
596 pin_reg = readl(gpio_dev->base + pin*4);
597 spin_unlock_irqrestore(&gpio_dev->lock, flags);
598 switch (param) {
599 case PIN_CONFIG_INPUT_DEBOUNCE:
600 arg = pin_reg & DB_TMR_OUT_MASK;
601 break;
602
603 case PIN_CONFIG_BIAS_PULL_DOWN:
604 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
605 break;
606
607 case PIN_CONFIG_BIAS_PULL_UP:
608 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
609 break;
610
611 case PIN_CONFIG_DRIVE_STRENGTH:
612 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
613 break;
614
615 default:
616 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
617 param);
618 return -ENOTSUPP;
619 }
620
621 *config = pinconf_to_config_packed(param, arg);
622
623 return 0;
624}
625
626static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
627 unsigned long *configs, unsigned num_configs)
628{
629 int i;
dbad75dd 630 u32 arg;
25a853d0
KX		 631 int ret = 0;
632 u32 pin_reg;
dbad75dd
KX		 633 unsigned long flags;
634 enum pin_config_param param;
635 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
636
637 spin_lock_irqsave(&gpio_dev->lock, flags);
638 for (i = 0; i < num_configs; i++) {
639 param = pinconf_to_config_param(configs[i]);
640 arg = pinconf_to_config_argument(configs[i]);
641 pin_reg = readl(gpio_dev->base + pin*4);
642
643 switch (param) {
644 case PIN_CONFIG_INPUT_DEBOUNCE:
645 pin_reg &= ~DB_TMR_OUT_MASK;
646 pin_reg |= arg & DB_TMR_OUT_MASK;
647 break;
648
649 case PIN_CONFIG_BIAS_PULL_DOWN:
650 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
651 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
652 break;
653
654 case PIN_CONFIG_BIAS_PULL_UP:
655 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
656 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
657 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
658 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
659 break;
660
661 case PIN_CONFIG_DRIVE_STRENGTH:
662 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
663 << DRV_STRENGTH_SEL_OFF);
664 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
665 << DRV_STRENGTH_SEL_OFF;
666 break;
667
668 default:
669 dev_err(&gpio_dev->pdev->dev,
670 "Invalid config param %04x\n", param);
25a853d0 671 ret = -ENOTSUPP;
dbad75dd
KX		 672 }
673
674 writel(pin_reg, gpio_dev->base + pin*4);
675 }
676 spin_unlock_irqrestore(&gpio_dev->lock, flags);
677
25a853d0 678 return ret;
dbad75dd
KX		 679}
680
681static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
682 unsigned int group,
683 unsigned long *config)
684{
685 const unsigned *pins;
686 unsigned npins;
687 int ret;
688
689 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
690 if (ret)
691 return ret;
692
693 if (amd_pinconf_get(pctldev, pins[0], config))
694 return -ENOTSUPP;
695
696 return 0;
697}
698
699static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
700 unsigned group, unsigned long *configs,
701 unsigned num_configs)
702{
703 const unsigned *pins;
704 unsigned npins;
705 int i, ret;
706
707 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
708 if (ret)
709 return ret;
710 for (i = 0; i < npins; i++) {
711 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
712 return -ENOTSUPP;
713 }
714 return 0;
715}
716
717static const struct pinconf_ops amd_pinconf_ops = {
718 .pin_config_get = amd_pinconf_get,
719 .pin_config_set = amd_pinconf_set,
720 .pin_config_group_get = amd_pinconf_group_get,
721 .pin_config_group_set = amd_pinconf_group_set,
722};
723
724static struct pinctrl_desc amd_pinctrl_desc = {
725 .pins = kerncz_pins,
726 .npins = ARRAY_SIZE(kerncz_pins),
727 .pctlops = &amd_pinctrl_ops,
728 .confops = &amd_pinconf_ops,
729 .owner = THIS_MODULE,
730};
731
732static int amd_gpio_probe(struct platform_device *pdev)
733{
734 int ret = 0;
25a853d0 735 int irq_base;
dbad75dd
KX		 736 struct resource *res;
737 struct amd_gpio *gpio_dev;
738
739 gpio_dev = devm_kzalloc(&pdev->dev,
740 sizeof(struct amd_gpio), GFP_KERNEL);
741 if (!gpio_dev)
742 return -ENOMEM;
743
744 spin_lock_init(&gpio_dev->lock);
745
746 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
747 if (!res) {
748 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
749 return -EINVAL;
750 }
751
752 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
753 resource_size(res));
424a6c60
WY		 754 if (!gpio_dev->base)
755 return -ENOMEM;
dbad75dd
KX		 756
757 irq_base = platform_get_irq(pdev, 0);
758 if (irq_base < 0) {
759 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
760 return -EINVAL;
761 }
762
763 gpio_dev->pdev = pdev;
764 gpio_dev->gc.direction_input = amd_gpio_direction_input;
765 gpio_dev->gc.direction_output = amd_gpio_direction_output;
766 gpio_dev->gc.get = amd_gpio_get_value;
767 gpio_dev->gc.set = amd_gpio_set_value;
768 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
769 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
770
3bfd4430 771 gpio_dev->gc.base = -1;
dbad75dd
KX		 772 gpio_dev->gc.label = pdev->name;
773 gpio_dev->gc.owner = THIS_MODULE;
58383c78 774 gpio_dev->gc.parent = &pdev->dev;
3bfd4430 775 gpio_dev->gc.ngpio = resource_size(res) / 4;
dbad75dd
KX		 776#if defined(CONFIG_OF_GPIO)
777 gpio_dev->gc.of_node = pdev->dev.of_node;
778#endif
779
3bfd4430 780 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
dbad75dd
KX		 781 gpio_dev->groups = kerncz_groups;
782 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
783
784 amd_pinctrl_desc.name = dev_name(&pdev->dev);
251e22ab
LD		 785 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
786 gpio_dev);
323de9ef 787 if (IS_ERR(gpio_dev->pctrl)) {
dbad75dd 788 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
323de9ef 789 return PTR_ERR(gpio_dev->pctrl);
dbad75dd
KX		 790 }
791
04d36723 792 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
dbad75dd 793 if (ret)
251e22ab 794 return ret;
dbad75dd
KX		 795
796 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
3bfd4430 797 0, 0, gpio_dev->gc.ngpio);
dbad75dd
KX		 798 if (ret) {
799 dev_err(&pdev->dev, "Failed to add pin range\n");
800 goto out2;
801 }
802
803 ret = gpiochip_irqchip_add(&gpio_dev->gc,
804 &amd_gpio_irqchip,
805 0,
806 handle_simple_irq,
807 IRQ_TYPE_NONE);
808 if (ret) {
809 dev_err(&pdev->dev, "could not add irqchip\n");
810 ret = -ENODEV;
811 goto out2;
812 }
813
814 gpiochip_set_chained_irqchip(&gpio_dev->gc,
815 &amd_gpio_irqchip,
816 irq_base,
817 amd_gpio_irq_handler);
dbad75dd
KX		 818 platform_set_drvdata(pdev, gpio_dev);
819
820 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
821 return ret;
822
823out2:
824 gpiochip_remove(&gpio_dev->gc);
825
dbad75dd
KX		 826 return ret;
827}
828
829static int amd_gpio_remove(struct platform_device *pdev)
830{
831 struct amd_gpio *gpio_dev;
832
833 gpio_dev = platform_get_drvdata(pdev);
834
835 gpiochip_remove(&gpio_dev->gc);
3bfd4430 836 pinctrl_unregister(gpio_dev->pctrl);
dbad75dd
KX		 837
838 return 0;
839}
840
841static const struct acpi_device_id amd_gpio_acpi_match[] = {
842 { "AMD0030", 0 },
42a44402 843 { "AMDI0030", 0},
dbad75dd
KX		 844 { },
845};
846MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
847
848static struct platform_driver amd_gpio_driver = {
849 .driver = {
850 .name = "amd_gpio",
dbad75dd
KX		 851 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
852 },
853 .probe = amd_gpio_probe,
854 .remove = amd_gpio_remove,
855};
856
857module_platform_driver(amd_gpio_driver);
858
859MODULE_LICENSE("GPL v2");
860MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
861MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux 6.x block layer and io_uring tree(s)