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pinctrl / gpio: Introduce .set_config() callback for GPIO chips
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-amd.c
CommitLineData
dbad75dd
KX		 1/*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/bug.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/compiler.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/log2.h>
22#include <linux/io.h>
23#include <linux/gpio.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <linux/mutex.h>
27#include <linux/acpi.h>
28#include <linux/seq_file.h>
29#include <linux/interrupt.h>
30#include <linux/list.h>
31#include <linux/bitops.h>
dbad75dd
KX		 32#include <linux/pinctrl/pinconf.h>
33#include <linux/pinctrl/pinconf-generic.h>
34
35#include "pinctrl-utils.h"
36#include "pinctrl-amd.h"
37
dbad75dd
KX		 38static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
39{
40 unsigned long flags;
41 u32 pin_reg;
04d36723 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 43
44 spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4);
dbad75dd
KX		 46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
47 writel(pin_reg, gpio_dev->base + offset * 4);
48 spin_unlock_irqrestore(&gpio_dev->lock, flags);
49
50 return 0;
51}
52
53static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
54 int value)
55{
56 u32 pin_reg;
57 unsigned long flags;
04d36723 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 59
60 spin_lock_irqsave(&gpio_dev->lock, flags);
61 pin_reg = readl(gpio_dev->base + offset * 4);
62 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
63 if (value)
64 pin_reg |= BIT(OUTPUT_VALUE_OFF);
65 else
66 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
67 writel(pin_reg, gpio_dev->base + offset * 4);
68 spin_unlock_irqrestore(&gpio_dev->lock, flags);
69
70 return 0;
71}
72
73static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
74{
75 u32 pin_reg;
76 unsigned long flags;
04d36723 77 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 78
79 spin_lock_irqsave(&gpio_dev->lock, flags);
80 pin_reg = readl(gpio_dev->base + offset * 4);
81 spin_unlock_irqrestore(&gpio_dev->lock, flags);
82
83 return !!(pin_reg & BIT(PIN_STS_OFF));
84}
85
86static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
87{
88 u32 pin_reg;
89 unsigned long flags;
04d36723 90 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 91
92 spin_lock_irqsave(&gpio_dev->lock, flags);
93 pin_reg = readl(gpio_dev->base + offset * 4);
94 if (value)
95 pin_reg |= BIT(OUTPUT_VALUE_OFF);
96 else
97 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
98 writel(pin_reg, gpio_dev->base + offset * 4);
99 spin_unlock_irqrestore(&gpio_dev->lock, flags);
100}
101
102static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
103 unsigned debounce)
104{
dbad75dd 105 u32 time;
25a853d0
KX		 106 u32 pin_reg;
107 int ret = 0;
dbad75dd 108 unsigned long flags;
04d36723 109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 110
111 spin_lock_irqsave(&gpio_dev->lock, flags);
112 pin_reg = readl(gpio_dev->base + offset * 4);
113
114 if (debounce) {
115 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
116 pin_reg &= ~DB_TMR_OUT_MASK;
117 /*
118 Debounce Debounce Timer Max
119 TmrLarge TmrOutUnit Unit Debounce
120 Time
121 0 0 61 usec (2 RtcClk) 976 usec
122 0 1 244 usec (8 RtcClk) 3.9 msec
123 1 0 15.6 msec (512 RtcClk) 250 msec
124 1 1 62.5 msec (2048 RtcClk) 1 sec
125 */
126
127 if (debounce < 61) {
128 pin_reg |= 1;
129 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
130 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
131 } else if (debounce < 976) {
132 time = debounce / 61;
133 pin_reg |= time & DB_TMR_OUT_MASK;
134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
136 } else if (debounce < 3900) {
137 time = debounce / 244;
138 pin_reg |= time & DB_TMR_OUT_MASK;
139 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
141 } else if (debounce < 250000) {
142 time = debounce / 15600;
143 pin_reg |= time & DB_TMR_OUT_MASK;
144 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
145 pin_reg |= BIT(DB_TMR_LARGE_OFF);
146 } else if (debounce < 1000000) {
147 time = debounce / 62500;
148 pin_reg |= time & DB_TMR_OUT_MASK;
149 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
150 pin_reg |= BIT(DB_TMR_LARGE_OFF);
151 } else {
152 pin_reg &= ~DB_CNTRl_MASK;
25a853d0 153 ret = -EINVAL;
dbad75dd
KX		 154 }
155 } else {
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 pin_reg &= ~DB_TMR_OUT_MASK;
159 pin_reg &= ~DB_CNTRl_MASK;
160 }
161 writel(pin_reg, gpio_dev->base + offset * 4);
162 spin_unlock_irqrestore(&gpio_dev->lock, flags);
163
25a853d0 164 return ret;
dbad75dd
KX		 165}
166
2956b5d9
MW		 167static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
168 unsigned long config)
169{
170 u32 debounce;
171
172 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
173 return -ENOTSUPP;
174
175 debounce = pinconf_to_config_argument(config);
176 return amd_gpio_set_debounce(gc, offset, debounce);
177}
178
dbad75dd
KX		 179#ifdef CONFIG_DEBUG_FS
180static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
181{
182 u32 pin_reg;
183 unsigned long flags;
184 unsigned int bank, i, pin_num;
04d36723 185 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 186
187 char *level_trig;
188 char *active_level;
189 char *interrupt_enable;
190 char *interrupt_mask;
191 char *wake_cntrl0;
192 char *wake_cntrl1;
193 char *wake_cntrl2;
194 char *pin_sts;
195 char *pull_up_sel;
196 char *pull_up_enable;
197 char *pull_down_enable;
198 char *output_value;
199 char *output_enable;
200
201 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
202 seq_printf(s, "GPIO bank%d\t", bank);
203
204 switch (bank) {
205 case 0:
206 i = 0;
207 pin_num = AMD_GPIO_PINS_BANK0;
208 break;
209 case 1:
210 i = 64;
211 pin_num = AMD_GPIO_PINS_BANK1 + i;
212 break;
213 case 2:
214 i = 128;
215 pin_num = AMD_GPIO_PINS_BANK2 + i;
216 break;
217 }
218
219 for (; i < pin_num; i++) {
220 seq_printf(s, "pin%d\t", i);
221 spin_lock_irqsave(&gpio_dev->lock, flags);
222 pin_reg = readl(gpio_dev->base + i * 4);
223 spin_unlock_irqrestore(&gpio_dev->lock, flags);
224
225 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
226 interrupt_enable = "interrupt is enabled|";
227
228 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
229 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
230 active_level = "Active low|";
231 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
232 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
233 active_level = "Active high|";
234 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
235 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
236 active_level = "Active on both|";
237 else
238 active_level = "Unknow Active level|";
239
240 if (pin_reg & BIT(LEVEL_TRIG_OFF))
241 level_trig = "Level trigger|";
242 else
243 level_trig = "Edge trigger|";
244
245 } else {
246 interrupt_enable =
247 "interrupt is disabled|";
248 active_level = " ";
249 level_trig = " ";
250 }
251
252 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
253 interrupt_mask =
254 "interrupt is unmasked|";
255 else
256 interrupt_mask =
257 "interrupt is masked|";
258
259 if (pin_reg & BIT(WAKE_CNTRL_OFF))
260 wake_cntrl0 = "enable wakeup in S0i3 state|";
261 else
262 wake_cntrl0 = "disable wakeup in S0i3 state|";
263
264 if (pin_reg & BIT(WAKE_CNTRL_OFF))
265 wake_cntrl1 = "enable wakeup in S3 state|";
266 else
267 wake_cntrl1 = "disable wakeup in S3 state|";
268
269 if (pin_reg & BIT(WAKE_CNTRL_OFF))
270 wake_cntrl2 = "enable wakeup in S4/S5 state|";
271 else
272 wake_cntrl2 = "disable wakeup in S4/S5 state|";
273
274 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
275 pull_up_enable = "pull-up is enabled|";
276 if (pin_reg & BIT(PULL_UP_SEL_OFF))
277 pull_up_sel = "8k pull-up|";
278 else
279 pull_up_sel = "4k pull-up|";
280 } else {
281 pull_up_enable = "pull-up is disabled|";
282 pull_up_sel = " ";
283 }
284
285 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
286 pull_down_enable = "pull-down is enabled|";
287 else
288 pull_down_enable = "Pull-down is disabled|";
289
290 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
291 pin_sts = " ";
292 output_enable = "output is enabled|";
293 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
294 output_value = "output is high|";
295 else
296 output_value = "output is low|";
297 } else {
298 output_enable = "output is disabled|";
299 output_value = " ";
300
301 if (pin_reg & BIT(PIN_STS_OFF))
302 pin_sts = "input is high|";
303 else
304 pin_sts = "input is low|";
305 }
306
307 seq_printf(s, "%s %s %s %s %s %s\n"
308 " %s %s %s %s %s %s %s 0x%x\n",
309 level_trig, active_level, interrupt_enable,
310 interrupt_mask, wake_cntrl0, wake_cntrl1,
311 wake_cntrl2, pin_sts, pull_up_sel,
312 pull_up_enable, pull_down_enable,
313 output_value, output_enable, pin_reg);
314 }
315 }
316}
317#else
318#define amd_gpio_dbg_show NULL
319#endif
320
321static void amd_gpio_irq_enable(struct irq_data *d)
322{
323 u32 pin_reg;
324 unsigned long flags;
325 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 326 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 327
328 spin_lock_irqsave(&gpio_dev->lock, flags);
329 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
dbad75dd
KX		 330 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
331 pin_reg |= BIT(INTERRUPT_MASK_OFF);
332 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
333 spin_unlock_irqrestore(&gpio_dev->lock, flags);
334}
335
336static void amd_gpio_irq_disable(struct irq_data *d)
337{
338 u32 pin_reg;
339 unsigned long flags;
340 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 341 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 342
343 spin_lock_irqsave(&gpio_dev->lock, flags);
344 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
345 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
346 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
347 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
348 spin_unlock_irqrestore(&gpio_dev->lock, flags);
349}
350
351static void amd_gpio_irq_mask(struct irq_data *d)
352{
353 u32 pin_reg;
354 unsigned long flags;
355 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 356 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 357
358 spin_lock_irqsave(&gpio_dev->lock, flags);
359 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
360 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
361 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
362 spin_unlock_irqrestore(&gpio_dev->lock, flags);
363}
364
365static void amd_gpio_irq_unmask(struct irq_data *d)
366{
367 u32 pin_reg;
368 unsigned long flags;
369 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 370 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 371
372 spin_lock_irqsave(&gpio_dev->lock, flags);
373 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
374 pin_reg |= BIT(INTERRUPT_MASK_OFF);
375 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
376 spin_unlock_irqrestore(&gpio_dev->lock, flags);
377}
378
379static void amd_gpio_irq_eoi(struct irq_data *d)
380{
381 u32 reg;
382 unsigned long flags;
383 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 384 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 385
386 spin_lock_irqsave(&gpio_dev->lock, flags);
387 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
388 reg |= EOI_MASK;
389 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
390 spin_unlock_irqrestore(&gpio_dev->lock, flags);
391}
392
393static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
394{
395 int ret = 0;
396 u32 pin_reg;
397 unsigned long flags;
e084448b 398 bool level_trig;
499c7196 399 u32 active_level;
dbad75dd 400 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 401 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 402
403 spin_lock_irqsave(&gpio_dev->lock, flags);
404 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
405
499c7196
AN		 406 /*
407 * When level_trig is set EDGE and active_level is set HIGH in BIOS
408 * default settings, ignore incoming settings from client and use
409 * BIOS settings to configure GPIO register.
410 */
e084448b 411 level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF));
499c7196
AN		 412 active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
413
e084448b
AN		 414 if(level_trig &&
415 ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH))
499c7196 416 type = IRQ_TYPE_EDGE_FALLING;
499c7196 417
dbad75dd
KX		 418 switch (type & IRQ_TYPE_SENSE_MASK) {
419 case IRQ_TYPE_EDGE_RISING:
420 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
421 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
422 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
423 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 424 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 425 break;
426
427 case IRQ_TYPE_EDGE_FALLING:
428 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
429 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
430 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
431 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 432 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 433 break;
434
435 case IRQ_TYPE_EDGE_BOTH:
436 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
437 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
438 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
439 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 440 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 441 break;
442
443 case IRQ_TYPE_LEVEL_HIGH:
444 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
445 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
446 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
447 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
448 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
9d829314 449 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 450 break;
451
452 case IRQ_TYPE_LEVEL_LOW:
453 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
454 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
455 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
456 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
457 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
9d829314 458 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 459 break;
460
461 case IRQ_TYPE_NONE:
462 break;
463
464 default:
465 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
466 ret = -EINVAL;
dbad75dd
KX		 467 }
468
469 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
470 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
471 spin_unlock_irqrestore(&gpio_dev->lock, flags);
472
dbad75dd
KX		 473 return ret;
474}
475
476static void amd_irq_ack(struct irq_data *d)
477{
478 /*
479 * based on HW design,there is no need to ack HW
480 * before handle current irq. But this routine is
481 * necessary for handle_edge_irq
482 */
483}
484
485static struct irq_chip amd_gpio_irqchip = {
486 .name = "amd_gpio",
487 .irq_ack = amd_irq_ack,
488 .irq_enable = amd_gpio_irq_enable,
489 .irq_disable = amd_gpio_irq_disable,
490 .irq_mask = amd_gpio_irq_mask,
491 .irq_unmask = amd_gpio_irq_unmask,
492 .irq_eoi = amd_gpio_irq_eoi,
493 .irq_set_type = amd_gpio_irq_set_type,
494};
495
bd0b9ac4 496static void amd_gpio_irq_handler(struct irq_desc *desc)
dbad75dd
KX		 497{
498 u32 i;
499 u32 off;
500 u32 reg;
501 u32 pin_reg;
502 u64 reg64;
503 int handled = 0;
bd0b9ac4 504 unsigned int irq;
dbad75dd 505 unsigned long flags;
5663bb27 506 struct irq_chip *chip = irq_desc_get_chip(desc);
dbad75dd 507 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
04d36723 508 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 509
510 chained_irq_enter(chip, desc);
511 /*enable GPIO interrupt again*/
512 spin_lock_irqsave(&gpio_dev->lock, flags);
513 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
514 reg64 = reg;
515 reg64 = reg64 << 32;
516
517 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
518 reg64 |= reg;
519 spin_unlock_irqrestore(&gpio_dev->lock, flags);
520
521 /*
522 * first 46 bits indicates interrupt status.
523 * one bit represents four interrupt sources.
524 */
525 for (off = 0; off < 46 ; off++) {
526 if (reg64 & BIT(off)) {
527 for (i = 0; i < 4; i++) {
528 pin_reg = readl(gpio_dev->base +
529 (off * 4 + i) * 4);
530 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
531 (pin_reg & BIT(WAKE_STS_OFF))) {
532 irq = irq_find_mapping(gc->irqdomain,
533 off * 4 + i);
534 generic_handle_irq(irq);
535 writel(pin_reg,
536 gpio_dev->base
537 + (off * 4 + i) * 4);
538 handled++;
539 }
540 }
541 }
542 }
543
544 if (handled == 0)
bd0b9ac4 545 handle_bad_irq(desc);
dbad75dd
KX		 546
547 spin_lock_irqsave(&gpio_dev->lock, flags);
548 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
549 reg |= EOI_MASK;
550 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
551 spin_unlock_irqrestore(&gpio_dev->lock, flags);
552
553 chained_irq_exit(chip, desc);
554}
555
556static int amd_get_groups_count(struct pinctrl_dev *pctldev)
557{
558 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
559
560 return gpio_dev->ngroups;
561}
562
563static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
564 unsigned group)
565{
566 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
567
568 return gpio_dev->groups[group].name;
569}
570
571static int amd_get_group_pins(struct pinctrl_dev *pctldev,
572 unsigned group,
573 const unsigned **pins,
574 unsigned *num_pins)
575{
576 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
577
578 *pins = gpio_dev->groups[group].pins;
579 *num_pins = gpio_dev->groups[group].npins;
580 return 0;
581}
582
583static const struct pinctrl_ops amd_pinctrl_ops = {
584 .get_groups_count = amd_get_groups_count,
585 .get_group_name = amd_get_group_name,
586 .get_group_pins = amd_get_group_pins,
587#ifdef CONFIG_OF
588 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
d32f7fd3 589 .dt_free_map = pinctrl_utils_free_map,
dbad75dd
KX		 590#endif
591};
592
593static int amd_pinconf_get(struct pinctrl_dev *pctldev,
594 unsigned int pin,
595 unsigned long *config)
596{
597 u32 pin_reg;
598 unsigned arg;
599 unsigned long flags;
600 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
601 enum pin_config_param param = pinconf_to_config_param(*config);
602
603 spin_lock_irqsave(&gpio_dev->lock, flags);
604 pin_reg = readl(gpio_dev->base + pin*4);
605 spin_unlock_irqrestore(&gpio_dev->lock, flags);
606 switch (param) {
607 case PIN_CONFIG_INPUT_DEBOUNCE:
608 arg = pin_reg & DB_TMR_OUT_MASK;
609 break;
610
611 case PIN_CONFIG_BIAS_PULL_DOWN:
612 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
613 break;
614
615 case PIN_CONFIG_BIAS_PULL_UP:
616 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
617 break;
618
619 case PIN_CONFIG_DRIVE_STRENGTH:
620 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
621 break;
622
623 default:
624 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
625 param);
626 return -ENOTSUPP;
627 }
628
629 *config = pinconf_to_config_packed(param, arg);
630
631 return 0;
632}
633
634static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
635 unsigned long *configs, unsigned num_configs)
636{
637 int i;
dbad75dd 638 u32 arg;
25a853d0
KX		 639 int ret = 0;
640 u32 pin_reg;
dbad75dd
KX		 641 unsigned long flags;
642 enum pin_config_param param;
643 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
644
645 spin_lock_irqsave(&gpio_dev->lock, flags);
646 for (i = 0; i < num_configs; i++) {
647 param = pinconf_to_config_param(configs[i]);
648 arg = pinconf_to_config_argument(configs[i]);
649 pin_reg = readl(gpio_dev->base + pin*4);
650
651 switch (param) {
652 case PIN_CONFIG_INPUT_DEBOUNCE:
653 pin_reg &= ~DB_TMR_OUT_MASK;
654 pin_reg |= arg & DB_TMR_OUT_MASK;
655 break;
656
657 case PIN_CONFIG_BIAS_PULL_DOWN:
658 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
659 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
660 break;
661
662 case PIN_CONFIG_BIAS_PULL_UP:
663 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
664 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
665 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
666 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
667 break;
668
669 case PIN_CONFIG_DRIVE_STRENGTH:
670 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
671 << DRV_STRENGTH_SEL_OFF);
672 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
673 << DRV_STRENGTH_SEL_OFF;
674 break;
675
676 default:
677 dev_err(&gpio_dev->pdev->dev,
678 "Invalid config param %04x\n", param);
25a853d0 679 ret = -ENOTSUPP;
dbad75dd
KX		 680 }
681
682 writel(pin_reg, gpio_dev->base + pin*4);
683 }
684 spin_unlock_irqrestore(&gpio_dev->lock, flags);
685
25a853d0 686 return ret;
dbad75dd
KX		 687}
688
689static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
690 unsigned int group,
691 unsigned long *config)
692{
693 const unsigned *pins;
694 unsigned npins;
695 int ret;
696
697 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
698 if (ret)
699 return ret;
700
701 if (amd_pinconf_get(pctldev, pins[0], config))
702 return -ENOTSUPP;
703
704 return 0;
705}
706
707static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
708 unsigned group, unsigned long *configs,
709 unsigned num_configs)
710{
711 const unsigned *pins;
712 unsigned npins;
713 int i, ret;
714
715 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
716 if (ret)
717 return ret;
718 for (i = 0; i < npins; i++) {
719 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
720 return -ENOTSUPP;
721 }
722 return 0;
723}
724
725static const struct pinconf_ops amd_pinconf_ops = {
726 .pin_config_get = amd_pinconf_get,
727 .pin_config_set = amd_pinconf_set,
728 .pin_config_group_get = amd_pinconf_group_get,
729 .pin_config_group_set = amd_pinconf_group_set,
730};
731
732static struct pinctrl_desc amd_pinctrl_desc = {
733 .pins = kerncz_pins,
734 .npins = ARRAY_SIZE(kerncz_pins),
735 .pctlops = &amd_pinctrl_ops,
736 .confops = &amd_pinconf_ops,
737 .owner = THIS_MODULE,
738};
739
740static int amd_gpio_probe(struct platform_device *pdev)
741{
742 int ret = 0;
25a853d0 743 int irq_base;
dbad75dd
KX		 744 struct resource *res;
745 struct amd_gpio *gpio_dev;
746
747 gpio_dev = devm_kzalloc(&pdev->dev,
748 sizeof(struct amd_gpio), GFP_KERNEL);
749 if (!gpio_dev)
750 return -ENOMEM;
751
752 spin_lock_init(&gpio_dev->lock);
753
754 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
755 if (!res) {
756 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
757 return -EINVAL;
758 }
759
760 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
761 resource_size(res));
424a6c60
WY		 762 if (!gpio_dev->base)
763 return -ENOMEM;
dbad75dd
KX		 764
765 irq_base = platform_get_irq(pdev, 0);
766 if (irq_base < 0) {
767 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
768 return -EINVAL;
769 }
770
771 gpio_dev->pdev = pdev;
772 gpio_dev->gc.direction_input = amd_gpio_direction_input;
773 gpio_dev->gc.direction_output = amd_gpio_direction_output;
774 gpio_dev->gc.get = amd_gpio_get_value;
775 gpio_dev->gc.set = amd_gpio_set_value;
2956b5d9 776 gpio_dev->gc.set_config = amd_gpio_set_config;
dbad75dd
KX		 777 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
778
779 gpio_dev->gc.base = 0;
780 gpio_dev->gc.label = pdev->name;
781 gpio_dev->gc.owner = THIS_MODULE;
58383c78 782 gpio_dev->gc.parent = &pdev->dev;
dbad75dd
KX		 783 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS;
784#if defined(CONFIG_OF_GPIO)
785 gpio_dev->gc.of_node = pdev->dev.of_node;
786#endif
787
788 gpio_dev->groups = kerncz_groups;
789 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
790
791 amd_pinctrl_desc.name = dev_name(&pdev->dev);
251e22ab
LD		 792 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
793 gpio_dev);
323de9ef 794 if (IS_ERR(gpio_dev->pctrl)) {
dbad75dd 795 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
323de9ef 796 return PTR_ERR(gpio_dev->pctrl);
dbad75dd
KX		 797 }
798
04d36723 799 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
dbad75dd 800 if (ret)
251e22ab 801 return ret;
dbad75dd
KX		 802
803 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
804 0, 0, TOTAL_NUMBER_OF_PINS);
805 if (ret) {
806 dev_err(&pdev->dev, "Failed to add pin range\n");
807 goto out2;
808 }
809
810 ret = gpiochip_irqchip_add(&gpio_dev->gc,
811 &amd_gpio_irqchip,
812 0,
813 handle_simple_irq,
814 IRQ_TYPE_NONE);
815 if (ret) {
816 dev_err(&pdev->dev, "could not add irqchip\n");
817 ret = -ENODEV;
818 goto out2;
819 }
820
821 gpiochip_set_chained_irqchip(&gpio_dev->gc,
822 &amd_gpio_irqchip,
823 irq_base,
824 amd_gpio_irq_handler);
825
826 platform_set_drvdata(pdev, gpio_dev);
827
828 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
829 return ret;
830
831out2:
832 gpiochip_remove(&gpio_dev->gc);
833
dbad75dd
KX		 834 return ret;
835}
836
837static int amd_gpio_remove(struct platform_device *pdev)
838{
839 struct amd_gpio *gpio_dev;
840
841 gpio_dev = platform_get_drvdata(pdev);
842
843 gpiochip_remove(&gpio_dev->gc);
dbad75dd
KX		 844
845 return 0;
846}
847
848static const struct acpi_device_id amd_gpio_acpi_match[] = {
849 { "AMD0030", 0 },
42a44402 850 { "AMDI0030", 0},
dbad75dd
KX		 851 { },
852};
853MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
854
855static struct platform_driver amd_gpio_driver = {
856 .driver = {
857 .name = "amd_gpio",
dbad75dd
KX		 858 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
859 },
860 .probe = amd_gpio_probe,
861 .remove = amd_gpio_remove,
862};
863
864module_platform_driver(amd_gpio_driver);
865
866MODULE_LICENSE("GPL v2");
867MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
868MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux 6.x block layer and io_uring tree(s)