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pinctrl: mediatek: fix build for tristate changes
[linux-block.git] / drivers / pinctrl / pinctrl-amd.c
CommitLineData
75a6faf6 1// SPDX-License-Identifier: GPL-2.0-only
dbad75dd
KX		 2/*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
8 *
add7bfce
SS		 9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
dbad75dd
KX		 11 */
12
13#include <linux/err.h>
14#include <linux/bug.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/compiler.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/log2.h>
22#include <linux/io.h>
1c5fb66a 23#include <linux/gpio/driver.h>
dbad75dd
KX		 24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <linux/mutex.h>
27#include <linux/acpi.h>
28#include <linux/seq_file.h>
29#include <linux/interrupt.h>
30#include <linux/list.h>
31#include <linux/bitops.h>
dbad75dd
KX		 32#include <linux/pinctrl/pinconf.h>
33#include <linux/pinctrl/pinconf-generic.h>
34
79d2c8be 35#include "core.h"
dbad75dd
KX		 36#include "pinctrl-utils.h"
37#include "pinctrl-amd.h"
38
12b10f47
DK		 39static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
40{
41 unsigned long flags;
42 u32 pin_reg;
43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
44
45 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
46 pin_reg = readl(gpio_dev->base + offset * 4);
47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
48
3c827873
MV		 49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
50 return GPIO_LINE_DIRECTION_OUT;
51
52 return GPIO_LINE_DIRECTION_IN;
12b10f47
DK		 53}
54
dbad75dd
KX		 55static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
56{
57 unsigned long flags;
58 u32 pin_reg;
04d36723 59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 60
229710fe 61 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 62 pin_reg = readl(gpio_dev->base + offset * 4);
dbad75dd
KX		 63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
64 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 66
67 return 0;
68}
69
70static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
71 int value)
72{
73 u32 pin_reg;
74 unsigned long flags;
04d36723 75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 76
229710fe 77 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 78 pin_reg = readl(gpio_dev->base + offset * 4);
79 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
80 if (value)
81 pin_reg |= BIT(OUTPUT_VALUE_OFF);
82 else
83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
84 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 86
87 return 0;
88}
89
90static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
91{
92 u32 pin_reg;
93 unsigned long flags;
04d36723 94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 95
229710fe 96 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 97 pin_reg = readl(gpio_dev->base + offset * 4);
229710fe 98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 99
100 return !!(pin_reg & BIT(PIN_STS_OFF));
101}
102
103static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
104{
105 u32 pin_reg;
106 unsigned long flags;
04d36723 107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 108
229710fe 109 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 110 pin_reg = readl(gpio_dev->base + offset * 4);
111 if (value)
112 pin_reg |= BIT(OUTPUT_VALUE_OFF);
113 else
114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
115 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 117}
118
119static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
120 unsigned debounce)
121{
dbad75dd 122 u32 time;
25a853d0
KX		 123 u32 pin_reg;
124 int ret = 0;
dbad75dd 125 unsigned long flags;
04d36723 126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 127
229710fe 128 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 129 pin_reg = readl(gpio_dev->base + offset * 4);
130
131 if (debounce) {
132 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
133 pin_reg &= ~DB_TMR_OUT_MASK;
134 /*
135 Debounce Debounce Timer Max
136 TmrLarge TmrOutUnit Unit Debounce
137 Time
138 0 0 61 usec (2 RtcClk) 976 usec
139 0 1 244 usec (8 RtcClk) 3.9 msec
140 1 0 15.6 msec (512 RtcClk) 250 msec
141 1 1 62.5 msec (2048 RtcClk) 1 sec
142 */
143
144 if (debounce < 61) {
145 pin_reg |= 1;
146 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
147 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
148 } else if (debounce < 976) {
149 time = debounce / 61;
150 pin_reg |= time & DB_TMR_OUT_MASK;
151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
153 } else if (debounce < 3900) {
154 time = debounce / 244;
155 pin_reg |= time & DB_TMR_OUT_MASK;
156 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 } else if (debounce < 250000) {
159 time = debounce / 15600;
160 pin_reg |= time & DB_TMR_OUT_MASK;
161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
162 pin_reg |= BIT(DB_TMR_LARGE_OFF);
163 } else if (debounce < 1000000) {
164 time = debounce / 62500;
165 pin_reg |= time & DB_TMR_OUT_MASK;
166 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
167 pin_reg |= BIT(DB_TMR_LARGE_OFF);
168 } else {
169 pin_reg &= ~DB_CNTRl_MASK;
25a853d0 170 ret = -EINVAL;
dbad75dd
KX		 171 }
172 } else {
173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
174 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
175 pin_reg &= ~DB_TMR_OUT_MASK;
176 pin_reg &= ~DB_CNTRl_MASK;
177 }
178 writel(pin_reg, gpio_dev->base + offset * 4);
229710fe 179 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 180
25a853d0 181 return ret;
dbad75dd
KX		 182}
183
2956b5d9
MW		 184static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
185 unsigned long config)
186{
187 u32 debounce;
188
189 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
190 return -ENOTSUPP;
191
192 debounce = pinconf_to_config_argument(config);
193 return amd_gpio_set_debounce(gc, offset, debounce);
194}
195
dbad75dd
KX		 196#ifdef CONFIG_DEBUG_FS
197static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
198{
199 u32 pin_reg;
200 unsigned long flags;
201 unsigned int bank, i, pin_num;
04d36723 202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 203
204 char *level_trig;
205 char *active_level;
206 char *interrupt_enable;
207 char *interrupt_mask;
208 char *wake_cntrl0;
209 char *wake_cntrl1;
210 char *wake_cntrl2;
211 char *pin_sts;
212 char *pull_up_sel;
213 char *pull_up_enable;
214 char *pull_down_enable;
215 char *output_value;
216 char *output_enable;
217
3bfd4430 218 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
dbad75dd
KX		 219 seq_printf(s, "GPIO bank%d\t", bank);
220
221 switch (bank) {
222 case 0:
223 i = 0;
224 pin_num = AMD_GPIO_PINS_BANK0;
225 break;
226 case 1:
227 i = 64;
228 pin_num = AMD_GPIO_PINS_BANK1 + i;
229 break;
230 case 2:
231 i = 128;
232 pin_num = AMD_GPIO_PINS_BANK2 + i;
233 break;
3bfd4430
SN		 234 case 3:
235 i = 192;
236 pin_num = AMD_GPIO_PINS_BANK3 + i;
237 break;
6ac4c1ad
LW		 238 default:
239 /* Illegal bank number, ignore */
240 continue;
dbad75dd 241 }
dbad75dd
KX		 242 for (; i < pin_num; i++) {
243 seq_printf(s, "pin%d\t", i);
229710fe 244 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 245 pin_reg = readl(gpio_dev->base + i * 4);
229710fe 246 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 247
248 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
1766e4b7
DK		 249 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
250 ACTIVE_LEVEL_MASK;
dbad75dd
KX		 251 interrupt_enable = "interrupt is enabled|";
252
1766e4b7 253 if (level == ACTIVE_LEVEL_HIGH)
dbad75dd 254 active_level = "Active high|";
1766e4b7
DK		 255 else if (level == ACTIVE_LEVEL_LOW)
256 active_level = "Active low|";
257 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
258 level == ACTIVE_LEVEL_BOTH)
dbad75dd
KX		 259 active_level = "Active on both|";
260 else
0a95160e 261 active_level = "Unknown Active level|";
dbad75dd
KX		 262
263 if (pin_reg & BIT(LEVEL_TRIG_OFF))
264 level_trig = "Level trigger|";
265 else
266 level_trig = "Edge trigger|";
267
268 } else {
269 interrupt_enable =
270 "interrupt is disabled|";
271 active_level = " ";
272 level_trig = " ";
273 }
274
275 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
276 interrupt_mask =
277 "interrupt is unmasked|";
278 else
279 interrupt_mask =
280 "interrupt is masked|";
281
3bfd4430 282 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
dbad75dd
KX		 283 wake_cntrl0 = "enable wakeup in S0i3 state|";
284 else
285 wake_cntrl0 = "disable wakeup in S0i3 state|";
286
3bfd4430 287 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
dbad75dd
KX		 288 wake_cntrl1 = "enable wakeup in S3 state|";
289 else
290 wake_cntrl1 = "disable wakeup in S3 state|";
291
3bfd4430 292 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
dbad75dd
KX		 293 wake_cntrl2 = "enable wakeup in S4/S5 state|";
294 else
295 wake_cntrl2 = "disable wakeup in S4/S5 state|";
296
297 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
298 pull_up_enable = "pull-up is enabled|";
299 if (pin_reg & BIT(PULL_UP_SEL_OFF))
300 pull_up_sel = "8k pull-up|";
301 else
302 pull_up_sel = "4k pull-up|";
303 } else {
304 pull_up_enable = "pull-up is disabled|";
305 pull_up_sel = " ";
306 }
307
308 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
309 pull_down_enable = "pull-down is enabled|";
310 else
311 pull_down_enable = "Pull-down is disabled|";
312
313 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
314 pin_sts = " ";
315 output_enable = "output is enabled|";
316 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
317 output_value = "output is high|";
318 else
319 output_value = "output is low|";
320 } else {
321 output_enable = "output is disabled|";
322 output_value = " ";
323
324 if (pin_reg & BIT(PIN_STS_OFF))
325 pin_sts = "input is high|";
326 else
327 pin_sts = "input is low|";
328 }
329
330 seq_printf(s, "%s %s %s %s %s %s\n"
331 " %s %s %s %s %s %s %s 0x%x\n",
332 level_trig, active_level, interrupt_enable,
333 interrupt_mask, wake_cntrl0, wake_cntrl1,
334 wake_cntrl2, pin_sts, pull_up_sel,
335 pull_up_enable, pull_down_enable,
336 output_value, output_enable, pin_reg);
337 }
338 }
339}
340#else
341#define amd_gpio_dbg_show NULL
342#endif
343
344static void amd_gpio_irq_enable(struct irq_data *d)
345{
346 u32 pin_reg;
347 unsigned long flags;
348 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 349 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 350
229710fe 351 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 352 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
dbad75dd
KX		 353 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
354 pin_reg |= BIT(INTERRUPT_MASK_OFF);
355 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 356 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 357}
358
359static void amd_gpio_irq_disable(struct irq_data *d)
360{
361 u32 pin_reg;
362 unsigned long flags;
363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 364 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 365
229710fe 366 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 367 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
368 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
369 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
370 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 371 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 372}
373
374static void amd_gpio_irq_mask(struct irq_data *d)
375{
376 u32 pin_reg;
377 unsigned long flags;
378 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 379 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 380
229710fe 381 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 382 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
383 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
384 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 385 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 386}
387
388static void amd_gpio_irq_unmask(struct irq_data *d)
389{
390 u32 pin_reg;
391 unsigned long flags;
392 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 393 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 394
229710fe 395 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 396 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
397 pin_reg |= BIT(INTERRUPT_MASK_OFF);
398 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 399 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 400}
401
402static void amd_gpio_irq_eoi(struct irq_data *d)
403{
404 u32 reg;
405 unsigned long flags;
406 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 407 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 408
229710fe 409 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 410 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
411 reg |= EOI_MASK;
412 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
229710fe 413 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 414}
415
416static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
417{
418 int ret = 0;
b85bfa24 419 u32 pin_reg, pin_reg_irq_en, mask;
5f4962dd 420 unsigned long flags;
dbad75dd 421 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 422 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 423
229710fe 424 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 425 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
426
427 switch (type & IRQ_TYPE_SENSE_MASK) {
428 case IRQ_TYPE_EDGE_RISING:
429 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
430 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
431 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
432 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 433 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 434 break;
435
436 case IRQ_TYPE_EDGE_FALLING:
437 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
438 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
439 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
440 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 441 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 442 break;
443
444 case IRQ_TYPE_EDGE_BOTH:
445 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
446 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
447 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
448 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 449 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 450 break;
451
452 case IRQ_TYPE_LEVEL_HIGH:
453 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
454 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
455 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
456 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
457 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
9d829314 458 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 459 break;
460
461 case IRQ_TYPE_LEVEL_LOW:
462 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
463 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
464 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
465 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
466 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
9d829314 467 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 468 break;
469
470 case IRQ_TYPE_NONE:
471 break;
472
473 default:
474 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
475 ret = -EINVAL;
dbad75dd
KX		 476 }
477
478 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
b85bfa24
DK		 479 /*
480 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
481 * debounce registers of any GPIO will block wake/interrupt status
48c67f1f 482 * generation for *all* GPIOs for a length of time that depends on
b85bfa24
DK		 483 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
484 * INTERRUPT_ENABLE bit will read as 0.
485 *
486 * We temporarily enable irq for the GPIO whose configuration is
487 * changing, and then wait for it to read back as 1 to know when
488 * debounce has settled and then disable the irq again.
489 * We do this polling with the spinlock held to ensure other GPIO
490 * access routines do not read an incorrect value for the irq enable
491 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
492 * spurious irqs, and disable the irq again after polling.
493 */
494 mask = BIT(INTERRUPT_ENABLE_OFF);
495 pin_reg_irq_en = pin_reg;
496 pin_reg_irq_en |= mask;
497 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
498 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
499 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
500 continue;
dbad75dd 501 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
229710fe 502 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 503
dbad75dd
KX		 504 return ret;
505}
506
507static void amd_irq_ack(struct irq_data *d)
508{
509 /*
510 * based on HW design,there is no need to ack HW
511 * before handle current irq. But this routine is
512 * necessary for handle_edge_irq
513 */
514}
515
516static struct irq_chip amd_gpio_irqchip = {
517 .name = "amd_gpio",
518 .irq_ack = amd_irq_ack,
519 .irq_enable = amd_gpio_irq_enable,
520 .irq_disable = amd_gpio_irq_disable,
521 .irq_mask = amd_gpio_irq_mask,
522 .irq_unmask = amd_gpio_irq_unmask,
523 .irq_eoi = amd_gpio_irq_eoi,
524 .irq_set_type = amd_gpio_irq_set_type,
3bfd4430 525 .flags = IRQCHIP_SKIP_SET_WAKE,
dbad75dd
KX		 526};
527
ba714a9c
TG		 528#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
529
530static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
dbad75dd 531{
ba714a9c
TG		 532 struct amd_gpio *gpio_dev = dev_id;
533 struct gpio_chip *gc = &gpio_dev->gc;
534 irqreturn_t ret = IRQ_NONE;
535 unsigned int i, irqnr;
dbad75dd 536 unsigned long flags;
10ff58aa
BDC		 537 u32 __iomem *regs;
538 u32 regval;
ba714a9c 539 u64 status, mask;
dbad75dd 540
ba714a9c 541 /* Read the wake status */
229710fe 542 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
ba714a9c
TG		 543 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
544 status <<= 32;
545 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
229710fe 546 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 547
ba714a9c
TG		 548 /* Bit 0-45 contain the relevant status bits */
549 status &= (1ULL << 46) - 1;
550 regs = gpio_dev->base;
551 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
552 if (!(status & mask))
553 continue;
554 status &= ~mask;
555
556 /* Each status bit covers four pins */
557 for (i = 0; i < 4; i++) {
558 regval = readl(regs + i);
8bbed1ee
DK		 559 if (!(regval & PIN_IRQ_PENDING) ||
560 !(regval & BIT(INTERRUPT_MASK_OFF)))
ba714a9c 561 continue;
f0fbe7bc 562 irq = irq_find_mapping(gc->irq.domain, irqnr + i);
d21b8adb
DD		 563 if (irq != 0)
564 generic_handle_irq(irq);
6afb1026
DD		 565
566 /* Clear interrupt.
567 * We must read the pin register again, in case the
568 * value was changed while executing
569 * generic_handle_irq() above.
d21b8adb
DD		 570 * If we didn't find a mapping for the interrupt,
571 * disable it in order to avoid a system hang caused
572 * by an interrupt storm.
6afb1026
DD		 573 */
574 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
575 regval = readl(regs + i);
d21b8adb
DD		 576 if (irq == 0) {
577 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
578 dev_dbg(&gpio_dev->pdev->dev,
579 "Disabling spurious GPIO IRQ %d\n",
580 irqnr + i);
581 }
ba714a9c 582 writel(regval, regs + i);
6afb1026 583 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
ba714a9c 584 ret = IRQ_HANDLED;
dbad75dd
KX		 585 }
586 }
587
ba714a9c 588 /* Signal EOI to the GPIO unit */
229710fe 589 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
ba714a9c
TG		 590 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
591 regval |= EOI_MASK;
592 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
229710fe 593 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 594
ba714a9c 595 return ret;
dbad75dd
KX		 596}
597
598static int amd_get_groups_count(struct pinctrl_dev *pctldev)
599{
600 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
601
602 return gpio_dev->ngroups;
603}
604
605static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
606 unsigned group)
607{
608 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
609
610 return gpio_dev->groups[group].name;
611}
612
613static int amd_get_group_pins(struct pinctrl_dev *pctldev,
614 unsigned group,
615 const unsigned **pins,
616 unsigned *num_pins)
617{
618 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
619
620 *pins = gpio_dev->groups[group].pins;
621 *num_pins = gpio_dev->groups[group].npins;
622 return 0;
623}
624
625static const struct pinctrl_ops amd_pinctrl_ops = {
626 .get_groups_count = amd_get_groups_count,
627 .get_group_name = amd_get_group_name,
628 .get_group_pins = amd_get_group_pins,
629#ifdef CONFIG_OF
630 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
d32f7fd3 631 .dt_free_map = pinctrl_utils_free_map,
dbad75dd
KX		 632#endif
633};
634
635static int amd_pinconf_get(struct pinctrl_dev *pctldev,
636 unsigned int pin,
637 unsigned long *config)
638{
639 u32 pin_reg;
640 unsigned arg;
641 unsigned long flags;
642 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
643 enum pin_config_param param = pinconf_to_config_param(*config);
644
229710fe 645 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 646 pin_reg = readl(gpio_dev->base + pin*4);
229710fe 647 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 648 switch (param) {
649 case PIN_CONFIG_INPUT_DEBOUNCE:
650 arg = pin_reg & DB_TMR_OUT_MASK;
651 break;
652
653 case PIN_CONFIG_BIAS_PULL_DOWN:
654 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
655 break;
656
657 case PIN_CONFIG_BIAS_PULL_UP:
658 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
659 break;
660
661 case PIN_CONFIG_DRIVE_STRENGTH:
662 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
663 break;
664
665 default:
666 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
667 param);
668 return -ENOTSUPP;
669 }
670
671 *config = pinconf_to_config_packed(param, arg);
672
673 return 0;
674}
675
676static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
677 unsigned long *configs, unsigned num_configs)
678{
679 int i;
dbad75dd 680 u32 arg;
25a853d0
KX		 681 int ret = 0;
682 u32 pin_reg;
dbad75dd
KX		 683 unsigned long flags;
684 enum pin_config_param param;
685 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
686
229710fe 687 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 688 for (i = 0; i < num_configs; i++) {
689 param = pinconf_to_config_param(configs[i]);
690 arg = pinconf_to_config_argument(configs[i]);
691 pin_reg = readl(gpio_dev->base + pin*4);
692
693 switch (param) {
694 case PIN_CONFIG_INPUT_DEBOUNCE:
695 pin_reg &= ~DB_TMR_OUT_MASK;
696 pin_reg |= arg & DB_TMR_OUT_MASK;
697 break;
698
699 case PIN_CONFIG_BIAS_PULL_DOWN:
700 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
701 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
702 break;
703
704 case PIN_CONFIG_BIAS_PULL_UP:
705 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
706 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
707 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
708 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
709 break;
710
711 case PIN_CONFIG_DRIVE_STRENGTH:
712 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
713 << DRV_STRENGTH_SEL_OFF);
714 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
715 << DRV_STRENGTH_SEL_OFF;
716 break;
717
718 default:
719 dev_err(&gpio_dev->pdev->dev,
720 "Invalid config param %04x\n", param);
25a853d0 721 ret = -ENOTSUPP;
dbad75dd
KX		 722 }
723
724 writel(pin_reg, gpio_dev->base + pin*4);
725 }
229710fe 726 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 727
25a853d0 728 return ret;
dbad75dd
KX		 729}
730
731static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
732 unsigned int group,
733 unsigned long *config)
734{
735 const unsigned *pins;
736 unsigned npins;
737 int ret;
738
739 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
740 if (ret)
741 return ret;
742
743 if (amd_pinconf_get(pctldev, pins[0], config))
744 return -ENOTSUPP;
745
746 return 0;
747}
748
749static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
750 unsigned group, unsigned long *configs,
751 unsigned num_configs)
752{
753 const unsigned *pins;
754 unsigned npins;
755 int i, ret;
756
757 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
758 if (ret)
759 return ret;
760 for (i = 0; i < npins; i++) {
761 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
762 return -ENOTSUPP;
763 }
764 return 0;
765}
766
767static const struct pinconf_ops amd_pinconf_ops = {
768 .pin_config_get = amd_pinconf_get,
769 .pin_config_set = amd_pinconf_set,
770 .pin_config_group_get = amd_pinconf_group_get,
771 .pin_config_group_set = amd_pinconf_group_set,
772};
773
79d2c8be
DD		 774#ifdef CONFIG_PM_SLEEP
775static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
776{
777 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
778
779 if (!pd)
780 return false;
781
782 /*
783 * Only restore the pin if it is actually in use by the kernel (or
784 * by userspace).
785 */
786 if (pd->mux_owner || pd->gpio_owner ||
787 gpiochip_line_is_irq(&gpio_dev->gc, pin))
788 return true;
789
790 return false;
791}
792
2d71dfa2 793static int amd_gpio_suspend(struct device *dev)
79d2c8be 794{
9f540c3e 795 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
79d2c8be
DD		 796 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
797 int i;
798
799 for (i = 0; i < desc->npins; i++) {
800 int pin = desc->pins[i].number;
801
802 if (!amd_gpio_should_save(gpio_dev, pin))
803 continue;
804
805 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
806 }
807
808 return 0;
809}
810
2d71dfa2 811static int amd_gpio_resume(struct device *dev)
79d2c8be 812{
9f540c3e 813 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
79d2c8be
DD		 814 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
815 int i;
816
817 for (i = 0; i < desc->npins; i++) {
818 int pin = desc->pins[i].number;
819
820 if (!amd_gpio_should_save(gpio_dev, pin))
821 continue;
822
823 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
824 }
825
826 return 0;
827}
828
829static const struct dev_pm_ops amd_gpio_pm_ops = {
830 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
831 amd_gpio_resume)
832};
833#endif
834
dbad75dd
KX		 835static struct pinctrl_desc amd_pinctrl_desc = {
836 .pins = kerncz_pins,
837 .npins = ARRAY_SIZE(kerncz_pins),
838 .pctlops = &amd_pinctrl_ops,
839 .confops = &amd_pinconf_ops,
840 .owner = THIS_MODULE,
841};
842
843static int amd_gpio_probe(struct platform_device *pdev)
844{
845 int ret = 0;
25a853d0 846 int irq_base;
dbad75dd
KX		 847 struct resource *res;
848 struct amd_gpio *gpio_dev;
849
850 gpio_dev = devm_kzalloc(&pdev->dev,
851 sizeof(struct amd_gpio), GFP_KERNEL);
852 if (!gpio_dev)
853 return -ENOMEM;
854
229710fe 855 raw_spin_lock_init(&gpio_dev->lock);
dbad75dd
KX		 856
857 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
858 if (!res) {
859 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
860 return -EINVAL;
861 }
862
4bdc0d67 863 gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
dbad75dd 864 resource_size(res));
424a6c60
WY		 865 if (!gpio_dev->base)
866 return -ENOMEM;
dbad75dd
KX		 867
868 irq_base = platform_get_irq(pdev, 0);
64c4dcbf 869 if (irq_base < 0)
2e6424ab 870 return irq_base;
dbad75dd 871
79d2c8be
DD		 872#ifdef CONFIG_PM_SLEEP
873 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
874 sizeof(*gpio_dev->saved_regs),
875 GFP_KERNEL);
876 if (!gpio_dev->saved_regs)
877 return -ENOMEM;
878#endif
879
dbad75dd 880 gpio_dev->pdev = pdev;
12b10f47 881 gpio_dev->gc.get_direction = amd_gpio_get_direction;
dbad75dd
KX		 882 gpio_dev->gc.direction_input = amd_gpio_direction_input;
883 gpio_dev->gc.direction_output = amd_gpio_direction_output;
884 gpio_dev->gc.get = amd_gpio_get_value;
885 gpio_dev->gc.set = amd_gpio_set_value;
2956b5d9 886 gpio_dev->gc.set_config = amd_gpio_set_config;
dbad75dd
KX		 887 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
888
3bfd4430 889 gpio_dev->gc.base = -1;
dbad75dd
KX		 890 gpio_dev->gc.label = pdev->name;
891 gpio_dev->gc.owner = THIS_MODULE;
58383c78 892 gpio_dev->gc.parent = &pdev->dev;
3bfd4430 893 gpio_dev->gc.ngpio = resource_size(res) / 4;
dbad75dd
KX		 894#if defined(CONFIG_OF_GPIO)
895 gpio_dev->gc.of_node = pdev->dev.of_node;
896#endif
897
3bfd4430 898 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
dbad75dd
KX		 899 gpio_dev->groups = kerncz_groups;
900 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
901
902 amd_pinctrl_desc.name = dev_name(&pdev->dev);
251e22ab
LD		 903 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
904 gpio_dev);
323de9ef 905 if (IS_ERR(gpio_dev->pctrl)) {
dbad75dd 906 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
323de9ef 907 return PTR_ERR(gpio_dev->pctrl);
dbad75dd
KX		 908 }
909
04d36723 910 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
dbad75dd 911 if (ret)
251e22ab 912 return ret;
dbad75dd
KX		 913
914 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
3bfd4430 915 0, 0, gpio_dev->gc.ngpio);
dbad75dd
KX		 916 if (ret) {
917 dev_err(&pdev->dev, "Failed to add pin range\n");
918 goto out2;
919 }
920
921 ret = gpiochip_irqchip_add(&gpio_dev->gc,
922 &amd_gpio_irqchip,
923 0,
924 handle_simple_irq,
925 IRQ_TYPE_NONE);
926 if (ret) {
927 dev_err(&pdev->dev, "could not add irqchip\n");
928 ret = -ENODEV;
929 goto out2;
930 }
931
279ffafa
SS		 932 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
933 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
ba714a9c
TG		 934 if (ret)
935 goto out2;
936
dbad75dd
KX		 937 platform_set_drvdata(pdev, gpio_dev);
938
939 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
940 return ret;
941
942out2:
943 gpiochip_remove(&gpio_dev->gc);
944
dbad75dd
KX		 945 return ret;
946}
947
948static int amd_gpio_remove(struct platform_device *pdev)
949{
950 struct amd_gpio *gpio_dev;
951
952 gpio_dev = platform_get_drvdata(pdev);
953
954 gpiochip_remove(&gpio_dev->gc);
dbad75dd
KX		 955
956 return 0;
957}
958
de4334f7 959#ifdef CONFIG_ACPI
dbad75dd
KX		 960static const struct acpi_device_id amd_gpio_acpi_match[] = {
961 { "AMD0030", 0 },
42a44402 962 { "AMDI0030", 0},
dbad75dd
KX		 963 { },
964};
965MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
de4334f7 966#endif
dbad75dd
KX		 967
968static struct platform_driver amd_gpio_driver = {
969 .driver = {
970 .name = "amd_gpio",
dbad75dd 971 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
79d2c8be
DD		 972#ifdef CONFIG_PM_SLEEP
973 .pm = &amd_gpio_pm_ops,
974#endif
dbad75dd
KX		 975 },
976 .probe = amd_gpio_probe,
977 .remove = amd_gpio_remove,
978};
979
980module_platform_driver(amd_gpio_driver);
981
982MODULE_LICENSE("GPL v2");
983MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
984MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux 6.x block layer and io_uring tree(s)