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0493e649 PC |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2013 | |
3 | * | |
4 | * Author: Patrice Chotard <patrice.chotard@st.com> | |
5 | * License terms: GNU General Public License (GPL) version 2 | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/err.h> | |
f30a3839 LJ |
17 | #include <linux/of.h> |
18 | #include <linux/of_device.h> | |
0493e649 PC |
19 | #include <linux/platform_device.h> |
20 | #include <linux/gpio.h> | |
21 | #include <linux/irq.h> | |
ac652d79 | 22 | #include <linux/irqdomain.h> |
0493e649 PC |
23 | #include <linux/interrupt.h> |
24 | #include <linux/bitops.h> | |
25 | #include <linux/mfd/abx500.h> | |
26 | #include <linux/mfd/abx500/ab8500.h> | |
27 | #include <linux/mfd/abx500/ab8500-gpio.h> | |
28 | #include <linux/pinctrl/pinctrl.h> | |
29 | #include <linux/pinctrl/consumer.h> | |
30 | #include <linux/pinctrl/pinmux.h> | |
31 | #include <linux/pinctrl/pinconf.h> | |
32 | #include <linux/pinctrl/pinconf-generic.h> | |
64a45c98 | 33 | #include <linux/pinctrl/machine.h> |
0493e649 PC |
34 | |
35 | #include "pinctrl-abx500.h" | |
64a45c98 | 36 | #include "pinconf.h" |
0493e649 PC |
37 | |
38 | /* | |
39 | * The AB9540 and AB8540 GPIO support are extended versions | |
40 | * of the AB8500 GPIO support. | |
41 | * The AB9540 supports an additional (7th) register so that | |
42 | * more GPIO may be configured and used. | |
43 | * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have | |
44 | * internal pull-up and pull-down capabilities. | |
45 | */ | |
46 | ||
47 | /* | |
48 | * GPIO registers offset | |
49 | * Bank: 0x10 | |
50 | */ | |
51 | #define AB8500_GPIO_SEL1_REG 0x00 | |
52 | #define AB8500_GPIO_SEL2_REG 0x01 | |
53 | #define AB8500_GPIO_SEL3_REG 0x02 | |
54 | #define AB8500_GPIO_SEL4_REG 0x03 | |
55 | #define AB8500_GPIO_SEL5_REG 0x04 | |
56 | #define AB8500_GPIO_SEL6_REG 0x05 | |
57 | #define AB9540_GPIO_SEL7_REG 0x06 | |
58 | ||
59 | #define AB8500_GPIO_DIR1_REG 0x10 | |
60 | #define AB8500_GPIO_DIR2_REG 0x11 | |
61 | #define AB8500_GPIO_DIR3_REG 0x12 | |
62 | #define AB8500_GPIO_DIR4_REG 0x13 | |
63 | #define AB8500_GPIO_DIR5_REG 0x14 | |
64 | #define AB8500_GPIO_DIR6_REG 0x15 | |
65 | #define AB9540_GPIO_DIR7_REG 0x16 | |
66 | ||
67 | #define AB8500_GPIO_OUT1_REG 0x20 | |
68 | #define AB8500_GPIO_OUT2_REG 0x21 | |
69 | #define AB8500_GPIO_OUT3_REG 0x22 | |
70 | #define AB8500_GPIO_OUT4_REG 0x23 | |
71 | #define AB8500_GPIO_OUT5_REG 0x24 | |
72 | #define AB8500_GPIO_OUT6_REG 0x25 | |
73 | #define AB9540_GPIO_OUT7_REG 0x26 | |
74 | ||
75 | #define AB8500_GPIO_PUD1_REG 0x30 | |
76 | #define AB8500_GPIO_PUD2_REG 0x31 | |
77 | #define AB8500_GPIO_PUD3_REG 0x32 | |
78 | #define AB8500_GPIO_PUD4_REG 0x33 | |
79 | #define AB8500_GPIO_PUD5_REG 0x34 | |
80 | #define AB8500_GPIO_PUD6_REG 0x35 | |
81 | #define AB9540_GPIO_PUD7_REG 0x36 | |
82 | ||
83 | #define AB8500_GPIO_IN1_REG 0x40 | |
84 | #define AB8500_GPIO_IN2_REG 0x41 | |
85 | #define AB8500_GPIO_IN3_REG 0x42 | |
86 | #define AB8500_GPIO_IN4_REG 0x43 | |
87 | #define AB8500_GPIO_IN5_REG 0x44 | |
88 | #define AB8500_GPIO_IN6_REG 0x45 | |
89 | #define AB9540_GPIO_IN7_REG 0x46 | |
90 | #define AB8540_GPIO_VINSEL_REG 0x47 | |
91 | #define AB8540_GPIO_PULL_UPDOWN_REG 0x48 | |
92 | #define AB8500_GPIO_ALTFUN_REG 0x50 | |
0493e649 PC |
93 | #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03 |
94 | #define AB8540_GPIO_VINSEL_MASK 0x03 | |
95 | #define AB8540_GPIOX_VBAT_START 51 | |
96 | #define AB8540_GPIOX_VBAT_END 54 | |
97 | ||
0493e649 PC |
98 | struct abx500_pinctrl { |
99 | struct device *dev; | |
100 | struct pinctrl_dev *pctldev; | |
101 | struct abx500_pinctrl_soc_data *soc; | |
102 | struct gpio_chip chip; | |
103 | struct ab8500 *parent; | |
0493e649 PC |
104 | struct abx500_gpio_irq_cluster *irq_cluster; |
105 | int irq_cluster_size; | |
0493e649 PC |
106 | }; |
107 | ||
108 | /** | |
109 | * to_abx500_pinctrl() - get the pointer to abx500_pinctrl | |
110 | * @chip: Member of the structure abx500_pinctrl | |
111 | */ | |
112 | static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip) | |
113 | { | |
114 | return container_of(chip, struct abx500_pinctrl, chip); | |
115 | } | |
116 | ||
117 | static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 118 | unsigned offset, bool *bit) |
0493e649 PC |
119 | { |
120 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
121 | u8 pos = offset % 8; | |
122 | u8 val; | |
123 | int ret; | |
124 | ||
125 | reg += offset / 8; | |
126 | ret = abx500_get_register_interruptible(pct->dev, | |
127 | AB8500_MISC, reg, &val); | |
128 | ||
129 | *bit = !!(val & BIT(pos)); | |
130 | ||
131 | if (ret < 0) | |
132 | dev_err(pct->dev, | |
133 | "%s read reg =%x, offset=%x failed\n", | |
134 | __func__, reg, offset); | |
135 | ||
136 | return ret; | |
137 | } | |
138 | ||
139 | static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 140 | unsigned offset, int val) |
0493e649 PC |
141 | { |
142 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
143 | u8 pos = offset % 8; | |
144 | int ret; | |
145 | ||
146 | reg += offset / 8; | |
147 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
49dcf086 | 148 | AB8500_MISC, reg, BIT(pos), val << pos); |
0493e649 PC |
149 | if (ret < 0) |
150 | dev_err(pct->dev, "%s write failed\n", __func__); | |
83b423c8 | 151 | |
0493e649 PC |
152 | return ret; |
153 | } | |
83b423c8 | 154 | |
0493e649 PC |
155 | /** |
156 | * abx500_gpio_get() - Get the particular GPIO value | |
83b423c8 LJ |
157 | * @chip: Gpio device |
158 | * @offset: GPIO number to read | |
0493e649 PC |
159 | */ |
160 | static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) | |
161 | { | |
162 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
163 | bool bit; | |
164 | int ret; | |
165 | ||
166 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, | |
167 | offset, &bit); | |
168 | if (ret < 0) { | |
169 | dev_err(pct->dev, "%s failed\n", __func__); | |
170 | return ret; | |
171 | } | |
83b423c8 | 172 | |
0493e649 PC |
173 | return bit; |
174 | } | |
175 | ||
176 | static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
177 | { | |
178 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
179 | int ret; | |
180 | ||
181 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
182 | if (ret < 0) | |
183 | dev_err(pct->dev, "%s write failed\n", __func__); | |
184 | } | |
185 | ||
d2752ae5 PC |
186 | static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset, |
187 | enum abx500_gpio_pull_updown *pull_updown) | |
0493e649 PC |
188 | { |
189 | u8 pos; | |
d2752ae5 | 190 | u8 val; |
0493e649 PC |
191 | int ret; |
192 | struct pullud *pullud; | |
193 | ||
194 | if (!pct->soc->pullud) { | |
195 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
196 | __func__); | |
197 | ret = -EPERM; | |
198 | goto out; | |
199 | } | |
200 | ||
201 | pullud = pct->soc->pullud; | |
202 | ||
203 | if ((offset < pullud->first_pin) | |
204 | || (offset > pullud->last_pin)) { | |
205 | ret = -EINVAL; | |
206 | goto out; | |
207 | } | |
208 | ||
d2752ae5 PC |
209 | ret = abx500_get_register_interruptible(pct->dev, |
210 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val); | |
211 | ||
212 | pos = (offset - pullud->first_pin) << 1; | |
213 | *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK; | |
214 | ||
215 | out: | |
216 | if (ret < 0) | |
217 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
218 | ||
219 | return ret; | |
220 | } | |
221 | ||
222 | static int abx500_set_pull_updown(struct abx500_pinctrl *pct, | |
223 | int offset, enum abx500_gpio_pull_updown val) | |
224 | { | |
225 | u8 pos; | |
226 | int ret; | |
227 | struct pullud *pullud; | |
228 | ||
229 | if (!pct->soc->pullud) { | |
230 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
231 | __func__); | |
232 | ret = -EPERM; | |
233 | goto out; | |
234 | } | |
235 | ||
236 | pullud = pct->soc->pullud; | |
237 | ||
238 | if ((offset < pullud->first_pin) | |
239 | || (offset > pullud->last_pin)) { | |
240 | ret = -EINVAL; | |
241 | goto out; | |
242 | } | |
10a8be54 | 243 | pos = (offset - pullud->first_pin) << 1; |
0493e649 PC |
244 | |
245 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
246 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, | |
247 | AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos); | |
248 | ||
249 | out: | |
250 | if (ret < 0) | |
251 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
83b423c8 | 252 | |
0493e649 PC |
253 | return ret; |
254 | } | |
255 | ||
256 | static int abx500_gpio_direction_output(struct gpio_chip *chip, | |
257 | unsigned offset, | |
258 | int val) | |
259 | { | |
260 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
261 | struct pullud *pullud = pct->soc->pullud; | |
262 | unsigned gpio; | |
263 | int ret; | |
83b423c8 | 264 | |
0493e649 PC |
265 | /* set direction as output */ |
266 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1); | |
267 | if (ret < 0) | |
268 | return ret; | |
269 | ||
270 | /* disable pull down */ | |
271 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1); | |
272 | if (ret < 0) | |
273 | return ret; | |
274 | ||
275 | /* if supported, disable both pull down and pull up */ | |
276 | gpio = offset + 1; | |
277 | if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) { | |
d2752ae5 | 278 | ret = abx500_set_pull_updown(pct, |
0493e649 PC |
279 | gpio, |
280 | ABX500_GPIO_PULL_NONE); | |
281 | if (ret < 0) | |
282 | return ret; | |
283 | } | |
83b423c8 | 284 | |
0493e649 PC |
285 | /* set the output as 1 or 0 */ |
286 | return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
287 | } | |
288 | ||
289 | static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
290 | { | |
291 | /* set the register as input */ | |
292 | return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0); | |
293 | } | |
294 | ||
295 | static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
296 | { | |
297 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
b9fab6e4 LJ |
298 | /* The AB8500 GPIO numbers are off by one */ |
299 | int gpio = offset + 1; | |
a6a16d27 | 300 | int hwirq; |
0493e649 PC |
301 | int i; |
302 | ||
303 | for (i = 0; i < pct->irq_cluster_size; i++) { | |
304 | struct abx500_gpio_irq_cluster *cluster = | |
305 | &pct->irq_cluster[i]; | |
306 | ||
a6a16d27 LJ |
307 | if (gpio >= cluster->start && gpio <= cluster->end) { |
308 | /* | |
309 | * The ABx500 GPIO's associated IRQs are clustered together | |
310 | * throughout the interrupt numbers at irregular intervals. | |
311 | * To solve this quandry, we have placed the read-in values | |
312 | * into the cluster information table. | |
313 | */ | |
43a255db | 314 | hwirq = gpio - cluster->start + cluster->to_irq; |
a6a16d27 LJ |
315 | return irq_create_mapping(pct->parent->domain, hwirq); |
316 | } | |
0493e649 PC |
317 | } |
318 | ||
319 | return -EINVAL; | |
320 | } | |
321 | ||
322 | static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
83b423c8 | 323 | unsigned gpio, int alt_setting) |
0493e649 PC |
324 | { |
325 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
326 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
327 | int ret; | |
328 | int val; | |
329 | unsigned offset; | |
83b423c8 | 330 | |
0493e649 PC |
331 | const char *modes[] = { |
332 | [ABX500_DEFAULT] = "default", | |
333 | [ABX500_ALT_A] = "altA", | |
334 | [ABX500_ALT_B] = "altB", | |
335 | [ABX500_ALT_C] = "altC", | |
336 | }; | |
337 | ||
338 | /* sanity check */ | |
339 | if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || | |
340 | ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || | |
341 | ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { | |
342 | dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, | |
343 | modes[alt_setting]); | |
344 | return -EINVAL; | |
345 | } | |
346 | ||
347 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ | |
348 | offset = gpio - 1; | |
83b423c8 | 349 | |
0493e649 PC |
350 | switch (alt_setting) { |
351 | case ABX500_DEFAULT: | |
352 | /* | |
353 | * for ABx5xx family, default mode is always selected by | |
354 | * writing 0 to GPIOSELx register, except for pins which | |
355 | * support at least ALT_B mode, default mode is selected | |
356 | * by writing 1 to GPIOSELx register | |
357 | */ | |
358 | val = 0; | |
359 | if (af.alt_bit1 != UNUSED) | |
360 | val++; | |
361 | ||
362 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
363 | offset, val); | |
364 | break; | |
83b423c8 | 365 | |
0493e649 PC |
366 | case ABX500_ALT_A: |
367 | /* | |
368 | * for ABx5xx family, alt_a mode is always selected by | |
369 | * writing 1 to GPIOSELx register, except for pins which | |
370 | * support at least ALT_B mode, alt_a mode is selected | |
371 | * by writing 0 to GPIOSELx register and 0 in ALTFUNC | |
372 | * register | |
373 | */ | |
374 | if (af.alt_bit1 != UNUSED) { | |
375 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
376 | offset, 0); | |
377 | ret = abx500_gpio_set_bits(chip, | |
378 | AB8500_GPIO_ALTFUN_REG, | |
379 | af.alt_bit1, | |
380 | !!(af.alta_val && BIT(0))); | |
381 | if (af.alt_bit2 != UNUSED) | |
382 | ret = abx500_gpio_set_bits(chip, | |
383 | AB8500_GPIO_ALTFUN_REG, | |
384 | af.alt_bit2, | |
385 | !!(af.alta_val && BIT(1))); | |
386 | } else | |
387 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
388 | offset, 1); | |
389 | break; | |
83b423c8 | 390 | |
0493e649 PC |
391 | case ABX500_ALT_B: |
392 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
393 | offset, 0); | |
394 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
395 | af.alt_bit1, !!(af.altb_val && BIT(0))); | |
396 | if (af.alt_bit2 != UNUSED) | |
397 | ret = abx500_gpio_set_bits(chip, | |
398 | AB8500_GPIO_ALTFUN_REG, | |
399 | af.alt_bit2, | |
400 | !!(af.altb_val && BIT(1))); | |
401 | break; | |
83b423c8 | 402 | |
0493e649 PC |
403 | case ABX500_ALT_C: |
404 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
405 | offset, 0); | |
406 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
407 | af.alt_bit2, !!(af.altc_val && BIT(0))); | |
408 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
409 | af.alt_bit2, !!(af.altc_val && BIT(1))); | |
410 | break; | |
411 | ||
412 | default: | |
413 | dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting); | |
83b423c8 | 414 | |
0493e649 PC |
415 | return -EINVAL; |
416 | } | |
83b423c8 | 417 | |
0493e649 PC |
418 | return ret; |
419 | } | |
420 | ||
421 | static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
83b423c8 | 422 | unsigned gpio) |
0493e649 PC |
423 | { |
424 | u8 mode; | |
425 | bool bit_mode; | |
426 | bool alt_bit1; | |
427 | bool alt_bit2; | |
428 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
429 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
a950cb74 LW |
430 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ |
431 | unsigned offset = gpio - 1; | |
0493e649 PC |
432 | |
433 | /* | |
434 | * if gpiosel_bit is set to unused, | |
435 | * it means no GPIO or special case | |
436 | */ | |
437 | if (af.gpiosel_bit == UNUSED) | |
438 | return ABX500_DEFAULT; | |
439 | ||
440 | /* read GpioSelx register */ | |
a950cb74 | 441 | abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), |
0493e649 PC |
442 | af.gpiosel_bit, &bit_mode); |
443 | mode = bit_mode; | |
444 | ||
445 | /* sanity check */ | |
446 | if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || | |
447 | (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { | |
448 | dev_err(pct->dev, | |
449 | "alt_bitX value not in correct range (-1 to 7)\n"); | |
450 | return -EINVAL; | |
451 | } | |
83b423c8 | 452 | |
0493e649 PC |
453 | /* if alt_bit2 is used, alt_bit1 must be used too */ |
454 | if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { | |
455 | dev_err(pct->dev, | |
456 | "if alt_bit2 is used, alt_bit1 can't be unused\n"); | |
457 | return -EINVAL; | |
458 | } | |
459 | ||
460 | /* check if pin use AlternateFunction register */ | |
6a40cdd5 | 461 | if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED)) |
0493e649 PC |
462 | return mode; |
463 | /* | |
464 | * if pin GPIOSEL bit is set and pin supports alternate function, | |
465 | * it means DEFAULT mode | |
466 | */ | |
467 | if (mode) | |
468 | return ABX500_DEFAULT; | |
83b423c8 | 469 | |
0493e649 PC |
470 | /* |
471 | * pin use the AlternatFunction register | |
472 | * read alt_bit1 value | |
473 | */ | |
474 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, | |
475 | af.alt_bit1, &alt_bit1); | |
476 | ||
477 | if (af.alt_bit2 != UNUSED) | |
478 | /* read alt_bit2 value */ | |
479 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, | |
480 | &alt_bit2); | |
481 | else | |
482 | alt_bit2 = 0; | |
483 | ||
484 | mode = (alt_bit2 << 1) + alt_bit1; | |
485 | if (mode == af.alta_val) | |
486 | return ABX500_ALT_A; | |
487 | else if (mode == af.altb_val) | |
488 | return ABX500_ALT_B; | |
489 | else | |
490 | return ABX500_ALT_C; | |
491 | } | |
492 | ||
493 | #ifdef CONFIG_DEBUG_FS | |
494 | ||
495 | #include <linux/seq_file.h> | |
496 | ||
497 | static void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
498 | struct pinctrl_dev *pctldev, |
499 | struct gpio_chip *chip, | |
500 | unsigned offset, unsigned gpio) | |
0493e649 | 501 | { |
d2752ae5 PC |
502 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
503 | struct pullud *pullud = pct->soc->pullud; | |
0493e649 PC |
504 | const char *label = gpiochip_is_requested(chip, offset - 1); |
505 | u8 gpio_offset = offset - 1; | |
506 | int mode = -1; | |
507 | bool is_out; | |
d2752ae5 | 508 | bool pd; |
ce06f407 | 509 | enum abx500_gpio_pull_updown pud = 0; |
83b423c8 | 510 | |
0493e649 PC |
511 | const char *modes[] = { |
512 | [ABX500_DEFAULT] = "default", | |
513 | [ABX500_ALT_A] = "altA", | |
514 | [ABX500_ALT_B] = "altB", | |
515 | [ABX500_ALT_C] = "altC", | |
516 | }; | |
517 | ||
d2752ae5 PC |
518 | const char *pull_up_down[] = { |
519 | [ABX500_GPIO_PULL_DOWN] = "pull down", | |
520 | [ABX500_GPIO_PULL_NONE] = "pull none", | |
521 | [ABX500_GPIO_PULL_NONE + 1] = "pull none", | |
522 | [ABX500_GPIO_PULL_UP] = "pull up", | |
523 | }; | |
524 | ||
0493e649 | 525 | abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out); |
d2752ae5 PC |
526 | |
527 | seq_printf(s, " gpio-%-3d (%-20.20s) %-3s", | |
528 | gpio, label ?: "(none)", | |
529 | is_out ? "out" : "in "); | |
530 | ||
531 | if (!is_out) { | |
532 | if (pullud && | |
533 | (offset >= pullud->first_pin) && | |
534 | (offset <= pullud->last_pin)) { | |
535 | abx500_get_pull_updown(pct, offset, &pud); | |
536 | seq_printf(s, " %-9s", pull_up_down[pud]); | |
537 | } else { | |
538 | abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, | |
539 | gpio_offset, &pd); | |
540 | seq_printf(s, " %-9s", pull_up_down[pd]); | |
541 | } | |
542 | } else | |
543 | seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); | |
0493e649 PC |
544 | |
545 | if (pctldev) | |
546 | mode = abx500_get_mode(pctldev, chip, offset); | |
547 | ||
d2752ae5 | 548 | seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); |
0493e649 PC |
549 | } |
550 | ||
551 | static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
552 | { | |
553 | unsigned i; | |
554 | unsigned gpio = chip->base; | |
555 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
556 | struct pinctrl_dev *pctldev = pct->pctldev; | |
557 | ||
558 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
559 | /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ | |
560 | abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); | |
561 | seq_printf(s, "\n"); | |
562 | } | |
563 | } | |
564 | ||
565 | #else | |
566 | static inline void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
567 | struct pinctrl_dev *pctldev, |
568 | struct gpio_chip *chip, | |
569 | unsigned offset, unsigned gpio) | |
0493e649 PC |
570 | { |
571 | } | |
572 | #define abx500_gpio_dbg_show NULL | |
573 | #endif | |
574 | ||
9c4154ef | 575 | static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
576 | { |
577 | int gpio = chip->base + offset; | |
578 | ||
579 | return pinctrl_request_gpio(gpio); | |
580 | } | |
581 | ||
9c4154ef | 582 | static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
583 | { |
584 | int gpio = chip->base + offset; | |
585 | ||
586 | pinctrl_free_gpio(gpio); | |
587 | } | |
588 | ||
589 | static struct gpio_chip abx500gpio_chip = { | |
590 | .label = "abx500-gpio", | |
591 | .owner = THIS_MODULE, | |
592 | .request = abx500_gpio_request, | |
593 | .free = abx500_gpio_free, | |
594 | .direction_input = abx500_gpio_direction_input, | |
595 | .get = abx500_gpio_get, | |
596 | .direction_output = abx500_gpio_direction_output, | |
597 | .set = abx500_gpio_set, | |
598 | .to_irq = abx500_gpio_to_irq, | |
599 | .dbg_show = abx500_gpio_dbg_show, | |
600 | }; | |
601 | ||
0493e649 PC |
602 | static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
603 | { | |
604 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
605 | ||
606 | return pct->soc->nfunctions; | |
607 | } | |
608 | ||
609 | static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
610 | unsigned function) | |
611 | { | |
612 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
613 | ||
614 | return pct->soc->functions[function].name; | |
615 | } | |
616 | ||
617 | static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
618 | unsigned function, |
619 | const char * const **groups, | |
620 | unsigned * const num_groups) | |
0493e649 PC |
621 | { |
622 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
623 | ||
624 | *groups = pct->soc->functions[function].groups; | |
625 | *num_groups = pct->soc->functions[function].ngroups; | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
0493e649 | 630 | static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, |
83b423c8 | 631 | unsigned group) |
0493e649 PC |
632 | { |
633 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
634 | struct gpio_chip *chip = &pct->chip; | |
635 | const struct abx500_pingroup *g; | |
636 | int i; | |
637 | int ret = 0; | |
638 | ||
639 | g = &pct->soc->groups[group]; | |
640 | if (g->altsetting < 0) | |
641 | return -EINVAL; | |
642 | ||
643 | dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
644 | ||
645 | for (i = 0; i < g->npins; i++) { | |
646 | dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", | |
647 | g->pins[i], g->altsetting); | |
648 | ||
0493e649 PC |
649 | ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); |
650 | } | |
83b423c8 | 651 | |
0493e649 PC |
652 | return ret; |
653 | } | |
654 | ||
655 | static void abx500_pmx_disable(struct pinctrl_dev *pctldev, | |
83b423c8 | 656 | unsigned function, unsigned group) |
0493e649 PC |
657 | { |
658 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
659 | const struct abx500_pingroup *g; | |
660 | ||
661 | g = &pct->soc->groups[group]; | |
662 | if (g->altsetting < 0) | |
663 | return; | |
664 | ||
665 | /* FIXME: poke out the mux, set the pin to some default state? */ | |
666 | dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
667 | } | |
668 | ||
9c4154ef | 669 | static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
670 | struct pinctrl_gpio_range *range, |
671 | unsigned offset) | |
0493e649 PC |
672 | { |
673 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
674 | const struct abx500_pinrange *p; | |
675 | int ret; | |
676 | int i; | |
677 | ||
678 | /* | |
679 | * Different ranges have different ways to enable GPIO function on a | |
680 | * pin, so refer back to our local range type, where we handily define | |
681 | * what altfunc enables GPIO for a certain pin. | |
682 | */ | |
683 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
684 | p = &pct->soc->gpio_ranges[i]; | |
685 | if ((offset >= p->offset) && | |
686 | (offset < (p->offset + p->npins))) | |
687 | break; | |
688 | } | |
689 | ||
690 | if (i == pct->soc->gpio_num_ranges) { | |
691 | dev_err(pct->dev, "%s failed to locate range\n", __func__); | |
692 | return -ENODEV; | |
693 | } | |
694 | ||
695 | dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", | |
696 | p->altfunc, offset); | |
697 | ||
698 | ret = abx500_set_mode(pct->pctldev, &pct->chip, | |
699 | offset, p->altfunc); | |
700 | if (ret < 0) { | |
701 | dev_err(pct->dev, "%s setting altfunc failed\n", __func__); | |
702 | return ret; | |
703 | } | |
704 | ||
705 | return ret; | |
706 | } | |
707 | ||
708 | static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
709 | struct pinctrl_gpio_range *range, |
710 | unsigned offset) | |
0493e649 PC |
711 | { |
712 | } | |
713 | ||
022ab148 | 714 | static const struct pinmux_ops abx500_pinmux_ops = { |
0493e649 PC |
715 | .get_functions_count = abx500_pmx_get_funcs_cnt, |
716 | .get_function_name = abx500_pmx_get_func_name, | |
717 | .get_function_groups = abx500_pmx_get_func_groups, | |
718 | .enable = abx500_pmx_enable, | |
719 | .disable = abx500_pmx_disable, | |
720 | .gpio_request_enable = abx500_gpio_request_enable, | |
721 | .gpio_disable_free = abx500_gpio_disable_free, | |
722 | }; | |
723 | ||
724 | static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) | |
725 | { | |
726 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
727 | ||
728 | return pct->soc->ngroups; | |
729 | } | |
730 | ||
731 | static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, | |
83b423c8 | 732 | unsigned selector) |
0493e649 PC |
733 | { |
734 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
735 | ||
736 | return pct->soc->groups[selector].name; | |
737 | } | |
738 | ||
739 | static int abx500_get_group_pins(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
740 | unsigned selector, |
741 | const unsigned **pins, | |
742 | unsigned *num_pins) | |
0493e649 PC |
743 | { |
744 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
745 | ||
746 | *pins = pct->soc->groups[selector].pins; | |
747 | *num_pins = pct->soc->groups[selector].npins; | |
83b423c8 | 748 | |
0493e649 PC |
749 | return 0; |
750 | } | |
751 | ||
752 | static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, | |
83b423c8 | 753 | struct seq_file *s, unsigned offset) |
0493e649 PC |
754 | { |
755 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
756 | struct gpio_chip *chip = &pct->chip; | |
757 | ||
758 | abx500_gpio_dbg_show_one(s, pctldev, chip, offset, | |
759 | chip->base + offset - 1); | |
760 | } | |
761 | ||
64a45c98 PC |
762 | static void abx500_dt_free_map(struct pinctrl_dev *pctldev, |
763 | struct pinctrl_map *map, unsigned num_maps) | |
764 | { | |
765 | int i; | |
766 | ||
767 | for (i = 0; i < num_maps; i++) | |
768 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) | |
769 | kfree(map[i].data.configs.configs); | |
770 | kfree(map); | |
771 | } | |
772 | ||
773 | static int abx500_dt_reserve_map(struct pinctrl_map **map, | |
774 | unsigned *reserved_maps, | |
775 | unsigned *num_maps, | |
776 | unsigned reserve) | |
777 | { | |
778 | unsigned old_num = *reserved_maps; | |
779 | unsigned new_num = *num_maps + reserve; | |
780 | struct pinctrl_map *new_map; | |
781 | ||
782 | if (old_num >= new_num) | |
783 | return 0; | |
784 | ||
785 | new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); | |
786 | if (!new_map) | |
787 | return -ENOMEM; | |
788 | ||
789 | memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); | |
790 | ||
791 | *map = new_map; | |
792 | *reserved_maps = new_num; | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
797 | static int abx500_dt_add_map_mux(struct pinctrl_map **map, | |
798 | unsigned *reserved_maps, | |
799 | unsigned *num_maps, const char *group, | |
800 | const char *function) | |
801 | { | |
802 | if (*num_maps == *reserved_maps) | |
803 | return -ENOSPC; | |
804 | ||
805 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
806 | (*map)[*num_maps].data.mux.group = group; | |
807 | (*map)[*num_maps].data.mux.function = function; | |
808 | (*num_maps)++; | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | static int abx500_dt_add_map_configs(struct pinctrl_map **map, | |
814 | unsigned *reserved_maps, | |
815 | unsigned *num_maps, const char *group, | |
816 | unsigned long *configs, unsigned num_configs) | |
817 | { | |
818 | unsigned long *dup_configs; | |
819 | ||
820 | if (*num_maps == *reserved_maps) | |
821 | return -ENOSPC; | |
822 | ||
823 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
824 | GFP_KERNEL); | |
825 | if (!dup_configs) | |
826 | return -ENOMEM; | |
827 | ||
828 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
829 | ||
830 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
831 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
832 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
833 | (*num_maps)++; | |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
838 | static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev, | |
839 | const char *pin_name) | |
840 | { | |
841 | int i, pin_number; | |
842 | struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
843 | ||
844 | if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) | |
845 | for (i = 0; i < npct->soc->npins; i++) | |
846 | if (npct->soc->pins[i].number == pin_number) | |
847 | return npct->soc->pins[i].name; | |
848 | return NULL; | |
849 | } | |
850 | ||
851 | static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
852 | struct device_node *np, | |
853 | struct pinctrl_map **map, | |
854 | unsigned *reserved_maps, | |
855 | unsigned *num_maps) | |
856 | { | |
857 | int ret; | |
858 | const char *function = NULL; | |
859 | unsigned long *configs; | |
860 | unsigned int nconfigs = 0; | |
861 | bool has_config = 0; | |
862 | unsigned reserve = 0; | |
863 | struct property *prop; | |
864 | const char *group, *gpio_name; | |
865 | struct device_node *np_config; | |
866 | ||
867 | ret = of_property_read_string(np, "ste,function", &function); | |
868 | if (ret >= 0) | |
869 | reserve = 1; | |
870 | ||
871 | ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); | |
872 | if (nconfigs) | |
873 | has_config = 1; | |
874 | ||
875 | np_config = of_parse_phandle(np, "ste,config", 0); | |
876 | if (np_config) { | |
877 | ret = pinconf_generic_parse_dt_config(np_config, &configs, | |
878 | &nconfigs); | |
879 | if (ret) | |
880 | goto exit; | |
881 | has_config |= nconfigs; | |
882 | } | |
883 | ||
884 | ret = of_property_count_strings(np, "ste,pins"); | |
885 | if (ret < 0) | |
886 | goto exit; | |
887 | ||
888 | if (has_config) | |
889 | reserve++; | |
890 | ||
891 | reserve *= ret; | |
892 | ||
893 | ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve); | |
894 | if (ret < 0) | |
895 | goto exit; | |
896 | ||
897 | of_property_for_each_string(np, "ste,pins", prop, group) { | |
898 | if (function) { | |
899 | ret = abx500_dt_add_map_mux(map, reserved_maps, | |
900 | num_maps, group, function); | |
901 | if (ret < 0) | |
902 | goto exit; | |
903 | } | |
904 | if (has_config) { | |
905 | gpio_name = abx500_find_pin_name(pctldev, group); | |
906 | ||
907 | ret = abx500_dt_add_map_configs(map, reserved_maps, | |
908 | num_maps, gpio_name, configs, 1); | |
909 | if (ret < 0) | |
910 | goto exit; | |
911 | } | |
912 | ||
913 | } | |
914 | exit: | |
915 | return ret; | |
916 | } | |
917 | ||
918 | static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, | |
919 | struct device_node *np_config, | |
920 | struct pinctrl_map **map, unsigned *num_maps) | |
921 | { | |
922 | unsigned reserved_maps; | |
923 | struct device_node *np; | |
924 | int ret; | |
925 | ||
926 | reserved_maps = 0; | |
927 | *map = NULL; | |
928 | *num_maps = 0; | |
929 | ||
930 | for_each_child_of_node(np_config, np) { | |
931 | ret = abx500_dt_subnode_to_map(pctldev, np, map, | |
932 | &reserved_maps, num_maps); | |
933 | if (ret < 0) { | |
934 | abx500_dt_free_map(pctldev, *map, *num_maps); | |
935 | return ret; | |
936 | } | |
937 | } | |
938 | ||
939 | return 0; | |
940 | } | |
941 | ||
022ab148 | 942 | static const struct pinctrl_ops abx500_pinctrl_ops = { |
0493e649 PC |
943 | .get_groups_count = abx500_get_groups_cnt, |
944 | .get_group_name = abx500_get_group_name, | |
945 | .get_group_pins = abx500_get_group_pins, | |
946 | .pin_dbg_show = abx500_pin_dbg_show, | |
64a45c98 PC |
947 | .dt_node_to_map = abx500_dt_node_to_map, |
948 | .dt_free_map = abx500_dt_free_map, | |
0493e649 PC |
949 | }; |
950 | ||
9c4154ef | 951 | static int abx500_pin_config_get(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
952 | unsigned pin, |
953 | unsigned long *config) | |
0493e649 | 954 | { |
1abeebea | 955 | return -ENOSYS; |
0493e649 PC |
956 | } |
957 | ||
9c4154ef | 958 | static int abx500_pin_config_set(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
959 | unsigned pin, |
960 | unsigned long config) | |
0493e649 PC |
961 | { |
962 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
963 | struct pullud *pullud = pct->soc->pullud; | |
964 | struct gpio_chip *chip = &pct->chip; | |
965 | unsigned offset; | |
9ed3cd33 | 966 | int ret = 0; |
0493e649 PC |
967 | enum pin_config_param param = pinconf_to_config_param(config); |
968 | enum pin_config_param argument = pinconf_to_config_argument(config); | |
969 | ||
970 | dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", | |
971 | pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input", | |
972 | (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") : | |
973 | (argument ? "pull up" : "pull down")); | |
83b423c8 | 974 | |
0493e649 PC |
975 | /* on ABx500, there is no GPIO0, so adjust the offset */ |
976 | offset = pin - 1; | |
977 | ||
978 | switch (param) { | |
979 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
980 | /* | |
981 | * if argument = 1 set the pull down | |
982 | * else clear the pull down | |
983 | */ | |
984 | ret = abx500_gpio_direction_input(chip, offset); | |
985 | /* | |
986 | * Some chips only support pull down, while some actually | |
987 | * support both pull up and pull down. Such chips have | |
988 | * a "pullud" range specified for the pins that support | |
989 | * both features. If the pin is not within that range, we | |
990 | * fall back to the old bit set that only support pull down. | |
991 | */ | |
992 | if (pullud && | |
993 | pin >= pullud->first_pin && | |
994 | pin <= pullud->last_pin) | |
d2752ae5 | 995 | ret = abx500_set_pull_updown(pct, |
0493e649 PC |
996 | pin, |
997 | argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); | |
998 | else | |
999 | /* Chip only supports pull down */ | |
1000 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, | |
1001 | offset, argument ? 0 : 1); | |
1002 | break; | |
83b423c8 | 1003 | |
9ed3cd33 PC |
1004 | case PIN_CONFIG_BIAS_PULL_UP: |
1005 | /* | |
1006 | * if argument = 1 set the pull up | |
1007 | * else clear the pull up | |
1008 | */ | |
1009 | ret = abx500_gpio_direction_input(chip, offset); | |
1010 | /* | |
1011 | * Some chips only support pull down, while some actually | |
1012 | * support both pull up and pull down. Such chips have | |
1013 | * a "pullud" range specified for the pins that support | |
1014 | * both features. If the pin is not within that range, do | |
1015 | * nothing | |
1016 | */ | |
1017 | if (pullud && | |
1018 | pin >= pullud->first_pin && | |
1019 | pin <= pullud->last_pin) { | |
d2752ae5 | 1020 | ret = abx500_set_pull_updown(pct, |
9ed3cd33 PC |
1021 | pin, |
1022 | argument ? ABX500_GPIO_PULL_UP : ABX500_GPIO_PULL_NONE); | |
1023 | } | |
1024 | break; | |
1025 | ||
0493e649 PC |
1026 | case PIN_CONFIG_OUTPUT: |
1027 | ret = abx500_gpio_direction_output(chip, offset, argument); | |
83b423c8 | 1028 | |
0493e649 | 1029 | break; |
83b423c8 | 1030 | |
0493e649 PC |
1031 | default: |
1032 | dev_err(chip->dev, "illegal configuration requested\n"); | |
83b423c8 | 1033 | |
0493e649 PC |
1034 | return -EINVAL; |
1035 | } | |
83b423c8 | 1036 | |
0493e649 PC |
1037 | return ret; |
1038 | } | |
1039 | ||
022ab148 | 1040 | static const struct pinconf_ops abx500_pinconf_ops = { |
0493e649 PC |
1041 | .pin_config_get = abx500_pin_config_get, |
1042 | .pin_config_set = abx500_pin_config_set, | |
1043 | }; | |
1044 | ||
1045 | static struct pinctrl_desc abx500_pinctrl_desc = { | |
1046 | .name = "pinctrl-abx500", | |
1047 | .pctlops = &abx500_pinctrl_ops, | |
1048 | .pmxops = &abx500_pinmux_ops, | |
1049 | .confops = &abx500_pinconf_ops, | |
1050 | .owner = THIS_MODULE, | |
1051 | }; | |
1052 | ||
1053 | static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) | |
1054 | { | |
1055 | unsigned int lowest = 0; | |
1056 | unsigned int highest = 0; | |
1057 | unsigned int npins = 0; | |
1058 | int i; | |
1059 | ||
1060 | /* | |
1061 | * Compute number of GPIOs from the last SoC gpio range descriptors | |
1062 | * These ranges may include "holes" but the GPIO number space shall | |
1063 | * still be homogeneous, so we need to detect and account for any | |
1064 | * such holes so that these are included in the number of GPIO pins. | |
1065 | */ | |
1066 | for (i = 0; i < soc->gpio_num_ranges; i++) { | |
1067 | unsigned gstart; | |
1068 | unsigned gend; | |
1069 | const struct abx500_pinrange *p; | |
1070 | ||
1071 | p = &soc->gpio_ranges[i]; | |
1072 | gstart = p->offset; | |
1073 | gend = p->offset + p->npins - 1; | |
1074 | ||
1075 | if (i == 0) { | |
1076 | /* First iteration, set start values */ | |
1077 | lowest = gstart; | |
1078 | highest = gend; | |
1079 | } else { | |
1080 | if (gstart < lowest) | |
1081 | lowest = gstart; | |
1082 | if (gend > highest) | |
1083 | highest = gend; | |
1084 | } | |
1085 | } | |
1086 | /* this gives the absolute number of pins */ | |
1087 | npins = highest - lowest + 1; | |
1088 | return npins; | |
1089 | } | |
1090 | ||
f30a3839 LJ |
1091 | static const struct of_device_id abx500_gpio_match[] = { |
1092 | { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, }, | |
1093 | { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, | |
1094 | { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, | |
1095 | { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, | |
e3929714 | 1096 | { } |
f30a3839 LJ |
1097 | }; |
1098 | ||
0493e649 PC |
1099 | static int abx500_gpio_probe(struct platform_device *pdev) |
1100 | { | |
1101 | struct ab8500_platform_data *abx500_pdata = | |
1102 | dev_get_platdata(pdev->dev.parent); | |
f30a3839 LJ |
1103 | struct abx500_gpio_platform_data *pdata = NULL; |
1104 | struct device_node *np = pdev->dev.of_node; | |
0493e649 PC |
1105 | struct abx500_pinctrl *pct; |
1106 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
f30a3839 | 1107 | unsigned int id = -1; |
fa1ec996 | 1108 | int ret, err; |
0493e649 PC |
1109 | int i; |
1110 | ||
f30a3839 LJ |
1111 | if (abx500_pdata) |
1112 | pdata = abx500_pdata->gpio; | |
f30a3839 | 1113 | |
86c976e4 LJ |
1114 | if (!(pdata || np)) { |
1115 | dev_err(&pdev->dev, "gpio dt and platform data missing\n"); | |
1116 | return -ENODEV; | |
0493e649 PC |
1117 | } |
1118 | ||
1119 | pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), | |
1120 | GFP_KERNEL); | |
1121 | if (pct == NULL) { | |
1122 | dev_err(&pdev->dev, | |
1123 | "failed to allocate memory for pct\n"); | |
1124 | return -ENOMEM; | |
1125 | } | |
1126 | ||
1127 | pct->dev = &pdev->dev; | |
1128 | pct->parent = dev_get_drvdata(pdev->dev.parent); | |
1129 | pct->chip = abx500gpio_chip; | |
1130 | pct->chip.dev = &pdev->dev; | |
f30a3839 | 1131 | pct->chip.base = (np) ? -1 : pdata->gpio_base; |
0493e649 | 1132 | |
86c976e4 LJ |
1133 | if (platid) |
1134 | id = platid->driver_data; | |
1135 | else if (np) { | |
1136 | const struct of_device_id *match; | |
1137 | ||
1138 | match = of_match_device(abx500_gpio_match, &pdev->dev); | |
1139 | if (match) | |
1140 | id = (unsigned long)match->data; | |
1141 | } | |
1142 | ||
0493e649 | 1143 | /* Poke in other ASIC variants here */ |
f30a3839 | 1144 | switch (id) { |
3c937993 PC |
1145 | case PINCTRL_AB8500: |
1146 | abx500_pinctrl_ab8500_init(&pct->soc); | |
1147 | break; | |
a8f96e41 PC |
1148 | case PINCTRL_AB8540: |
1149 | abx500_pinctrl_ab8540_init(&pct->soc); | |
1150 | break; | |
09dbec3f PC |
1151 | case PINCTRL_AB9540: |
1152 | abx500_pinctrl_ab9540_init(&pct->soc); | |
1153 | break; | |
1aa2d8d4 PC |
1154 | case PINCTRL_AB8505: |
1155 | abx500_pinctrl_ab8505_init(&pct->soc); | |
1156 | break; | |
0493e649 | 1157 | default: |
2fcad12e | 1158 | dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); |
0493e649 PC |
1159 | return -EINVAL; |
1160 | } | |
1161 | ||
1162 | if (!pct->soc) { | |
1163 | dev_err(&pdev->dev, "Invalid SOC data\n"); | |
1164 | return -EINVAL; | |
1165 | } | |
1166 | ||
1167 | pct->chip.ngpio = abx500_get_gpio_num(pct->soc); | |
1168 | pct->irq_cluster = pct->soc->gpio_irq_cluster; | |
1169 | pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; | |
0493e649 | 1170 | |
0493e649 PC |
1171 | ret = gpiochip_add(&pct->chip); |
1172 | if (ret) { | |
83b423c8 | 1173 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); |
ac652d79 | 1174 | return ret; |
0493e649 PC |
1175 | } |
1176 | dev_info(&pdev->dev, "added gpiochip\n"); | |
1177 | ||
1178 | abx500_pinctrl_desc.pins = pct->soc->pins; | |
1179 | abx500_pinctrl_desc.npins = pct->soc->npins; | |
1180 | pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); | |
1181 | if (!pct->pctldev) { | |
1182 | dev_err(&pdev->dev, | |
1183 | "could not register abx500 pinctrl driver\n"); | |
fa1ec996 | 1184 | ret = -EINVAL; |
0493e649 PC |
1185 | goto out_rem_chip; |
1186 | } | |
1187 | dev_info(&pdev->dev, "registered pin controller\n"); | |
1188 | ||
1189 | /* We will handle a range of GPIO pins */ | |
1190 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
1191 | const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; | |
1192 | ||
1193 | ret = gpiochip_add_pin_range(&pct->chip, | |
1194 | dev_name(&pdev->dev), | |
1195 | p->offset - 1, p->offset, p->npins); | |
1196 | if (ret < 0) | |
fa1ec996 | 1197 | goto out_rem_chip; |
0493e649 PC |
1198 | } |
1199 | ||
1200 | platform_set_drvdata(pdev, pct); | |
1201 | dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); | |
1202 | ||
1203 | return 0; | |
1204 | ||
1205 | out_rem_chip: | |
fa1ec996 LJ |
1206 | err = gpiochip_remove(&pct->chip); |
1207 | if (err) | |
0493e649 | 1208 | dev_info(&pdev->dev, "failed to remove gpiochip\n"); |
ac652d79 | 1209 | |
0493e649 PC |
1210 | return ret; |
1211 | } | |
1212 | ||
83b423c8 | 1213 | /** |
0493e649 | 1214 | * abx500_gpio_remove() - remove Ab8500-gpio driver |
83b423c8 | 1215 | * @pdev: Platform device registered |
0493e649 PC |
1216 | */ |
1217 | static int abx500_gpio_remove(struct platform_device *pdev) | |
1218 | { | |
1219 | struct abx500_pinctrl *pct = platform_get_drvdata(pdev); | |
1220 | int ret; | |
1221 | ||
1222 | ret = gpiochip_remove(&pct->chip); | |
1223 | if (ret < 0) { | |
1224 | dev_err(pct->dev, "unable to remove gpiochip: %d\n", | |
1225 | ret); | |
1226 | return ret; | |
1227 | } | |
1228 | ||
0493e649 PC |
1229 | return 0; |
1230 | } | |
1231 | ||
1232 | static const struct platform_device_id abx500_pinctrl_id[] = { | |
1233 | { "pinctrl-ab8500", PINCTRL_AB8500 }, | |
1234 | { "pinctrl-ab8540", PINCTRL_AB8540 }, | |
1235 | { "pinctrl-ab9540", PINCTRL_AB9540 }, | |
1236 | { "pinctrl-ab8505", PINCTRL_AB8505 }, | |
1237 | { }, | |
1238 | }; | |
1239 | ||
1240 | static struct platform_driver abx500_gpio_driver = { | |
1241 | .driver = { | |
1242 | .name = "abx500-gpio", | |
1243 | .owner = THIS_MODULE, | |
f30a3839 | 1244 | .of_match_table = abx500_gpio_match, |
0493e649 PC |
1245 | }, |
1246 | .probe = abx500_gpio_probe, | |
1247 | .remove = abx500_gpio_remove, | |
1248 | .id_table = abx500_pinctrl_id, | |
1249 | }; | |
1250 | ||
1251 | static int __init abx500_gpio_init(void) | |
1252 | { | |
1253 | return platform_driver_register(&abx500_gpio_driver); | |
1254 | } | |
1255 | core_initcall(abx500_gpio_init); | |
1256 | ||
1257 | MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); | |
1258 | MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); | |
1259 | MODULE_ALIAS("platform:abx500-gpio"); | |
1260 | MODULE_LICENSE("GPL v2"); |