Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2ec1d359 AR |
2 | /* |
3 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
4 | * | |
5 | * Copyright (C) 2008,2009 STMicroelectronics | |
6 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
7 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
f4b3f523 | 8 | * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
9 | */ |
10 | #include <linux/kernel.h> | |
2ec1d359 AR |
11 | #include <linux/init.h> |
12 | #include <linux/device.h> | |
3e3c62ca | 13 | #include <linux/platform_device.h> |
2ec1d359 | 14 | #include <linux/io.h> |
af7dc228 RV |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
1c5fb66a | 17 | #include <linux/gpio/driver.h> |
2ec1d359 AR |
18 | #include <linux/spinlock.h> |
19 | #include <linux/interrupt.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
855f80cd | 21 | #include <linux/of_device.h> |
32e67eee | 22 | #include <linux/of_address.h> |
5e81e0a0 | 23 | #include <linux/bitops.h> |
e32af889 | 24 | #include <linux/pinctrl/machine.h> |
e98ea774 | 25 | #include <linux/pinctrl/pinctrl.h> |
dbfe8ca2 | 26 | #include <linux/pinctrl/pinmux.h> |
d41af627 | 27 | #include <linux/pinctrl/pinconf.h> |
dbfe8ca2 LW |
28 | /* Since we request GPIOs from ourself */ |
29 | #include <linux/pinctrl/consumer.h> | |
e98ea774 | 30 | #include "pinctrl-nomadik.h" |
3a198059 | 31 | #include "../core.h" |
ba388294 | 32 | #include "../pinctrl-utils.h" |
e98ea774 | 33 | |
2ec1d359 AR |
34 | /* |
35 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
36 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 37 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
38 | * |
39 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
40 | */ | |
41 | ||
8d993397 LW |
42 | /* |
43 | * pin configurations are represented by 32-bit integers: | |
44 | * | |
45 | * bit 0.. 8 - Pin Number (512 Pins Maximum) | |
46 | * bit 9..10 - Alternate Function Selection | |
47 | * bit 11..12 - Pull up/down state | |
48 | * bit 13 - Sleep mode behaviour | |
49 | * bit 14 - Direction | |
50 | * bit 15 - Value (if output) | |
51 | * bit 16..18 - SLPM pull up/down state | |
52 | * bit 19..20 - SLPM direction | |
53 | * bit 21..22 - SLPM Value (if output) | |
54 | * bit 23..25 - PDIS value (if input) | |
55 | * bit 26 - Gpio mode | |
56 | * bit 27 - Sleep mode | |
57 | * | |
58 | * to facilitate the definition, the following macros are provided | |
59 | * | |
60 | * PIN_CFG_DEFAULT - default config (0): | |
61 | * pull up/down = disabled | |
62 | * sleep mode = input/wakeup | |
63 | * direction = input | |
64 | * value = low | |
65 | * SLPM direction = same as normal | |
66 | * SLPM pull = same as normal | |
67 | * SLPM value = same as normal | |
68 | * | |
69 | * PIN_CFG - default config with alternate function | |
70 | */ | |
71 | ||
72 | typedef unsigned long pin_cfg_t; | |
73 | ||
74 | #define PIN_NUM_MASK 0x1ff | |
75 | #define PIN_NUM(x) ((x) & PIN_NUM_MASK) | |
76 | ||
77 | #define PIN_ALT_SHIFT 9 | |
78 | #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) | |
79 | #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) | |
80 | #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) | |
81 | #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) | |
82 | #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) | |
83 | #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) | |
84 | ||
85 | #define PIN_PULL_SHIFT 11 | |
86 | #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) | |
87 | #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) | |
88 | #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) | |
89 | #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) | |
90 | #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) | |
91 | ||
92 | #define PIN_SLPM_SHIFT 13 | |
93 | #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) | |
94 | #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) | |
95 | #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) | |
96 | #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) | |
97 | /* These two replace the above in DB8500v2+ */ | |
98 | #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) | |
99 | #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) | |
100 | #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE | |
101 | ||
102 | #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ | |
103 | #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ | |
104 | ||
105 | #define PIN_DIR_SHIFT 14 | |
106 | #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) | |
107 | #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) | |
108 | #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) | |
109 | #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) | |
110 | ||
111 | #define PIN_VAL_SHIFT 15 | |
112 | #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) | |
113 | #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) | |
114 | #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) | |
115 | #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) | |
116 | ||
117 | #define PIN_SLPM_PULL_SHIFT 16 | |
118 | #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) | |
119 | #define PIN_SLPM_PULL(x) \ | |
120 | (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) | |
121 | #define PIN_SLPM_PULL_NONE \ | |
122 | ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) | |
123 | #define PIN_SLPM_PULL_UP \ | |
124 | ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) | |
125 | #define PIN_SLPM_PULL_DOWN \ | |
126 | ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) | |
127 | ||
128 | #define PIN_SLPM_DIR_SHIFT 19 | |
129 | #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) | |
130 | #define PIN_SLPM_DIR(x) \ | |
131 | (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) | |
132 | #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) | |
133 | #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) | |
134 | ||
135 | #define PIN_SLPM_VAL_SHIFT 21 | |
136 | #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) | |
137 | #define PIN_SLPM_VAL(x) \ | |
138 | (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) | |
139 | #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) | |
140 | #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) | |
141 | ||
142 | #define PIN_SLPM_PDIS_SHIFT 23 | |
143 | #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) | |
144 | #define PIN_SLPM_PDIS(x) \ | |
145 | (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) | |
146 | #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) | |
147 | #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) | |
148 | #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) | |
149 | ||
150 | #define PIN_LOWEMI_SHIFT 25 | |
151 | #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) | |
152 | #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) | |
153 | #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) | |
154 | #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) | |
155 | ||
156 | #define PIN_GPIOMODE_SHIFT 26 | |
157 | #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) | |
158 | #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) | |
159 | #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) | |
160 | #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) | |
161 | ||
162 | #define PIN_SLEEPMODE_SHIFT 27 | |
163 | #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) | |
164 | #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) | |
165 | #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) | |
166 | #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) | |
167 | ||
168 | ||
169 | /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ | |
170 | #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) | |
171 | #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) | |
172 | #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) | |
173 | #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) | |
174 | #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) | |
175 | ||
176 | #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) | |
177 | #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) | |
178 | #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) | |
179 | #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) | |
180 | #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) | |
181 | ||
182 | #define PIN_CFG_DEFAULT (0) | |
183 | ||
184 | #define PIN_CFG(num, alt) \ | |
185 | (PIN_CFG_DEFAULT |\ | |
186 | (PIN_NUM(num) | PIN_##alt)) | |
187 | ||
188 | #define PIN_CFG_INPUT(num, alt, pull) \ | |
189 | (PIN_CFG_DEFAULT |\ | |
190 | (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) | |
191 | ||
192 | #define PIN_CFG_OUTPUT(num, alt, val) \ | |
193 | (PIN_CFG_DEFAULT |\ | |
194 | (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) | |
195 | ||
196 | /* | |
197 | * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving | |
198 | * the "gpio" namespace for generic and cross-machine functions | |
199 | */ | |
200 | ||
201 | #define GPIO_BLOCK_SHIFT 5 | |
202 | #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) | |
1c5fb66a | 203 | #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP) |
8d993397 LW |
204 | |
205 | /* Register in the logic block */ | |
206 | #define NMK_GPIO_DAT 0x00 | |
207 | #define NMK_GPIO_DATS 0x04 | |
208 | #define NMK_GPIO_DATC 0x08 | |
209 | #define NMK_GPIO_PDIS 0x0c | |
210 | #define NMK_GPIO_DIR 0x10 | |
211 | #define NMK_GPIO_DIRS 0x14 | |
212 | #define NMK_GPIO_DIRC 0x18 | |
213 | #define NMK_GPIO_SLPC 0x1c | |
214 | #define NMK_GPIO_AFSLA 0x20 | |
215 | #define NMK_GPIO_AFSLB 0x24 | |
216 | #define NMK_GPIO_LOWEMI 0x28 | |
217 | ||
218 | #define NMK_GPIO_RIMSC 0x40 | |
219 | #define NMK_GPIO_FIMSC 0x44 | |
220 | #define NMK_GPIO_IS 0x48 | |
221 | #define NMK_GPIO_IC 0x4c | |
222 | #define NMK_GPIO_RWIMSC 0x50 | |
223 | #define NMK_GPIO_FWIMSC 0x54 | |
224 | #define NMK_GPIO_WKS 0x58 | |
225 | /* These appear in DB8540 and later ASICs */ | |
226 | #define NMK_GPIO_EDGELEVEL 0x5C | |
227 | #define NMK_GPIO_LEVEL 0x60 | |
228 | ||
229 | ||
230 | /* Pull up/down values */ | |
231 | enum nmk_gpio_pull { | |
232 | NMK_GPIO_PULL_NONE, | |
233 | NMK_GPIO_PULL_UP, | |
234 | NMK_GPIO_PULL_DOWN, | |
235 | }; | |
236 | ||
237 | /* Sleep mode */ | |
238 | enum nmk_gpio_slpm { | |
239 | NMK_GPIO_SLPM_INPUT, | |
240 | NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, | |
241 | NMK_GPIO_SLPM_NOCHANGE, | |
242 | NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, | |
243 | }; | |
244 | ||
2ec1d359 AR |
245 | struct nmk_gpio_chip { |
246 | struct gpio_chip chip; | |
3007d941 | 247 | struct irq_chip irqchip; |
2ec1d359 | 248 | void __iomem *addr; |
af7dc228 | 249 | struct clk *clk; |
33b744b3 | 250 | unsigned int bank; |
01727e61 | 251 | void (*set_ioforce)(bool enable); |
c0fcb8db | 252 | spinlock_t lock; |
33d78647 | 253 | bool sleepmode; |
2ec1d359 AR |
254 | /* Keep track of configured edges */ |
255 | u32 edge_rising; | |
256 | u32 edge_falling; | |
b9df468d RV |
257 | u32 real_wake; |
258 | u32 rwimsc; | |
259 | u32 fwimsc; | |
6c12fe88 RV |
260 | u32 rimsc; |
261 | u32 fimsc; | |
bc6f5cf6 | 262 | u32 pull_up; |
ebc6178d | 263 | u32 lowemi; |
2ec1d359 AR |
264 | }; |
265 | ||
f1671bf5 JA |
266 | /** |
267 | * struct nmk_pinctrl - state container for the Nomadik pin controller | |
268 | * @dev: containing device pointer | |
269 | * @pctl: corresponding pin controller device | |
270 | * @soc: SoC data for this specific chip | |
271 | * @prcm_base: PRCM register range virtual base | |
272 | */ | |
e98ea774 LW |
273 | struct nmk_pinctrl { |
274 | struct device *dev; | |
275 | struct pinctrl_dev *pctl; | |
276 | const struct nmk_pinctrl_soc_data *soc; | |
f1671bf5 | 277 | void __iomem *prcm_base; |
e98ea774 LW |
278 | }; |
279 | ||
bc222ef4 | 280 | static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS]; |
01727e61 RV |
281 | |
282 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
283 | ||
284 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
285 | ||
6f9a974c RV |
286 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
287 | unsigned offset, int gpio_mode) | |
288 | { | |
6f9a974c RV |
289 | u32 afunc, bfunc; |
290 | ||
5e81e0a0 LW |
291 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset); |
292 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset); | |
6f9a974c | 293 | if (gpio_mode & NMK_GPIO_ALT_A) |
5e81e0a0 | 294 | afunc |= BIT(offset); |
6f9a974c | 295 | if (gpio_mode & NMK_GPIO_ALT_B) |
5e81e0a0 | 296 | bfunc |= BIT(offset); |
6f9a974c RV |
297 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); |
298 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
299 | } | |
300 | ||
81a3c298 RV |
301 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
302 | unsigned offset, enum nmk_gpio_slpm mode) | |
303 | { | |
81a3c298 RV |
304 | u32 slpm; |
305 | ||
306 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
307 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
5e81e0a0 | 308 | slpm |= BIT(offset); |
81a3c298 | 309 | else |
5e81e0a0 | 310 | slpm &= ~BIT(offset); |
81a3c298 RV |
311 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); |
312 | } | |
313 | ||
5b327edf RV |
314 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
315 | unsigned offset, enum nmk_gpio_pull pull) | |
316 | { | |
5b327edf RV |
317 | u32 pdis; |
318 | ||
319 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 320 | if (pull == NMK_GPIO_PULL_NONE) { |
5e81e0a0 LW |
321 | pdis |= BIT(offset); |
322 | nmk_chip->pull_up &= ~BIT(offset); | |
bc6f5cf6 | 323 | } else { |
5e81e0a0 | 324 | pdis &= ~BIT(offset); |
bc6f5cf6 RA |
325 | } |
326 | ||
5b327edf RV |
327 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
328 | ||
bc6f5cf6 | 329 | if (pull == NMK_GPIO_PULL_UP) { |
5e81e0a0 LW |
330 | nmk_chip->pull_up |= BIT(offset); |
331 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); | |
bc6f5cf6 | 332 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
5e81e0a0 LW |
333 | nmk_chip->pull_up &= ~BIT(offset); |
334 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); | |
bc6f5cf6 | 335 | } |
5b327edf RV |
336 | } |
337 | ||
ebc6178d RV |
338 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
339 | unsigned offset, bool lowemi) | |
340 | { | |
5e81e0a0 | 341 | bool enabled = nmk_chip->lowemi & BIT(offset); |
ebc6178d RV |
342 | |
343 | if (lowemi == enabled) | |
344 | return; | |
345 | ||
346 | if (lowemi) | |
5e81e0a0 | 347 | nmk_chip->lowemi |= BIT(offset); |
ebc6178d | 348 | else |
5e81e0a0 | 349 | nmk_chip->lowemi &= ~BIT(offset); |
ebc6178d RV |
350 | |
351 | writel_relaxed(nmk_chip->lowemi, | |
352 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
353 | } | |
354 | ||
378be066 RV |
355 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
356 | unsigned offset) | |
357 | { | |
5e81e0a0 | 358 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); |
378be066 RV |
359 | } |
360 | ||
6720db7c RV |
361 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
362 | unsigned offset, int val) | |
363 | { | |
364 | if (val) | |
5e81e0a0 | 365 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); |
6720db7c | 366 | else |
5e81e0a0 | 367 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); |
6720db7c RV |
368 | } |
369 | ||
370 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
371 | unsigned offset, int val) | |
372 | { | |
5e81e0a0 | 373 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS); |
6720db7c RV |
374 | __nmk_gpio_set_output(nmk_chip, offset, val); |
375 | } | |
376 | ||
01727e61 RV |
377 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
378 | unsigned offset, int gpio_mode, | |
379 | bool glitch) | |
380 | { | |
6c12fe88 RV |
381 | u32 rwimsc = nmk_chip->rwimsc; |
382 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
383 | |
384 | if (glitch && nmk_chip->set_ioforce) { | |
385 | u32 bit = BIT(offset); | |
386 | ||
01727e61 RV |
387 | /* Prevent spurious wakeups */ |
388 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
389 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
390 | ||
391 | nmk_chip->set_ioforce(true); | |
392 | } | |
393 | ||
394 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
395 | ||
396 | if (glitch && nmk_chip->set_ioforce) { | |
397 | nmk_chip->set_ioforce(false); | |
398 | ||
399 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
400 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
401 | } | |
402 | } | |
403 | ||
6c42ad1c RV |
404 | static void |
405 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
406 | { | |
407 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
408 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
409 | int gpio = nmk_chip->chip.base + offset; | |
f0fbe7bc | 410 | int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset); |
6c42ad1c RV |
411 | struct irq_data *d = irq_get_irq_data(irq); |
412 | ||
413 | if (!rising && !falling) | |
414 | return; | |
415 | ||
416 | if (!d || !irqd_irq_disabled(d)) | |
417 | return; | |
418 | ||
419 | if (rising) { | |
420 | nmk_chip->rimsc &= ~BIT(offset); | |
421 | writel_relaxed(nmk_chip->rimsc, | |
422 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
423 | } | |
424 | ||
425 | if (falling) { | |
426 | nmk_chip->fimsc &= ~BIT(offset); | |
427 | writel_relaxed(nmk_chip->fimsc, | |
428 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
429 | } | |
430 | ||
58383c78 | 431 | dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio); |
6c42ad1c RV |
432 | } |
433 | ||
f1671bf5 JA |
434 | static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) |
435 | { | |
436 | u32 val; | |
437 | ||
438 | val = readl(reg); | |
439 | val = ((val & ~mask) | (value & mask)); | |
440 | writel(val, reg); | |
441 | } | |
442 | ||
c22df08c JNG |
443 | static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, |
444 | unsigned offset, unsigned alt_num) | |
445 | { | |
446 | int i; | |
447 | u16 reg; | |
448 | u8 bit; | |
449 | u8 alt_index; | |
450 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
451 | const u16 *gpiocr_regs; | |
452 | ||
4ca075de FB |
453 | if (!npct->prcm_base) |
454 | return; | |
455 | ||
c22df08c JNG |
456 | if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { |
457 | dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", | |
458 | alt_num); | |
459 | return; | |
460 | } | |
461 | ||
462 | for (i = 0 ; i < npct->soc->npins_altcx ; i++) { | |
463 | if (npct->soc->altcx_pins[i].pin == offset) | |
464 | break; | |
465 | } | |
466 | if (i == npct->soc->npins_altcx) { | |
467 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", | |
468 | offset); | |
469 | return; | |
470 | } | |
471 | ||
472 | pin_desc = npct->soc->altcx_pins + i; | |
473 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
474 | ||
475 | /* | |
476 | * If alt_num is NULL, just clear current ALTCx selection | |
477 | * to make sure we come back to a pure ALTC selection | |
478 | */ | |
479 | if (!alt_num) { | |
480 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
481 | if (pin_desc->altcx[i].used == true) { | |
482 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
483 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
484 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
485 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
486 | dev_dbg(npct->dev, |
487 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
488 | offset, i+1); | |
489 | } | |
490 | } | |
491 | } | |
492 | return; | |
493 | } | |
494 | ||
495 | alt_index = alt_num - 1; | |
496 | if (pin_desc->altcx[alt_index].used == false) { | |
497 | dev_warn(npct->dev, | |
498 | "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", | |
499 | offset, alt_num); | |
500 | return; | |
501 | } | |
502 | ||
503 | /* | |
504 | * Check if any other ALTCx functions are activated on this pin | |
505 | * and disable it first. | |
506 | */ | |
507 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
508 | if (i == alt_index) | |
509 | continue; | |
510 | if (pin_desc->altcx[i].used == true) { | |
511 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
512 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
513 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
514 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
515 | dev_dbg(npct->dev, |
516 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
517 | offset, i+1); | |
518 | } | |
519 | } | |
520 | } | |
521 | ||
522 | reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; | |
523 | bit = pin_desc->altcx[alt_index].control_bit; | |
524 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", | |
525 | offset, alt_index+1); | |
f1671bf5 | 526 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); |
c22df08c JNG |
527 | } |
528 | ||
01727e61 RV |
529 | /* |
530 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
531 | * - Save SLPM registers | |
532 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
533 | * - Configure the GPIO registers for the IOs that are being switched | |
534 | * - Set IOFORCE=1 | |
535 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
536 | * - Set IOFORCE=0 | |
537 | * - Restore SLPM registers | |
538 | * - Any spurious wake up event during switch sequence to be ignored and | |
539 | * cleared | |
540 | */ | |
541 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
542 | { | |
543 | int i; | |
544 | ||
545 | for (i = 0; i < NUM_BANKS; i++) { | |
546 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
547 | unsigned int temp = slpm[i]; | |
548 | ||
549 | if (!chip) | |
550 | break; | |
551 | ||
3c0227d2 RV |
552 | clk_enable(chip->clk); |
553 | ||
01727e61 RV |
554 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
555 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
556 | } | |
557 | } | |
558 | ||
559 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
560 | { | |
561 | int i; | |
562 | ||
563 | for (i = 0; i < NUM_BANKS; i++) { | |
564 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
565 | ||
566 | if (!chip) | |
567 | break; | |
568 | ||
569 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
570 | |
571 | clk_disable(chip->clk); | |
01727e61 RV |
572 | } |
573 | } | |
574 | ||
0fafd50e | 575 | static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) |
2249b19f JNG |
576 | { |
577 | int i; | |
578 | u16 reg; | |
579 | u8 bit; | |
580 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
581 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
582 | const u16 *gpiocr_regs; | |
583 | ||
4ca075de FB |
584 | if (!npct->prcm_base) |
585 | return NMK_GPIO_ALT_C; | |
586 | ||
2249b19f JNG |
587 | for (i = 0; i < npct->soc->npins_altcx; i++) { |
588 | if (npct->soc->altcx_pins[i].pin == gpio) | |
589 | break; | |
590 | } | |
591 | if (i == npct->soc->npins_altcx) | |
592 | return NMK_GPIO_ALT_C; | |
593 | ||
594 | pin_desc = npct->soc->altcx_pins + i; | |
595 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
596 | for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { | |
597 | if (pin_desc->altcx[i].used == true) { | |
598 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
599 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 | 600 | if (readl(npct->prcm_base + reg) & BIT(bit)) |
2249b19f JNG |
601 | return NMK_GPIO_ALT_C+i+1; |
602 | } | |
603 | } | |
604 | return NMK_GPIO_ALT_C; | |
605 | } | |
606 | ||
2ec1d359 | 607 | /* IRQ functions */ |
2ec1d359 | 608 | |
f272c00e | 609 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 610 | { |
e0bc34a3 | 611 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
68ab0126 | 612 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
3c0227d2 RV |
613 | |
614 | clk_enable(nmk_chip->clk); | |
5e81e0a0 | 615 | writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 616 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
617 | } |
618 | ||
4d4e20f7 RV |
619 | enum nmk_gpio_irq_type { |
620 | NORMAL, | |
621 | WAKE, | |
622 | }; | |
623 | ||
040e5ecd | 624 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
5e81e0a0 | 625 | int offset, enum nmk_gpio_irq_type which, |
4d4e20f7 | 626 | bool enable) |
2ec1d359 | 627 | { |
6c12fe88 RV |
628 | u32 *rimscval; |
629 | u32 *fimscval; | |
630 | u32 rimscreg; | |
631 | u32 fimscreg; | |
632 | ||
633 | if (which == NORMAL) { | |
634 | rimscreg = NMK_GPIO_RIMSC; | |
635 | fimscreg = NMK_GPIO_FIMSC; | |
636 | rimscval = &nmk_chip->rimsc; | |
637 | fimscval = &nmk_chip->fimsc; | |
638 | } else { | |
639 | rimscreg = NMK_GPIO_RWIMSC; | |
640 | fimscreg = NMK_GPIO_FWIMSC; | |
641 | rimscval = &nmk_chip->rwimsc; | |
642 | fimscval = &nmk_chip->fwimsc; | |
643 | } | |
2ec1d359 | 644 | |
040e5ecd | 645 | /* we must individually set/clear the two edges */ |
5e81e0a0 | 646 | if (nmk_chip->edge_rising & BIT(offset)) { |
040e5ecd | 647 | if (enable) |
5e81e0a0 | 648 | *rimscval |= BIT(offset); |
040e5ecd | 649 | else |
5e81e0a0 | 650 | *rimscval &= ~BIT(offset); |
6c12fe88 | 651 | writel(*rimscval, nmk_chip->addr + rimscreg); |
2ec1d359 | 652 | } |
5e81e0a0 | 653 | if (nmk_chip->edge_falling & BIT(offset)) { |
040e5ecd | 654 | if (enable) |
5e81e0a0 | 655 | *fimscval |= BIT(offset); |
040e5ecd | 656 | else |
5e81e0a0 | 657 | *fimscval &= ~BIT(offset); |
6c12fe88 | 658 | writel(*fimscval, nmk_chip->addr + fimscreg); |
2ec1d359 | 659 | } |
040e5ecd | 660 | } |
2ec1d359 | 661 | |
b9df468d | 662 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
5e81e0a0 | 663 | int offset, bool on) |
b9df468d | 664 | { |
b982ff0e RV |
665 | /* |
666 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
667 | * disabled, since setting SLPM to 1 increases power consumption, and | |
668 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
669 | */ | |
670 | if (nmk_chip->sleepmode && on) { | |
5e81e0a0 | 671 | __nmk_gpio_set_slpm(nmk_chip, offset, |
b982ff0e | 672 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
673 | } |
674 | ||
5e81e0a0 | 675 | __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on); |
b9df468d RV |
676 | } |
677 | ||
678 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 679 | { |
2ec1d359 AR |
680 | struct nmk_gpio_chip *nmk_chip; |
681 | unsigned long flags; | |
2ec1d359 | 682 | |
f272c00e | 683 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 | 684 | if (!nmk_chip) |
4d4e20f7 | 685 | return -EINVAL; |
2ec1d359 | 686 | |
3c0227d2 | 687 | clk_enable(nmk_chip->clk); |
b9df468d RV |
688 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
689 | spin_lock(&nmk_chip->lock); | |
690 | ||
a60b57ed | 691 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d | 692 | |
5e81e0a0 | 693 | if (!(nmk_chip->real_wake & BIT(d->hwirq))) |
a60b57ed | 694 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
695 | |
696 | spin_unlock(&nmk_chip->lock); | |
697 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 698 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
699 | |
700 | return 0; | |
2ec1d359 AR |
701 | } |
702 | ||
f272c00e | 703 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 704 | { |
b9df468d | 705 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 706 | } |
040e5ecd | 707 | |
f272c00e | 708 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 709 | { |
b9df468d | 710 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
711 | } |
712 | ||
f272c00e | 713 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 714 | { |
7e3f7e59 RV |
715 | struct nmk_gpio_chip *nmk_chip; |
716 | unsigned long flags; | |
7e3f7e59 | 717 | |
f272c00e | 718 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
719 | if (!nmk_chip) |
720 | return -EINVAL; | |
721 | ||
3c0227d2 | 722 | clk_enable(nmk_chip->clk); |
01727e61 RV |
723 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
724 | spin_lock(&nmk_chip->lock); | |
725 | ||
479a0c7e | 726 | if (irqd_irq_disabled(d)) |
a60b57ed | 727 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
728 | |
729 | if (on) | |
5e81e0a0 | 730 | nmk_chip->real_wake |= BIT(d->hwirq); |
b9df468d | 731 | else |
5e81e0a0 | 732 | nmk_chip->real_wake &= ~BIT(d->hwirq); |
01727e61 RV |
733 | |
734 | spin_unlock(&nmk_chip->lock); | |
735 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 736 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
737 | |
738 | return 0; | |
040e5ecd RV |
739 | } |
740 | ||
f272c00e | 741 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 742 | { |
479a0c7e | 743 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 744 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
745 | struct nmk_gpio_chip *nmk_chip; |
746 | unsigned long flags; | |
2ec1d359 | 747 | |
f272c00e | 748 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 AR |
749 | if (!nmk_chip) |
750 | return -EINVAL; | |
2ec1d359 AR |
751 | if (type & IRQ_TYPE_LEVEL_HIGH) |
752 | return -EINVAL; | |
753 | if (type & IRQ_TYPE_LEVEL_LOW) | |
754 | return -EINVAL; | |
755 | ||
3c0227d2 | 756 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
757 | spin_lock_irqsave(&nmk_chip->lock, flags); |
758 | ||
7a852d80 | 759 | if (enabled) |
a60b57ed | 760 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 761 | |
b9df468d | 762 | if (enabled || wake) |
a60b57ed | 763 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 764 | |
5e81e0a0 | 765 | nmk_chip->edge_rising &= ~BIT(d->hwirq); |
2ec1d359 | 766 | if (type & IRQ_TYPE_EDGE_RISING) |
5e81e0a0 | 767 | nmk_chip->edge_rising |= BIT(d->hwirq); |
2ec1d359 | 768 | |
5e81e0a0 | 769 | nmk_chip->edge_falling &= ~BIT(d->hwirq); |
2ec1d359 | 770 | if (type & IRQ_TYPE_EDGE_FALLING) |
5e81e0a0 | 771 | nmk_chip->edge_falling |= BIT(d->hwirq); |
2ec1d359 | 772 | |
7a852d80 | 773 | if (enabled) |
a60b57ed | 774 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 775 | |
b9df468d | 776 | if (enabled || wake) |
a60b57ed | 777 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 778 | |
7a852d80 | 779 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 780 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
781 | |
782 | return 0; | |
783 | } | |
784 | ||
3c0227d2 RV |
785 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
786 | { | |
787 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 788 | |
3c0227d2 RV |
789 | clk_enable(nmk_chip->clk); |
790 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
791 | return 0; |
792 | } | |
793 | ||
3c0227d2 RV |
794 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
795 | { | |
796 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
797 | ||
798 | nmk_gpio_irq_mask(d); | |
799 | clk_disable(nmk_chip->clk); | |
800 | } | |
801 | ||
22406b3e | 802 | static void nmk_gpio_irq_handler(struct irq_desc *desc) |
2ec1d359 | 803 | { |
5663bb27 | 804 | struct irq_chip *host_chip = irq_desc_get_chip(desc); |
e0bc34a3 | 805 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
22406b3e LW |
806 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
807 | u32 status; | |
2ec1d359 | 808 | |
adfed159 | 809 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 810 | |
22406b3e LW |
811 | clk_enable(nmk_chip->clk); |
812 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
813 | clk_disable(nmk_chip->clk); | |
814 | ||
33b744b3 RV |
815 | while (status) { |
816 | int bit = __ffs(status); | |
817 | ||
a9cb09b7 | 818 | generic_handle_domain_irq(chip->irq.domain, bit); |
33b744b3 | 819 | status &= ~BIT(bit); |
2ec1d359 | 820 | } |
aaedaa2b | 821 | |
adfed159 | 822 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
823 | } |
824 | ||
2ec1d359 | 825 | /* I/O Functions */ |
dbfe8ca2 | 826 | |
67668a57 LW |
827 | static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset) |
828 | { | |
829 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); | |
830 | int dir; | |
831 | ||
832 | clk_enable(nmk_chip->clk); | |
833 | ||
3c827873 | 834 | dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset); |
67668a57 LW |
835 | |
836 | clk_disable(nmk_chip->clk); | |
837 | ||
3c827873 MV |
838 | if (dir) |
839 | return GPIO_LINE_DIRECTION_OUT; | |
840 | ||
841 | return GPIO_LINE_DIRECTION_IN; | |
67668a57 LW |
842 | } |
843 | ||
2ec1d359 AR |
844 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
845 | { | |
68ab0126 | 846 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
2ec1d359 | 847 | |
3c0227d2 RV |
848 | clk_enable(nmk_chip->clk); |
849 | ||
5e81e0a0 | 850 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
851 | |
852 | clk_disable(nmk_chip->clk); | |
853 | ||
2ec1d359 AR |
854 | return 0; |
855 | } | |
856 | ||
2ec1d359 AR |
857 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
858 | { | |
68ab0126 | 859 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
3c0227d2 RV |
860 | int value; |
861 | ||
862 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 863 | |
5e81e0a0 | 864 | value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); |
2ec1d359 | 865 | |
3c0227d2 RV |
866 | clk_disable(nmk_chip->clk); |
867 | ||
868 | return value; | |
2ec1d359 AR |
869 | } |
870 | ||
871 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
872 | int val) | |
873 | { | |
68ab0126 | 874 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
2ec1d359 | 875 | |
3c0227d2 RV |
876 | clk_enable(nmk_chip->clk); |
877 | ||
6720db7c | 878 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
879 | |
880 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
881 | } |
882 | ||
6647c6c0 RV |
883 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
884 | int val) | |
885 | { | |
68ab0126 | 886 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
6647c6c0 | 887 | |
3c0227d2 RV |
888 | clk_enable(nmk_chip->clk); |
889 | ||
6720db7c | 890 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 891 | |
3c0227d2 RV |
892 | clk_disable(nmk_chip->clk); |
893 | ||
6647c6c0 RV |
894 | return 0; |
895 | } | |
896 | ||
d0b543c7 | 897 | #ifdef CONFIG_DEBUG_FS |
caee57ec AB |
898 | static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) |
899 | { | |
900 | u32 afunc, bfunc; | |
901 | ||
902 | clk_enable(nmk_chip->clk); | |
903 | ||
904 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset); | |
905 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset); | |
906 | ||
907 | clk_disable(nmk_chip->clk); | |
908 | ||
909 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); | |
910 | } | |
d0b543c7 RV |
911 | |
912 | #include <linux/seq_file.h> | |
913 | ||
2249b19f JNG |
914 | static void nmk_gpio_dbg_show_one(struct seq_file *s, |
915 | struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
916 | unsigned offset, unsigned gpio) | |
d0b543c7 | 917 | { |
6f4350a6 | 918 | const char *label = gpiochip_is_requested(chip, offset); |
68ab0126 | 919 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
6f4350a6 LW |
920 | int mode; |
921 | bool is_out; | |
8f1774a2 | 922 | bool data_out; |
6f4350a6 | 923 | bool pull; |
d0b543c7 RV |
924 | const char *modes[] = { |
925 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
926 | [NMK_GPIO_ALT_A] = "altA", | |
927 | [NMK_GPIO_ALT_B] = "altB", | |
928 | [NMK_GPIO_ALT_C] = "altC", | |
2249b19f JNG |
929 | [NMK_GPIO_ALT_C+1] = "altC1", |
930 | [NMK_GPIO_ALT_C+2] = "altC2", | |
931 | [NMK_GPIO_ALT_C+3] = "altC3", | |
932 | [NMK_GPIO_ALT_C+4] = "altC4", | |
d0b543c7 RV |
933 | }; |
934 | ||
3c0227d2 | 935 | clk_enable(nmk_chip->clk); |
5e81e0a0 LW |
936 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); |
937 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset)); | |
938 | data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); | |
939 | mode = nmk_gpio_get_mode(nmk_chip, offset); | |
2249b19f JNG |
940 | if ((mode == NMK_GPIO_ALT_C) && pctldev) |
941 | mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); | |
6f4350a6 | 942 | |
8f1774a2 | 943 | if (is_out) { |
fe9c3644 | 944 | seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", |
8f1774a2 LW |
945 | gpio, |
946 | label ?: "(none)", | |
947 | data_out ? "hi" : "lo", | |
948 | (mode < 0) ? "unknown" : modes[mode]); | |
949 | } else { | |
936a3a23 | 950 | int irq = chip->to_irq(chip, offset); |
fe9c3644 | 951 | const int pullidx = pull ? 1 : 0; |
d7f005e8 | 952 | int val; |
fe9c3644 AH |
953 | static const char * const pulls[] = { |
954 | "none ", | |
955 | "pull enabled", | |
956 | }; | |
8f1774a2 LW |
957 | |
958 | seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", | |
959 | gpio, | |
960 | label ?: "(none)", | |
961 | pulls[pullidx], | |
962 | (mode < 0) ? "unknown" : modes[mode]); | |
d7f005e8 LW |
963 | |
964 | val = nmk_gpio_get_input(chip, offset); | |
965 | seq_printf(s, " VAL %d", val); | |
966 | ||
8f1774a2 LW |
967 | /* |
968 | * This races with request_irq(), set_irq_type(), | |
6f4350a6 LW |
969 | * and set_irq_wake() ... but those are "rare". |
970 | */ | |
f3925032 | 971 | if (irq > 0 && irq_has_action(irq)) { |
6f4350a6 | 972 | char *trigger; |
f3925032 | 973 | bool wake; |
6f4350a6 | 974 | |
5e81e0a0 | 975 | if (nmk_chip->edge_rising & BIT(offset)) |
6f4350a6 | 976 | trigger = "edge-rising"; |
5e81e0a0 | 977 | else if (nmk_chip->edge_falling & BIT(offset)) |
6f4350a6 LW |
978 | trigger = "edge-falling"; |
979 | else | |
980 | trigger = "edge-undefined"; | |
981 | ||
f3925032 TG |
982 | wake = !!(nmk_chip->real_wake & BIT(offset)); |
983 | ||
6f4350a6 | 984 | seq_printf(s, " irq-%d %s%s", |
f3925032 | 985 | irq, trigger, wake ? " wakeup" : ""); |
8ea72a30 | 986 | } |
6f4350a6 LW |
987 | } |
988 | clk_disable(nmk_chip->clk); | |
989 | } | |
990 | ||
991 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
992 | { | |
993 | unsigned i; | |
994 | unsigned gpio = chip->base; | |
8ea72a30 | 995 | |
6f4350a6 | 996 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
2249b19f | 997 | nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
d0b543c7 RV |
998 | seq_printf(s, "\n"); |
999 | } | |
1000 | } | |
1001 | ||
1002 | #else | |
6f4350a6 | 1003 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, |
2249b19f | 1004 | struct pinctrl_dev *pctldev, |
6f4350a6 LW |
1005 | struct gpio_chip *chip, |
1006 | unsigned offset, unsigned gpio) | |
1007 | { | |
1008 | } | |
d0b543c7 RV |
1009 | #define nmk_gpio_dbg_show NULL |
1010 | #endif | |
1011 | ||
bc222ef4 LW |
1012 | /* |
1013 | * We will allocate memory for the state container using devm* allocators | |
1014 | * binding to the first device reaching this point, it doesn't matter if | |
1015 | * it is the pin controller or GPIO driver. However we need to use the right | |
1016 | * platform device when looking up resources so pay attention to pdev. | |
1017 | */ | |
1018 | static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, | |
1019 | struct platform_device *pdev) | |
1020 | { | |
1021 | struct nmk_gpio_chip *nmk_chip; | |
1022 | struct platform_device *gpio_pdev; | |
1023 | struct gpio_chip *chip; | |
1024 | struct resource *res; | |
1025 | struct clk *clk; | |
1026 | void __iomem *base; | |
1027 | u32 id; | |
1028 | ||
1029 | gpio_pdev = of_find_device_by_node(np); | |
1030 | if (!gpio_pdev) { | |
94f4e54c | 1031 | pr_err("populate \"%pOFn\": device not found\n", np); |
bc222ef4 LW |
1032 | return ERR_PTR(-ENODEV); |
1033 | } | |
1034 | if (of_property_read_u32(np, "gpio-bank", &id)) { | |
1035 | dev_err(&pdev->dev, "populate: gpio-bank property not found\n"); | |
7c6daeaf | 1036 | platform_device_put(gpio_pdev); |
bc222ef4 LW |
1037 | return ERR_PTR(-EINVAL); |
1038 | } | |
1039 | ||
1040 | /* Already populated? */ | |
1041 | nmk_chip = nmk_gpio_chips[id]; | |
7c6daeaf W |
1042 | if (nmk_chip) { |
1043 | platform_device_put(gpio_pdev); | |
bc222ef4 | 1044 | return nmk_chip; |
7c6daeaf | 1045 | } |
bc222ef4 LW |
1046 | |
1047 | nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); | |
7c6daeaf W |
1048 | if (!nmk_chip) { |
1049 | platform_device_put(gpio_pdev); | |
bc222ef4 | 1050 | return ERR_PTR(-ENOMEM); |
7c6daeaf | 1051 | } |
bc222ef4 LW |
1052 | |
1053 | nmk_chip->bank = id; | |
1054 | chip = &nmk_chip->chip; | |
1055 | chip->base = id * NMK_GPIO_PER_CHIP; | |
1056 | chip->ngpio = NMK_GPIO_PER_CHIP; | |
1057 | chip->label = dev_name(&gpio_pdev->dev); | |
58383c78 | 1058 | chip->parent = &gpio_pdev->dev; |
bc222ef4 LW |
1059 | |
1060 | res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); | |
1061 | base = devm_ioremap_resource(&pdev->dev, res); | |
7c6daeaf W |
1062 | if (IS_ERR(base)) { |
1063 | platform_device_put(gpio_pdev); | |
376c7a75 | 1064 | return ERR_CAST(base); |
7c6daeaf | 1065 | } |
bc222ef4 LW |
1066 | nmk_chip->addr = base; |
1067 | ||
1068 | clk = clk_get(&gpio_pdev->dev, NULL); | |
7c6daeaf W |
1069 | if (IS_ERR(clk)) { |
1070 | platform_device_put(gpio_pdev); | |
bc222ef4 | 1071 | return (void *) clk; |
7c6daeaf | 1072 | } |
bc222ef4 LW |
1073 | clk_prepare(clk); |
1074 | nmk_chip->clk = clk; | |
1075 | ||
1076 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); | |
1077 | nmk_gpio_chips[id] = nmk_chip; | |
1078 | return nmk_chip; | |
1079 | } | |
1080 | ||
150632b0 | 1081 | static int nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1082 | { |
513c27f8 | 1083 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1084 | struct nmk_gpio_chip *nmk_chip; |
1085 | struct gpio_chip *chip; | |
2da7852e | 1086 | struct gpio_irq_chip *girq; |
3007d941 | 1087 | struct irq_chip *irqchip; |
8f18bcfc | 1088 | bool supports_sleepmode; |
3e3c62ca | 1089 | int irq; |
2ec1d359 AR |
1090 | int ret; |
1091 | ||
bc222ef4 LW |
1092 | nmk_chip = nmk_gpio_populate_chip(np, dev); |
1093 | if (IS_ERR(nmk_chip)) { | |
1094 | dev_err(&dev->dev, "could not populate nmk chip struct\n"); | |
1095 | return PTR_ERR(nmk_chip); | |
1096 | } | |
1097 | ||
0f9d85b7 JL |
1098 | supports_sleepmode = |
1099 | of_property_read_bool(np, "st,supports-sleepmode"); | |
513c27f8 | 1100 | |
bc222ef4 LW |
1101 | /* Correct platform device ID */ |
1102 | dev->id = nmk_chip->bank; | |
3e3c62ca | 1103 | |
3e3c62ca | 1104 | irq = platform_get_irq(dev, 0); |
50f690d8 LW |
1105 | if (irq < 0) |
1106 | return irq; | |
3e3c62ca | 1107 | |
2ec1d359 AR |
1108 | /* |
1109 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1110 | * so we can simply convert the resource address, without remapping | |
1111 | */ | |
8f18bcfc | 1112 | nmk_chip->sleepmode = supports_sleepmode; |
c0fcb8db | 1113 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1114 | |
1115 | chip = &nmk_chip->chip; | |
98c85d58 JG |
1116 | chip->request = gpiochip_generic_request; |
1117 | chip->free = gpiochip_generic_free; | |
67668a57 | 1118 | chip->get_direction = nmk_gpio_get_dir; |
3007d941 LW |
1119 | chip->direction_input = nmk_gpio_make_input; |
1120 | chip->get = nmk_gpio_get_input; | |
1121 | chip->direction_output = nmk_gpio_make_output; | |
1122 | chip->set = nmk_gpio_set_output; | |
1123 | chip->dbg_show = nmk_gpio_dbg_show; | |
1124 | chip->can_sleep = false; | |
2ec1d359 AR |
1125 | chip->owner = THIS_MODULE; |
1126 | ||
3007d941 LW |
1127 | irqchip = &nmk_chip->irqchip; |
1128 | irqchip->irq_ack = nmk_gpio_irq_ack; | |
1129 | irqchip->irq_mask = nmk_gpio_irq_mask; | |
1130 | irqchip->irq_unmask = nmk_gpio_irq_unmask; | |
1131 | irqchip->irq_set_type = nmk_gpio_irq_set_type; | |
1132 | irqchip->irq_set_wake = nmk_gpio_irq_set_wake; | |
1133 | irqchip->irq_startup = nmk_gpio_irq_startup; | |
1134 | irqchip->irq_shutdown = nmk_gpio_irq_shutdown; | |
1135 | irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; | |
1136 | irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", | |
1137 | dev->id, | |
1138 | chip->base, | |
1139 | chip->base + chip->ngpio - 1); | |
1140 | ||
2da7852e LW |
1141 | girq = &chip->irq; |
1142 | girq->chip = irqchip; | |
1143 | girq->parent_handler = nmk_gpio_irq_handler; | |
1144 | girq->num_parents = 1; | |
1145 | girq->parents = devm_kcalloc(&dev->dev, 1, | |
1146 | sizeof(*girq->parents), | |
1147 | GFP_KERNEL); | |
1148 | if (!girq->parents) | |
1149 | return -ENOMEM; | |
1150 | girq->parents[0] = irq; | |
1151 | girq->default_type = IRQ_TYPE_NONE; | |
1152 | girq->handler = handle_edge_irq; | |
1153 | ||
ebc6178d RV |
1154 | clk_enable(nmk_chip->clk); |
1155 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1156 | clk_disable(nmk_chip->clk); | |
513c27f8 LJ |
1157 | chip->of_node = np; |
1158 | ||
68ab0126 | 1159 | ret = gpiochip_add_data(chip, nmk_chip); |
2ec1d359 | 1160 | if (ret) |
50f690d8 | 1161 | return ret; |
2ec1d359 | 1162 | |
3e3c62ca | 1163 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1164 | |
2da7852e | 1165 | dev_info(&dev->dev, "chip registered\n"); |
513c27f8 | 1166 | |
2ec1d359 | 1167 | return 0; |
2ec1d359 AR |
1168 | } |
1169 | ||
e98ea774 LW |
1170 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) |
1171 | { | |
1172 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1173 | ||
1174 | return npct->soc->ngroups; | |
1175 | } | |
1176 | ||
1177 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | |
1178 | unsigned selector) | |
1179 | { | |
1180 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1181 | ||
1182 | return npct->soc->groups[selector].name; | |
1183 | } | |
1184 | ||
1185 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
1186 | const unsigned **pins, | |
1187 | unsigned *num_pins) | |
1188 | { | |
1189 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1190 | ||
1191 | *pins = npct->soc->groups[selector].pins; | |
1192 | *num_pins = npct->soc->groups[selector].npins; | |
1193 | return 0; | |
1194 | } | |
1195 | ||
6ca7d2e3 | 1196 | static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin) |
24cbdd75 | 1197 | { |
24cbdd75 | 1198 | int i; |
6ca7d2e3 | 1199 | struct nmk_gpio_chip *nmk_gpio; |
24cbdd75 | 1200 | |
6ca7d2e3 LW |
1201 | for(i = 0; i < NMK_MAX_BANKS; i++) { |
1202 | nmk_gpio = nmk_gpio_chips[i]; | |
1203 | if (!nmk_gpio) | |
1204 | continue; | |
1205 | if (pin >= nmk_gpio->chip.base && | |
1206 | pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) | |
1207 | return nmk_gpio; | |
24cbdd75 LW |
1208 | } |
1209 | return NULL; | |
1210 | } | |
1211 | ||
6ca7d2e3 LW |
1212 | static struct gpio_chip *find_gc_from_pin(unsigned pin) |
1213 | { | |
1214 | struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin); | |
1215 | ||
1216 | if (nmk_gpio) | |
1217 | return &nmk_gpio->chip; | |
1218 | return NULL; | |
1219 | } | |
1220 | ||
e98ea774 LW |
1221 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1222 | unsigned offset) | |
1223 | { | |
6ca7d2e3 | 1224 | struct gpio_chip *chip = find_gc_from_pin(offset); |
24cbdd75 | 1225 | |
6ca7d2e3 | 1226 | if (!chip) { |
24cbdd75 LW |
1227 | seq_printf(s, "invalid pin offset"); |
1228 | return; | |
1229 | } | |
2249b19f | 1230 | nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); |
e98ea774 LW |
1231 | } |
1232 | ||
e32af889 GF |
1233 | static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, |
1234 | unsigned *num_maps, const char *group, | |
1235 | const char *function) | |
1236 | { | |
1237 | if (*num_maps == *reserved_maps) | |
1238 | return -ENOSPC; | |
1239 | ||
1240 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
1241 | (*map)[*num_maps].data.mux.group = group; | |
1242 | (*map)[*num_maps].data.mux.function = function; | |
1243 | (*num_maps)++; | |
1244 | ||
1245 | return 0; | |
1246 | } | |
1247 | ||
1248 | static int nmk_dt_add_map_configs(struct pinctrl_map **map, | |
1249 | unsigned *reserved_maps, | |
1250 | unsigned *num_maps, const char *group, | |
1251 | unsigned long *configs, unsigned num_configs) | |
1252 | { | |
1253 | unsigned long *dup_configs; | |
1254 | ||
1255 | if (*num_maps == *reserved_maps) | |
1256 | return -ENOSPC; | |
1257 | ||
1258 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
1259 | GFP_KERNEL); | |
1260 | if (!dup_configs) | |
1261 | return -ENOMEM; | |
1262 | ||
1263 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
1264 | ||
1265 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
1266 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
1267 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
1268 | (*num_maps)++; | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
87ff934a SK |
1273 | #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } |
1274 | #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ | |
e32af889 GF |
1275 | .size = ARRAY_SIZE(y), } |
1276 | ||
1277 | static const unsigned long nmk_pin_input_modes[] = { | |
1278 | PIN_INPUT_NOPULL, | |
1279 | PIN_INPUT_PULLUP, | |
1280 | PIN_INPUT_PULLDOWN, | |
1281 | }; | |
1282 | ||
1283 | static const unsigned long nmk_pin_output_modes[] = { | |
1284 | PIN_OUTPUT_LOW, | |
1285 | PIN_OUTPUT_HIGH, | |
1286 | PIN_DIR_OUTPUT, | |
1287 | }; | |
1288 | ||
1289 | static const unsigned long nmk_pin_sleep_modes[] = { | |
1290 | PIN_SLEEPMODE_DISABLED, | |
1291 | PIN_SLEEPMODE_ENABLED, | |
1292 | }; | |
1293 | ||
1294 | static const unsigned long nmk_pin_sleep_input_modes[] = { | |
1295 | PIN_SLPM_INPUT_NOPULL, | |
1296 | PIN_SLPM_INPUT_PULLUP, | |
1297 | PIN_SLPM_INPUT_PULLDOWN, | |
1298 | PIN_SLPM_DIR_INPUT, | |
1299 | }; | |
1300 | ||
1301 | static const unsigned long nmk_pin_sleep_output_modes[] = { | |
1302 | PIN_SLPM_OUTPUT_LOW, | |
1303 | PIN_SLPM_OUTPUT_HIGH, | |
1304 | PIN_SLPM_DIR_OUTPUT, | |
1305 | }; | |
1306 | ||
1307 | static const unsigned long nmk_pin_sleep_wakeup_modes[] = { | |
1308 | PIN_SLPM_WAKEUP_DISABLE, | |
1309 | PIN_SLPM_WAKEUP_ENABLE, | |
1310 | }; | |
1311 | ||
1312 | static const unsigned long nmk_pin_gpio_modes[] = { | |
1313 | PIN_GPIOMODE_DISABLED, | |
1314 | PIN_GPIOMODE_ENABLED, | |
1315 | }; | |
1316 | ||
1317 | static const unsigned long nmk_pin_sleep_pdis_modes[] = { | |
1318 | PIN_SLPM_PDIS_DISABLED, | |
1319 | PIN_SLPM_PDIS_ENABLED, | |
1320 | }; | |
1321 | ||
1322 | struct nmk_cfg_param { | |
1323 | const char *property; | |
1324 | unsigned long config; | |
1325 | const unsigned long *choice; | |
1326 | int size; | |
1327 | }; | |
1328 | ||
1329 | static const struct nmk_cfg_param nmk_cfg_params[] = { | |
1330 | NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), | |
1331 | NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), | |
1332 | NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), | |
1333 | NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), | |
1334 | NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), | |
1335 | NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), | |
1336 | NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), | |
1337 | NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), | |
1338 | }; | |
1339 | ||
1340 | static int nmk_dt_pin_config(int index, int val, unsigned long *config) | |
1341 | { | |
e32af889 GF |
1342 | if (nmk_cfg_params[index].choice == NULL) |
1343 | *config = nmk_cfg_params[index].config; | |
1344 | else { | |
1345 | /* test if out of range */ | |
1346 | if (val < nmk_cfg_params[index].size) { | |
1347 | *config = nmk_cfg_params[index].config | | |
1348 | nmk_cfg_params[index].choice[val]; | |
1349 | } | |
1350 | } | |
7e23ab72 | 1351 | return 0; |
e32af889 GF |
1352 | } |
1353 | ||
1354 | static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) | |
1355 | { | |
1356 | int i, pin_number; | |
1357 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1358 | ||
1359 | if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) | |
1360 | for (i = 0; i < npct->soc->npins; i++) | |
1361 | if (npct->soc->pins[i].number == pin_number) | |
1362 | return npct->soc->pins[i].name; | |
1363 | return NULL; | |
1364 | } | |
1365 | ||
1366 | static bool nmk_pinctrl_dt_get_config(struct device_node *np, | |
1367 | unsigned long *configs) | |
1368 | { | |
1369 | bool has_config = 0; | |
1370 | unsigned long cfg = 0; | |
1371 | int i, val, ret; | |
1372 | ||
1373 | for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { | |
1374 | ret = of_property_read_u32(np, | |
1375 | nmk_cfg_params[i].property, &val); | |
1376 | if (ret != -EINVAL) { | |
1377 | if (nmk_dt_pin_config(i, val, &cfg) == 0) { | |
1378 | *configs |= cfg; | |
1379 | has_config = 1; | |
1380 | } | |
1381 | } | |
1382 | } | |
1383 | ||
1384 | return has_config; | |
1385 | } | |
1386 | ||
2230a36e | 1387 | static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
e32af889 GF |
1388 | struct device_node *np, |
1389 | struct pinctrl_map **map, | |
1390 | unsigned *reserved_maps, | |
1391 | unsigned *num_maps) | |
1392 | { | |
1393 | int ret; | |
1394 | const char *function = NULL; | |
1395 | unsigned long configs = 0; | |
1396 | bool has_config = 0; | |
e32af889 | 1397 | struct property *prop; |
e32af889 GF |
1398 | struct device_node *np_config; |
1399 | ||
68d41f23 | 1400 | ret = of_property_read_string(np, "function", &function); |
c2f6d059 | 1401 | if (ret >= 0) { |
68d41f23 LW |
1402 | const char *group; |
1403 | ||
1404 | ret = of_property_count_strings(np, "groups"); | |
c2f6d059 LW |
1405 | if (ret < 0) |
1406 | goto exit; | |
1407 | ||
1408 | ret = pinctrl_utils_reserve_map(pctldev, map, | |
1409 | reserved_maps, | |
1410 | num_maps, ret); | |
1411 | if (ret < 0) | |
1412 | goto exit; | |
1413 | ||
68d41f23 | 1414 | of_property_for_each_string(np, "groups", prop, group) { |
e32af889 GF |
1415 | ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, |
1416 | group, function); | |
1417 | if (ret < 0) | |
1418 | goto exit; | |
1419 | } | |
c2f6d059 LW |
1420 | } |
1421 | ||
1422 | has_config = nmk_pinctrl_dt_get_config(np, &configs); | |
1423 | np_config = of_parse_phandle(np, "ste,config", 0); | |
1424 | if (np_config) | |
1425 | has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); | |
1426 | if (has_config) { | |
68d41f23 LW |
1427 | const char *gpio_name; |
1428 | const char *pin; | |
1429 | ||
1637d480 | 1430 | ret = of_property_count_strings(np, "pins"); |
c2f6d059 LW |
1431 | if (ret < 0) |
1432 | goto exit; | |
1433 | ret = pinctrl_utils_reserve_map(pctldev, map, | |
1434 | reserved_maps, | |
1435 | num_maps, ret); | |
1436 | if (ret < 0) | |
1437 | goto exit; | |
1438 | ||
1637d480 | 1439 | of_property_for_each_string(np, "pins", prop, pin) { |
68d41f23 | 1440 | gpio_name = nmk_find_pin_name(pctldev, pin); |
e32af889 | 1441 | |
c2f6d059 LW |
1442 | ret = nmk_dt_add_map_configs(map, reserved_maps, |
1443 | num_maps, | |
1444 | gpio_name, &configs, 1); | |
e32af889 GF |
1445 | if (ret < 0) |
1446 | goto exit; | |
1447 | } | |
e32af889 | 1448 | } |
c2f6d059 | 1449 | |
e32af889 GF |
1450 | exit: |
1451 | return ret; | |
1452 | } | |
1453 | ||
2230a36e | 1454 | static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
e32af889 GF |
1455 | struct device_node *np_config, |
1456 | struct pinctrl_map **map, unsigned *num_maps) | |
1457 | { | |
1458 | unsigned reserved_maps; | |
1459 | struct device_node *np; | |
1460 | int ret; | |
1461 | ||
1462 | reserved_maps = 0; | |
1463 | *map = NULL; | |
1464 | *num_maps = 0; | |
1465 | ||
1466 | for_each_child_of_node(np_config, np) { | |
1467 | ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, | |
1468 | &reserved_maps, num_maps); | |
1469 | if (ret < 0) { | |
d32f7fd3 | 1470 | pinctrl_utils_free_map(pctldev, *map, *num_maps); |
ea8cf5c5 | 1471 | of_node_put(np); |
e32af889 GF |
1472 | return ret; |
1473 | } | |
1474 | } | |
1475 | ||
1476 | return 0; | |
1477 | } | |
1478 | ||
022ab148 | 1479 | static const struct pinctrl_ops nmk_pinctrl_ops = { |
e98ea774 LW |
1480 | .get_groups_count = nmk_get_groups_cnt, |
1481 | .get_group_name = nmk_get_group_name, | |
1482 | .get_group_pins = nmk_get_group_pins, | |
1483 | .pin_dbg_show = nmk_pin_dbg_show, | |
e32af889 | 1484 | .dt_node_to_map = nmk_pinctrl_dt_node_to_map, |
d32f7fd3 | 1485 | .dt_free_map = pinctrl_utils_free_map, |
e98ea774 LW |
1486 | }; |
1487 | ||
dbfe8ca2 LW |
1488 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
1489 | { | |
1490 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1491 | ||
1492 | return npct->soc->nfunctions; | |
1493 | } | |
1494 | ||
1495 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1496 | unsigned function) | |
1497 | { | |
1498 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1499 | ||
1500 | return npct->soc->functions[function].name; | |
1501 | } | |
1502 | ||
1503 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1504 | unsigned function, | |
1505 | const char * const **groups, | |
1506 | unsigned * const num_groups) | |
1507 | { | |
1508 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1509 | ||
1510 | *groups = npct->soc->functions[function].groups; | |
1511 | *num_groups = npct->soc->functions[function].ngroups; | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
03e9f0ca LW |
1516 | static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, |
1517 | unsigned group) | |
dbfe8ca2 LW |
1518 | { |
1519 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1520 | const struct nmk_pingroup *g; | |
1521 | static unsigned int slpm[NUM_BANKS]; | |
f84b4171 | 1522 | unsigned long flags = 0; |
dbfe8ca2 LW |
1523 | bool glitch; |
1524 | int ret = -EINVAL; | |
1525 | int i; | |
1526 | ||
1527 | g = &npct->soc->groups[group]; | |
1528 | ||
1529 | if (g->altsetting < 0) | |
1530 | return -EINVAL; | |
1531 | ||
1532 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
1533 | ||
daf73174 LW |
1534 | /* |
1535 | * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, | |
1536 | * we may pass through an undesired state. In this case we take | |
1537 | * some extra care. | |
1538 | * | |
1539 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
1540 | * - Save SLPM registers (since we have a shadow register in the | |
1541 | * nmk_chip we're using that as backup) | |
1542 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
1543 | * - Configure the GPIO registers for the IOs that are being switched | |
1544 | * - Set IOFORCE=1 | |
1545 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
1546 | * - Set IOFORCE=0 | |
1547 | * - Restore SLPM registers | |
1548 | * - Any spurious wake up event during switch sequence to be ignored | |
1549 | * and cleared | |
1550 | * | |
1551 | * We REALLY need to save ALL slpm registers, because the external | |
1552 | * IOFORCE will switch *all* ports to their sleepmode setting to as | |
1553 | * to avoid glitches. (Not just one port!) | |
1554 | */ | |
c22df08c | 1555 | glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); |
dbfe8ca2 LW |
1556 | |
1557 | if (glitch) { | |
1558 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
1559 | ||
1560 | /* Initially don't put any pins to sleep when switching */ | |
1561 | memset(slpm, 0xff, sizeof(slpm)); | |
1562 | ||
1563 | /* | |
1564 | * Then mask the pins that need to be sleeping now when we're | |
1565 | * switching to the ALT C function. | |
1566 | */ | |
1567 | for (i = 0; i < g->npins; i++) | |
1568 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | |
1569 | nmk_gpio_glitch_slpm_init(slpm); | |
1570 | } | |
1571 | ||
1572 | for (i = 0; i < g->npins; i++) { | |
dbfe8ca2 | 1573 | struct nmk_gpio_chip *nmk_chip; |
dbfe8ca2 LW |
1574 | unsigned bit; |
1575 | ||
6ca7d2e3 LW |
1576 | nmk_chip = find_nmk_gpio_from_pin(g->pins[i]); |
1577 | if (!nmk_chip) { | |
dbfe8ca2 LW |
1578 | dev_err(npct->dev, |
1579 | "invalid pin offset %d in group %s at index %d\n", | |
1580 | g->pins[i], g->name, i); | |
1581 | goto out_glitch; | |
1582 | } | |
dbfe8ca2 LW |
1583 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); |
1584 | ||
1585 | clk_enable(nmk_chip->clk); | |
1586 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | |
1587 | /* | |
1588 | * If the pin is switching to altfunc, and there was an | |
1589 | * interrupt installed on it which has been lazy disabled, | |
1590 | * actually mask the interrupt to prevent spurious interrupts | |
1591 | * that would occur while the pin is under control of the | |
1592 | * peripheral. Only SKE does this. | |
1593 | */ | |
1594 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | |
1595 | ||
c22df08c JNG |
1596 | __nmk_gpio_set_mode_safe(nmk_chip, bit, |
1597 | (g->altsetting & NMK_GPIO_ALT_C), glitch); | |
dbfe8ca2 | 1598 | clk_disable(nmk_chip->clk); |
c22df08c JNG |
1599 | |
1600 | /* | |
1601 | * Call PRCM GPIOCR config function in case ALTC | |
1602 | * has been selected: | |
1603 | * - If selection is a ALTCx, some bits in PRCM GPIOCR registers | |
1604 | * must be set. | |
1605 | * - If selection is pure ALTC and previous selection was ALTCx, | |
1606 | * then some bits in PRCM GPIOCR registers must be cleared. | |
1607 | */ | |
1608 | if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) | |
1609 | nmk_prcm_altcx_set_mode(npct, g->pins[i], | |
1610 | g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); | |
dbfe8ca2 LW |
1611 | } |
1612 | ||
1613 | /* When all pins are successfully reconfigured we get here */ | |
1614 | ret = 0; | |
1615 | ||
1616 | out_glitch: | |
1617 | if (glitch) { | |
1618 | nmk_gpio_glitch_slpm_restore(slpm); | |
1619 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
1620 | } | |
1621 | ||
1622 | return ret; | |
1623 | } | |
1624 | ||
5212d096 AL |
1625 | static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, |
1626 | struct pinctrl_gpio_range *range, | |
1627 | unsigned offset) | |
dbfe8ca2 LW |
1628 | { |
1629 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1630 | struct nmk_gpio_chip *nmk_chip; | |
1631 | struct gpio_chip *chip; | |
1632 | unsigned bit; | |
1633 | ||
1634 | if (!range) { | |
1635 | dev_err(npct->dev, "invalid range\n"); | |
1636 | return -EINVAL; | |
1637 | } | |
1638 | if (!range->gc) { | |
1639 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
1640 | return -EINVAL; | |
1641 | } | |
1642 | chip = range->gc; | |
68ab0126 | 1643 | nmk_chip = gpiochip_get_data(chip); |
dbfe8ca2 LW |
1644 | |
1645 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
1646 | ||
1647 | clk_enable(nmk_chip->clk); | |
1648 | bit = offset % NMK_GPIO_PER_CHIP; | |
1649 | /* There is no glitch when converting any pin to GPIO */ | |
1650 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1651 | clk_disable(nmk_chip->clk); | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
5212d096 AL |
1656 | static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, |
1657 | struct pinctrl_gpio_range *range, | |
1658 | unsigned offset) | |
dbfe8ca2 LW |
1659 | { |
1660 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1661 | ||
1662 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
1663 | /* Set the pin to some default state, GPIO is usually default */ | |
1664 | } | |
1665 | ||
022ab148 | 1666 | static const struct pinmux_ops nmk_pinmux_ops = { |
dbfe8ca2 LW |
1667 | .get_functions_count = nmk_pmx_get_funcs_cnt, |
1668 | .get_function_name = nmk_pmx_get_func_name, | |
1669 | .get_function_groups = nmk_pmx_get_func_groups, | |
03e9f0ca | 1670 | .set_mux = nmk_pmx_set, |
dbfe8ca2 LW |
1671 | .gpio_request_enable = nmk_gpio_request_enable, |
1672 | .gpio_disable_free = nmk_gpio_disable_free, | |
a21763a0 | 1673 | .strict = true, |
dbfe8ca2 LW |
1674 | }; |
1675 | ||
5212d096 AL |
1676 | static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, |
1677 | unsigned long *config) | |
d41af627 LW |
1678 | { |
1679 | /* Not implemented */ | |
1680 | return -EINVAL; | |
1681 | } | |
1682 | ||
5212d096 | 1683 | static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
03b054e9 | 1684 | unsigned long *configs, unsigned num_configs) |
d41af627 LW |
1685 | { |
1686 | static const char *pullnames[] = { | |
1687 | [NMK_GPIO_PULL_NONE] = "none", | |
1688 | [NMK_GPIO_PULL_UP] = "up", | |
1689 | [NMK_GPIO_PULL_DOWN] = "down", | |
1690 | [3] /* illegal */ = "??" | |
1691 | }; | |
1692 | static const char *slpmnames[] = { | |
1693 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | |
1694 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
1695 | }; | |
1696 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1697 | struct nmk_gpio_chip *nmk_chip; | |
d41af627 | 1698 | unsigned bit; |
03b054e9 SY |
1699 | pin_cfg_t cfg; |
1700 | int pull, slpm, output, val, i; | |
1701 | bool lowemi, gpiomode, sleep; | |
d41af627 | 1702 | |
6ca7d2e3 LW |
1703 | nmk_chip = find_nmk_gpio_from_pin(pin); |
1704 | if (!nmk_chip) { | |
1705 | dev_err(npct->dev, | |
1706 | "invalid pin offset %d\n", pin); | |
d41af627 LW |
1707 | return -EINVAL; |
1708 | } | |
d41af627 | 1709 | |
03b054e9 | 1710 | for (i = 0; i < num_configs; i++) { |
d41af627 | 1711 | /* |
03b054e9 SY |
1712 | * The pin config contains pin number and altfunction fields, |
1713 | * here we just ignore that part. It's being handled by the | |
1714 | * framework and pinmux callback respectively. | |
d41af627 | 1715 | */ |
03b054e9 SY |
1716 | cfg = (pin_cfg_t) configs[i]; |
1717 | pull = PIN_PULL(cfg); | |
1718 | slpm = PIN_SLPM(cfg); | |
1719 | output = PIN_DIR(cfg); | |
1720 | val = PIN_VAL(cfg); | |
1721 | lowemi = PIN_LOWEMI(cfg); | |
1722 | gpiomode = PIN_GPIOMODE(cfg); | |
1723 | sleep = PIN_SLEEPMODE(cfg); | |
1724 | ||
1725 | if (sleep) { | |
1726 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
1727 | int slpm_output = PIN_SLPM_DIR(cfg); | |
1728 | int slpm_val = PIN_SLPM_VAL(cfg); | |
1729 | ||
1730 | /* All pins go into GPIO mode at sleep */ | |
1731 | gpiomode = true; | |
1732 | ||
1733 | /* | |
1734 | * The SLPM_* values are normal values + 1 to allow zero | |
1735 | * to mean "same as normal". | |
1736 | */ | |
1737 | if (slpm_pull) | |
1738 | pull = slpm_pull - 1; | |
1739 | if (slpm_output) | |
1740 | output = slpm_output - 1; | |
1741 | if (slpm_val) | |
1742 | val = slpm_val - 1; | |
1743 | ||
58383c78 | 1744 | dev_dbg(nmk_chip->chip.parent, |
03b054e9 SY |
1745 | "pin %d: sleep pull %s, dir %s, val %s\n", |
1746 | pin, | |
1747 | slpm_pull ? pullnames[pull] : "same", | |
1748 | slpm_output ? (output ? "output" : "input") | |
1749 | : "same", | |
1750 | slpm_val ? (val ? "high" : "low") : "same"); | |
1751 | } | |
d41af627 | 1752 | |
58383c78 | 1753 | dev_dbg(nmk_chip->chip.parent, |
03b054e9 SY |
1754 | "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", |
1755 | pin, cfg, pullnames[pull], slpmnames[slpm], | |
1756 | output ? "output " : "input", | |
1757 | output ? (val ? "high" : "low") : "", | |
1758 | lowemi ? "on" : "off"); | |
d41af627 | 1759 | |
03b054e9 SY |
1760 | clk_enable(nmk_chip->clk); |
1761 | bit = pin % NMK_GPIO_PER_CHIP; | |
1762 | if (gpiomode) | |
1763 | /* No glitch when going to GPIO mode */ | |
1764 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1765 | if (output) | |
1766 | __nmk_gpio_make_output(nmk_chip, bit, val); | |
1767 | else { | |
1768 | __nmk_gpio_make_input(nmk_chip, bit); | |
1769 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | |
1770 | } | |
1771 | /* TODO: isn't this only applicable on output pins? */ | |
1772 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | |
1773 | ||
1774 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | |
1775 | clk_disable(nmk_chip->clk); | |
1776 | } /* for each config */ | |
d41af627 | 1777 | |
d41af627 LW |
1778 | return 0; |
1779 | } | |
1780 | ||
022ab148 | 1781 | static const struct pinconf_ops nmk_pinconf_ops = { |
d41af627 LW |
1782 | .pin_config_get = nmk_pin_config_get, |
1783 | .pin_config_set = nmk_pin_config_set, | |
1784 | }; | |
1785 | ||
e98ea774 LW |
1786 | static struct pinctrl_desc nmk_pinctrl_desc = { |
1787 | .name = "pinctrl-nomadik", | |
1788 | .pctlops = &nmk_pinctrl_ops, | |
dbfe8ca2 | 1789 | .pmxops = &nmk_pinmux_ops, |
d41af627 | 1790 | .confops = &nmk_pinconf_ops, |
e98ea774 LW |
1791 | .owner = THIS_MODULE, |
1792 | }; | |
1793 | ||
855f80cd | 1794 | static const struct of_device_id nmk_pinctrl_match[] = { |
6010d403 | 1795 | { |
3fd765a9 | 1796 | .compatible = "stericsson,stn8815-pinctrl", |
6010d403 LW |
1797 | .data = (void *)PINCTRL_NMK_STN8815, |
1798 | }, | |
855f80cd | 1799 | { |
6b09a834 | 1800 | .compatible = "stericsson,db8500-pinctrl", |
855f80cd LJ |
1801 | .data = (void *)PINCTRL_NMK_DB8500, |
1802 | }, | |
356d3e45 | 1803 | { |
6b09a834 | 1804 | .compatible = "stericsson,db8540-pinctrl", |
356d3e45 GF |
1805 | .data = (void *)PINCTRL_NMK_DB8540, |
1806 | }, | |
855f80cd LJ |
1807 | {}, |
1808 | }; | |
1809 | ||
131d85bc | 1810 | #ifdef CONFIG_PM_SLEEP |
c003eed7 | 1811 | static int nmk_pinctrl_suspend(struct device *dev) |
8d99b32d JD |
1812 | { |
1813 | struct nmk_pinctrl *npct; | |
1814 | ||
c003eed7 | 1815 | npct = dev_get_drvdata(dev); |
8d99b32d JD |
1816 | if (!npct) |
1817 | return -EINVAL; | |
1818 | ||
1819 | return pinctrl_force_sleep(npct->pctl); | |
1820 | } | |
1821 | ||
c003eed7 | 1822 | static int nmk_pinctrl_resume(struct device *dev) |
8d99b32d JD |
1823 | { |
1824 | struct nmk_pinctrl *npct; | |
1825 | ||
c003eed7 | 1826 | npct = dev_get_drvdata(dev); |
8d99b32d JD |
1827 | if (!npct) |
1828 | return -EINVAL; | |
1829 | ||
1830 | return pinctrl_force_default(npct->pctl); | |
1831 | } | |
131d85bc | 1832 | #endif |
8d99b32d | 1833 | |
150632b0 | 1834 | static int nmk_pinctrl_probe(struct platform_device *pdev) |
e98ea774 | 1835 | { |
f4b3f523 | 1836 | const struct of_device_id *match; |
855f80cd | 1837 | struct device_node *np = pdev->dev.of_node; |
32e67eee | 1838 | struct device_node *prcm_np; |
e98ea774 | 1839 | struct nmk_pinctrl *npct; |
855f80cd | 1840 | unsigned int version = 0; |
e98ea774 LW |
1841 | int i; |
1842 | ||
1843 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | |
1844 | if (!npct) | |
1845 | return -ENOMEM; | |
1846 | ||
f4b3f523 LW |
1847 | match = of_match_device(nmk_pinctrl_match, &pdev->dev); |
1848 | if (!match) | |
1849 | return -ENODEV; | |
1850 | version = (unsigned int) match->data; | |
855f80cd | 1851 | |
e98ea774 | 1852 | /* Poke in other ASIC variants here */ |
f79c5ed9 LW |
1853 | if (version == PINCTRL_NMK_STN8815) |
1854 | nmk_pinctrl_stn8815_init(&npct->soc); | |
855f80cd | 1855 | if (version == PINCTRL_NMK_DB8500) |
e98ea774 | 1856 | nmk_pinctrl_db8500_init(&npct->soc); |
45a1b531 PC |
1857 | if (version == PINCTRL_NMK_DB8540) |
1858 | nmk_pinctrl_db8540_init(&npct->soc); | |
e98ea774 | 1859 | |
ab4a9362 LW |
1860 | /* |
1861 | * Since we depend on the GPIO chips to provide clock and register base | |
1862 | * for the pin control operations, make sure that we have these | |
1863 | * populated before we continue. Follow the phandles to instantiate | |
1864 | * them. The GPIO portion of the actual hardware may be probed before | |
1865 | * or after this point: it shouldn't matter as the APIs are orthogonal. | |
1866 | */ | |
1867 | for (i = 0; i < NMK_MAX_BANKS; i++) { | |
1868 | struct device_node *gpio_np; | |
1869 | struct nmk_gpio_chip *nmk_chip; | |
1870 | ||
1871 | gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i); | |
1872 | if (gpio_np) { | |
1873 | dev_info(&pdev->dev, | |
94f4e54c RH |
1874 | "populate NMK GPIO %d \"%pOFn\"\n", |
1875 | i, gpio_np); | |
ab4a9362 LW |
1876 | nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); |
1877 | if (IS_ERR(nmk_chip)) | |
1878 | dev_err(&pdev->dev, | |
1879 | "could not populate nmk chip struct " | |
1880 | "- continue anyway\n"); | |
1881 | of_node_put(gpio_np); | |
1882 | } | |
1883 | } | |
1884 | ||
f4b3f523 LW |
1885 | prcm_np = of_parse_phandle(np, "prcm", 0); |
1886 | if (prcm_np) | |
1887 | npct->prcm_base = of_iomap(prcm_np, 0); | |
32e67eee LJ |
1888 | if (!npct->prcm_base) { |
1889 | if (version == PINCTRL_NMK_STN8815) { | |
1890 | dev_info(&pdev->dev, | |
1891 | "No PRCM base, " | |
1892 | "assuming no ALT-Cx control is available\n"); | |
1893 | } else { | |
1894 | dev_err(&pdev->dev, "missing PRCM base address\n"); | |
1895 | return -EINVAL; | |
f1671bf5 | 1896 | } |
f1671bf5 JA |
1897 | } |
1898 | ||
e98ea774 LW |
1899 | nmk_pinctrl_desc.pins = npct->soc->pins; |
1900 | nmk_pinctrl_desc.npins = npct->soc->npins; | |
1901 | npct->dev = &pdev->dev; | |
f1671bf5 | 1902 | |
0ee60110 | 1903 | npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct); |
323de9ef | 1904 | if (IS_ERR(npct->pctl)) { |
e98ea774 | 1905 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); |
323de9ef | 1906 | return PTR_ERR(npct->pctl); |
e98ea774 LW |
1907 | } |
1908 | ||
e98ea774 LW |
1909 | platform_set_drvdata(pdev, npct); |
1910 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | |
1911 | ||
1912 | return 0; | |
1913 | } | |
1914 | ||
513c27f8 LJ |
1915 | static const struct of_device_id nmk_gpio_match[] = { |
1916 | { .compatible = "st,nomadik-gpio", }, | |
1917 | {} | |
1918 | }; | |
1919 | ||
3e3c62ca RV |
1920 | static struct platform_driver nmk_gpio_driver = { |
1921 | .driver = { | |
2ec1d359 | 1922 | .name = "gpio", |
513c27f8 | 1923 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 1924 | }, |
2ec1d359 | 1925 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1926 | }; |
1927 | ||
c003eed7 UH |
1928 | static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, |
1929 | nmk_pinctrl_suspend, | |
1930 | nmk_pinctrl_resume); | |
1931 | ||
e98ea774 LW |
1932 | static struct platform_driver nmk_pinctrl_driver = { |
1933 | .driver = { | |
e98ea774 | 1934 | .name = "pinctrl-nomadik", |
855f80cd | 1935 | .of_match_table = nmk_pinctrl_match, |
c003eed7 | 1936 | .pm = &nmk_pinctrl_pm_ops, |
e98ea774 LW |
1937 | }, |
1938 | .probe = nmk_pinctrl_probe, | |
e98ea774 LW |
1939 | }; |
1940 | ||
2ec1d359 AR |
1941 | static int __init nmk_gpio_init(void) |
1942 | { | |
802bb9b6 LW |
1943 | return platform_driver_register(&nmk_gpio_driver); |
1944 | } | |
1945 | subsys_initcall(nmk_gpio_init); | |
e98ea774 | 1946 | |
802bb9b6 LW |
1947 | static int __init nmk_pinctrl_init(void) |
1948 | { | |
e98ea774 | 1949 | return platform_driver_register(&nmk_pinctrl_driver); |
2ec1d359 | 1950 | } |
802bb9b6 | 1951 | core_initcall(nmk_pinctrl_init); |