pinctrl: ns2: rename pinctrl_utils_dt_free_map
[linux-block.git] / drivers / pinctrl / nomadik / pinctrl-nomadik.c
CommitLineData
2ec1d359
AR
1/*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
f4b3f523 7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
2ec1d359
AR
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/device.h>
3e3c62ca 17#include <linux/platform_device.h>
2ec1d359 18#include <linux/io.h>
af7dc228
RV
19#include <linux/clk.h>
20#include <linux/err.h>
2ec1d359
AR
21#include <linux/gpio.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
5a0e3ad6 24#include <linux/slab.h>
855f80cd 25#include <linux/of_device.h>
32e67eee 26#include <linux/of_address.h>
5e81e0a0 27#include <linux/bitops.h>
e32af889 28#include <linux/pinctrl/machine.h>
e98ea774 29#include <linux/pinctrl/pinctrl.h>
dbfe8ca2 30#include <linux/pinctrl/pinmux.h>
d41af627 31#include <linux/pinctrl/pinconf.h>
dbfe8ca2
LW
32/* Since we request GPIOs from ourself */
33#include <linux/pinctrl/consumer.h>
e98ea774 34#include "pinctrl-nomadik.h"
3a198059 35#include "../core.h"
ba388294 36#include "../pinctrl-utils.h"
e98ea774 37
2ec1d359
AR
38/*
39 * The GPIO module in the Nomadik family of Systems-on-Chip is an
40 * AMBA device, managing 32 pins and alternate functions. The logic block
9c66ee6f 41 * is currently used in the Nomadik and ux500.
2ec1d359
AR
42 *
43 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
44 */
45
8d993397
LW
46/*
47 * pin configurations are represented by 32-bit integers:
48 *
49 * bit 0.. 8 - Pin Number (512 Pins Maximum)
50 * bit 9..10 - Alternate Function Selection
51 * bit 11..12 - Pull up/down state
52 * bit 13 - Sleep mode behaviour
53 * bit 14 - Direction
54 * bit 15 - Value (if output)
55 * bit 16..18 - SLPM pull up/down state
56 * bit 19..20 - SLPM direction
57 * bit 21..22 - SLPM Value (if output)
58 * bit 23..25 - PDIS value (if input)
59 * bit 26 - Gpio mode
60 * bit 27 - Sleep mode
61 *
62 * to facilitate the definition, the following macros are provided
63 *
64 * PIN_CFG_DEFAULT - default config (0):
65 * pull up/down = disabled
66 * sleep mode = input/wakeup
67 * direction = input
68 * value = low
69 * SLPM direction = same as normal
70 * SLPM pull = same as normal
71 * SLPM value = same as normal
72 *
73 * PIN_CFG - default config with alternate function
74 */
75
76typedef unsigned long pin_cfg_t;
77
78#define PIN_NUM_MASK 0x1ff
79#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
80
81#define PIN_ALT_SHIFT 9
82#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
83#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
84#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
85#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
86#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
87#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
88
89#define PIN_PULL_SHIFT 11
90#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
91#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
92#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
93#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
94#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
95
96#define PIN_SLPM_SHIFT 13
97#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
98#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
99#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
100#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
101/* These two replace the above in DB8500v2+ */
102#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
103#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
104#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
105
106#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
107#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
108
109#define PIN_DIR_SHIFT 14
110#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
111#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
112#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
113#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
114
115#define PIN_VAL_SHIFT 15
116#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
117#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
118#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
119#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
120
121#define PIN_SLPM_PULL_SHIFT 16
122#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
123#define PIN_SLPM_PULL(x) \
124 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
125#define PIN_SLPM_PULL_NONE \
126 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
127#define PIN_SLPM_PULL_UP \
128 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
129#define PIN_SLPM_PULL_DOWN \
130 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
131
132#define PIN_SLPM_DIR_SHIFT 19
133#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
134#define PIN_SLPM_DIR(x) \
135 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
136#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
137#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
138
139#define PIN_SLPM_VAL_SHIFT 21
140#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
141#define PIN_SLPM_VAL(x) \
142 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
143#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
144#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
145
146#define PIN_SLPM_PDIS_SHIFT 23
147#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
148#define PIN_SLPM_PDIS(x) \
149 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
150#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
151#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
152#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
153
154#define PIN_LOWEMI_SHIFT 25
155#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
156#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
157#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
158#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
159
160#define PIN_GPIOMODE_SHIFT 26
161#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
162#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
163#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
164#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
165
166#define PIN_SLEEPMODE_SHIFT 27
167#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
168#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
169#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
170#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
171
172
173/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
174#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
175#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
176#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
177#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
178#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
179
180#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
181#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
182#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
183#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
184#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
185
186#define PIN_CFG_DEFAULT (0)
187
188#define PIN_CFG(num, alt) \
189 (PIN_CFG_DEFAULT |\
190 (PIN_NUM(num) | PIN_##alt))
191
192#define PIN_CFG_INPUT(num, alt, pull) \
193 (PIN_CFG_DEFAULT |\
194 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
195
196#define PIN_CFG_OUTPUT(num, alt, val) \
197 (PIN_CFG_DEFAULT |\
198 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
199
200/*
201 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
202 * the "gpio" namespace for generic and cross-machine functions
203 */
204
205#define GPIO_BLOCK_SHIFT 5
206#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
bc222ef4 207#define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)
8d993397
LW
208
209/* Register in the logic block */
210#define NMK_GPIO_DAT 0x00
211#define NMK_GPIO_DATS 0x04
212#define NMK_GPIO_DATC 0x08
213#define NMK_GPIO_PDIS 0x0c
214#define NMK_GPIO_DIR 0x10
215#define NMK_GPIO_DIRS 0x14
216#define NMK_GPIO_DIRC 0x18
217#define NMK_GPIO_SLPC 0x1c
218#define NMK_GPIO_AFSLA 0x20
219#define NMK_GPIO_AFSLB 0x24
220#define NMK_GPIO_LOWEMI 0x28
221
222#define NMK_GPIO_RIMSC 0x40
223#define NMK_GPIO_FIMSC 0x44
224#define NMK_GPIO_IS 0x48
225#define NMK_GPIO_IC 0x4c
226#define NMK_GPIO_RWIMSC 0x50
227#define NMK_GPIO_FWIMSC 0x54
228#define NMK_GPIO_WKS 0x58
229/* These appear in DB8540 and later ASICs */
230#define NMK_GPIO_EDGELEVEL 0x5C
231#define NMK_GPIO_LEVEL 0x60
232
233
234/* Pull up/down values */
235enum nmk_gpio_pull {
236 NMK_GPIO_PULL_NONE,
237 NMK_GPIO_PULL_UP,
238 NMK_GPIO_PULL_DOWN,
239};
240
241/* Sleep mode */
242enum nmk_gpio_slpm {
243 NMK_GPIO_SLPM_INPUT,
244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
245 NMK_GPIO_SLPM_NOCHANGE,
246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
247};
248
2ec1d359
AR
249struct nmk_gpio_chip {
250 struct gpio_chip chip;
3007d941 251 struct irq_chip irqchip;
2ec1d359 252 void __iomem *addr;
af7dc228 253 struct clk *clk;
33b744b3 254 unsigned int bank;
2ec1d359 255 unsigned int parent_irq;
194e15ba
LW
256 int latent_parent_irq;
257 u32 (*get_latent_status)(unsigned int bank);
01727e61 258 void (*set_ioforce)(bool enable);
c0fcb8db 259 spinlock_t lock;
33d78647 260 bool sleepmode;
2ec1d359
AR
261 /* Keep track of configured edges */
262 u32 edge_rising;
263 u32 edge_falling;
b9df468d
RV
264 u32 real_wake;
265 u32 rwimsc;
266 u32 fwimsc;
6c12fe88
RV
267 u32 rimsc;
268 u32 fimsc;
bc6f5cf6 269 u32 pull_up;
ebc6178d 270 u32 lowemi;
2ec1d359
AR
271};
272
f1671bf5
JA
273/**
274 * struct nmk_pinctrl - state container for the Nomadik pin controller
275 * @dev: containing device pointer
276 * @pctl: corresponding pin controller device
277 * @soc: SoC data for this specific chip
278 * @prcm_base: PRCM register range virtual base
279 */
e98ea774
LW
280struct nmk_pinctrl {
281 struct device *dev;
282 struct pinctrl_dev *pctl;
283 const struct nmk_pinctrl_soc_data *soc;
f1671bf5 284 void __iomem *prcm_base;
e98ea774
LW
285};
286
bc222ef4 287static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
01727e61
RV
288
289static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
290
291#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
292
6f9a974c
RV
293static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
294 unsigned offset, int gpio_mode)
295{
6f9a974c
RV
296 u32 afunc, bfunc;
297
5e81e0a0
LW
298 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
299 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
6f9a974c 300 if (gpio_mode & NMK_GPIO_ALT_A)
5e81e0a0 301 afunc |= BIT(offset);
6f9a974c 302 if (gpio_mode & NMK_GPIO_ALT_B)
5e81e0a0 303 bfunc |= BIT(offset);
6f9a974c
RV
304 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
305 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
306}
307
81a3c298
RV
308static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
309 unsigned offset, enum nmk_gpio_slpm mode)
310{
81a3c298
RV
311 u32 slpm;
312
313 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
314 if (mode == NMK_GPIO_SLPM_NOCHANGE)
5e81e0a0 315 slpm |= BIT(offset);
81a3c298 316 else
5e81e0a0 317 slpm &= ~BIT(offset);
81a3c298
RV
318 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
319}
320
5b327edf
RV
321static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
322 unsigned offset, enum nmk_gpio_pull pull)
323{
5b327edf
RV
324 u32 pdis;
325
326 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
bc6f5cf6 327 if (pull == NMK_GPIO_PULL_NONE) {
5e81e0a0
LW
328 pdis |= BIT(offset);
329 nmk_chip->pull_up &= ~BIT(offset);
bc6f5cf6 330 } else {
5e81e0a0 331 pdis &= ~BIT(offset);
bc6f5cf6
RA
332 }
333
5b327edf
RV
334 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
335
bc6f5cf6 336 if (pull == NMK_GPIO_PULL_UP) {
5e81e0a0
LW
337 nmk_chip->pull_up |= BIT(offset);
338 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
bc6f5cf6 339 } else if (pull == NMK_GPIO_PULL_DOWN) {
5e81e0a0
LW
340 nmk_chip->pull_up &= ~BIT(offset);
341 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
bc6f5cf6 342 }
5b327edf
RV
343}
344
ebc6178d
RV
345static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
346 unsigned offset, bool lowemi)
347{
5e81e0a0 348 bool enabled = nmk_chip->lowemi & BIT(offset);
ebc6178d
RV
349
350 if (lowemi == enabled)
351 return;
352
353 if (lowemi)
5e81e0a0 354 nmk_chip->lowemi |= BIT(offset);
ebc6178d 355 else
5e81e0a0 356 nmk_chip->lowemi &= ~BIT(offset);
ebc6178d
RV
357
358 writel_relaxed(nmk_chip->lowemi,
359 nmk_chip->addr + NMK_GPIO_LOWEMI);
360}
361
378be066
RV
362static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
363 unsigned offset)
364{
5e81e0a0 365 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
378be066
RV
366}
367
6720db7c
RV
368static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
369 unsigned offset, int val)
370{
371 if (val)
5e81e0a0 372 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
6720db7c 373 else
5e81e0a0 374 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
6720db7c
RV
375}
376
377static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
378 unsigned offset, int val)
379{
5e81e0a0 380 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
6720db7c
RV
381 __nmk_gpio_set_output(nmk_chip, offset, val);
382}
383
01727e61
RV
384static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
385 unsigned offset, int gpio_mode,
386 bool glitch)
387{
6c12fe88
RV
388 u32 rwimsc = nmk_chip->rwimsc;
389 u32 fwimsc = nmk_chip->fwimsc;
01727e61
RV
390
391 if (glitch && nmk_chip->set_ioforce) {
392 u32 bit = BIT(offset);
393
01727e61
RV
394 /* Prevent spurious wakeups */
395 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
396 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
397
398 nmk_chip->set_ioforce(true);
399 }
400
401 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
402
403 if (glitch && nmk_chip->set_ioforce) {
404 nmk_chip->set_ioforce(false);
405
406 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
407 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
408 }
409}
410
6c42ad1c
RV
411static void
412nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
413{
414 u32 falling = nmk_chip->fimsc & BIT(offset);
415 u32 rising = nmk_chip->rimsc & BIT(offset);
416 int gpio = nmk_chip->chip.base + offset;
e0bc34a3 417 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset);
6c42ad1c
RV
418 struct irq_data *d = irq_get_irq_data(irq);
419
420 if (!rising && !falling)
421 return;
422
423 if (!d || !irqd_irq_disabled(d))
424 return;
425
426 if (rising) {
427 nmk_chip->rimsc &= ~BIT(offset);
428 writel_relaxed(nmk_chip->rimsc,
429 nmk_chip->addr + NMK_GPIO_RIMSC);
430 }
431
432 if (falling) {
433 nmk_chip->fimsc &= ~BIT(offset);
434 writel_relaxed(nmk_chip->fimsc,
435 nmk_chip->addr + NMK_GPIO_FIMSC);
436 }
437
58383c78 438 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
6c42ad1c
RV
439}
440
f1671bf5
JA
441static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
442{
443 u32 val;
444
445 val = readl(reg);
446 val = ((val & ~mask) | (value & mask));
447 writel(val, reg);
448}
449
c22df08c
JNG
450static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
451 unsigned offset, unsigned alt_num)
452{
453 int i;
454 u16 reg;
455 u8 bit;
456 u8 alt_index;
457 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
458 const u16 *gpiocr_regs;
459
4ca075de
FB
460 if (!npct->prcm_base)
461 return;
462
c22df08c
JNG
463 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
464 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
465 alt_num);
466 return;
467 }
468
469 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
470 if (npct->soc->altcx_pins[i].pin == offset)
471 break;
472 }
473 if (i == npct->soc->npins_altcx) {
474 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
475 offset);
476 return;
477 }
478
479 pin_desc = npct->soc->altcx_pins + i;
480 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
481
482 /*
483 * If alt_num is NULL, just clear current ALTCx selection
484 * to make sure we come back to a pure ALTC selection
485 */
486 if (!alt_num) {
487 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
488 if (pin_desc->altcx[i].used == true) {
489 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
490 bit = pin_desc->altcx[i].control_bit;
f1671bf5
JA
491 if (readl(npct->prcm_base + reg) & BIT(bit)) {
492 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
c22df08c
JNG
493 dev_dbg(npct->dev,
494 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
495 offset, i+1);
496 }
497 }
498 }
499 return;
500 }
501
502 alt_index = alt_num - 1;
503 if (pin_desc->altcx[alt_index].used == false) {
504 dev_warn(npct->dev,
505 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
506 offset, alt_num);
507 return;
508 }
509
510 /*
511 * Check if any other ALTCx functions are activated on this pin
512 * and disable it first.
513 */
514 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
515 if (i == alt_index)
516 continue;
517 if (pin_desc->altcx[i].used == true) {
518 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
519 bit = pin_desc->altcx[i].control_bit;
f1671bf5
JA
520 if (readl(npct->prcm_base + reg) & BIT(bit)) {
521 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
c22df08c
JNG
522 dev_dbg(npct->dev,
523 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
524 offset, i+1);
525 }
526 }
527 }
528
529 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
530 bit = pin_desc->altcx[alt_index].control_bit;
531 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
532 offset, alt_index+1);
f1671bf5 533 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
c22df08c
JNG
534}
535
01727e61
RV
536/*
537 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
538 * - Save SLPM registers
539 * - Set SLPM=0 for the IOs you want to switch and others to 1
540 * - Configure the GPIO registers for the IOs that are being switched
541 * - Set IOFORCE=1
542 * - Modify the AFLSA/B registers for the IOs that are being switched
543 * - Set IOFORCE=0
544 * - Restore SLPM registers
545 * - Any spurious wake up event during switch sequence to be ignored and
546 * cleared
547 */
548static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
549{
550 int i;
551
552 for (i = 0; i < NUM_BANKS; i++) {
553 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
554 unsigned int temp = slpm[i];
555
556 if (!chip)
557 break;
558
3c0227d2
RV
559 clk_enable(chip->clk);
560
01727e61
RV
561 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
562 writel(temp, chip->addr + NMK_GPIO_SLPC);
563 }
564}
565
566static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
567{
568 int i;
569
570 for (i = 0; i < NUM_BANKS; i++) {
571 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
572
573 if (!chip)
574 break;
575
576 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
3c0227d2
RV
577
578 clk_disable(chip->clk);
01727e61
RV
579 }
580}
581
0fafd50e 582static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
2249b19f
JNG
583{
584 int i;
585 u16 reg;
586 u8 bit;
587 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
588 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
589 const u16 *gpiocr_regs;
590
4ca075de
FB
591 if (!npct->prcm_base)
592 return NMK_GPIO_ALT_C;
593
2249b19f
JNG
594 for (i = 0; i < npct->soc->npins_altcx; i++) {
595 if (npct->soc->altcx_pins[i].pin == gpio)
596 break;
597 }
598 if (i == npct->soc->npins_altcx)
599 return NMK_GPIO_ALT_C;
600
601 pin_desc = npct->soc->altcx_pins + i;
602 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
603 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
604 if (pin_desc->altcx[i].used == true) {
605 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
606 bit = pin_desc->altcx[i].control_bit;
f1671bf5 607 if (readl(npct->prcm_base + reg) & BIT(bit))
2249b19f
JNG
608 return NMK_GPIO_ALT_C+i+1;
609 }
610 }
611 return NMK_GPIO_ALT_C;
612}
613
5e81e0a0 614static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
2ec1d359 615{
5e81e0a0 616 u32 afunc, bfunc;
2ec1d359 617
3c0227d2
RV
618 clk_enable(nmk_chip->clk);
619
5e81e0a0
LW
620 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
621 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
2ec1d359 622
3c0227d2
RV
623 clk_disable(nmk_chip->clk);
624
2ec1d359
AR
625 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
626}
2ec1d359
AR
627
628/* IRQ functions */
2ec1d359 629
f272c00e 630static void nmk_gpio_irq_ack(struct irq_data *d)
2ec1d359 631{
e0bc34a3 632 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
68ab0126 633 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
3c0227d2
RV
634
635 clk_enable(nmk_chip->clk);
5e81e0a0 636 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
3c0227d2 637 clk_disable(nmk_chip->clk);
2ec1d359
AR
638}
639
4d4e20f7
RV
640enum nmk_gpio_irq_type {
641 NORMAL,
642 WAKE,
643};
644
040e5ecd 645static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
5e81e0a0 646 int offset, enum nmk_gpio_irq_type which,
4d4e20f7 647 bool enable)
2ec1d359 648{
6c12fe88
RV
649 u32 *rimscval;
650 u32 *fimscval;
651 u32 rimscreg;
652 u32 fimscreg;
653
654 if (which == NORMAL) {
655 rimscreg = NMK_GPIO_RIMSC;
656 fimscreg = NMK_GPIO_FIMSC;
657 rimscval = &nmk_chip->rimsc;
658 fimscval = &nmk_chip->fimsc;
659 } else {
660 rimscreg = NMK_GPIO_RWIMSC;
661 fimscreg = NMK_GPIO_FWIMSC;
662 rimscval = &nmk_chip->rwimsc;
663 fimscval = &nmk_chip->fwimsc;
664 }
2ec1d359 665
040e5ecd 666 /* we must individually set/clear the two edges */
5e81e0a0 667 if (nmk_chip->edge_rising & BIT(offset)) {
040e5ecd 668 if (enable)
5e81e0a0 669 *rimscval |= BIT(offset);
040e5ecd 670 else
5e81e0a0 671 *rimscval &= ~BIT(offset);
6c12fe88 672 writel(*rimscval, nmk_chip->addr + rimscreg);
2ec1d359 673 }
5e81e0a0 674 if (nmk_chip->edge_falling & BIT(offset)) {
040e5ecd 675 if (enable)
5e81e0a0 676 *fimscval |= BIT(offset);
040e5ecd 677 else
5e81e0a0 678 *fimscval &= ~BIT(offset);
6c12fe88 679 writel(*fimscval, nmk_chip->addr + fimscreg);
2ec1d359 680 }
040e5ecd 681}
2ec1d359 682
b9df468d 683static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
5e81e0a0 684 int offset, bool on)
b9df468d 685{
b982ff0e
RV
686 /*
687 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
688 * disabled, since setting SLPM to 1 increases power consumption, and
689 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
690 */
691 if (nmk_chip->sleepmode && on) {
5e81e0a0 692 __nmk_gpio_set_slpm(nmk_chip, offset,
b982ff0e 693 NMK_GPIO_SLPM_WAKEUP_ENABLE);
33d78647
LW
694 }
695
5e81e0a0 696 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
b9df468d
RV
697}
698
699static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
2ec1d359 700{
2ec1d359
AR
701 struct nmk_gpio_chip *nmk_chip;
702 unsigned long flags;
2ec1d359 703
f272c00e 704 nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359 705 if (!nmk_chip)
4d4e20f7 706 return -EINVAL;
2ec1d359 707
3c0227d2 708 clk_enable(nmk_chip->clk);
b9df468d
RV
709 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
710 spin_lock(&nmk_chip->lock);
711
a60b57ed 712 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
b9df468d 713
5e81e0a0 714 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
a60b57ed 715 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
b9df468d
RV
716
717 spin_unlock(&nmk_chip->lock);
718 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
3c0227d2 719 clk_disable(nmk_chip->clk);
4d4e20f7
RV
720
721 return 0;
2ec1d359
AR
722}
723
f272c00e 724static void nmk_gpio_irq_mask(struct irq_data *d)
040e5ecd 725{
b9df468d 726 nmk_gpio_irq_maskunmask(d, false);
4d4e20f7 727}
040e5ecd 728
f272c00e 729static void nmk_gpio_irq_unmask(struct irq_data *d)
040e5ecd 730{
b9df468d 731 nmk_gpio_irq_maskunmask(d, true);
4d4e20f7
RV
732}
733
f272c00e 734static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
4d4e20f7 735{
7e3f7e59
RV
736 struct nmk_gpio_chip *nmk_chip;
737 unsigned long flags;
7e3f7e59 738
f272c00e 739 nmk_chip = irq_data_get_irq_chip_data(d);
7e3f7e59
RV
740 if (!nmk_chip)
741 return -EINVAL;
742
3c0227d2 743 clk_enable(nmk_chip->clk);
01727e61
RV
744 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
745 spin_lock(&nmk_chip->lock);
746
479a0c7e 747 if (irqd_irq_disabled(d))
a60b57ed 748 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
b9df468d
RV
749
750 if (on)
5e81e0a0 751 nmk_chip->real_wake |= BIT(d->hwirq);
b9df468d 752 else
5e81e0a0 753 nmk_chip->real_wake &= ~BIT(d->hwirq);
01727e61
RV
754
755 spin_unlock(&nmk_chip->lock);
756 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
3c0227d2 757 clk_disable(nmk_chip->clk);
7e3f7e59
RV
758
759 return 0;
040e5ecd
RV
760}
761
f272c00e 762static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
2ec1d359 763{
479a0c7e 764 bool enabled = !irqd_irq_disabled(d);
3c0227d2 765 bool wake = irqd_is_wakeup_set(d);
2ec1d359
AR
766 struct nmk_gpio_chip *nmk_chip;
767 unsigned long flags;
2ec1d359 768
f272c00e 769 nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359
AR
770 if (!nmk_chip)
771 return -EINVAL;
2ec1d359
AR
772 if (type & IRQ_TYPE_LEVEL_HIGH)
773 return -EINVAL;
774 if (type & IRQ_TYPE_LEVEL_LOW)
775 return -EINVAL;
776
3c0227d2 777 clk_enable(nmk_chip->clk);
2ec1d359
AR
778 spin_lock_irqsave(&nmk_chip->lock, flags);
779
7a852d80 780 if (enabled)
a60b57ed 781 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
4d4e20f7 782
b9df468d 783 if (enabled || wake)
a60b57ed 784 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
7a852d80 785
5e81e0a0 786 nmk_chip->edge_rising &= ~BIT(d->hwirq);
2ec1d359 787 if (type & IRQ_TYPE_EDGE_RISING)
5e81e0a0 788 nmk_chip->edge_rising |= BIT(d->hwirq);
2ec1d359 789
5e81e0a0 790 nmk_chip->edge_falling &= ~BIT(d->hwirq);
2ec1d359 791 if (type & IRQ_TYPE_EDGE_FALLING)
5e81e0a0 792 nmk_chip->edge_falling |= BIT(d->hwirq);
2ec1d359 793
7a852d80 794 if (enabled)
a60b57ed 795 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
4d4e20f7 796
b9df468d 797 if (enabled || wake)
a60b57ed 798 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
2ec1d359 799
7a852d80 800 spin_unlock_irqrestore(&nmk_chip->lock, flags);
3c0227d2 801 clk_disable(nmk_chip->clk);
2ec1d359
AR
802
803 return 0;
804}
805
3c0227d2
RV
806static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
807{
808 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359 809
3c0227d2
RV
810 clk_enable(nmk_chip->clk);
811 nmk_gpio_irq_unmask(d);
2ec1d359
AR
812 return 0;
813}
814
3c0227d2
RV
815static void nmk_gpio_irq_shutdown(struct irq_data *d)
816{
817 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
818
819 nmk_gpio_irq_mask(d);
820 clk_disable(nmk_chip->clk);
821}
822
5663bb27 823static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status)
2ec1d359 824{
5663bb27 825 struct irq_chip *host_chip = irq_desc_get_chip(desc);
e0bc34a3 826 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
2ec1d359 827
adfed159 828 chained_irq_enter(host_chip, desc);
aaedaa2b 829
33b744b3
RV
830 while (status) {
831 int bit = __ffs(status);
832
e0bc34a3 833 generic_handle_irq(irq_find_mapping(chip->irqdomain, bit));
33b744b3 834 status &= ~BIT(bit);
2ec1d359 835 }
aaedaa2b 836
adfed159 837 chained_irq_exit(host_chip, desc);
2ec1d359
AR
838}
839
bd0b9ac4 840static void nmk_gpio_irq_handler(struct irq_desc *desc)
33b744b3 841{
e0bc34a3 842 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
68ab0126 843 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
3c0227d2
RV
844 u32 status;
845
846 clk_enable(nmk_chip->clk);
847 status = readl(nmk_chip->addr + NMK_GPIO_IS);
848 clk_disable(nmk_chip->clk);
33b744b3 849
5663bb27 850 __nmk_gpio_irq_handler(desc, status);
33b744b3
RV
851}
852
bd0b9ac4 853static void nmk_gpio_latent_irq_handler(struct irq_desc *desc)
33b744b3 854{
e0bc34a3 855 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
68ab0126 856 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
194e15ba 857 u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
33b744b3 858
5663bb27 859 __nmk_gpio_irq_handler(desc, status);
33b744b3
RV
860}
861
2ec1d359 862/* I/O Functions */
dbfe8ca2 863
67668a57
LW
864static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
865{
866 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
867 int dir;
868
869 clk_enable(nmk_chip->clk);
870
871 dir = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
872
873 clk_disable(nmk_chip->clk);
874
875 return dir;
876}
877
2ec1d359
AR
878static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
879{
68ab0126 880 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
2ec1d359 881
3c0227d2
RV
882 clk_enable(nmk_chip->clk);
883
5e81e0a0 884 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
3c0227d2
RV
885
886 clk_disable(nmk_chip->clk);
887
2ec1d359
AR
888 return 0;
889}
890
2ec1d359
AR
891static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
892{
68ab0126 893 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
3c0227d2
RV
894 int value;
895
896 clk_enable(nmk_chip->clk);
2ec1d359 897
5e81e0a0 898 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
2ec1d359 899
3c0227d2
RV
900 clk_disable(nmk_chip->clk);
901
902 return value;
2ec1d359
AR
903}
904
905static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
906 int val)
907{
68ab0126 908 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
2ec1d359 909
3c0227d2
RV
910 clk_enable(nmk_chip->clk);
911
6720db7c 912 __nmk_gpio_set_output(nmk_chip, offset, val);
3c0227d2
RV
913
914 clk_disable(nmk_chip->clk);
2ec1d359
AR
915}
916
6647c6c0
RV
917static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
918 int val)
919{
68ab0126 920 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
6647c6c0 921
3c0227d2
RV
922 clk_enable(nmk_chip->clk);
923
6720db7c 924 __nmk_gpio_make_output(nmk_chip, offset, val);
6647c6c0 925
3c0227d2
RV
926 clk_disable(nmk_chip->clk);
927
6647c6c0
RV
928 return 0;
929}
930
d0b543c7
RV
931#ifdef CONFIG_DEBUG_FS
932
933#include <linux/seq_file.h>
934
2249b19f
JNG
935static void nmk_gpio_dbg_show_one(struct seq_file *s,
936 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
937 unsigned offset, unsigned gpio)
d0b543c7 938{
6f4350a6 939 const char *label = gpiochip_is_requested(chip, offset);
68ab0126 940 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
6f4350a6
LW
941 int mode;
942 bool is_out;
8f1774a2 943 bool data_out;
6f4350a6 944 bool pull;
d0b543c7
RV
945 const char *modes[] = {
946 [NMK_GPIO_ALT_GPIO] = "gpio",
947 [NMK_GPIO_ALT_A] = "altA",
948 [NMK_GPIO_ALT_B] = "altB",
949 [NMK_GPIO_ALT_C] = "altC",
2249b19f
JNG
950 [NMK_GPIO_ALT_C+1] = "altC1",
951 [NMK_GPIO_ALT_C+2] = "altC2",
952 [NMK_GPIO_ALT_C+3] = "altC3",
953 [NMK_GPIO_ALT_C+4] = "altC4",
d0b543c7 954 };
8f1774a2
LW
955 const char *pulls[] = {
956 "none ",
957 "pull down",
958 "pull up ",
959 };
d0b543c7 960
3c0227d2 961 clk_enable(nmk_chip->clk);
5e81e0a0
LW
962 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
963 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
964 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
965 mode = nmk_gpio_get_mode(nmk_chip, offset);
2249b19f
JNG
966 if ((mode == NMK_GPIO_ALT_C) && pctldev)
967 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
6f4350a6 968
8f1774a2
LW
969 if (is_out) {
970 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
971 gpio,
972 label ?: "(none)",
973 data_out ? "hi" : "lo",
974 (mode < 0) ? "unknown" : modes[mode]);
975 } else {
4705845b 976 int irq = gpio_to_irq(gpio);
6f4350a6 977 struct irq_desc *desc = irq_to_desc(irq);
8f1774a2 978 int pullidx = 0;
d7f005e8 979 int val;
8f1774a2
LW
980
981 if (pull)
982 pullidx = data_out ? 1 : 2;
983
984 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
985 gpio,
986 label ?: "(none)",
987 pulls[pullidx],
988 (mode < 0) ? "unknown" : modes[mode]);
d7f005e8
LW
989
990 val = nmk_gpio_get_input(chip, offset);
991 seq_printf(s, " VAL %d", val);
992
8f1774a2
LW
993 /*
994 * This races with request_irq(), set_irq_type(),
6f4350a6
LW
995 * and set_irq_wake() ... but those are "rare".
996 */
4705845b 997 if (irq > 0 && desc && desc->action) {
6f4350a6 998 char *trigger;
6f4350a6 999
5e81e0a0 1000 if (nmk_chip->edge_rising & BIT(offset))
6f4350a6 1001 trigger = "edge-rising";
5e81e0a0 1002 else if (nmk_chip->edge_falling & BIT(offset))
6f4350a6
LW
1003 trigger = "edge-falling";
1004 else
1005 trigger = "edge-undefined";
1006
1007 seq_printf(s, " irq-%d %s%s",
1008 irq, trigger,
1009 irqd_is_wakeup_set(&desc->irq_data)
1010 ? " wakeup" : "");
8ea72a30 1011 }
6f4350a6
LW
1012 }
1013 clk_disable(nmk_chip->clk);
1014}
1015
1016static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1017{
1018 unsigned i;
1019 unsigned gpio = chip->base;
8ea72a30 1020
6f4350a6 1021 for (i = 0; i < chip->ngpio; i++, gpio++) {
2249b19f 1022 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
d0b543c7
RV
1023 seq_printf(s, "\n");
1024 }
1025}
1026
1027#else
6f4350a6 1028static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
2249b19f 1029 struct pinctrl_dev *pctldev,
6f4350a6
LW
1030 struct gpio_chip *chip,
1031 unsigned offset, unsigned gpio)
1032{
1033}
d0b543c7
RV
1034#define nmk_gpio_dbg_show NULL
1035#endif
1036
3c0227d2
RV
1037void nmk_gpio_clocks_enable(void)
1038{
1039 int i;
1040
1041 for (i = 0; i < NUM_BANKS; i++) {
1042 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1043
1044 if (!chip)
1045 continue;
1046
1047 clk_enable(chip->clk);
1048 }
1049}
1050
1051void nmk_gpio_clocks_disable(void)
1052{
1053 int i;
1054
1055 for (i = 0; i < NUM_BANKS; i++) {
1056 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1057
1058 if (!chip)
1059 continue;
1060
1061 clk_disable(chip->clk);
1062 }
1063}
1064
b9df468d
RV
1065/*
1066 * Called from the suspend/resume path to only keep the real wakeup interrupts
1067 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1068 * and not the rest of the interrupts which we needed to have as wakeups for
1069 * cpuidle.
1070 *
1071 * PM ops are not used since this needs to be done at the end, after all the
1072 * other drivers are done with their suspend callbacks.
1073 */
1074void nmk_gpio_wakeups_suspend(void)
1075{
1076 int i;
1077
1078 for (i = 0; i < NUM_BANKS; i++) {
1079 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1080
1081 if (!chip)
1082 break;
1083
3c0227d2
RV
1084 clk_enable(chip->clk);
1085
b9df468d
RV
1086 writel(chip->rwimsc & chip->real_wake,
1087 chip->addr + NMK_GPIO_RWIMSC);
1088 writel(chip->fwimsc & chip->real_wake,
1089 chip->addr + NMK_GPIO_FWIMSC);
1090
3c0227d2 1091 clk_disable(chip->clk);
b9df468d
RV
1092 }
1093}
1094
1095void nmk_gpio_wakeups_resume(void)
1096{
1097 int i;
1098
1099 for (i = 0; i < NUM_BANKS; i++) {
1100 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1101
1102 if (!chip)
1103 break;
1104
3c0227d2
RV
1105 clk_enable(chip->clk);
1106
b9df468d
RV
1107 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1108 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1109
3c0227d2 1110 clk_disable(chip->clk);
b9df468d
RV
1111 }
1112}
1113
bc6f5cf6
RA
1114/*
1115 * Read the pull up/pull down status.
1116 * A bit set in 'pull_up' means that pull up
1117 * is selected if pull is enabled in PDIS register.
1118 * Note: only pull up/down set via this driver can
1119 * be detected due to HW limitations.
1120 */
1121void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1122{
1123 if (gpio_bank < NUM_BANKS) {
1124 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1125
1126 if (!chip)
1127 return;
1128
1129 *pull_up = chip->pull_up;
1130 }
1131}
1132
bc222ef4
LW
1133/*
1134 * We will allocate memory for the state container using devm* allocators
1135 * binding to the first device reaching this point, it doesn't matter if
1136 * it is the pin controller or GPIO driver. However we need to use the right
1137 * platform device when looking up resources so pay attention to pdev.
1138 */
1139static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1140 struct platform_device *pdev)
1141{
1142 struct nmk_gpio_chip *nmk_chip;
1143 struct platform_device *gpio_pdev;
1144 struct gpio_chip *chip;
1145 struct resource *res;
1146 struct clk *clk;
1147 void __iomem *base;
1148 u32 id;
1149
1150 gpio_pdev = of_find_device_by_node(np);
1151 if (!gpio_pdev) {
1152 pr_err("populate \"%s\": device not found\n", np->name);
1153 return ERR_PTR(-ENODEV);
1154 }
1155 if (of_property_read_u32(np, "gpio-bank", &id)) {
1156 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1157 return ERR_PTR(-EINVAL);
1158 }
1159
1160 /* Already populated? */
1161 nmk_chip = nmk_gpio_chips[id];
1162 if (nmk_chip)
1163 return nmk_chip;
1164
1165 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1166 if (!nmk_chip)
1167 return ERR_PTR(-ENOMEM);
1168
1169 nmk_chip->bank = id;
1170 chip = &nmk_chip->chip;
1171 chip->base = id * NMK_GPIO_PER_CHIP;
1172 chip->ngpio = NMK_GPIO_PER_CHIP;
1173 chip->label = dev_name(&gpio_pdev->dev);
58383c78 1174 chip->parent = &gpio_pdev->dev;
bc222ef4
LW
1175
1176 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1177 base = devm_ioremap_resource(&pdev->dev, res);
1178 if (IS_ERR(base))
1179 return base;
1180 nmk_chip->addr = base;
1181
1182 clk = clk_get(&gpio_pdev->dev, NULL);
1183 if (IS_ERR(clk))
1184 return (void *) clk;
1185 clk_prepare(clk);
1186 nmk_chip->clk = clk;
1187
1188 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1189 nmk_gpio_chips[id] = nmk_chip;
1190 return nmk_chip;
1191}
1192
150632b0 1193static int nmk_gpio_probe(struct platform_device *dev)
2ec1d359 1194{
513c27f8 1195 struct device_node *np = dev->dev.of_node;
2ec1d359
AR
1196 struct nmk_gpio_chip *nmk_chip;
1197 struct gpio_chip *chip;
3007d941 1198 struct irq_chip *irqchip;
194e15ba 1199 int latent_irq;
8f18bcfc 1200 bool supports_sleepmode;
3e3c62ca 1201 int irq;
2ec1d359
AR
1202 int ret;
1203
bc222ef4
LW
1204 nmk_chip = nmk_gpio_populate_chip(np, dev);
1205 if (IS_ERR(nmk_chip)) {
1206 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1207 return PTR_ERR(nmk_chip);
1208 }
1209
f4b3f523 1210 if (of_get_property(np, "st,supports-sleepmode", NULL))
8f18bcfc
LW
1211 supports_sleepmode = true;
1212 else
1213 supports_sleepmode = false;
513c27f8 1214
bc222ef4
LW
1215 /* Correct platform device ID */
1216 dev->id = nmk_chip->bank;
3e3c62ca 1217
3e3c62ca 1218 irq = platform_get_irq(dev, 0);
50f690d8
LW
1219 if (irq < 0)
1220 return irq;
3e3c62ca 1221
8f18bcfc 1222 /* It's OK for this IRQ not to be present */
194e15ba 1223 latent_irq = platform_get_irq(dev, 1);
33b744b3 1224
2ec1d359
AR
1225 /*
1226 * The virt address in nmk_chip->addr is in the nomadik register space,
1227 * so we can simply convert the resource address, without remapping
1228 */
3e3c62ca 1229 nmk_chip->parent_irq = irq;
194e15ba 1230 nmk_chip->latent_parent_irq = latent_irq;
8f18bcfc 1231 nmk_chip->sleepmode = supports_sleepmode;
c0fcb8db 1232 spin_lock_init(&nmk_chip->lock);
2ec1d359
AR
1233
1234 chip = &nmk_chip->chip;
98c85d58
JG
1235 chip->request = gpiochip_generic_request;
1236 chip->free = gpiochip_generic_free;
67668a57 1237 chip->get_direction = nmk_gpio_get_dir;
3007d941
LW
1238 chip->direction_input = nmk_gpio_make_input;
1239 chip->get = nmk_gpio_get_input;
1240 chip->direction_output = nmk_gpio_make_output;
1241 chip->set = nmk_gpio_set_output;
1242 chip->dbg_show = nmk_gpio_dbg_show;
1243 chip->can_sleep = false;
2ec1d359
AR
1244 chip->owner = THIS_MODULE;
1245
3007d941
LW
1246 irqchip = &nmk_chip->irqchip;
1247 irqchip->irq_ack = nmk_gpio_irq_ack;
1248 irqchip->irq_mask = nmk_gpio_irq_mask;
1249 irqchip->irq_unmask = nmk_gpio_irq_unmask;
1250 irqchip->irq_set_type = nmk_gpio_irq_set_type;
1251 irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
1252 irqchip->irq_startup = nmk_gpio_irq_startup;
1253 irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
1254 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
1255 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
1256 dev->id,
1257 chip->base,
1258 chip->base + chip->ngpio - 1);
1259
ebc6178d
RV
1260 clk_enable(nmk_chip->clk);
1261 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1262 clk_disable(nmk_chip->clk);
513c27f8
LJ
1263 chip->of_node = np;
1264
68ab0126 1265 ret = gpiochip_add_data(chip, nmk_chip);
2ec1d359 1266 if (ret)
50f690d8 1267 return ret;
2ec1d359 1268
3e3c62ca 1269 platform_set_drvdata(dev, nmk_chip);
2ec1d359 1270
e0bc34a3
LW
1271 /*
1272 * Let the generic code handle this edge IRQ, the the chained
1273 * handler will perform the actual work of handling the parent
1274 * interrupt.
1275 */
3007d941
LW
1276 ret = gpiochip_irqchip_add(chip,
1277 irqchip,
e0bc34a3
LW
1278 0,
1279 handle_edge_irq,
1280 IRQ_TYPE_EDGE_FALLING);
1281 if (ret) {
1282 dev_err(&dev->dev, "could not add irqchip\n");
2fcea6ce 1283 gpiochip_remove(&nmk_chip->chip);
e0bc34a3 1284 return -ENODEV;
a60b57ed 1285 }
e0bc34a3 1286 /* Then register the chain on the parent IRQ */
3007d941
LW
1287 gpiochip_set_chained_irqchip(chip,
1288 irqchip,
e0bc34a3
LW
1289 nmk_chip->parent_irq,
1290 nmk_gpio_irq_handler);
1291 if (nmk_chip->latent_parent_irq > 0)
3007d941
LW
1292 gpiochip_set_chained_irqchip(chip,
1293 irqchip,
e0bc34a3
LW
1294 nmk_chip->latent_parent_irq,
1295 nmk_gpio_latent_irq_handler);
2ec1d359 1296
513c27f8
LJ
1297 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1298
2ec1d359 1299 return 0;
2ec1d359
AR
1300}
1301
e98ea774
LW
1302static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1303{
1304 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1305
1306 return npct->soc->ngroups;
1307}
1308
1309static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1310 unsigned selector)
1311{
1312 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1313
1314 return npct->soc->groups[selector].name;
1315}
1316
1317static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1318 const unsigned **pins,
1319 unsigned *num_pins)
1320{
1321 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1322
1323 *pins = npct->soc->groups[selector].pins;
1324 *num_pins = npct->soc->groups[selector].npins;
1325 return 0;
1326}
1327
6ca7d2e3 1328static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
24cbdd75 1329{
24cbdd75 1330 int i;
6ca7d2e3 1331 struct nmk_gpio_chip *nmk_gpio;
24cbdd75 1332
6ca7d2e3
LW
1333 for(i = 0; i < NMK_MAX_BANKS; i++) {
1334 nmk_gpio = nmk_gpio_chips[i];
1335 if (!nmk_gpio)
1336 continue;
1337 if (pin >= nmk_gpio->chip.base &&
1338 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1339 return nmk_gpio;
24cbdd75
LW
1340 }
1341 return NULL;
1342}
1343
6ca7d2e3
LW
1344static struct gpio_chip *find_gc_from_pin(unsigned pin)
1345{
1346 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1347
1348 if (nmk_gpio)
1349 return &nmk_gpio->chip;
1350 return NULL;
1351}
1352
e98ea774
LW
1353static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1354 unsigned offset)
1355{
6ca7d2e3 1356 struct gpio_chip *chip = find_gc_from_pin(offset);
24cbdd75 1357
6ca7d2e3 1358 if (!chip) {
24cbdd75
LW
1359 seq_printf(s, "invalid pin offset");
1360 return;
1361 }
2249b19f 1362 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
e98ea774
LW
1363}
1364
e32af889
GF
1365static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1366 unsigned *num_maps, const char *group,
1367 const char *function)
1368{
1369 if (*num_maps == *reserved_maps)
1370 return -ENOSPC;
1371
1372 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1373 (*map)[*num_maps].data.mux.group = group;
1374 (*map)[*num_maps].data.mux.function = function;
1375 (*num_maps)++;
1376
1377 return 0;
1378}
1379
1380static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1381 unsigned *reserved_maps,
1382 unsigned *num_maps, const char *group,
1383 unsigned long *configs, unsigned num_configs)
1384{
1385 unsigned long *dup_configs;
1386
1387 if (*num_maps == *reserved_maps)
1388 return -ENOSPC;
1389
1390 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1391 GFP_KERNEL);
1392 if (!dup_configs)
1393 return -ENOMEM;
1394
1395 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1396
1397 (*map)[*num_maps].data.configs.group_or_pin = group;
1398 (*map)[*num_maps].data.configs.configs = dup_configs;
1399 (*map)[*num_maps].data.configs.num_configs = num_configs;
1400 (*num_maps)++;
1401
1402 return 0;
1403}
1404
87ff934a
SK
1405#define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1406#define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
e32af889
GF
1407 .size = ARRAY_SIZE(y), }
1408
1409static const unsigned long nmk_pin_input_modes[] = {
1410 PIN_INPUT_NOPULL,
1411 PIN_INPUT_PULLUP,
1412 PIN_INPUT_PULLDOWN,
1413};
1414
1415static const unsigned long nmk_pin_output_modes[] = {
1416 PIN_OUTPUT_LOW,
1417 PIN_OUTPUT_HIGH,
1418 PIN_DIR_OUTPUT,
1419};
1420
1421static const unsigned long nmk_pin_sleep_modes[] = {
1422 PIN_SLEEPMODE_DISABLED,
1423 PIN_SLEEPMODE_ENABLED,
1424};
1425
1426static const unsigned long nmk_pin_sleep_input_modes[] = {
1427 PIN_SLPM_INPUT_NOPULL,
1428 PIN_SLPM_INPUT_PULLUP,
1429 PIN_SLPM_INPUT_PULLDOWN,
1430 PIN_SLPM_DIR_INPUT,
1431};
1432
1433static const unsigned long nmk_pin_sleep_output_modes[] = {
1434 PIN_SLPM_OUTPUT_LOW,
1435 PIN_SLPM_OUTPUT_HIGH,
1436 PIN_SLPM_DIR_OUTPUT,
1437};
1438
1439static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1440 PIN_SLPM_WAKEUP_DISABLE,
1441 PIN_SLPM_WAKEUP_ENABLE,
1442};
1443
1444static const unsigned long nmk_pin_gpio_modes[] = {
1445 PIN_GPIOMODE_DISABLED,
1446 PIN_GPIOMODE_ENABLED,
1447};
1448
1449static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1450 PIN_SLPM_PDIS_DISABLED,
1451 PIN_SLPM_PDIS_ENABLED,
1452};
1453
1454struct nmk_cfg_param {
1455 const char *property;
1456 unsigned long config;
1457 const unsigned long *choice;
1458 int size;
1459};
1460
1461static const struct nmk_cfg_param nmk_cfg_params[] = {
1462 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1463 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1464 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1465 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1466 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1467 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1468 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1469 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1470};
1471
1472static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1473{
1474 int ret = 0;
1475
1476 if (nmk_cfg_params[index].choice == NULL)
1477 *config = nmk_cfg_params[index].config;
1478 else {
1479 /* test if out of range */
1480 if (val < nmk_cfg_params[index].size) {
1481 *config = nmk_cfg_params[index].config |
1482 nmk_cfg_params[index].choice[val];
1483 }
1484 }
1485 return ret;
1486}
1487
1488static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1489{
1490 int i, pin_number;
1491 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1492
1493 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1494 for (i = 0; i < npct->soc->npins; i++)
1495 if (npct->soc->pins[i].number == pin_number)
1496 return npct->soc->pins[i].name;
1497 return NULL;
1498}
1499
1500static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1501 unsigned long *configs)
1502{
1503 bool has_config = 0;
1504 unsigned long cfg = 0;
1505 int i, val, ret;
1506
1507 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1508 ret = of_property_read_u32(np,
1509 nmk_cfg_params[i].property, &val);
1510 if (ret != -EINVAL) {
1511 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1512 *configs |= cfg;
1513 has_config = 1;
1514 }
1515 }
1516 }
1517
1518 return has_config;
1519}
1520
2230a36e 1521static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
e32af889
GF
1522 struct device_node *np,
1523 struct pinctrl_map **map,
1524 unsigned *reserved_maps,
1525 unsigned *num_maps)
1526{
1527 int ret;
1528 const char *function = NULL;
1529 unsigned long configs = 0;
1530 bool has_config = 0;
e32af889 1531 struct property *prop;
e32af889
GF
1532 struct device_node *np_config;
1533
68d41f23 1534 ret = of_property_read_string(np, "function", &function);
c2f6d059 1535 if (ret >= 0) {
68d41f23
LW
1536 const char *group;
1537
1538 ret = of_property_count_strings(np, "groups");
c2f6d059
LW
1539 if (ret < 0)
1540 goto exit;
1541
1542 ret = pinctrl_utils_reserve_map(pctldev, map,
1543 reserved_maps,
1544 num_maps, ret);
1545 if (ret < 0)
1546 goto exit;
1547
68d41f23 1548 of_property_for_each_string(np, "groups", prop, group) {
e32af889
GF
1549 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1550 group, function);
1551 if (ret < 0)
1552 goto exit;
1553 }
c2f6d059
LW
1554 }
1555
1556 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1557 np_config = of_parse_phandle(np, "ste,config", 0);
1558 if (np_config)
1559 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1560 if (has_config) {
68d41f23
LW
1561 const char *gpio_name;
1562 const char *pin;
1563
1637d480 1564 ret = of_property_count_strings(np, "pins");
c2f6d059
LW
1565 if (ret < 0)
1566 goto exit;
1567 ret = pinctrl_utils_reserve_map(pctldev, map,
1568 reserved_maps,
1569 num_maps, ret);
1570 if (ret < 0)
1571 goto exit;
1572
1637d480 1573 of_property_for_each_string(np, "pins", prop, pin) {
68d41f23 1574 gpio_name = nmk_find_pin_name(pctldev, pin);
e32af889 1575
c2f6d059
LW
1576 ret = nmk_dt_add_map_configs(map, reserved_maps,
1577 num_maps,
1578 gpio_name, &configs, 1);
e32af889
GF
1579 if (ret < 0)
1580 goto exit;
1581 }
e32af889 1582 }
c2f6d059 1583
e32af889
GF
1584exit:
1585 return ret;
1586}
1587
2230a36e 1588static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
e32af889
GF
1589 struct device_node *np_config,
1590 struct pinctrl_map **map, unsigned *num_maps)
1591{
1592 unsigned reserved_maps;
1593 struct device_node *np;
1594 int ret;
1595
1596 reserved_maps = 0;
1597 *map = NULL;
1598 *num_maps = 0;
1599
1600 for_each_child_of_node(np_config, np) {
1601 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1602 &reserved_maps, num_maps);
1603 if (ret < 0) {
d32f7fd3 1604 pinctrl_utils_free_map(pctldev, *map, *num_maps);
e32af889
GF
1605 return ret;
1606 }
1607 }
1608
1609 return 0;
1610}
1611
022ab148 1612static const struct pinctrl_ops nmk_pinctrl_ops = {
e98ea774
LW
1613 .get_groups_count = nmk_get_groups_cnt,
1614 .get_group_name = nmk_get_group_name,
1615 .get_group_pins = nmk_get_group_pins,
1616 .pin_dbg_show = nmk_pin_dbg_show,
e32af889 1617 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
d32f7fd3 1618 .dt_free_map = pinctrl_utils_free_map,
e98ea774
LW
1619};
1620
dbfe8ca2
LW
1621static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1622{
1623 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1624
1625 return npct->soc->nfunctions;
1626}
1627
1628static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1629 unsigned function)
1630{
1631 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1632
1633 return npct->soc->functions[function].name;
1634}
1635
1636static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1637 unsigned function,
1638 const char * const **groups,
1639 unsigned * const num_groups)
1640{
1641 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1642
1643 *groups = npct->soc->functions[function].groups;
1644 *num_groups = npct->soc->functions[function].ngroups;
1645
1646 return 0;
1647}
1648
03e9f0ca
LW
1649static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1650 unsigned group)
dbfe8ca2
LW
1651{
1652 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1653 const struct nmk_pingroup *g;
1654 static unsigned int slpm[NUM_BANKS];
f84b4171 1655 unsigned long flags = 0;
dbfe8ca2
LW
1656 bool glitch;
1657 int ret = -EINVAL;
1658 int i;
1659
1660 g = &npct->soc->groups[group];
1661
1662 if (g->altsetting < 0)
1663 return -EINVAL;
1664
1665 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1666
daf73174
LW
1667 /*
1668 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1669 * we may pass through an undesired state. In this case we take
1670 * some extra care.
1671 *
1672 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1673 * - Save SLPM registers (since we have a shadow register in the
1674 * nmk_chip we're using that as backup)
1675 * - Set SLPM=0 for the IOs you want to switch and others to 1
1676 * - Configure the GPIO registers for the IOs that are being switched
1677 * - Set IOFORCE=1
1678 * - Modify the AFLSA/B registers for the IOs that are being switched
1679 * - Set IOFORCE=0
1680 * - Restore SLPM registers
1681 * - Any spurious wake up event during switch sequence to be ignored
1682 * and cleared
1683 *
1684 * We REALLY need to save ALL slpm registers, because the external
1685 * IOFORCE will switch *all* ports to their sleepmode setting to as
1686 * to avoid glitches. (Not just one port!)
1687 */
c22df08c 1688 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
dbfe8ca2
LW
1689
1690 if (glitch) {
1691 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1692
1693 /* Initially don't put any pins to sleep when switching */
1694 memset(slpm, 0xff, sizeof(slpm));
1695
1696 /*
1697 * Then mask the pins that need to be sleeping now when we're
1698 * switching to the ALT C function.
1699 */
1700 for (i = 0; i < g->npins; i++)
1701 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1702 nmk_gpio_glitch_slpm_init(slpm);
1703 }
1704
1705 for (i = 0; i < g->npins; i++) {
dbfe8ca2 1706 struct nmk_gpio_chip *nmk_chip;
dbfe8ca2
LW
1707 unsigned bit;
1708
6ca7d2e3
LW
1709 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
1710 if (!nmk_chip) {
dbfe8ca2
LW
1711 dev_err(npct->dev,
1712 "invalid pin offset %d in group %s at index %d\n",
1713 g->pins[i], g->name, i);
1714 goto out_glitch;
1715 }
dbfe8ca2
LW
1716 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1717
1718 clk_enable(nmk_chip->clk);
1719 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1720 /*
1721 * If the pin is switching to altfunc, and there was an
1722 * interrupt installed on it which has been lazy disabled,
1723 * actually mask the interrupt to prevent spurious interrupts
1724 * that would occur while the pin is under control of the
1725 * peripheral. Only SKE does this.
1726 */
1727 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1728
c22df08c
JNG
1729 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1730 (g->altsetting & NMK_GPIO_ALT_C), glitch);
dbfe8ca2 1731 clk_disable(nmk_chip->clk);
c22df08c
JNG
1732
1733 /*
1734 * Call PRCM GPIOCR config function in case ALTC
1735 * has been selected:
1736 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1737 * must be set.
1738 * - If selection is pure ALTC and previous selection was ALTCx,
1739 * then some bits in PRCM GPIOCR registers must be cleared.
1740 */
1741 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1742 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1743 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
dbfe8ca2
LW
1744 }
1745
1746 /* When all pins are successfully reconfigured we get here */
1747 ret = 0;
1748
1749out_glitch:
1750 if (glitch) {
1751 nmk_gpio_glitch_slpm_restore(slpm);
1752 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1753 }
1754
1755 return ret;
1756}
1757
5212d096
AL
1758static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1759 struct pinctrl_gpio_range *range,
1760 unsigned offset)
dbfe8ca2
LW
1761{
1762 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1763 struct nmk_gpio_chip *nmk_chip;
1764 struct gpio_chip *chip;
1765 unsigned bit;
1766
1767 if (!range) {
1768 dev_err(npct->dev, "invalid range\n");
1769 return -EINVAL;
1770 }
1771 if (!range->gc) {
1772 dev_err(npct->dev, "missing GPIO chip in range\n");
1773 return -EINVAL;
1774 }
1775 chip = range->gc;
68ab0126 1776 nmk_chip = gpiochip_get_data(chip);
dbfe8ca2
LW
1777
1778 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1779
1780 clk_enable(nmk_chip->clk);
1781 bit = offset % NMK_GPIO_PER_CHIP;
1782 /* There is no glitch when converting any pin to GPIO */
1783 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1784 clk_disable(nmk_chip->clk);
1785
1786 return 0;
1787}
1788
5212d096
AL
1789static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1790 struct pinctrl_gpio_range *range,
1791 unsigned offset)
dbfe8ca2
LW
1792{
1793 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1794
1795 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1796 /* Set the pin to some default state, GPIO is usually default */
1797}
1798
022ab148 1799static const struct pinmux_ops nmk_pinmux_ops = {
dbfe8ca2
LW
1800 .get_functions_count = nmk_pmx_get_funcs_cnt,
1801 .get_function_name = nmk_pmx_get_func_name,
1802 .get_function_groups = nmk_pmx_get_func_groups,
03e9f0ca 1803 .set_mux = nmk_pmx_set,
dbfe8ca2
LW
1804 .gpio_request_enable = nmk_gpio_request_enable,
1805 .gpio_disable_free = nmk_gpio_disable_free,
a21763a0 1806 .strict = true,
dbfe8ca2
LW
1807};
1808
5212d096
AL
1809static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1810 unsigned long *config)
d41af627
LW
1811{
1812 /* Not implemented */
1813 return -EINVAL;
1814}
1815
5212d096 1816static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
03b054e9 1817 unsigned long *configs, unsigned num_configs)
d41af627
LW
1818{
1819 static const char *pullnames[] = {
1820 [NMK_GPIO_PULL_NONE] = "none",
1821 [NMK_GPIO_PULL_UP] = "up",
1822 [NMK_GPIO_PULL_DOWN] = "down",
1823 [3] /* illegal */ = "??"
1824 };
1825 static const char *slpmnames[] = {
1826 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1827 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1828 };
1829 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1830 struct nmk_gpio_chip *nmk_chip;
d41af627 1831 unsigned bit;
03b054e9
SY
1832 pin_cfg_t cfg;
1833 int pull, slpm, output, val, i;
1834 bool lowemi, gpiomode, sleep;
d41af627 1835
6ca7d2e3
LW
1836 nmk_chip = find_nmk_gpio_from_pin(pin);
1837 if (!nmk_chip) {
1838 dev_err(npct->dev,
1839 "invalid pin offset %d\n", pin);
d41af627
LW
1840 return -EINVAL;
1841 }
d41af627 1842
03b054e9 1843 for (i = 0; i < num_configs; i++) {
d41af627 1844 /*
03b054e9
SY
1845 * The pin config contains pin number and altfunction fields,
1846 * here we just ignore that part. It's being handled by the
1847 * framework and pinmux callback respectively.
d41af627 1848 */
03b054e9
SY
1849 cfg = (pin_cfg_t) configs[i];
1850 pull = PIN_PULL(cfg);
1851 slpm = PIN_SLPM(cfg);
1852 output = PIN_DIR(cfg);
1853 val = PIN_VAL(cfg);
1854 lowemi = PIN_LOWEMI(cfg);
1855 gpiomode = PIN_GPIOMODE(cfg);
1856 sleep = PIN_SLEEPMODE(cfg);
1857
1858 if (sleep) {
1859 int slpm_pull = PIN_SLPM_PULL(cfg);
1860 int slpm_output = PIN_SLPM_DIR(cfg);
1861 int slpm_val = PIN_SLPM_VAL(cfg);
1862
1863 /* All pins go into GPIO mode at sleep */
1864 gpiomode = true;
1865
1866 /*
1867 * The SLPM_* values are normal values + 1 to allow zero
1868 * to mean "same as normal".
1869 */
1870 if (slpm_pull)
1871 pull = slpm_pull - 1;
1872 if (slpm_output)
1873 output = slpm_output - 1;
1874 if (slpm_val)
1875 val = slpm_val - 1;
1876
58383c78 1877 dev_dbg(nmk_chip->chip.parent,
03b054e9
SY
1878 "pin %d: sleep pull %s, dir %s, val %s\n",
1879 pin,
1880 slpm_pull ? pullnames[pull] : "same",
1881 slpm_output ? (output ? "output" : "input")
1882 : "same",
1883 slpm_val ? (val ? "high" : "low") : "same");
1884 }
d41af627 1885
58383c78 1886 dev_dbg(nmk_chip->chip.parent,
03b054e9
SY
1887 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1888 pin, cfg, pullnames[pull], slpmnames[slpm],
1889 output ? "output " : "input",
1890 output ? (val ? "high" : "low") : "",
1891 lowemi ? "on" : "off");
d41af627 1892
03b054e9
SY
1893 clk_enable(nmk_chip->clk);
1894 bit = pin % NMK_GPIO_PER_CHIP;
1895 if (gpiomode)
1896 /* No glitch when going to GPIO mode */
1897 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1898 if (output)
1899 __nmk_gpio_make_output(nmk_chip, bit, val);
1900 else {
1901 __nmk_gpio_make_input(nmk_chip, bit);
1902 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1903 }
1904 /* TODO: isn't this only applicable on output pins? */
1905 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1906
1907 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1908 clk_disable(nmk_chip->clk);
1909 } /* for each config */
d41af627 1910
d41af627
LW
1911 return 0;
1912}
1913
022ab148 1914static const struct pinconf_ops nmk_pinconf_ops = {
d41af627
LW
1915 .pin_config_get = nmk_pin_config_get,
1916 .pin_config_set = nmk_pin_config_set,
1917};
1918
e98ea774
LW
1919static struct pinctrl_desc nmk_pinctrl_desc = {
1920 .name = "pinctrl-nomadik",
1921 .pctlops = &nmk_pinctrl_ops,
dbfe8ca2 1922 .pmxops = &nmk_pinmux_ops,
d41af627 1923 .confops = &nmk_pinconf_ops,
e98ea774
LW
1924 .owner = THIS_MODULE,
1925};
1926
855f80cd 1927static const struct of_device_id nmk_pinctrl_match[] = {
6010d403 1928 {
3fd765a9 1929 .compatible = "stericsson,stn8815-pinctrl",
6010d403
LW
1930 .data = (void *)PINCTRL_NMK_STN8815,
1931 },
855f80cd 1932 {
6b09a834 1933 .compatible = "stericsson,db8500-pinctrl",
855f80cd
LJ
1934 .data = (void *)PINCTRL_NMK_DB8500,
1935 },
356d3e45 1936 {
6b09a834 1937 .compatible = "stericsson,db8540-pinctrl",
356d3e45
GF
1938 .data = (void *)PINCTRL_NMK_DB8540,
1939 },
855f80cd
LJ
1940 {},
1941};
1942
131d85bc 1943#ifdef CONFIG_PM_SLEEP
c003eed7 1944static int nmk_pinctrl_suspend(struct device *dev)
8d99b32d
JD
1945{
1946 struct nmk_pinctrl *npct;
1947
c003eed7 1948 npct = dev_get_drvdata(dev);
8d99b32d
JD
1949 if (!npct)
1950 return -EINVAL;
1951
1952 return pinctrl_force_sleep(npct->pctl);
1953}
1954
c003eed7 1955static int nmk_pinctrl_resume(struct device *dev)
8d99b32d
JD
1956{
1957 struct nmk_pinctrl *npct;
1958
c003eed7 1959 npct = dev_get_drvdata(dev);
8d99b32d
JD
1960 if (!npct)
1961 return -EINVAL;
1962
1963 return pinctrl_force_default(npct->pctl);
1964}
131d85bc 1965#endif
8d99b32d 1966
150632b0 1967static int nmk_pinctrl_probe(struct platform_device *pdev)
e98ea774 1968{
f4b3f523 1969 const struct of_device_id *match;
855f80cd 1970 struct device_node *np = pdev->dev.of_node;
32e67eee 1971 struct device_node *prcm_np;
e98ea774 1972 struct nmk_pinctrl *npct;
855f80cd 1973 unsigned int version = 0;
e98ea774
LW
1974 int i;
1975
1976 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1977 if (!npct)
1978 return -ENOMEM;
1979
f4b3f523
LW
1980 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1981 if (!match)
1982 return -ENODEV;
1983 version = (unsigned int) match->data;
855f80cd 1984
e98ea774 1985 /* Poke in other ASIC variants here */
f79c5ed9
LW
1986 if (version == PINCTRL_NMK_STN8815)
1987 nmk_pinctrl_stn8815_init(&npct->soc);
855f80cd 1988 if (version == PINCTRL_NMK_DB8500)
e98ea774 1989 nmk_pinctrl_db8500_init(&npct->soc);
45a1b531
PC
1990 if (version == PINCTRL_NMK_DB8540)
1991 nmk_pinctrl_db8540_init(&npct->soc);
e98ea774 1992
ab4a9362
LW
1993 /*
1994 * Since we depend on the GPIO chips to provide clock and register base
1995 * for the pin control operations, make sure that we have these
1996 * populated before we continue. Follow the phandles to instantiate
1997 * them. The GPIO portion of the actual hardware may be probed before
1998 * or after this point: it shouldn't matter as the APIs are orthogonal.
1999 */
2000 for (i = 0; i < NMK_MAX_BANKS; i++) {
2001 struct device_node *gpio_np;
2002 struct nmk_gpio_chip *nmk_chip;
2003
2004 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
2005 if (gpio_np) {
2006 dev_info(&pdev->dev,
2007 "populate NMK GPIO %d \"%s\"\n",
2008 i, gpio_np->name);
2009 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
2010 if (IS_ERR(nmk_chip))
2011 dev_err(&pdev->dev,
2012 "could not populate nmk chip struct "
2013 "- continue anyway\n");
2014 of_node_put(gpio_np);
2015 }
2016 }
2017
f4b3f523
LW
2018 prcm_np = of_parse_phandle(np, "prcm", 0);
2019 if (prcm_np)
2020 npct->prcm_base = of_iomap(prcm_np, 0);
32e67eee
LJ
2021 if (!npct->prcm_base) {
2022 if (version == PINCTRL_NMK_STN8815) {
2023 dev_info(&pdev->dev,
2024 "No PRCM base, "
2025 "assuming no ALT-Cx control is available\n");
2026 } else {
2027 dev_err(&pdev->dev, "missing PRCM base address\n");
2028 return -EINVAL;
f1671bf5 2029 }
f1671bf5
JA
2030 }
2031
e98ea774
LW
2032 nmk_pinctrl_desc.pins = npct->soc->pins;
2033 nmk_pinctrl_desc.npins = npct->soc->npins;
2034 npct->dev = &pdev->dev;
f1671bf5 2035
0ee60110 2036 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
323de9ef 2037 if (IS_ERR(npct->pctl)) {
e98ea774 2038 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
323de9ef 2039 return PTR_ERR(npct->pctl);
e98ea774
LW
2040 }
2041
e98ea774
LW
2042 platform_set_drvdata(pdev, npct);
2043 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
2044
2045 return 0;
2046}
2047
513c27f8
LJ
2048static const struct of_device_id nmk_gpio_match[] = {
2049 { .compatible = "st,nomadik-gpio", },
2050 {}
2051};
2052
3e3c62ca
RV
2053static struct platform_driver nmk_gpio_driver = {
2054 .driver = {
2ec1d359 2055 .name = "gpio",
513c27f8 2056 .of_match_table = nmk_gpio_match,
5317e4d1 2057 },
2ec1d359 2058 .probe = nmk_gpio_probe,
2ec1d359
AR
2059};
2060
c003eed7
UH
2061static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
2062 nmk_pinctrl_suspend,
2063 nmk_pinctrl_resume);
2064
e98ea774
LW
2065static struct platform_driver nmk_pinctrl_driver = {
2066 .driver = {
e98ea774 2067 .name = "pinctrl-nomadik",
855f80cd 2068 .of_match_table = nmk_pinctrl_match,
c003eed7 2069 .pm = &nmk_pinctrl_pm_ops,
e98ea774
LW
2070 },
2071 .probe = nmk_pinctrl_probe,
e98ea774
LW
2072};
2073
2ec1d359
AR
2074static int __init nmk_gpio_init(void)
2075{
802bb9b6
LW
2076 return platform_driver_register(&nmk_gpio_driver);
2077}
2078subsys_initcall(nmk_gpio_init);
e98ea774 2079
802bb9b6
LW
2080static int __init nmk_pinctrl_init(void)
2081{
e98ea774 2082 return platform_driver_register(&nmk_pinctrl_driver);
2ec1d359 2083}
802bb9b6 2084core_initcall(nmk_pinctrl_init);
2ec1d359
AR
2085
2086MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
2087MODULE_DESCRIPTION("Nomadik GPIO Driver");
2088MODULE_LICENSE("GPL");