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pinctrl: armada-37xx: account for const type of of_device_id.data
[linux-2.6-block.git] / drivers / pinctrl / mvebu / pinctrl-armada-37xx.c
CommitLineData
87466ccd
GC		 1/*
2 * Marvell 37xx SoC pinctrl driver
3 *
4 * Copyright (C) 2017 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 */
12
5715092a 13#include <linux/gpio/driver.h>
87466ccd
GC		 14#include <linux/mfd/syscon.h>
15#include <linux/of.h>
2f227605 16#include <linux/of_address.h>
87466ccd 17#include <linux/of_device.h>
2f227605 18#include <linux/of_irq.h>
87466ccd
GC		 19#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/pinctrl/pinconf.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23#include <linux/platform_device.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26
27#include "../pinctrl-utils.h"
28
29#define OUTPUT_EN 0x0
5715092a
GC		 30#define INPUT_VAL 0x10
31#define OUTPUT_VAL 0x18
87466ccd
GC		 32#define OUTPUT_CTL 0x20
33#define SELECTION 0x30
34
2f227605
GC		 35#define IRQ_EN 0x0
36#define IRQ_POL 0x08
37#define IRQ_STATUS 0x10
38#define IRQ_WKUP 0x18
39
9ac6e7cc 40#define NB_FUNCS 3
87466ccd
GC		 41#define GPIO_PER_REG 32
42
43/**
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
46 * pins.
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
49 * the group
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
57 */
58struct armada_37xx_pin_group {
59 const char *name;
60 unsigned int start_pin;
61 unsigned int npins;
62 u32 reg_mask;
63 u32 val[NB_FUNCS];
64 unsigned int extra_pin;
65 unsigned int extra_npins;
66 const char *funcs[NB_FUNCS];
67 unsigned int *pins;
68};
69
70struct armada_37xx_pin_data {
71 u8 nr_pins;
72 char *name;
73 struct armada_37xx_pin_group *groups;
74 int ngroups;
75};
76
77struct armada_37xx_pmx_func {
78 const char *name;
79 const char **groups;
80 unsigned int ngroups;
81};
82
83struct armada_37xx_pinctrl {
84 struct regmap *regmap;
2f227605 85 void __iomem *base;
87466ccd
GC		 86 const struct armada_37xx_pin_data *data;
87 struct device *dev;
5715092a 88 struct gpio_chip gpio_chip;
2f227605
GC		 89 struct irq_chip irq_chip;
90 spinlock_t irq_lock;
87466ccd
GC		 91 struct pinctrl_desc pctl;
92 struct pinctrl_dev *pctl_dev;
93 struct armada_37xx_pin_group *groups;
94 unsigned int ngroups;
95 struct armada_37xx_pmx_func *funcs;
96 unsigned int nfuncs;
97};
98
99#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
100 { \
101 .name = _name, \
102 .start_pin = _start, \
103 .npins = _nr, \
104 .reg_mask = _mask, \
105 .val = {0, _mask}, \
106 .funcs = {_func1, _func2} \
107 }
108
109#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
110 { \
111 .name = _name, \
112 .start_pin = _start, \
113 .npins = _nr, \
114 .reg_mask = _mask, \
115 .val = {0, _mask}, \
116 .funcs = {_func1, "gpio"} \
117 }
118
119#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
120 { \
121 .name = _name, \
122 .start_pin = _start, \
123 .npins = _nr, \
124 .reg_mask = _mask, \
125 .val = {_val1, _val2}, \
126 .funcs = {_func1, "gpio"} \
127 }
128
9ac6e7cc
GC		 129#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
130 { \
131 .name = _name, \
132 .start_pin = _start, \
133 .npins = _nr, \
134 .reg_mask = _mask, \
135 .val = {_v1, _v2, _v3}, \
136 .funcs = {_f1, _f2, "gpio"} \
137 }
138
87466ccd
GC		 139#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
140 _f1, _f2) \
141 { \
142 .name = _name, \
143 .start_pin = _start, \
144 .npins = _nr, \
145 .reg_mask = _mask, \
146 .val = {_v1, _v2}, \
147 .extra_pin = _start2, \
148 .extra_npins = _nr2, \
149 .funcs = {_f1, _f2} \
150 }
151
152static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
153 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
154 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
155 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
156 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
157 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
158 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
159 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
160 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
161 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
162 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
163 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
164 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
165 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
166 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
167 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
168 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
169 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
ce8a4a38
KM		 170 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
171 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
172 18, 2, "gpio", "uart"),
87466ccd
GC		 173 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
174 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
175 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
176 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
177
178};
179
180static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
181 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
182 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
8137f78a 183 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
9ac6e7cc 184 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
87466ccd
GC		 185 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
186 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
187 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
188 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
9ac6e7cc
GC		 189 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
190 "mii", "mii_err"),
87466ccd
GC		 191};
192
aea1dd4b 193static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
87466ccd
GC		 194 .nr_pins = 36,
195 .name = "GPIO1",
196 .groups = armada_37xx_nb_groups,
197 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
198};
199
aea1dd4b 200static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
6b67c390 201 .nr_pins = 30,
87466ccd
GC		 202 .name = "GPIO2",
203 .groups = armada_37xx_sb_groups,
204 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
205};
206
5715092a
GC		 207static inline void armada_37xx_update_reg(unsigned int *reg,
208 unsigned int offset)
209{
210 /* We never have more than 2 registers */
211 if (offset >= GPIO_PER_REG) {
212 offset -= GPIO_PER_REG;
213 *reg += sizeof(u32);
214 }
215}
216
87466ccd
GC		 217static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
218 const char *func)
219{
220 int f;
221
9ac6e7cc 222 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
87466ccd
GC		 223 if (!strcmp(grp->funcs[f], func))
224 return f;
225
226 return -ENOTSUPP;
227}
228
229static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
230 struct armada_37xx_pinctrl *info, int pin, int *grp)
231{
232 while (*grp < info->ngroups) {
233 struct armada_37xx_pin_group *group = &info->groups[*grp];
234 int j;
235
236 *grp = *grp + 1;
237 for (j = 0; j < (group->npins + group->extra_npins); j++)
238 if (group->pins[j] == pin)
239 return group;
240 }
241 return NULL;
242}
243
244static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
245 unsigned int selector, unsigned long *config)
246{
247 return -ENOTSUPP;
248}
249
250static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
251 unsigned int selector, unsigned long *configs,
252 unsigned int num_configs)
253{
254 return -ENOTSUPP;
255}
256
9b4e2ba4 257static const struct pinconf_ops armada_37xx_pinconf_ops = {
87466ccd
GC		 258 .is_generic = true,
259 .pin_config_group_get = armada_37xx_pin_config_group_get,
260 .pin_config_group_set = armada_37xx_pin_config_group_set,
261};
262
263static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
264{
265 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
266
267 return info->ngroups;
268}
269
270static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
271 unsigned int group)
272{
273 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
274
275 return info->groups[group].name;
276}
277
278static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
279 unsigned int selector,
280 const unsigned int **pins,
281 unsigned int *npins)
282{
283 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
284
285 if (selector >= info->ngroups)
286 return -EINVAL;
287
288 *pins = info->groups[selector].pins;
289 *npins = info->groups[selector].npins +
290 info->groups[selector].extra_npins;
291
292 return 0;
293}
294
295static const struct pinctrl_ops armada_37xx_pctrl_ops = {
296 .get_groups_count = armada_37xx_get_groups_count,
297 .get_group_name = armada_37xx_get_group_name,
298 .get_group_pins = armada_37xx_get_group_pins,
299 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
300 .dt_free_map = pinctrl_utils_free_map,
301};
302
303/*
304 * Pinmux_ops handling
305 */
306
307static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
308{
309 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
310
311 return info->nfuncs;
312}
313
314static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
315 unsigned int selector)
316{
317 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
318
319 return info->funcs[selector].name;
320}
321
322static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
323 unsigned int selector,
324 const char * const **groups,
325 unsigned int * const num_groups)
326{
327 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
328
329 *groups = info->funcs[selector].groups;
330 *num_groups = info->funcs[selector].ngroups;
331
332 return 0;
333}
334
335static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
336 const char *name,
337 struct armada_37xx_pin_group *grp)
338{
339 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
340 unsigned int reg = SELECTION;
341 unsigned int mask = grp->reg_mask;
342 int func, val;
343
344 dev_dbg(info->dev, "enable function %s group %s\n",
345 name, grp->name);
346
347 func = armada_37xx_get_func_reg(grp, name);
348
349 if (func < 0)
350 return func;
351
352 val = grp->val[func];
353
354 regmap_update_bits(info->regmap, reg, mask, val);
355
356 return 0;
357}
358
359static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
360 unsigned int selector,
361 unsigned int group)
362{
363
364 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
365 struct armada_37xx_pin_group *grp = &info->groups[group];
366 const char *name = info->funcs[selector].name;
367
368 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
369}
370
2f227605
GC		 371static inline void armada_37xx_irq_update_reg(unsigned int *reg,
372 struct irq_data *d)
373{
374 int offset = irqd_to_hwirq(d);
375
376 armada_37xx_update_reg(reg, offset);
377}
378
5715092a
GC		 379static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
380 unsigned int offset)
87466ccd 381{
5715092a 382 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
87466ccd
GC		 383 unsigned int reg = OUTPUT_EN;
384 unsigned int mask;
385
5715092a 386 armada_37xx_update_reg(&reg, offset);
87466ccd
GC		 387 mask = BIT(offset);
388
389 return regmap_update_bits(info->regmap, reg, mask, 0);
390}
391
5715092a
GC		 392static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
393 unsigned int offset)
87466ccd 394{
5715092a
GC		 395 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
396 unsigned int reg = OUTPUT_EN;
397 unsigned int val, mask;
398
399 armada_37xx_update_reg(&reg, offset);
400 mask = BIT(offset);
401 regmap_read(info->regmap, reg, &val);
402
403 return !(val & mask);
404}
405
406static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
407 unsigned int offset, int value)
408{
409 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
87466ccd
GC		 410 unsigned int reg = OUTPUT_EN;
411 unsigned int mask;
412
5715092a 413 armada_37xx_update_reg(&reg, offset);
87466ccd
GC		 414 mask = BIT(offset);
415
416 return regmap_update_bits(info->regmap, reg, mask, mask);
417}
418
5715092a
GC		 419static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
420{
421 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
422 unsigned int reg = INPUT_VAL;
423 unsigned int val, mask;
424
425 armada_37xx_update_reg(&reg, offset);
426 mask = BIT(offset);
427
428 regmap_read(info->regmap, reg, &val);
429
430 return (val & mask) != 0;
431}
432
433static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
434 int value)
435{
436 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
437 unsigned int reg = OUTPUT_VAL;
438 unsigned int mask, val;
439
440 armada_37xx_update_reg(&reg, offset);
441 mask = BIT(offset);
442 val = value ? mask : 0;
443
444 regmap_update_bits(info->regmap, reg, mask, val);
445}
446
87466ccd
GC		 447static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
448 struct pinctrl_gpio_range *range,
449 unsigned int offset, bool input)
450{
451 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
5715092a 452 struct gpio_chip *chip = range->gc;
87466ccd
GC		 453
454 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
455 offset, range->name, offset, input ? "input" : "output");
456
457 if (input)
5715092a 458 armada_37xx_gpio_direction_input(chip, offset);
87466ccd 459 else
5715092a 460 armada_37xx_gpio_direction_output(chip, offset, 0);
87466ccd
GC		 461
462 return 0;
463}
464
465static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
466 struct pinctrl_gpio_range *range,
467 unsigned int offset)
468{
469 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
470 struct armada_37xx_pin_group *group;
471 int grp = 0;
472
473 dev_dbg(info->dev, "requesting gpio %d\n", offset);
474
475 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
476 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
477
478 return 0;
479}
480
481static const struct pinmux_ops armada_37xx_pmx_ops = {
482 .get_functions_count = armada_37xx_pmx_get_funcs_count,
483 .get_function_name = armada_37xx_pmx_get_func_name,
484 .get_function_groups = armada_37xx_pmx_get_groups,
485 .set_mux = armada_37xx_pmx_set,
486 .gpio_request_enable = armada_37xx_gpio_request_enable,
487 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
488};
489
5715092a
GC		 490static const struct gpio_chip armada_37xx_gpiolib_chip = {
491 .request = gpiochip_generic_request,
492 .free = gpiochip_generic_free,
493 .set = armada_37xx_gpio_set,
494 .get = armada_37xx_gpio_get,
495 .get_direction = armada_37xx_gpio_get_direction,
496 .direction_input = armada_37xx_gpio_direction_input,
497 .direction_output = armada_37xx_gpio_direction_output,
498 .owner = THIS_MODULE,
499};
500
2f227605
GC		 501static void armada_37xx_irq_ack(struct irq_data *d)
502{
503 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
504 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
505 u32 reg = IRQ_STATUS;
506 unsigned long flags;
507
508 armada_37xx_irq_update_reg(&reg, d);
509 spin_lock_irqsave(&info->irq_lock, flags);
510 writel(d->mask, info->base + reg);
511 spin_unlock_irqrestore(&info->irq_lock, flags);
512}
513
514static void armada_37xx_irq_mask(struct irq_data *d)
515{
516 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
517 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
518 u32 val, reg = IRQ_EN;
519 unsigned long flags;
520
521 armada_37xx_irq_update_reg(&reg, d);
522 spin_lock_irqsave(&info->irq_lock, flags);
523 val = readl(info->base + reg);
524 writel(val & ~d->mask, info->base + reg);
525 spin_unlock_irqrestore(&info->irq_lock, flags);
526}
527
528static void armada_37xx_irq_unmask(struct irq_data *d)
529{
530 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
531 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
532 u32 val, reg = IRQ_EN;
533 unsigned long flags;
534
535 armada_37xx_irq_update_reg(&reg, d);
536 spin_lock_irqsave(&info->irq_lock, flags);
537 val = readl(info->base + reg);
538 writel(val | d->mask, info->base + reg);
539 spin_unlock_irqrestore(&info->irq_lock, flags);
540}
541
542static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
543{
544 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
545 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
546 u32 val, reg = IRQ_WKUP;
547 unsigned long flags;
548
549 armada_37xx_irq_update_reg(&reg, d);
550 spin_lock_irqsave(&info->irq_lock, flags);
551 val = readl(info->base + reg);
552 if (on)
a9a1a483 553 val |= (BIT(d->hwirq % GPIO_PER_REG));
2f227605 554 else
a9a1a483 555 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
2f227605
GC		 556 writel(val, info->base + reg);
557 spin_unlock_irqrestore(&info->irq_lock, flags);
558
559 return 0;
560}
561
562static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
563{
564 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
565 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
566 u32 val, reg = IRQ_POL;
567 unsigned long flags;
568
569 spin_lock_irqsave(&info->irq_lock, flags);
570 armada_37xx_irq_update_reg(&reg, d);
571 val = readl(info->base + reg);
572 switch (type) {
573 case IRQ_TYPE_EDGE_RISING:
a9a1a483 574 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
2f227605
GC		 575 break;
576 case IRQ_TYPE_EDGE_FALLING:
a9a1a483 577 val |= (BIT(d->hwirq % GPIO_PER_REG));
2f227605 578 break;
30ac0d3b
KM		 579 case IRQ_TYPE_EDGE_BOTH: {
580 u32 in_val, in_reg = INPUT_VAL;
581
582 armada_37xx_irq_update_reg(&in_reg, d);
583 regmap_read(info->regmap, in_reg, &in_val);
584
585 /* Set initial polarity based on current input level. */
586 if (in_val & d->mask)
587 val |= d->mask; /* falling */
588 else
589 val &= ~d->mask; /* rising */
590 break;
591 }
2f227605
GC		 592 default:
593 spin_unlock_irqrestore(&info->irq_lock, flags);
594 return -EINVAL;
595 }
596 writel(val, info->base + reg);
597 spin_unlock_irqrestore(&info->irq_lock, flags);
598
599 return 0;
600}
601
30ac0d3b
KM		 602static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
603 u32 pin_idx)
604{
605 u32 reg_idx = pin_idx / GPIO_PER_REG;
606 u32 bit_num = pin_idx % GPIO_PER_REG;
607 u32 p, l, ret;
608 unsigned long flags;
609
610 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
611
612 spin_lock_irqsave(&info->irq_lock, flags);
613 p = readl(info->base + IRQ_POL + 4 * reg_idx);
614 if ((p ^ l) & (1 << bit_num)) {
615 /*
616 * For the gpios which are used for both-edge irqs, when their
617 * interrupts happen, their input levels are changed,
618 * yet their interrupt polarities are kept in old values, we
619 * should synchronize their interrupt polarities; for example,
620 * at first a gpio's input level is low and its interrupt
621 * polarity control is "Detect rising edge", then the gpio has
622 * a interrupt , its level turns to high, we should change its
623 * polarity control to "Detect falling edge" correspondingly.
624 */
625 p ^= 1 << bit_num;
626 writel(p, info->base + IRQ_POL + 4 * reg_idx);
627 ret = 0;
628 } else {
629 /* Spurious irq */
630 ret = -1;
631 }
632
633 spin_unlock_irqrestore(&info->irq_lock, flags);
634 return ret;
635}
2f227605
GC		 636
637static void armada_37xx_irq_handler(struct irq_desc *desc)
638{
639 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
640 struct irq_chip *chip = irq_desc_get_chip(desc);
641 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
f0fbe7bc 642 struct irq_domain *d = gc->irq.domain;
2f227605
GC		 643 int i;
644
645 chained_irq_enter(chip, desc);
646 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
647 u32 status;
648 unsigned long flags;
649
650 spin_lock_irqsave(&info->irq_lock, flags);
651 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
652 /* Manage only the interrupt that was enabled */
653 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
654 spin_unlock_irqrestore(&info->irq_lock, flags);
655 while (status) {
656 u32 hwirq = ffs(status) - 1;
657 u32 virq = irq_find_mapping(d, hwirq +
658 i * GPIO_PER_REG);
30ac0d3b
KM		 659 u32 t = irq_get_trigger_type(virq);
660
661 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
662 /* Swap polarity (race with GPIO line) */
663 if (armada_37xx_edge_both_irq_swap_pol(info,
664 hwirq + i * GPIO_PER_REG)) {
665 /*
666 * For spurious irq, which gpio level
667 * is not as expected after incoming
668 * edge, just ack the gpio irq.
669 */
670 writel(1 << hwirq,
671 info->base +
672 IRQ_STATUS + 4 * i);
673 continue;
674 }
675 }
2f227605
GC		 676
677 generic_handle_irq(virq);
678
679 /* Update status in case a new IRQ appears */
680 spin_lock_irqsave(&info->irq_lock, flags);
681 status = readl_relaxed(info->base +
682 IRQ_STATUS + 4 * i);
683 /* Manage only the interrupt that was enabled */
684 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
685 spin_unlock_irqrestore(&info->irq_lock, flags);
686 }
687 }
688 chained_irq_exit(chip, desc);
689}
690
a9a1a483
GC		 691static unsigned int armada_37xx_irq_startup(struct irq_data *d)
692{
a9a1a483
GC		 693 /*
694 * The mask field is a "precomputed bitmask for accessing the
695 * chip registers" which was introduced for the generic
696 * irqchip framework. As we don't use this framework, we can
697 * reuse this field for our own usage.
698 */
3ee9e605 699 d->mask = BIT(d->hwirq % GPIO_PER_REG);
a9a1a483
GC		 700
701 armada_37xx_irq_unmask(d);
702
703 return 0;
704}
705
2f227605
GC		 706static int armada_37xx_irqchip_register(struct platform_device *pdev,
707 struct armada_37xx_pinctrl *info)
708{
709 struct device_node *np = info->dev->of_node;
2f227605
GC		 710 struct gpio_chip *gc = &info->gpio_chip;
711 struct irq_chip *irqchip = &info->irq_chip;
712 struct resource res;
713 int ret = -ENODEV, i, nr_irq_parent;
714
715 /* Check if we have at least one gpio-controller child node */
716 for_each_child_of_node(info->dev->of_node, np) {
717 if (of_property_read_bool(np, "gpio-controller")) {
718 ret = 0;
719 break;
720 }
721 };
722 if (ret)
723 return ret;
724
725 nr_irq_parent = of_irq_count(np);
726 spin_lock_init(&info->irq_lock);
727
728 if (!nr_irq_parent) {
729 dev_err(&pdev->dev, "Invalid or no IRQ\n");
730 return 0;
731 }
732
733 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
734 dev_err(info->dev, "cannot find IO resource\n");
735 return -ENOENT;
736 }
737
738 info->base = devm_ioremap_resource(info->dev, &res);
739 if (IS_ERR(info->base))
740 return PTR_ERR(info->base);
741
742 irqchip->irq_ack = armada_37xx_irq_ack;
743 irqchip->irq_mask = armada_37xx_irq_mask;
744 irqchip->irq_unmask = armada_37xx_irq_unmask;
745 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
746 irqchip->irq_set_type = armada_37xx_irq_set_type;
a9a1a483 747 irqchip->irq_startup = armada_37xx_irq_startup;
2f227605 748 irqchip->name = info->data->name;
2f227605
GC		 749 ret = gpiochip_irqchip_add(gc, irqchip, 0,
750 handle_edge_irq, IRQ_TYPE_NONE);
751 if (ret) {
752 dev_info(&pdev->dev, "could not add irqchip\n");
753 return ret;
754 }
755
756 /*
757 * Many interrupts are connected to the parent interrupt
758 * controller. But we do not take advantage of this and use
759 * the chained irq with all of them.
760 */
2f227605
GC		 761 for (i = 0; i < nr_irq_parent; i++) {
762 int irq = irq_of_parse_and_map(np, i);
763
764 if (irq < 0)
765 continue;
766
767 gpiochip_set_chained_irqchip(gc, irqchip, irq,
768 armada_37xx_irq_handler);
769 }
770
771 return 0;
772}
773
5715092a
GC		 774static int armada_37xx_gpiochip_register(struct platform_device *pdev,
775 struct armada_37xx_pinctrl *info)
776{
777 struct device_node *np;
778 struct gpio_chip *gc;
779 int ret = -ENODEV;
780
781 for_each_child_of_node(info->dev->of_node, np) {
782 if (of_find_property(np, "gpio-controller", NULL)) {
783 ret = 0;
784 break;
785 }
786 };
787 if (ret)
788 return ret;
789
790 info->gpio_chip = armada_37xx_gpiolib_chip;
791
792 gc = &info->gpio_chip;
793 gc->ngpio = info->data->nr_pins;
794 gc->parent = &pdev->dev;
795 gc->base = -1;
796 gc->of_node = np;
797 gc->label = info->data->name;
798
799 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
2f227605
GC		 800 if (ret)
801 return ret;
802 ret = armada_37xx_irqchip_register(pdev, info);
5715092a
GC		 803 if (ret)
804 return ret;
805
806 return 0;
807}
808
87466ccd
GC		 809/**
810 * armada_37xx_add_function() - Add a new function to the list
811 * @funcs: array of function to add the new one
812 * @funcsize: size of the remaining space for the function
813 * @name: name of the function to add
814 *
815 * If it is a new function then create it by adding its name else
816 * increment the number of group associated to this function.
817 */
818static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
819 int *funcsize, const char *name)
820{
821 int i = 0;
822
823 if (*funcsize <= 0)
824 return -EOVERFLOW;
825
826 while (funcs->ngroups) {
827 /* function already there */
828 if (strcmp(funcs->name, name) == 0) {
829 funcs->ngroups++;
830
831 return -EEXIST;
832 }
833 funcs++;
834 i++;
835 }
836
837 /* append new unique function */
838 funcs->name = name;
839 funcs->ngroups = 1;
840 (*funcsize)--;
841
842 return 0;
843}
844
845/**
846 * armada_37xx_fill_group() - complete the group array
847 * @info: info driver instance
848 *
849 * Based on the data available from the armada_37xx_pin_group array
850 * completes the last member of the struct for each function: the list
851 * of the groups associated to this function.
852 *
853 */
854static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
855{
856 int n, num = 0, funcsize = info->data->nr_pins;
857
858 for (n = 0; n < info->ngroups; n++) {
859 struct armada_37xx_pin_group *grp = &info->groups[n];
860 int i, j, f;
861
862 grp->pins = devm_kzalloc(info->dev,
863 (grp->npins + grp->extra_npins) *
864 sizeof(*grp->pins), GFP_KERNEL);
865 if (!grp->pins)
866 return -ENOMEM;
867
868 for (i = 0; i < grp->npins; i++)
869 grp->pins[i] = grp->start_pin + i;
870
871 for (j = 0; j < grp->extra_npins; j++)
872 grp->pins[i+j] = grp->extra_pin + j;
873
9ac6e7cc 874 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
87466ccd
GC		 875 int ret;
876 /* check for unique functions and count groups */
877 ret = armada_37xx_add_function(info->funcs, &funcsize,
878 grp->funcs[f]);
879 if (ret == -EOVERFLOW)
880 dev_err(info->dev,
881 "More functions than pins(%d)\n",
882 info->data->nr_pins);
883 if (ret < 0)
884 continue;
885 num++;
886 }
887 }
888
889 info->nfuncs = num;
890
891 return 0;
892}
893
894/**
895 * armada_37xx_fill_funcs() - complete the funcs array
896 * @info: info driver instance
897 *
898 * Based on the data available from the armada_37xx_pin_group array
899 * completes the last two member of the struct for each group:
900 * - the list of the pins included in the group
901 * - the list of pinmux functions that can be selected for this group
902 *
903 */
904static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
905{
906 struct armada_37xx_pmx_func *funcs = info->funcs;
907 int n;
908
909 for (n = 0; n < info->nfuncs; n++) {
910 const char *name = funcs[n].name;
911 const char **groups;
912 int g;
913
914 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
915 sizeof(*(funcs[n].groups)),
916 GFP_KERNEL);
917 if (!funcs[n].groups)
918 return -ENOMEM;
919
920 groups = funcs[n].groups;
921
922 for (g = 0; g < info->ngroups; g++) {
923 struct armada_37xx_pin_group *gp = &info->groups[g];
924 int f;
925
9ac6e7cc 926 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
87466ccd
GC		 927 if (strcmp(gp->funcs[f], name) == 0) {
928 *groups = gp->name;
929 groups++;
930 }
931 }
932 }
933 }
934 return 0;
935}
936
937static int armada_37xx_pinctrl_register(struct platform_device *pdev,
938 struct armada_37xx_pinctrl *info)
939{
940 const struct armada_37xx_pin_data *pin_data = info->data;
941 struct pinctrl_desc *ctrldesc = &info->pctl;
942 struct pinctrl_pin_desc *pindesc, *pdesc;
943 int pin, ret;
944
945 info->groups = pin_data->groups;
946 info->ngroups = pin_data->ngroups;
947
948 ctrldesc->name = "armada_37xx-pinctrl";
949 ctrldesc->owner = THIS_MODULE;
950 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
951 ctrldesc->pmxops = &armada_37xx_pmx_ops;
952 ctrldesc->confops = &armada_37xx_pinconf_ops;
953
954 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
955 pin_data->nr_pins, GFP_KERNEL);
956 if (!pindesc)
957 return -ENOMEM;
958
959 ctrldesc->pins = pindesc;
960 ctrldesc->npins = pin_data->nr_pins;
961
962 pdesc = pindesc;
963 for (pin = 0; pin < pin_data->nr_pins; pin++) {
964 pdesc->number = pin;
965 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
966 pin_data->name, pin);
967 pdesc++;
968 }
969
970 /*
971 * we allocate functions for number of pins and hope there are
972 * fewer unique functions than pins available
973 */
974 info->funcs = devm_kzalloc(&pdev->dev, pin_data->nr_pins *
975 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
976 if (!info->funcs)
977 return -ENOMEM;
978
979
980 ret = armada_37xx_fill_group(info);
981 if (ret)
982 return ret;
983
984 ret = armada_37xx_fill_func(info);
985 if (ret)
986 return ret;
987
988 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
989 if (IS_ERR(info->pctl_dev)) {
990 dev_err(&pdev->dev, "could not register pinctrl driver\n");
991 return PTR_ERR(info->pctl_dev);
992 }
993
994 return 0;
995}
996
997static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
998 {
999 .compatible = "marvell,armada3710-sb-pinctrl",
924f5494 1000 .data = &armada_37xx_pin_sb,
87466ccd
GC		 1001 },
1002 {
1003 .compatible = "marvell,armada3710-nb-pinctrl",
924f5494 1004 .data = &armada_37xx_pin_nb,
87466ccd
GC		 1005 },
1006 { },
1007};
1008
1009static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1010{
1011 struct armada_37xx_pinctrl *info;
1012 struct device *dev = &pdev->dev;
1013 struct device_node *np = dev->of_node;
1014 struct regmap *regmap;
1015 int ret;
1016
1017 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
1018 GFP_KERNEL);
1019 if (!info)
1020 return -ENOMEM;
1021
1022 info->dev = dev;
1023
1024 regmap = syscon_node_to_regmap(np);
1025 if (IS_ERR(regmap)) {
1026 dev_err(&pdev->dev, "cannot get regmap\n");
1027 return PTR_ERR(regmap);
1028 }
1029 info->regmap = regmap;
1030
1031 info->data = of_device_get_match_data(dev);
1032
1033 ret = armada_37xx_pinctrl_register(pdev, info);
1034 if (ret)
1035 return ret;
1036
5715092a
GC		 1037 ret = armada_37xx_gpiochip_register(pdev, info);
1038 if (ret)
1039 return ret;
1040
87466ccd
GC		 1041 platform_set_drvdata(pdev, info);
1042
1043 return 0;
1044}
1045
1046static struct platform_driver armada_37xx_pinctrl_driver = {
1047 .driver = {
1048 .name = "armada-37xx-pinctrl",
1049 .of_match_table = armada_37xx_pinctrl_of_match,
1050 },
1051};
1052
1053builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1054 armada_37xx_pinctrl_probe);
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